KR102471411B1 - Circuit of fuse address - Google Patents

Abstract

A fuse address circuit according to the present invention includes a plurality of unit fuses, a logic operator disposed between adjacent unit fuses, and a plurality of first connection wires extending in a first direction to connect each unit fuse to the logic operator. It includes three or more input circuits each including , and an output operator disposed between the plurality of input circuits and providing a fuse output signal. The first connection wires provided to the plurality of input circuits are formed at the same height in a second direction substantially perpendicular to the first direction.

Description

Fuse address circuit {Circuit of fuse address}

Various embodiments of the present invention relate to a fuse address circuit.

A memory device may include a plurality of memory cells. There is a possibility that a plurality of memory cells may not operate normally due to a PVT variation in a manufacturing process. Accordingly, redundant memory cells to replace (repair) the plurality of memory cells may be provided together with the plurality of memory cells in case the plurality of memory cells do not operate normally.

When an address to access a memory cell at a specific location is input, repair is performed by changing the address to access a redundant memory cell to be replaced.

As the degree of integration of electronic devices increases, the degree of integration of a plurality of memory cells and redundant memory cells to replace them also increases. In addition, the degree of integration of a fuse address circuit for outputting a fuse address to perform repair should be increased.

A fuse address circuit according to various embodiments of the present disclosure minimizes a layout area required for the fuse address circuit by improving existing layout characteristics.

A fuse address circuit according to an embodiment of the present invention includes a plurality of unit fuses, a logic operator disposed between adjacent unit fuses, and extending in a first direction to connect each of the unit fuses to the logic operator. and three or more input circuits, each of which includes a plurality of first connection wires, and an output operator disposed between the plurality of input circuits and providing a fuse output signal. The first connection wires provided to the plurality of input circuits are formed at the same height in a second direction substantially perpendicular to the first direction.

According to various embodiments disclosed in this document, the fuse address circuit can save the number of metal wires crossing the circuit by improving the layout of the row fuse set, thereby minimizing the vertical height of the layout. .

Furthermore, according to various embodiments disclosed in this document, the fuse address circuit can reduce the bottle neck even when the vertical height thereof is reduced, thereby improving operational reliability.

In addition, the various embodiments disclosed in this document are for illustrative purposes, and those skilled in the art will be able to make various modifications, changes, substitutions, and additions through the technical spirit and scope of the appended claims, and these modifications and changes, etc. should be considered within the scope.

1 is a circuit diagram illustrating a fuse address circuit according to an exemplary embodiment of the present invention.
2 is a plan view illustrating a fuse address circuit according to an exemplary embodiment of the present invention.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. In this document, the same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components are omitted.

For various embodiments of the present invention disclosed in this document, specific structural or functional descriptions are merely exemplified for the purpose of describing the embodiments of the present invention, and various embodiments of the present invention may be implemented in various forms. and should not be construed as being limited to the embodiments described in this document.

Expressions such as "first", "second", "first", or "second" used in various embodiments may modify various elements regardless of order and/or importance, and the elements Not limited. For example, without departing from the scope of the present invention, a first element may be termed a second element, and similarly, the second element may also be renamed to the first element.

Terms used in this document are only used to describe a specific embodiment, and may not be intended to limit the scope of other embodiments. Singular expressions may include plural expressions unless the context clearly dictates otherwise.

All terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by a person of ordinary skill in the art of the present invention. Terms defined in commonly used dictionaries may be interpreted as having the same or similar meanings as those in the context of the related art, and unless explicitly defined in this document, they are not interpreted in ideal or excessively formal meanings. . In some cases, even terms defined in this document cannot be interpreted to exclude embodiments of the present invention.

1 is a circuit diagram illustrating a fuse address circuit according to an exemplary embodiment, and FIG. 2 is a plan view illustrating a fuse address circuit according to an exemplary embodiment.

First, referring to FIG. 1 , a fuse address circuit according to an embodiment of the present invention will be described from the circuit configuration point of view.

The fuse address circuit 1 includes three or more input circuits 100, 200, and 300 and an output operator SUM connected to the input circuits 100, 200, and 300 to provide a fuse output signal OUT. can do.

The first input circuit 100 may include four unit fuses FS<1>, FS<2>, FS<3>, and FS<4> and a first logic operator NAND1. The first input circuit 100 receives the fuse signals F1_1, F1_2, F1_3, and F1_4 provided from the four unit fuses FS<1>, FS<2>, FS<3>, and FS<4>. A negative AND operation (eg, a NAND operation) is performed through the logical operator NAND1 to output the first sum signal S1.

Each of the unit fuses FS<1>, ..., FS<12> includes a fuse latch storing a specific value, and compares an address bit supplied from the outside with one fuse bit to generate fuse signals F1_1, ..., F1_4, F2_1, ..., F2_4, F3_1, ..., F3_4) can be improved.

The second input circuit 200 may include four unit fuses FS<5>, FS<6>, FS<7>, and FS<8> and a second logic operator NAND2. The second input circuit 200 responds to the fuse signals F2_1, F2_2, F2_3, and F2_4 provided from the four unit fuses FS<5>, FS<6>, FS<7>, and FS<8>. A negative AND operation (eg, NAND operation) is performed through the logical operator NAND2 to output the second sum signal S2.

The third input circuit 300 may include four unit fuses FS<9>, FS<10>, FS<11>, and FS<12> and a third logic operator NAND3. The third input circuit 300 receives the fuse signals F3_1, F3_2, F3_3, and F3_4 provided from the four unit fuses FS<9>, FS<10>, FS<11>, and FS<12>. A third summation signal S3 is output by performing a negative AND operation (eg, a NAND operation) through the logic operator NAND3.

The output operator SUM may receive the first to third summation signals S1 , S2 , and S3 and perform a logic operation (eg, a NOR operation) to provide a fuse output signal OUT.

A fuse address circuit according to an embodiment of the present invention includes fuse signals FS1_1, ..., FS1_4, FS2_1, .. provided from a plurality of unit fuses FS<1>, ..., FS<12>. ., FS2_4, FS3_1, ..., FS3_4), the arrangement can be improved by performing logical operations in two steps.

In FIG. 1, the logical operators NAND1, NAND2, and NAND3 are shown as negative AND operators, and the output operator SUM is shown as a negative OR operator.

Referring to FIG. 2 , a layout configuration of a fuse address circuit 1 according to an exemplary embodiment of the present invention will be described. Reference numerals used for the circuit elements and signals described with reference to the circuit diagram of FIG. 1 are identically used for configuration matching and connection wiring of FIG. 2 . Like reference numerals indicate like elements.

Referring to FIG. 2 , the input circuits 100, 200, and 300 may have substantially the same structure. The first input circuit 100 may include a first logic operator NAND1 and first to fourth unit fuses FS<1>, ..., FS<4>.

The first to fourth unit fuses FS<1, .., FS<4> may be disposed left and right around the first logical operator NAND1. According to an embodiment, the first and second unit fuses FS<1> and FS<2> are disposed to the left of the first logical operator NAND1, and the third and fourth unit fuses FS<3>, FS<4>) may be disposed on the right side of the first logical operator NAND1.

First to fourth unit fuses FS<1>, FS<2>, FS<3>, and FS<4 providing fuse signals FS1_1, FS1_2, FS1_3, and FS1_4 to the first logical operator NAND1 Since >) is divided and arranged around the first logical operator NAND1, connection wires for providing the fuse signals FS1_1, FS1_2, FS1_3, and FS1_4 may extend left and right.

In this specification, connection wires providing the fuse signals FS1_1, ..., FS1_4, FS2_1, ..., FS2_4, FS3_1, ..., FS3_4 are referred to as first connection wires, and the summing signals S1, Connection wires providing S2 and S3) are referred to as second connection wires.

Accordingly, the first input circuit 100 includes first connection wires extending in the X direction at two heights of y1 and y2 when viewed from the Y direction. According to an embodiment, the same number of unit fuses may be disposed on the left and right sides of the first input circuit 100 with the first logic operator NAND1 as the center. Among them, one unit fuse on the left side and one unit fuse on the right side may include first connection wires formed at the same height as each other in the Y direction. Therefore, two unit fuses FS<1> and FS<2> disposed on the left side of the first logical operator NAND1 and two unit fuses FS<3> and FS<4 disposed on the right side of the first logical operator NAND1 >), first connection wires extending in parallel at two heights may be formed.

According to an embodiment, the first logical operator NAND1 constituting the first input circuit 100 and the plurality of unit fuses connected to the first logical operator NAND1 minimize the height at which the first connection wires match. can be placed. Accordingly, the number of unit fuses may be divided in half and each of the divided unit fuses may be disposed on the left and right sides of the first logic operator NAND1. 2, two unit fuses FS<1> and FS<2> are disposed on the left side of the first logical operator NAND1, and two unit fuses FS<3> and FS<4> are disposed on the right side of the first logical operator NAND1. Although shown as being arranged, when seven unit fuses are connected to the first logic operator NAND1, three unit fuses and four unit fuses may be disposed on the left or right side, respectively. In summary, in one embodiment of the present invention, the logic operator of the input circuit and the unit fuses disposed adjacent thereto divide the total number of connected unit fuses by half and may be disposed on the left and right sides of the logic operator, respectively. .

The second input circuit 200 may include a second logic operator NAND2 and fifth to eighth unit fuses FS<5>, ..., FS<8>. Similarly, the unit fuses FS<5>, FS<6>, FS<7>, and FS<8> of the second input circuit 200 may be arranged left and right around the second logical operator NAND2. . For example, the fifth and sixth unit fuses FS<5> and FS<6> are disposed on the left side of the second logical operator NAND2 and the seventh and eighth unit fuses FS<7>, FS<8>) may be disposed on the right side of the second logical operator NAND2.

A connection wire connecting the second logical operator NAND2 and the fifth and sixth unit fuses FS<5> and FS<6> to provide the fuse signals F2_1 and F2_2 is the second logical operator NAND2 A connection wire extending to the left of and connecting the second logic operator NAND2 and the seventh and eighth unit fuses FS<7> and FS<8> to provide fuse signals F2_3 and F2_4 is It extends to the right of the 2 logical operator NAND2.

The first connection wires of the second input signal 200 may extend in the X direction at two heights of y1 and y2 when viewed from the Y direction with the second logical operator NAND2 as the center. The first connection wires included in the first input signal 100 and the second input signal 200 may be formed at the same height when viewed from the Y direction, in other words, parallel to the X direction at both heights y1 and y2 Discontinuously extending wires may be connected to a unit fuse and a logic operator connected thereto, thereby forming a first connection wire.

The third input circuit 300 includes a third logic operator NAND3 and ninth to twelfth unit fuses FS<9>, FS<10>, and FS disposed left and right around the third logic operator NAND3. <11>, FS<12>). According to an embodiment, the ninth and tenth unit fuses FS<9> and FS<10> are disposed to the left of the third logic operator NAND3 and the eleventh and twelfth unit fuses FS<11> , FS<12>) may be disposed on the right side of the third logical operator NAND3.

A connection wire through which the ninth and tenth unit fuses FS<9> and FS<10> provide the fuse signals FS3_1 and FS3_2 for the third logical operator NAND3 is A connection wire extending to the left and providing fuse signals FS3_3 and FS3_4 to the eleventh and twelfth unit fuses FS<11> and FS<12> extends to the right of the third logical operator NAND3. .

The first connection wires provided in the third input circuit 300 may extend in the X direction in parallel at the heights of y1 and y2 in the Y direction.

In conclusion, in the fuse address circuit 1 according to an embodiment of the present invention, 12 unit fuses FS<1>, ..., FS< 12>) to provide the fuse signals FS1_1, ..., FS1_4, FS2_1, ..., FS2_4, FS3_1, ..., FS3_4 to the respective logic operators NAND1, NAND2, NAND3 Only space for wires extending at two heights, y1 and y2 in the Y direction, is required.

Since the 12 first connection wires are formed only at two heights in the Y direction, the vertical height h of the fuse address circuit 1 can be significantly reduced. Since the vertical height h of the fuse address circuit 1 may be reduced, a sufficient space between the connection wires may be secured, and thus the bottleneck of the fuse signal may be reduced.

The fuse address circuit 1 may include an output operator SUM disposed between the plurality of input circuits 100 , 200 , and 300 . The output operator SUM receives the sum signals S1, S2, and S3 from the first to third logic operators NAND1, NAND2, and NAND3 of the plurality of input circuits 100, 200, and 300, and outputs the fuse. A signal OUT may be provided.

Since the output operator SUM is disposed between the plurality of input circuits 100, 200, and 300, the plurality of input circuits 100, 200, and 300 may be disposed left and right around the output operator SUM. have. Accordingly, the second connection wire provided with the summation signals S1, S2, and S3 may also extend left and right with the output operator SUM as the center.

Accordingly, a vertical height required for disposition of the second connection wire may be reduced. In FIG. 2 , the first input circuit 100 is disposed on the left side of the output operator SUM, and the second and third input circuits 200 and 300 are disposed on the right side of the output operator SUM. However, this arrangement is exemplary and the arrangement of the output operator SUM between the input circuits may be included in an embodiment of the present invention.

Similarly to the arrangement of logic operators and unit fuses inside each of the input circuits 100, 200, and 300, the number of input circuits 100, 200, and 300 is divided in half, and each half is the output operator SUM. It can be placed on the left and right. Therefore, in FIG. 2, the first input circuit 100 is disposed on the left side of the output operator SUM and the second and third input circuits 200 and 300 are disposed on the right side of the output operator SUM, but the output operator ( The same number of input circuits may be disposed on the left and right sides of the output operator SUM, and the first and second input circuits 100 and 200 are disposed on the left side of the output operator SUM and on the right side of the output operator SUM. A third input circuit 300 may be disposed.

According to an embodiment, the fuse address circuit 1 may include a fuse activation circuit FS_EN disposed on one side of the first input circuit 100 . The fuse activation circuit (FS_EN) is connected to each unit fuse (FS<1>, ..., FS<12>) to activate the operation of the unit fuses (FS<1>, ..., FS<12>) can do.

As described above, the fuse address circuit according to an embodiment of the present invention is divided into circuits to perform multi-step logic operations. According to an embodiment, the fuse address circuit 1 according to an embodiment of the present invention performs the second step logic operation of the output operator SUM after the first step logic operation of the input circuits 100, 200, and 300. By doing this, you can make the layout structure simpler.

In order to secure a wiring space into which a plurality of signals are input, the fuse address circuit according to an embodiment of the present invention arranges a plurality of input signals on the left and right sides of a device to which the output signal is provided, so that the input wires are Vertical space can be secured.

A circuit or system according to various embodiments may include at least one or more of the aforementioned components, some may be omitted, or additional components may be further included. And the embodiments disclosed in this document are presented for explanation and understanding of the disclosed technical content, and do not limit the scope of the present invention. Therefore, the scope of this document should be construed as including all changes or various other embodiments based on the technical spirit of the present invention.

1: fuse address circuit
100, 200, 300: input circuit
NAND1, NAND2, NAND3: logical operators
SUM : output operator

Claims (11)

A plurality of unit fuses, a logic operator disposed between adjacent unit fuses among the plurality of unit fuses, and a plurality of first connections extending in a first direction to connect each of the unit fuses to the logic operator. a plurality of input circuits each including wires; and
An output operator disposed between the plurality of input circuits and providing a fuse output signal;
The plurality of unit fuses respectively included in the plurality of input circuits are distributed in equal numbers on the left and right sides of the logic operator,
Among the first connection wires included in each of the plurality of input circuits, the height of the first connection wire located on the left side of the logical operator and the height of the first connection wire located on the right side of the logical operator are equal to each other,
The plurality of input circuits are arranged in the same number on the left and right sides of the output operator,
A second connection wire extending in the first direction and connecting a logical operator included in each of the input circuits and the output operator,
Each of the logic operators included in the plurality of input circuits outputs a sum signal, and the output operator receives the sum signals through the second connection wire to provide the fuse output signal;
The fuse address circuit of claim 1 , wherein the height is a height in a second direction perpendicular to the first direction. delete delete delete ◈Claim 5 was abandoned when the registration fee was paid.◈ The method of claim 1,
The fuse address circuit of claim 1 , wherein the first connection wire is formed at the same height in the second direction with respect to one unit fuse disposed on the left side and one unit fuse disposed on the right side. delete ◈Claim 7 was abandoned when the registration fee was paid.◈ The method of claim 1,
The fuse address circuit of claim 1 , wherein the logical operator includes a negative AND operator, and the output operator includes an AND operator. ◈Claim 8 was abandoned when the registration fee was paid.◈ The method of claim 1,
In each of the plurality of input circuits, the plurality of unit fuses are disposed on the left side and the right side of the logic operator as a center, respectively. ◈Claim 9 was abandoned when the registration fee was paid.◈ The method of claim 8,
The fuse address circuit of claim 1 , wherein the first connection wires are formed so that wires formed in parallel with respect to two heights in the second direction discontinuously connect between each logic operator and unit fuses. ◈Claim 10 was abandoned when the registration fee was paid.◈ The method of claim 1,
The fuse address circuit of claim 1 , wherein the unit fuses include row or column unit fuses. ◈Claim 11 was abandoned when the registration fee was paid.◈ The method of claim 1,
The fuse address circuit of claim 1 , further comprising a fuse activating circuit on one side of the input circuit.

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