KR102467276B1 - Source and drain epitaxial layers - Google Patents

Abstract

The present disclosure relates to a semiconductor structure having a source/drain epitaxial stack having a low-melting top layer and a high-melting bottom layer. For example, the semiconductor structure includes a gate structure disposed on a fin and a recess formed in a portion of the fin not covered by the gate structure. The semiconductor structure also includes a source/drain epitaxial stack disposed within the recess, the source/drain epitaxial stack having a lower layer and an upper layer having a higher active dopant concentration than the lower layer.

Description

Source and drain epitaxial layers {SOURCE AND DRAIN EPITAXIAL LAYERS}

A dopant of a semiconductor material can function as a donor or acceptor only when it is part of a semiconductor lattice structure. For this reason, dopants in the semiconductor material (eg silicon) need to be activated. An activated dopant can act as either a donor or acceptor of electrons, eg acting as an n-type or p-type dopant for semiconductor materials. When a dopant occupies interstitial space in a semiconductor material, it is not considered active and has no effect as a dopant (eg, cannot function as a donor or acceptor). Thermal energy may be provided to the doped semiconductor material to move the dopant from the interstitial spaces to the crystal sites, a process referred to as “activation” or “crystal activation”.

Aspects of the present disclosure are best understood from the detailed description below when read in conjunction with the accompanying drawings. It is noted that, in accordance with common practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation.
1 is a partial cross-sectional view of an exemplary array of transistor structures formed on a fin and having a single crystal source/drain stack during a laser annealing process, in accordance with some embodiments.
2 is a partial cross-sectional view of a transistor structure having a source/drain epitaxial stack having an amorphous low melting point top layer and a single crystalline high melting point bottom layer during a laser annealing process, in accordance with some embodiments.
3 is a secondary ion overlaid with a spreading resistivity profile (SRP) for a source/drain epitaxial stack having a low-melting top layer and a high-melting bottom layer after a laser annealing process, in accordance with some embodiments. It is a secondary ion mass spectroscopy (SIMS) profile.
4 is a cross-sectional view of a transistor structure having a source/drain epitaxial stack with a laser annealed single crystal top layer and a single crystal bottom layer, in accordance with some embodiments.
5 is a flow diagram of a method of forming a source/drain epitaxial stack having a low-melting top layer and a high-melting bottom bottom layer, in accordance with some embodiments.
6 is a partial cross-sectional view of a transistor structure along the x-direction and the y-direction, in accordance with some embodiments.
7 is a partial cross-sectional view of a recessed fin portion of a transistor structure along an x-direction and a y-direction, in accordance with some embodiments.
8 is a portion of a transistor structure along the x- and y-directions after forming a source/drain epitaxial stack having a low-melting top layer and a high-melting bottom bottom layer in a recessed portion of a fin, in accordance with some embodiments. it is a cross section
9 is a partial cross-sectional view of a transistor structure along x- and y-directions after forming contacts on a source/drain epitaxial stack having a low-melting top layer and a high-melting bottom layer, in accordance with some embodiments.
10 is a partial cross-sectional view of a transistor structure along the x-direction and the y-direction, in accordance with some embodiments.
11 is a partial cross-sectional view of a recessed fin portion of a transistor structure along an x-direction and a y-direction, in accordance with some embodiments.

The following disclosure provides different embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these descriptions are by way of example only and are not intended to be limiting. For example, formation of a first feature on a second feature in the following description may include embodiments in which the first feature and the second feature are formed in direct contact, and the first feature and the second feature are not in direct contact. Embodiments may also be included in which additional features are formed between the first and second features so as not to

Moreover, spatially relative terms such as "below", "beneath", "below", "above", "above", etc. are used to describe one element(s) or feature(s) relative to another element(s) or feature(s) as shown in the figures. or may be used herein to describe a relationship of features, for ease of explanation. Spatially relative terms are intended to include different orientations of the device in use or operation as well as the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be understood accordingly.

The term "nominal" as used herein refers to a desired or target value of a characteristic or parameter for the operation of a component or process, established during the design phase of a product or process, together with above and/or below this desired value. has a range of values of These ranges of values are generally due to slight variations in manufacturing processes or tolerances.

In some embodiments, the terms “about” and “substantially” can refer to the value of a given quantity that varies within 5% of the value (e.g., ± 1%, ± 2%, ± 3% of the value). , ± 4%, ± 5%) In some embodiments, the terms “about” and “substantially” refer to other values based, for example, on capabilities provided by a manufacturing process, manufacturing operation, or manufacturing tool. indicate

The term "perpendicular" as used herein means nominally perpendicular to the surface of the substrate.

Diffusion is a fundamental property that describes the movement of one material (eg, a dopant) through another material (eg, a semiconductor host). Diffusion occurs from regions of relatively high dopant concentration to regions of low dopant concentration. Different dopant species may have different diffusivities within a semiconductor host material such as silicon (Si), silicon germanium (SiGe), silicon-carbon (SiC) or silicon-phosphorus (SP); The higher the diffusivity, the faster the dopant migrates into the semiconductor host material. Because the rate of diffusion of dopant species in a semiconductor host material increases with temperature, thermal diffusion is a major mechanism used in semiconductor fabrication to move dopant species through the semiconductor lattice. There are two basic methods for providing thermal energy for dopant diffusion: furnace anneal and rapid thermal anneal (RTA).

Furnace annealing is a method of annealing a semiconductor host material (eg, a semiconductor wafer) in a hotwall furnace at, for example, about 800° C. to about 910° C. for a duration of about 30 minutes. However, annealing cycles using these durations and temperatures can cause undesirably extensive (eg, not tightly controlled) dopant diffusion during some integrated circuit fabrication processes (eg, source/drain activation). . Also, furnace annealing applies heat globally rather than locally. That is, during furnace annealing, all layers and/or structures present on the semiconductor material experience elevated temperatures for the duration of the annealing process. This can pose limitations to integrated circuit (IC) manufacturing.

The RTA process is a fast ramp (e.g., in the millisecond (ms) or nanosecond (ns) range) and short dwell time (e.g., in the second or subsecond range) at a target temperature (e.g., above about 910 °C). to anneal the semiconductor material. Also, the RTA can be selective and can provide heat locally or globally. Types of RTA include thermal annealing using a lamp (eg, tungsten halogen lamp) or laser (eg, laser annealing). An RTA using a lamp may be a global anneal since the semiconductor surfaces (eg, top, bottom, or both) are simultaneously exposed to the lamp. On the other hand, laser annealing provides positional accuracy and heat transfer precision due to the beam size (eg, about 25 mm ² to about 100 mm ² ) and precise energy output. Because of these properties, laser annealing is the preferred method for source/drain dopant activation in IC fabrication.

As a non-limiting example, during a laser annealing process, a pulsed laser beam scans a semiconductor surface (eg, the surface of a semiconductor wafer) at a speed of about 100 mm/s. Local annealing may be achieved due to the beam size of the laser (eg, about 25 mm ² to about 100 mm ² ). Annealing depth can be controlled through process conditions such as laser energy or wavelength, number of pulses per site, and residence time of the laser beam (eg, time the laser spends at each site).

However, dopant activation for the source/drain epitaxial layers can be difficult even using a laser annealing process. This is because the source/drain area of the transistor is small compared to the laser beam size. This problem is exacerbated by the size and source/drain regions of the transistors shrinking with each technology generation (eg, with each technology node). For example, as the source/drain region shrinks, heat from the laser beam can diffuse to regions outside the source/drain region, such as a fin region located between the source and drain regions of a transistor. This can be illustrated with Figure 1, which shows a portion along the x-axis of an exemplary array of transistor structures 100 formed on fins 110 and having single crystal source/drain stacks 120 and channel regions 130. it is a cross section A pin 110 is disposed on a substrate 140 . As laser beam 150 begins scanning the surface of substrate 140, the heat generated by laser beam 150 extends out of single crystal source/drain stack 120 (e.g., fins 110 and channels). forming a molten front surface 160 (which extends into region 130). As a result, fin 110 may become deformed, which impairs the electrical characteristics of the transistor. To reduce fin deformation, the laser annealing conditions need to be modified so that the heat generated by the laser beam is reduced and the molten front 160 is better controlled. However, reducing the heat generated by the laser beam may affect the dopant activation process within single crystal source/drain stack 120 . For example, this change will result in less dopant being activated.

To address these challenges, embodiments described herein relate to the formation of a source/drain epitaxial stack having a low-melting “top” layer and a high-melting “bottom” layer. In some embodiments, the low melting point upper layer is polycrystalline or amorphous as deposited, and the high melting point lower layer is monocrystalline as deposited. In other embodiments, both the low-melting top layer and the high-melting bottom layer are monocrystalline or polycrystalline as deposited, but with different stoichiometry. In some embodiments, the as-deposited amorphous low-melting top layer recrystallizes as a result of the laser annealing process and exhibits a higher defect density compared to the high-melting bottom layer. Also, as a result of the laser annealing process, the low-melting top layer exhibits a higher activated dopant concentration compared to the high-melting bottom layer. In some embodiments, only the dopant of the low melting point top layer is activated during the laser annealing process. According to some embodiments, for the source/drain epitaxial stack disclosed herein, a laser beam with reduced power may be used. As a result, fin deformation can be prevented during the laser annealing process.

2 is a cross-sectional view across the x-axis of an exemplary transistor structure 200 formed on semiconductor fin 210 . Note that the length of the pin is parallel to the x-axis shown in FIG. 2 . Semiconductor fin 210 is disposed on semiconductor substrate 220 and is recessed to facilitate formation of source/drain epitaxial stack 230 . Semiconductor fin 210 is laterally isolated from other transistor structures via isolation layer 240 . In some embodiments, each source/drain epitaxial stack 230 includes an as-deposited amorphous low melting point top layer 230A and an as-deposited single crystal high melting point bottom layer 230B. As used herein, an “upper” layer refers to a layer that is located (or disposed) further away from the semiconductor substrate 220 along the z-axis, and a “lower” layer refers to the semiconductor substrate 220 along the z-axis. Refers to a closer positioned (or disposed) layer. Also, as used herein, the term “amorphous” also includes polycrystalline microstructures (eg, microstructures with short-range lattice periodicity).

According to some embodiments, the dopant and semiconductor host material included in the source/drain epitaxial stack 230 are the type of transistor structure 200, for example, the transistor structure 200 is an n-type field effect transistor (n It may be selected based on whether it is a -type field effect transistor (nFET) or a p-type field effect transistor (pFET). In some embodiments, the nFET's source/drain epitaxial stack (eg, n-type source/drain epitaxial stack) is a strained silicon-carbon (SiC) or strained silicon-phosphorus (SiP) doped with phosphorus (P). ) layer, the source/drain epitaxial stack of a p-type field effect transistor (pFET) (e.g., the p-type source/drain epitaxial stack) is made of strained silicon-germanium (SiGe) doped with boron (B). contains a layer According to some embodiments, the amount of P included in the n-type source/drain epitaxial stack may be up to about 1×10 ²¹ atoms/cm ⁻³ , and the amount of B included in the p-type source/drain epitaxial stack may be It may be up to about 1×10 ²¹ atoms/cm ⁻³ . As a non-limiting example, the P and B dopants may be incorporated into the layers of the source/drain epitaxial stack 230 using appropriate precursors during growth. In addition, the amorphous low melting point upper layer 230A and the single crystal high melting point lower layer 230B may be grown to have substantially the same amount of P or B concentration.

In some embodiments, the as-deposited amorphous low melting point upper layer 230A has a melting point of about 1420 K (eg, about 1147 °C), and the single crystalline high melting point lower layer 230B has a melting point of about 1687 K (eg, about 1147 °C). For example, it has a melting point greater than 1414 °C); However, both layers contain the same materials and have substantially the same stoichiometry, eg, substantially the same Si/Ge ratio for a SiGe source/drain epitaxial stack; and substantially the same Si/C ratio for a SiC source/drain epitaxial stack or substantially the same Si/P ratio for a SiP source/drain epitaxial stack. According to some embodiments, the melting point difference between the upper and lower layers in the source/drain epitaxial stack 230 is due to their microstructure (eg, amorphous as opposed to single crystal). In this example, the single crystalline high melting point lower layer 230B has a higher melting point (eg, a difference of about 267 K or about 267 °C) compared to the amorphous low melting point upper layer 230A. However, this is not limiting and a lower melting point difference between the low melting point layer and the high melting point layer (eg, about 200 K or more) may be used. A melting point difference greater than a critical value of about 200 K (e.g., 267 K) ensures that a molten front is “selectively” formed and contained within the amorphous low melting point upper layer 230A by the laser beam during the laser annealing process, whereas , the single crystal refractory lower layer 230B remains solid. If the melting point difference between the aforementioned layers is about 200 K or less, the melting front formed by the laser beam goes beyond the boundary of the amorphous low melting point upper layer 230A, for example, the high melting point lower layer 230B and the fin region. can be extended to As discussed earlier, this is not desirable. Therefore, the heat generated by the laser beam during the laser annealing process raises the temperature of the source/drain epitaxial stack 230 to above the melting point of the amorphous low melting point upper layer 230A and below the melting point of the single crystal high melting point lower layer 230B. As long as it is raised, the aforementioned selectivity can be achieved. In some embodiments, the temperature of the source/drain epitaxial stack 230 during the laser annealing process is above the melting point of the amorphous low melting point top layer 230A and below the melting point of the single crystal high melting point bottom layer 230B (eg For example, the melting point temperature of the amorphous low melting point upper layer ≤ the temperature of the laser annealing process ≤ the melting point temperature of the single crystal high melting point lower layer). In this operating window, a molten region such as the molten front 160 shown in FIG. 1 may be formed within the boundary of the amorphous low melting point upper layer 230A. In some embodiments, the melting point of the amorphous low melting point upper layer 230A is also lower than the melting point of the surrounding material, such as the semiconductor fin 210, about 1687 K for crystalline silicon (e.g., a single crystal high melting point lower layer). close to the melting point of (230B)). Therefore, deformation of the semiconductor fin 210 may be minimized or prevented during the laser annealing process.

Since the formation of the melting front in the amorphous low melting point upper layer 230A requires less heat (eg, due to the melting point of the amorphous layer), the power of the laser beam may be reduced. For example, if the source/drain epitaxial stack includes only a single crystalline layer, such as single crystalline refractory bottom layer 230B, the laser beam forms a molten front and activates a dopant (e.g., B or P); For example, it needs to operate on about 910 lines. At that power level, the laser beam will also generate enough heat to deform the semiconductor fin 210, which has a melting point substantially similar to that of the single crystal layer of the source/drain epitaxial stack. On the other hand, in the case of the source/drain epitaxial stack 230 including an amorphous low melting point upper layer 230A and a single crystal high melting point lower layer 230B in a deposited state, the laser beam generates less heat and consequently more It needs to operate at a lower power setting, eg 500 joules which is reduced by about 50% according to some embodiments.

In some embodiments, amorphous low melting point top layer 230A is grown to account for about 30% to about 75% of the total thickness of source/drain epitaxial stack 230 . In other words, referring to FIG. 2 , the thickness T1 of the amorphous low melting point upper layer 230A in the deposited state is about 30% to about 75% of the total thickness T of the source/drain epitaxial stack 230. (eg, 30% T ≤ T1 ≤ 75% T or 0.30 ≤ T1/T ≤ 0.75). In some embodiments, the single crystalline refractory lower layer 230B serves as a diffusion barrier for the dopant of the amorphous refractory upper layer 230A during the laser annealing process. This is because a molten front is not formed in the single crystalline lower melting point layer 230B, so that dopants that diffuse from the amorphous lower melting point upper layer 230A into the single crystalline lower melting point layer 230B are slowed down (e.g., blocked). Because. Single crystal high The lower melting point layer 230B will not be thick enough to block the diffusion of dopants from the amorphous lower melting point upper layer 230A. As a result, less dopant is activated in the amorphous low melting point upper layer 230A, which in turn can increase the resistance of the source/drain epitaxial stack 230 . Further, dopant diffusion may form an undesirable leakage path between the source/drain epitaxial stack 230 and the semiconductor fin 210 and/or the doped region of the semiconductor substrate 220 . Additionally, the thicker amorphous low melting point top layer 230A may require longer residence time and/or higher power settings for the laser beam during the laser annealing process, both of which adversely affect processing time and cost. can give On the other hand, if the thickness T1 of the amorphous low-melting-point top layer 230A is less than about 30% of the total thickness T (eg, T1/T > 30%), the amount of dopant activated in the top layer is This may be insufficient to provide an acceptable resistance to the drain epitaxial stack 230.

In some embodiments, the microstructure and consequently the melting point of the amorphous low-melting-point upper layer 230A and the single-crystalline high-melting-point lower layer 230B in the deposited state may be adjusted through respective growth conditions such as growth temperature and pressure. . For example, according to some embodiments, the single crystal refractory lower layer 230B may be grown at a temperature of about 650 °C to about 800 °C and a pressure of about 20 Torr to about 300 Torr. In contrast, the amorphous low melting point upper layer 230A may be grown at a temperature of about 450 °C to about 600 °C and a pressure of about 300 Torr to about 400 Torr. In other words, monocrystalline layers can be grown epitaxially at “higher” temperatures and “lower” pressures compared to amorphous epitaxial layers that can be grown at “lower” temperatures and “higher” pressures. In some embodiments, the aforementioned conditions apply equally to the growth of p-type (eg, B-doped SiGe) and n-type (eg, P-doped SiC and SiP) source/drain epitaxial layers. can

In some embodiments, the monocrystalline refractory lower layer 230B and the amorphous lower melting point upper layer 230A are grown in situ within the same processing reactor (eg, without the use of a vacuum crusher). For example, a rapid process temperature change can be achieved (eg, within about 10 seconds to about 20 seconds) using a heat lamp. In some embodiments, the single crystalline high melting point bottom layer 230B and the amorphous low melting point top layer 230A are grown by a chemical vapor deposition (CVD) process.

In some embodiments, the amorphous low melting point upper layer 230A may be formed by a pre-amorphization implant (PAI) process. For example, the source/drain epitaxial stack 230 may initially include only a single crystalline layer, such as the single crystalline refractory lower layer 230B shown in FIG. 2, and has a total thickness T. The PAI process using implantation consumes a portion of the monocrystalline layer and converts it to an amorphous layer through implantation ion bombardment. The type of implantation, amount of implantation, and implantation energy are parameters that can be used to fine-tune the thickness of the amorphous layer.

In some embodiments, a Ge or tin (Sn) implant may be used in a SiGe source/drain epitaxial stack, and a Si implant may be used in a SiC or SiP source/drain epitaxial stack. As a non-limiting example, an amorphous low-melting top having a thickness T1 of Ge or Sn capacity of about 1×10 ¹⁴ cm ⁻² to about 5×10 ¹⁴ cm ⁻² at an accelerating voltage of about 3 keV to about 20 keV. may be used to form layer 230A. To form an amorphous low melting point upper layer 230A having a thickness T1 of a Si capacity of about 1×10 ¹⁵ cm ⁻² to about 5×10 ¹⁵ cm ⁻² at an accelerating voltage of about 1 keV to about 5 keV. can be used In some embodiments, when the PAI method is used to form the amorphous low-melting upper layer 230A, the amorphous lower-melting upper layer 230A and the single crystalline lower melting-point layer 230B are different from Si/Ge and Si/ It can have a C or Si/P ratio.

After formation of the amorphous low-melting top layer 230A, the source/drain epitaxial stack 230 is applied to a laser beam via, for example, a scanning laser beam 250 to activate dopants in the amorphous low-melting top layer 230A. undergo an annealing process. As discussed above, the amorphous low-melting top layer 230A has a low melting point (eg, less than about 200 K) compared to the single-crystalline high-melting bottom layer 230B. Also, the power of the laser beam 250 is adjusted based on the melting point difference between the two layers so that a molten front is selectively formed on the amorphous low melting point upper layer 230A, while the single crystal lower layer remains solid. In some embodiments, the laser beam 250 has a wavelength of about 308 nm to about 532 nm and an annealing depth of about 7 nm to about 1200 nm (eg, as measured from the top surface of the amorphous low melting point top layer 230A). have) In some embodiments, the annealing depth corresponds to the thickness T1 of the amorphous upper layer 230A. As discussed above, the laser beam 250 covers an area of about 25 mm ² to about 100 mm ² (eg, an area of about 25 mm ² to about 30 mm ² ) and has a speed of about 100 mm/s. has a scanning speed. Further, the laser beam 250 is pulsed about 1 to 10 times per site, with each pulse having a duration of about 20 ns to 150 ns. As a non-limiting example, the annealing process may be performed in a nitrogen or other inert gas atmosphere (eg, argon, helium, xenon, etc.).

The above-mentioned laser beam characteristics are not designed to be limited, and include (i) the thickness of the amorphous low-melting-point upper layer 230A and the single-crystal high-melting-point lower layer 230B; and (ii) a difference in melting point between the amorphous low-melting-point upper layer 230A and the single-crystalline high-melting-point lower layer 230B. As a non-limiting example, for a thicker amorphous low melting point top layer 230A (eg, when T/T is close to about 0.75), longer pulses with an increased number of pulses (eg, 10) Duration times (eg, about 150 ns) may be used to achieve higher annealing depths (eg, 1200 nm); For shallower annealing depths (eg, about 7 nm), fewer and/or shorter pulses may be used.

The wavelength of the beam may also be based on other laser beam considerations (eg, pulse number, pulse duration, scanning speed, etc.) and layer properties (eg, thickness and melting point of amorphous low melting point top layer 230A). It can be adjusted to achieve the desired heat output. For example, assuming all other laser beam characteristics are the same, the thin amorphous low melting point top layer 230A has a short wavelength (e.g., about 300 nm) having a low absorption depth (e.g., about 10 nm). A laser beam may be used, and a laser beam having a long wavelength (eg, about 500 nm) having a deep absorption depth (eg, about 100 nm) may be used for the thick amorphous low-melting-point upper layer 230A. In both conditions, the laser power is substantially the same and may range, for example, between about 200 and 400 joules.

In some embodiments, the laser annealing process described above activates a dopant (eg, B or P) in amorphous low melting point upper layer 230A. The activated carrier concentration in the upper layer of the source/drain epitaxial stack 230 is from about 1×10 ²⁰ cm ^-3 to about 1 for both p-type and n-type stacks (eg, SiGe, SiC or SiP). It may be in the range of ×10 ²¹ cm ^-3 . In some embodiments, the dopant activation process is performed primarily in the refractory upper layer (eg, amorphous reflux upper layer 230A) and partially in the single crystalline reflux lower layer (eg, single crystalline reflux upper layer 230B). )) occurs in In some embodiments, the low-melting top layer can result in an activated carrier concentration substantially equal to the chemical dopant concentration (eg, about 100% activation rate), and the high-melting bottom layer to activate less than the chemical dopant concentration. carrier concentrations (eg less than 100% activation rate). For example, in the aforementioned case, the low-melting top layer 230A can generate an activated carrier concentration of up to about 1×10 ²¹ cm ^-3 , while the high-melting bottom layer 230B can generate up to about 1 may be limited to an activated carrier concentration of ×10 ²⁰ cm ⁻³ . Thus, in some embodiments, even if dopant activation occurs throughout the source/drain epitaxial stack 230 (eg, in both the low-melting layer and the high-melting layer), the low-melting top layer 230A has a high This will result in a higher activated dopant concentration (eg, about 10 times higher) compared to the submelting layer 230B.

In some embodiments, dopant diffusion outside the source/drain epitaxial stack can be prevented as shown in Figure 3, which is a secondary ion mass spectrometry (SIMS) profile denoted by curve 300, curve It overlaps with the diffusion resistance profile (SRP) denoted by (310). The y-axis of FIG. 3 is on a logarithmic scale and represents concentrations of dopants and activated dopants (eg, carriers). The x-axis represents depth within the source/drain epitaxial stack 230 . For example, the origin of the x-y plot in FIG. 3 corresponds to the top surface of the source/drain epitaxial stack 230 . In some embodiments, profiles 300 and 310 respectively represent dopant and carrier concentrations along line A-B shown in FIG. 2 after an annealing process. More specifically, the SIMS curve 300 corresponds to the total dopant concentration (eg, B or P) across the source/drain epitaxial stack 230, and the SRP curve 310 corresponds to the source/drain epitaxial stack ( 230) corresponds to the activated dopant concentration. As shown in FIG. 3 , all profiles 300 and 310 show a sharp decrease in dopant and carrier concentration near the interface with the semiconductor fin 210 . In some embodiments, slope 320 is about 2.6 nm/decade, demonstrating that the carrier and dopant concentrations of source/drain epitaxial stack 230 do not diffuse into semiconductor fin 210 .

In some embodiments, the as-deposited amorphous low melting point upper layer 230A recrystallizes as it cools after the laser annealing process. For example, the amorphous low melting point upper layer 230A may be converted into a single crystalline layer. FIG. 4 shows source/drain epitaxial stack 230 after the laser annealing process described in FIG. is converted to In some embodiments, the monocrystalline upper layer 400 has substantially the same thickness T1 as the as-deposited amorphous low melting point upper layer 230A shown in FIG. 2 . In addition, the thickness T of the source/drain epitaxial stack 230 is substantially the same before and after the laser annealing process.

In some embodiments, interface 410 (eg, the interface between upper and lower single crystal layers 400 and 230B of the laser annealed source/drain epitaxial stack) has a rough (eg, coarse) surface topography. , which can be detected by transmission electron microscopy (TEM) imaging. In some embodiments, interface 410 also appears rougher (eg, coarser) compared to top surface 420 of monocrystalline top layer 400 , which can also be detected by TEM imaging. In some embodiments, the top surface roughness of the low melting point top layer 230A is reduced by about 6 times after the laser annealing process. For example, the root mean square (RMS) top surface roughness of the low-melting top layer 230A may be about 3 nm, and the RMS top surface roughness of the monocrystalline top layer 400 (eg, the annealed top layer 230A) The surface roughness may be about 0.5 nm. In addition, the laser annealed single crystal upper layer 400 has a higher defect density (eg, number of dislocations per unit area) compared to the single crystal refractory lower layer 230B. This is due to the recrystallization process that the laser annealed single crystal top layer 400 undergoes when it is converted from an amorphous or polycrystalline layer to a single crystal layer. For example, single crystalline top layer 400 may have about 1×10 ¹⁸ dislocation/cm ² , while single crystalline refractory bottom layer 230B has about 1×10 ¹⁶ dislocation/cm ² , eg, unit It can have about two orders of magnitude less potential per area. In some embodiments, due to the difference in defect density between the two layers in the source/drain epitaxial stack 230, the laser annealed upper single crystalline layer 400 develops a compressive strain, while the single crystalline lower melting point layer 230B ) produces less tensile strain or compressive strain than the laser annealed single crystal top layer 400. In other words, the type or amount of strain between the laser annealed upper single crystal layer 400 and the single crystal lower melting point layer 230B may be different.

In some embodiments, the lower melting point layer may include a different material than the lower melting point layer, or may include the same material but with a different stoichiometry. Also, both the low-melting-point upper layer and the high-melting-point lower layer may be single-crystal layers. As a non-limiting example, for a p-type source/drain epitaxial stack, the low-melting top layer may include single crystal SiGe with a Ge concentration of about 20% to about 40%, while the high-melting bottom layer may have a notable It may contain single crystal Si with no positive Ge. In some embodiments, the inclusion of Ge in Si reduces the melting point of the resulting SiGe layer. For example, a SiGe layer with about 40% Ge has a lower melting point than a SiGe layer with about 20% Ge, and a SiGe layer with about 20% Ge has a lower melting point than Si that does not contain appreciable amounts of Ge.

For an n-type source/drain epitaxial stack, the low-melting top layer may include a single-crystal SiC layer with a low carbon concentration, while the high-melting bottom layer may include a single-crystal SiC layer with a high carbon concentration; According to some embodiments herein, the difference between the low carbon concentration and the high carbon concentration is about 2%.

In some embodiments, each of the aforementioned layers is grown by CVD at a temperature ranging from about 650 °C to about 800 °C, and at a pressure of about 20 Torr to about 300 Torr. According to some embodiments, a process temperature of greater than about 650° C. and a process pressure of less than about 300 Torr is required for growth of the single crystal refractory layer and the low melting point layer. As a result of the laser annealing process, both the low-melting top layer and the high-melting bottom layer can undergo the same type of strain (eg, compression or tension), and the activated dopant concentration in the single-crystal top layer is will be larger than that of the floor. In some embodiments, the strain gain after annealing for compressive type stress is about 0.8 GPa.

In other embodiments, the lower melting point layer may include a different material than the lower melting point layer, or the same material but with a different stoichiometry. Further, both the low-melting top layer and the high-melting bottom layer can be polycrystalline or amorphous layers with suitably tuned melting points (eg, with a melting point difference of at least 200 K). As a non-limiting example, for a p-type source/drain epitaxial stack, the low-melting top layer may include polycrystalline or amorphous SiGe with a Ge concentration of about 20% to about 40%, while the high-melting bottom layer is It may contain polycrystalline or amorphous Si without appreciable amounts of Ge. In some embodiments, the inclusion of Ge in the Si reduces the melting point of the resulting SiGe layer as discussed above. For example, the melting point of an amorphous Si layer is about 1420 K, while the melting point of an amorphous Ge layer is about 965 K to 1024 K. Thus, by introducing Ge into the amorphous Si layer and controlling the Ge concentration, the melting point of the resulting layer can be tuned to be higher than about 965 K and lower than about 1420 K. Consequently, the concentration of Ge in the Si layer can be adjusted to achieve a desired melting temperature differential of about 200 K or greater, as discussed above.

For an n-type source/drain epitaxial stack, the low-melting top layer may include a polycrystalline or amorphous SiC layer with a low carbon concentration, while the high-melting bottom layer includes a polycrystalline or amorphous SiC layer with a high carbon concentration. It may be, wherein according to some embodiments, the difference between the low carbon concentration and the high carbon concentration is about 2%. In some embodiments, a carbon concentration offset of about 2% is sufficient to achieve a melting point difference of about 200 K or greater.

In some embodiments, the aforementioned layers are grown by CVD at a temperature ranging from about 450 °C to about 600 °C, and at a pressure of about 300 Torr to about 400 Torr. According to some embodiments, a process temperature of about 600° C. or less and a process pressure of about 300 Torr or more are required for growth of the polycrystalline or amorphous high-melting point layer and low-melting point layer. As a result of the laser annealing process, both the low-melting top layer and the high-melting bottom layer will develop the same type of strain (eg, compression), and the activated dopant concentration in the top layer will be higher than that in the bottom layer. will be big In some embodiments, the low-melting top layer exhibits an activation rate of about 100%, eg all dopants in the top layer are activated (eg, about 1×10 ²¹ cm ⁻³ ). In comparison, the lower melting point layer may exhibit an activation rate of about 10%.

In some embodiments, any permutation of polycrystalline or amorphous and monocrystalline layers can be used for the top and bottom layers of the source/drain epitaxial stack, as long as the top layer has a lower melting point than the bottom layer, for example, As long as the melting point difference between the lower and upper layers is at least about 200 K, it is within the spirit and scope of the present disclosure. Additionally, the low-melting top layer has about 30% to about 75% of the total thickness of the source/drain epitaxial stack.

5 is a flow diagram of an example method 500 for fabrication of a source/drain epitaxial stack having a low-melting top layer and a high-melting bottom layer, in accordance with some embodiments. Other fabrication operations may be performed between the various operations of method 500 and may be omitted for clarity. Further, the fabrication operations of method 500 are not unique, and alternative operations may be performed in lieu of those of method 500. Embodiments of this disclosure are not limited to method 500 . An exemplary method 500 will be described with respect to FIGS. 6-11 .

Method 500 begins with operation 510 of forming a gate structure on a fin disposed on a substrate. 6 shows cross-sectional views of the resulting structure along the x axis (x cut) and y axis (y cut). The x-axis direction corresponds to the pin's length, and the y-axis direction corresponds to the pin's width. For example, a y-cut view is created by viewing a structure along line A-B of the x-cut in the y-axis direction, and an x-cut view is created by viewing a structure along line C-D of the y-cut in the direction of the x-axis. According to operation 510 , a fin 600 is formed on a substrate 610 . In some embodiments, both fin 600 and substrate 610 include one or more semiconductor materials. For example, fin 600 and substrate 610 may include a basic semiconductor material such as Si or Ge or a semiconductor compound such as SiGe. In addition, the fin 600 and the substrate 610 may include doped regions not shown in FIG. 6 . A dielectric layer 620, such as silicon oxide, isolates fin 600 from adjacent fins. In some embodiments, dielectric layer 620 may be an isolation structure such as a shallow trench isolation (STI) structure.

A gate structure 630 is formed on and around the fin 600 such that the gate structure 630 is not covered by the dielectric layer 620, as shown by the x-cut and y-cut cross-sectional views of FIG. "surrounds" a portion of the pin 600 that is not present. Gate structure 630 includes a sacrificial gate electrode 630A, a sacrificial gate dielectric 630B and one or more spacer layers 630C, in accordance with some embodiments. In some embodiments, the sacrificial gate electrode 630A includes polysilicon and the sacrificial gate dielectric includes silicon oxide. Also, one or more spacer layers 630C may include a nitride such as silicon nitride. According to some embodiments, sacrificial gate electrode 630A and sacrificial gate dielectric 630B form a sacrificial gate stack that can be replaced with a metal gate stack in a subsequent operation.

Referring to FIG. 5 , method 500 continues with operation 520 where a portion of pin 600 is recessed. According to some embodiments, recessing fin 600 facilitates formation of a source/drain epitaxial stack in a subsequent operation (eg, in operation 530 of method 500 ). As a non-limiting example, cut x in FIG. 7 shows the resulting structure after the recess process of operation 520 . In some embodiments, a portion of fin 600 is recessed to form a recessed fin portion 700 . The recessed fin portion 700 is positioned adjacent to the spacer layer 630C of the gate structure 630 . As a non-limiting example, the recessed fin portion 700 may be formed by masking the portion of the fin 600 to be protected and etching the remaining portion of the fin 600 (eg, the exposed portion). Masking may be accomplished with a hard mask layer such as an oxide layer or a nitride layer, a photoresist layer, or a combination thereof. The etching process may include an etchant such as chlorine (Cl ₂ ), hydrogen bromide (HBr), tetrafluoromethane (CF ₄ ), or a combination thereof. In some embodiments, any portion of fin 600 not covered by gate structure 630 is recessed during operation 520 as shown in the x-cut in FIG. 11 . The y-cut view of FIG. 7 shows the resulting structure along line EF of the x-cut in the y-direction. In the y-cut view, both the recessed (eg 700) and non-recessed parts (eg 600) of the pin are visible.

Referring to FIG. 5 , method 500 continues with operation 530 of forming a source/drain epitaxial stack having a low-melting top layer and a high-melting bottom bottom layer on recessed fin portion 700 . As discussed above, in some embodiments, the low-melting upper layer and the higher-melting lower layer include materials having substantially similar stoichiometry but different microstructures. For example, the lower melting point layer is amorphous and the lower melting point layer is monocrystalline. In this case, the melting point difference between the two layers is due to the different microstructures of the two layers. In some embodiments, the low-melting top layer and high-melting bottom layer include materials with different stoichiometry but substantially similar microstructures. For example, both the low-melting top layer and the high-melting bottom layer are monocrystalline layers or polycrystalline layers or amorphous layers. In this case, the difference in melting point between the two layers is due to the different stoichiometry of the two layers. In some embodiments, the melting point difference between the high melting point lower layer and the lower melting point layer is greater than about 200 K. In some embodiments, the low-melting top layer has a lower melting point than the surrounding structure, such as fin 600 . In some embodiments, fin 600 and the refractory underlying layer have substantially similar melting points.

As a non-limiting example, FIG. 8 shows an x-cut view and a y-cut view of the resulting structure after forming the source/drain epitaxial stack 800 . The y-cut view of FIG. 8 shows the resulting structure along line E-F of the x-cut in the y-direction, and the x-cut view of FIG. 8 shows the resulting structure along line C-D of the y-cut in the x-direction. In some embodiments, the source/drain epitaxial stack 800 has a diamond shape as shown in the y-cut of FIG. 8 . The source/drain epitaxial stack 800 includes a low melting point upper layer 810 and a high melting point lower layer 820 . In some embodiments, the refractory lower layer may include an additional epitaxial layer not shown in the diagram of FIG. 8 for simplicity. As a non-limiting example, the low-melting top layer 810 and high-melting bottom layer 820 are grown by a CVD process at a temperature range of 450 °C to 800 °C and a process pressure of about 20 Torr to about 400 Torr. In some embodiments, a combination of a low temperature range (eg, about 450 °C to about 600 °C) and a high pressure range (eg, about 300 Torr to about 400 Torr) produces an amorphous or polycrystalline layer, while a high temperature range The combination of the range (about 600° C. to about 800° C.) and the low pressure range (eg, about 20 Torr to about 300 Torr) produces a single crystal layer. In some embodiments, the thickness ratio between the low-melting top layer 810 and the source/drain epitaxial stack 800 is between about 0.3 and about 0.75 (eg, 0.30 ≤ T1/T ≤ 0.75). In some embodiments, the laser annealing process does not change the thickness of the low melting point top layer 810 and the high melting point bottom layer 820 .

In some embodiments, the source/drain epitaxial stack 800 may be a B doped SiGe stack, a P doped SiC stack, or a P doped SiP stack having a Ge concentration of about 20% to about 40%. In some embodiments, the dopant concentration of the lower melting point layer 810 is substantially similar to the dopant concentration of the lower melting point layer 820 (eg, about 1×10 ²¹ cm ⁻³ ).

5 and 8 , the method 500 continues with operation 540 where the laser annealing process anneals the source/drain epitaxial stack 800 to activate dopants. In some embodiments, a molten front is selectively formed in low-melting top layer 810 by passing laser beam 830 . As a result of this process, the low-melting top layer 810 can attain an activated dopant concentration of about 1×10 ²¹ cm ⁻³ (eg, about 100% activation rate). In some embodiments, as a result of the laser annealing process, the high-melting bottom layer 820 has a lower activated dopant concentration than the low-melting top layer 810 (eg, an activation rate of about 10%). For example, the activated dopant concentration of the refractory lower layer 820 may range from about 3×10 ¹⁸ cm ⁻³ to about 1×10 ²⁰ cm ⁻³ . In some embodiments, diffusion of the dopant outside the source/drain epitaxial stack is prevented as discussed above with respect to FIG. 3 .

In some embodiments, when the low-melting upper layer 810 is an amorphous layer in an as-deposited state, the laser annealing process recrystallizes the low-melting upper layer 810 . In addition, the recrystallized low-melting upper layer has a higher defect density (eg, about two orders of magnitude higher) than the high-melting lower layer 820 . In some embodiments, the interface between the lower melting point layer 810 and the lower melting point layer 820 has a rough (eg, non-planar or coarse) surface topography visible via TEM imaging. In some embodiments, the recrystallized low-melting top layer develops compressive strain, while the high-melting bottom layer 820 has less compressive strain compared to the tensile strain or recrystallized low-melting top layer.

Referring to FIG. 5 , method 500 completes with operation 550 of forming contacts on source/drain epitaxial stack 800 . As a non-limiting example, a contact may be formed as follows. Referring to FIG. 9 , dielectric layer 900 is deposited on dielectric layer 620 , and then a top surface of dielectric layer 900 is polished to be substantially coplanar with a top surface of gate structure 630 . In some embodiments, sacrificial gate electrode 630A and sacrificial gate dielectric 630B are replaced with metal gate electrode stack 910 and gate dielectric stack 920, respectively. In some embodiments, the gate electrode stack 910 may include a work function layer (eg, one or more titanium nitride layers), a barrier layer (eg, a tantalum nitride layer), a metal fill layer (eg, tungsten metal fill). , which are not shown in FIG. 9 for simplicity. In some embodiments, gate dielectric stack 920 includes an interfacial dielectric layer (eg, silicon oxide) and a high-k dielectric layer having a dielectric constant greater than about 3.9 (eg, hafnium oxide), both All are not shown in FIG. 9 for simplicity.

In some embodiments, a contact opening is formed in the dielectric layer 900 to expose the laser annealed low melting point top layer 810 . When the laser annealed low-melting upper layer 810 is exposed, a silicide 930 may be formed on the upper surface of the laser annealed low-melting upper layer 810 . In some embodiments, silicide 930 includes titanium, platinum, nickel, any other suitable metal or combination thereof. In some embodiments, a portion of the laser annealed low melting point top layer 810 is consumed to form silicide 930 . The contact opening is then coated with a liner layer such as titanium nitride. The liner layer is not shown in FIG. 9 for simplicity. The liner layer functions as a barrier layer and adhesion to the metal fill 940 . In some embodiments, metal fill 940 and liner layer (not shown in FIG. 10 ) are planarized to remove deposited material from the top surface of dielectric layer 900 and form contact 950 .

In some embodiments, method 500 may be applied to a transistor structure different from that shown in FIGS. 6-9. For example, referring to FIG. 6 , dielectric layer 620 may be grown so that its top surface is flush with the top surface of gate structure 630 , as shown in the x-cut of FIG. 10 . In some embodiments, the transistor structure shown in FIG. 10 may be a variation of the transistor structure shown in FIG. 6 . In the transistor structure of FIG. 10 , dielectric layer 620 may cover sidewalls and top surfaces of fin 600 and spacer layer 630C of gate structure 630 . In this exemplary transistor structure, fin 600 is recessed according to operation 520 of FIG. 5 between gate structure 630 and dielectric layer 620 as shown in cut x in FIG. 11 . For example, openings in dielectric layer 620 may be formed on both sides of gate stack 630 to expose portions of fin 600 that are not covered by gate stack 630 . The y-cut in FIG. 11 shows a view of the structure along line E-F of the x-cut in FIG. 11 . As a non-limiting example, this can be accomplished with a photolithography and etching operation. Pin 600 may then be recessed as described in FIG. 7 . Other operations of method 500 (eg, 530-550) are performed without modification.

Embodiments described herein relate to the formation of a source/drain epitaxial stack having a low-melting top layer and a high-melting bottom layer. In some embodiments, the low-melting top layer and high-melting bottom layer include materials with substantially similar stoichiometry but different microstructures. For example, the lower melting point layer may be amorphous and the lower melting point layer may be monocrystalline. In this case, the melting point difference between the two layers is due to the different microstructures between the two layers. In other embodiments, the lower melting point layer and the lower melting point layer include materials having different stoichiometry but substantially similar microstructures. For example, both the low-melting top layer and the high-melting bottom layer can be monocrystalline layers or polycrystalline layers or amorphous layers. In this case, the difference in melting point between the two layers is due to the different stoichiometry between the two layers. According to some embodiments, the melting point difference between the high-melting bottom layer and the low-melting top layer, regardless of their origin (eg, microstructure or stoichiometry), is greater than 200 K. In some embodiments, after the laser annealing process, the low-melting top layer and high-melting bottom layer can have different strain types and/or different strain sizes. In some embodiments, a combination of low growth temperature (eg, about 450 °C to about 600 °C) and high growth pressure (eg, about 300 Torr to about 400 Torr) produces an amorphous or polycrystalline layer, while , the combination of a high growth temperature (about 600 °C to about 800 °C) and a low growth pressure (eg, about 20 Torr to about 300 Torr) produces a single crystal layer. According to some embodiments, the thickness ratio between the low-melting top layer and the source/drain epitaxial stack is between about 0.3 and 0.75 (eg, 0.3 < thickness ratio < 0.75). In some embodiments, the laser annealing process does not substantially change the thickness of the low-melting top layer and high-melting bottom layer. In some embodiments, since the low melting point upper layer has a lower melting point than a surrounding structure such as a semiconductor fin or a semiconductor substrate, deformation of the fin may be prevented during the laser annealing process. In some embodiments, the as-deposited amorphous low-melting top layer recrystallizes as a result of the laser annealing process, resulting in a higher defect density compared to the high-melting bottom layer. Also, as a result of the laser annealing process, the low-melting top layer exhibits a higher activated dopant concentration than the high-melting bottom layer.

In some embodiments, the semiconductor structure includes a fin disposed on a substrate, and the fin and the substrate include a semiconductor material. The semiconductor structure further includes a gate structure disposed on the fin, the gate structure surrounding a portion of a sidewall surface of the fin. In addition, the semiconductor structure may include a recess formed in a portion of the fin and adjacent to the gate structure; and a source/drain epitaxial stack disposed within the recess, the source/drain epitaxial stack having a lower layer and an upper layer having a higher activated dopant concentration than the lower layer. Finally, a semiconductor structure is disposed on the upper layer of the source/drain epitaxial stack and includes a contact adjacent to the gate structure.

In some embodiments, a method includes forming a fin on a substrate; forming a sacrificial gate structure on the fin surrounding a portion of a top surface of the fin and a portion of a sidewall surface of the fin; recessing a portion of the fin not covered by the sacrificial gate structure; Forming a source/drain epitaxial stack in the recessed portion of the fin, wherein forming the source/drain epitaxial stack includes growing an underlying layer having a crystalline microstructure and an amorphous microstructure on the underlying layer. growing a top layer having a structure, wherein the top layer has a different melting point than the bottom layer. The method further includes annealing the source/drain epitaxial stack with a laser to form a molten front in the top layer.

In some embodiments, a method includes forming a fin on a substrate and forming a gate structure on the fin. The method further includes recessing a portion of the fin not covered by the gate structure, and forming a source/drain epitaxial stack on the recessed portion of the fin; Forming the source/drain epitaxial stack includes depositing a first layer having a first dopant and depositing a second layer having a second dopant, wherein the second layer is over the first layer. and has a lower melting point than the first layer. The method also includes exposing the source/drain epitaxial stack to an anneal source to activate the first and second dopants in the first layer and the second layer.

1) A semiconductor structure according to an embodiment of the present disclosure includes a fin disposed on a substrate, wherein the fin and the substrate include a semiconductor material; a gate structure disposed on the fin, the gate structure surrounding a portion of a sidewall surface of the fin; a recess formed in a portion of the fin adjacent to the gate structure; a source/drain epitaxial stack disposed within the recess, comprising: a bottom layer; and an upper layer having a higher activated dopant concentration than the lower layer; and a contact disposed on the upper layer of the source/drain epitaxial stack and adjacent to the gate structure.

2) In the semiconductor structure according to an embodiment of the present disclosure, the upper layer has an activated dopant concentration of about 100%, and the lower layer has an activated dopant concentration of about 10%.

3) In the semiconductor structure according to the embodiment of the present disclosure, the upper layer has a defect density two orders of magnitude higher than that of the lower layer.

4) In the semiconductor structure according to an embodiment of the present disclosure, the thickness of the upper layer is about 30% to about 75% of the thickness of the source/drain epitaxial stack.

5) In the semiconductor structure according to the embodiment of the present disclosure, the upper layer induces a higher compressive stress to the pin than the lower layer.

6) In the semiconductor structure according to an embodiment of the present disclosure, the upper layer has an activated dopant concentration of about 1×10 ²¹ cm ⁻³ .

7) In the semiconductor structure according to an embodiment of the present disclosure, each of the lower layer and the upper layer includes boron-doped silicon-germanium, phosphorus-doped silicon-carbon, or phosphorus-doped silicon-phosphorus.

8) A method according to another embodiment of the present disclosure includes forming fins on a substrate; forming a sacrificial gate structure on the fin, the sacrificial gate structure surrounding a portion of a top surface of the fin and a portion of a sidewall surface of the fin; recessing a portion of the fin not covered by the sacrificial gate structure; forming a source/drain epitaxial stack in the recessed portion of the fin, wherein forming the source/drain epitaxial stack comprises: growing an underlying layer having a crystalline microstructure; and growing an upper layer having an amorphous microstructure on the lower layer, wherein the upper layer has a different melting point than the lower layer; and annealing the source/drain epitaxial stack with a laser to form a molten front surface in the top layer.

9) In the method according to another embodiment of the present disclosure, the annealing step includes recrystallizing the upper layer.

10) In the method according to another embodiment of the present disclosure, after the annealing step, the upper layer has about two orders of magnitude more defects per unit area than the lower layer.

11) In the method according to another embodiment of the present disclosure, after the annealing step, the upper layer has a higher compressive stress than the lower layer.

12) In a method according to another embodiment of the present disclosure, growing the upper layer includes growing the upper layer to a thickness of 30% to 75% of the thickness of the source/drain epitaxial stack. do.

13) In a method according to another embodiment of the present disclosure, growing the lower layer and the upper layer includes obtaining a melting point difference between the lower layer and the upper layer greater than about 200 K. .

14) In the method according to another embodiment of the present disclosure, the step of annealing the source/drain epitaxial stack includes converting an amorphous microstructure of the upper layer into a crystalline microstructure.

15) In a method according to another embodiment of the present disclosure, annealing the source/drain epitaxial stack includes converting the upper layer into a crystalline layer having a higher defect density per unit area than the lower layer. do.

16) In a method according to another embodiment of the present disclosure, annealing the source/drain epitaxial stack includes converting the upper layer to a crystalline layer having a higher activated dopant concentration than the lower layer. do.

17) A method according to another embodiment of the present disclosure includes forming fins on a substrate; forming a gate structure on the fin; recessing a portion of the fin not covered by the gate structure; and forming a source/drain epitaxial stack on the recessed portion of the fin, wherein forming the source/drain epitaxial stack comprises: depositing a first layer comprising a first dopant; and depositing a second layer comprising a second dopant, wherein the second layer is disposed on the first layer and has a lower melting point than the first layer. forming a; and exposing the source/drain epitaxial stack to an annealing source to activate the first dopant and the second dopant in the first layer and the second layer.

18) In the method according to another embodiment of the present disclosure, exposing the source/drain epitaxial stack to an annealing source comprises activating the second dopant in the second layer and in the first layer and activating a portion of the first dopant.

19) In the method according to another embodiment of the present disclosure, the forming of the first layer and the second layer may include the first layer and the second layer having substantially similar microstructures and substantially different stoichiometry. Forming the second layer.

20) In the method according to another embodiment of the present disclosure, the forming of the first layer and the second layer may include the first layer and the second layer having substantially different microstructures and substantially similar stoichiometry. Forming the second layer.

It should be understood that the Detailed Description section, rather than the Summary section of this disclosure, is used to interpret the claims. The summary section of this disclosure may present one or more embodiments, but not all possible embodiments of this disclosure as contemplated by the inventor(s), and is therefore not intended to limit the subclaims in any way.

The foregoing disclosure has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art will realize that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. will know Those skilled in the art also know that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications can be made by those skilled in the art in the present invention without departing from the spirit and scope of the present disclosure. You have to realize that you can do it.

Claims (10)

in the method,
forming fins on the substrate;
forming a sacrificial gate structure on the fin, the sacrificial gate structure surrounding a portion of a top surface of the fin and a portion of a sidewall surface of the fin;
recessing a portion of the fin not covered by the sacrificial gate structure;
forming a source/drain epitaxial stack within the recessed portion of the fin, wherein forming the source/drain epitaxial stack comprises:
growing an underlying layer having a crystalline microstructure at a temperature of 650° C. to 800° C. and a pressure of 20 Torr to 300 Torr; and
growing an upper layer having an amorphous microstructure on the lower layer at a temperature of 450 ° C to 600 ° C and a pressure of 300 Torr to 400 Torr;
wherein the upper layer has a lower melting point than the lower layer, and wherein the upper layer and the lower layer include materials having the same stoichiometry and different microstructures. forming; and
annealing the source/drain epitaxial stack with a laser to form a molten front in the top layer;
To include, the method. According to claim 1,
Wherein the step of annealing comprises recrystallizing the top layer. According to claim 1,
and wherein after the step of annealing, the top layer has two orders of magnitude more defects per unit area than the bottom layer. According to claim 1,
and wherein after the step of annealing, the top layer has a higher compressive stress than the bottom layer. According to claim 1,
Wherein growing the top layer comprises growing the top layer to a thickness of 30% to 75% of a thickness of the source/drain epitaxial stack. According to claim 1,
Wherein growing the bottom layer and the top layer comprises obtaining a melting point difference between the bottom layer and the top layer greater than 200 K. According to claim 1,
and wherein annealing the source/drain epitaxial stack comprises converting an amorphous microstructure of the top layer to a crystalline microstructure. According to claim 1,
wherein annealing the source/drain epitaxial stack comprises converting the upper layer to a crystalline layer having a higher defect density per unit area than the lower layer. According to claim 1,
wherein annealing the source/drain epitaxial stack comprises converting the upper layer to a crystalline layer having a higher activated dopant concentration than the lower layer. in the method,
forming fins on the substrate;
forming a gate structure on the fin;
recessing a portion of the fin not covered by the gate structure; and
forming a source/drain epitaxial stack on a recessed portion of the fin, wherein forming the source/drain epitaxial stack comprises:
forming a first layer including a first dopant at a temperature of 650° C. to 800° C. and a pressure of 20 Torr to 300 Torr; and
Forming a second layer including a second dopant at a temperature of 450 ° C. to 600 ° C. and a pressure of 300 Torr to 400 Torr.
wherein the second layer is disposed on the first layer and has a lower melting point than the first layer, and the first layer and the second layer include materials having the same stoichiometry and different microstructures. Forming the source/drain epitaxial stack, which is to do; and
exposing the source/drain epitaxial stack to an annealing source to activate the first dopant and the second dopant in the first layer and the second layer.
To include, the method.

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