KR102455504B1 - Display device - Google Patents

Abstract

The present invention relates to a display device, and more particularly, to a display device having an improved aperture ratio. A display device according to the present invention includes a plurality of sub-pixels and a plurality of data lines, and each of the plurality of sub-pixels includes a first electrode and a second electrode forming an electric field with the first electrode, and includes one of the plurality of sub-pixels. The first electrode of one sub-pixel and the second electrode of another sub-pixel adjacent to any one sub-pixel are electrically connected to each other to improve the aperture ratio of the display device.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device having an improved aperture ratio.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and in recent years, liquid crystal display devices, plasma display panels, organic light emitting display devices ( Various display devices such as Organic Light Emitting Display Device) are being used.

Such a display device includes a display panel in which data lines and gate lines are disposed and pixels are disposed at points where the data lines and gate lines cross each other. Also, the display device includes a data driver supplying a data voltage Vdata to the data lines, a gate driver supplying a gate signal to the gate lines, and a timing controller controlling the data driver and the gate driver.

In particular, in the liquid crystal display, each of the plurality of pixels is disposed between a pixel electrode to which a data voltage is applied, a common electrode corresponding to the pixel electrode and applied with a common voltage, and between the pixel electrode and the common electrode, so that a data voltage and a pixel voltage are applied. It includes a liquid crystal layer that is rotated by an electric field caused by it.

Here, the liquid crystal display not only needs a data line for supplying a data voltage to each pixel, but also additionally needs a common voltage line for supplying a common voltage to each pixel.

In this way, by including the common voltage line, the non-display area of each pixel is expanded, which leads to a decrease in the aperture ratio of the liquid crystal display. As a result, the luminance efficiency of the liquid crystal display is reduced, resulting in an increase in power consumption.

Accordingly, an object of the present invention is to provide a liquid crystal display having an improved aperture ratio by deleting a common voltage line.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, a display device according to an exemplary embodiment includes a plurality of sub-pixels and a plurality of data lines, and each of the plurality of sub-pixels forms a first electrode and an electric field with the first electrode. and a second electrode, wherein the first electrode of any one sub-pixel among the plurality of sub-pixels and the second electrode of the other sub-pixel adjacent to the one sub-pixel are electrically connected to improve the aperture ratio of the display device can do it

The details of other embodiments are included in the detailed description and drawings.

According to the present invention, the first electrode of the sub-pixel and the second electrode of the adjacent sub-pixel are connected, and the data line is connected to the first electrode of the connected sub-pixel and the second electrode of the other sub-pixel adjacent to the data line. By applying a data voltage or a common voltage to the data line, a common voltage can be applied to the data line, so that a separate common voltage line is not required. do. Accordingly, there is an advantage in that the overall luminance efficiency of the sub-pixel is increased, and power consumption is also reduced.

In addition, according to the present invention, light leakage is prevented by the dummy electrode and the floating electrode, and unnecessary light does not enter the transistor, so that a phenomenon in which image quality is deteriorated due to the flow of photocurrent to the transistor can be prevented.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a schematic block diagram illustrating a display device according to an exemplary embodiment.
2 is a diagram for explaining a connection relationship between sub-pixels included in a display panel of a display device according to an exemplary embodiment of the present invention.
3 is a diagram for describing a first electrode and a second electrode of a first sub-pixel of a display device according to an exemplary embodiment.
FIG. 4 is an enlarged view of area A of FIG. 2 .
5A and 5B are diagrams for explaining voltages applied to a first electrode and a second electrode of a display device according to an exemplary embodiment.
6 is a graph for explaining voltages applied to a first electrode and a second electrode of a display device according to an exemplary embodiment.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

In describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to like elements throughout.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, and as those skilled in the art will fully understand, technically various interlocking and driving are possible, and each embodiment may be independently implemented with respect to each other. It may be possible to implement together in a related relationship.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram illustrating a display device according to an exemplary embodiment.

Referring to FIG. 1 , the display device 100 includes a display panel 110 , a data driver 120 , a gate driver 130 , and a timing controller 140 .

The display panel 110 includes a plurality of gate lines GL1 to GLp and a plurality of data lines DL1 to DLq intersected in a matrix form on a substrate made of glass or plastic. In addition, a plurality of pixels PX are defined at intersections of the plurality of gate lines GL1 to GLp and the data lines DL1 to DLq. Here, p and q are natural numbers.

In addition, each pixel PX may include a plurality of sub-pixels, and each sub-pixel may implement light of a specific color. For example, the plurality of sub-pixels may include a red sub-pixel implementing red, a green sub-pixel implementing green, and a blue sub-pixel implementing blue, but is not limited thereto. Each of the plurality of sub-pixels is connected to at least one transistor.

In addition, when the display device according to an embodiment of the present invention is a liquid crystal display, the gate electrode of the transistor is connected to the gate lines GL1 to GLp, and the source electrode is connected to the data lines DL1 to DLq. , the drain electrode is connected to the plurality of sub-pixels to control a voltage applied to the plurality of sub-pixels. Accordingly, the liquid crystal display device realizes grayscale by controlling the movement of liquid crystals provided in the plurality of sub-pixels. A specific transistor connection relationship will be described later with reference to FIG. 2 .

As described above, the display device 100 is not limited to a liquid crystal display, and may be a display device of various types, such as an organic light emitting diode display.

The timing controller 140 supplies various control signals DCS and GCS and image data RGB to the data driver 120 and the gate driver 130 to control the data driver 120 and the gate driver 130 . .

Specifically, the timing controller 140 starts a scan according to the timing implemented in each frame based on the timing signal TS received from the external host system. In addition, the timing controller 140 converts the image signal VS received from the external host system according to a data signal format that can be processed by the data driver 120 , and outputs image data RGB. Accordingly, the timing controller 140 controls data driving at an appropriate time according to the scan.

The timing controller 140 is configured to include a vertical synchronization signal Vsync, a vertical synchronization signal Hsync, a data enable signal (DE), a data clock signal DCLK, and the like together with the image signal VS. The timing signals TS are received from an external host system.

The timing controller 140 controls the data driver 120 and the gate driver 130 , a vertical synchronization signal Vsync, a vertical synchronization signal Hsync, a data enable signal DE, and a data clock signal DCLK. It receives the timing signal TS such as, etc., generates various control signals DCS and GCS, and outputs them to the data driver 120 and the gate driver 130 .

For example, the timing controller 140 controls the gate driver 130 , a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (Gate Output). Various gate control signals (GCS) including Enable (GOE) and the like are output.

Here, the gate start pulse controls the operation start timing of one or more gate circuits constituting the gate driver 130 . The gate shift clock is a clock signal commonly input to one or more gate circuits, and controls shift timing of a scan signal (gate pulse). The gate output enable signal specifies timing information of one or more gate circuits.

In addition, the timing controller 140 controls the data driver 120 , a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (Source Output Enable; Various data control signals (DCS) including SOE) are output.

Here, the source start pulse controls the data sampling start timing of one or more data circuits constituting the data driver 120 . The source sampling clock is a clock signal that controls the sampling timing of data in each of the data circuits. The source output enable signal controls the output timing of the data driver 120 .

The timing controller 140 is a control connected to the source printed circuit board to which the data driver 120 is bonded through a connection medium such as a flexible flat cable (FFC) or a flexible printed circuit (FPC). It may be disposed on a printed circuit board (Control Printed Circuit Board).

A power control unit for supplying various voltages or currents to the display panel 110 , the data driver 120 , and the gate driver 130 , or controlling various voltages or currents to be supplied may be further disposed on the control printed circuit board. The power control unit may be referred to as a power management integrated circuit (PMIC).

The above-described source printed circuit board and control printed circuit board may be configured as one printed circuit board.

The gate driver 130 sequentially supplies high-level or low-level gate signals to the gate lines GL1 to GLp under the control of the timing controller 140 .

The gate driver 130 may be positioned on only one side of the display panel 110 or on both sides in some cases depending on a driving method.

The gate driver 130 is connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) method, or a gate (GIP) method. In Panel) type and may be disposed directly on the display panel 110 , or may be integrated and disposed on the display panel 110 in some cases.

The gate driver 130 may include a shift register, a level shifter, and the like.

The data driver 120 converts the image data RGB received from the timing controller 140 into an analog data voltage Vdata and outputs the converted image data to the data lines DL1 to DLq.

The data driver 120 may be connected to a bonding pad of the display panel 110 by a tape automated bonding method or a chip-on-glass method or may be directly disposed on the display panel 110 , and in some cases, the display panel 110 . It may be integrated and arranged in

Also, the data driver 120 may be implemented in a Chip On Film (COF) method. In this case, one end of the data driver 120 may be bonded to at least one source printed circuit board, and the other end may be bonded to the display panel 110 .

The data driver 120 may include a logic unit including various circuits such as a level shifter and a latch unit, a digital analog converter (DAC), an output buffer, and the like.

Hereinafter, a part of the display panel 110 of the display device 100 according to an embodiment of the present invention will be taken as an example, and components of the display panel 110 of the display device 100 according to the embodiment will be described below. Describe the connection relationship.

FIG. 2 is a diagram for explaining a connection relationship between sub-pixels included in a display panel of a display device according to an embodiment of the present invention, and FIG. 3 is a diagram of a first sub-pixel of the display device according to an embodiment of the present invention. It is a figure for demonstrating a 1st electrode and a 2nd electrode.

Specifically, in FIG. 2 , in order to explain the connection relationship between the sub-pixels, the first sub-pixel SPa and the second sub-pixel SPb and the first sub-pixel SPa and the second sub-pixel are connected to each other in the vertical direction. The data line DL connected to SPb is shown.

A configuration of each sub-pixel based on the first sub-pixel SPa will be described as follows.

The first sub-pixel SPa includes a first electrode E1a and a second electrode E2a forming an electric field corresponding to the first electrode E1a, and a data line DL is connected to the second electrode E2a. and a transistor TR for supplying a voltage applied therefrom.

The second sub-pixel SPb and all other sub-pixels also have transistors TR connected to the first electrode E1b, the second electrode E2b, and the data line DL like the first sub-pixel SPa. include

Referring to FIG. 3 , the first electrode E1a of the first sub-pixel SPa includes a plurality of first branch electrodes BR1a extending apart from each other and a first branch electrode connecting the plurality of first branch electrodes BR1a to each other. One connection electrode CNT1a is included.

In addition, the second electrode E2a of the first sub-pixel SPa is alternately disposed with the plurality of first branch electrodes BR1a, a plurality of second branch electrodes BR2a extending apart from each other, and a plurality of second branch electrodes BR2a and a second connection electrode CNT2a connecting the branch electrodes BR2a to each other.

In addition, the first electrode E1a and the second electrode E2a may be disposed on the same plane.

In this way, a horizontal electric field is formed between the plurality of first branch electrodes BR1a of the first electrode E1a and the plurality of second branch electrodes BR2a of the second electrode E2, so that the first electrode E1a and A gradation is expressed by controlling the movement of the liquid crystal provided between the second electrodes E2a.

That is, the display device 100 according to an exemplary embodiment is an In-Plane Switching (IPS) liquid crystal display device.

Additionally, as shown in FIG. 2 , the plurality of first branch electrodes BR1a of the first electrode E1a and the plurality of second branch electrodes BR2a of the second electrode E2 are spaced apart from each other, but comb teeth It may be formed in a shape bent in a pattern. However, this extended form is not limited to the form shown in FIG. 2 and may be modified into various forms.

In addition, the second electrode E2a disposed below the first sub-pixel SPa may be connected to the first electrode E1b disposed above the second sub-pixel SPb via the center electrode CT. have.

Specifically, the second connection electrode CNT2a of the second electrode E2a of the first sub-pixel SPa and the first connection electrode CNT1b of the first electrode E1b of the second sub-pixel SPb are at the center The electrode CT may be connected as a medium.

Here, the second electrode E2a disposed below the first sub-pixel SPa and the first electrode E1b disposed above the second sub-pixel SPb are both disposed on the same plane, so The center electrode CT may also be disposed on the same plane as the arrangement plane of the first electrode E1b and the second electrode E2a.

In addition, the transistor TR disposed in the first sub-pixel SPa applies the voltage applied from the data line DL to the second electrode E2a and the second electrode E2a of the first sub-pixel SPa through the center electrode CT. It may be transmitted to the first electrode E1b of the second sub-pixel SPb.

FIG. 4 is an enlarged view of area A of FIG. 2 .

Specifically, referring to FIG. 4 , in the transistor TR disposed in the first sub-pixel SPa, the source electrode S is connected to the data line DL, and the gate electrode G is the gate line GL. ), and the drain electrode D is connected to the center electrode CT. That is, the drain electrode D is connected to the second electrode E2a of the first sub-pixel SPa and the first electrode E1b of the second sub-pixel SPb through the center electrode CT.

Here, the data line DL may be disposed outside the first branch electrode BR1a disposed at the outermost portion. Accordingly, the shape of the data line DL may be the same as that of the first branch electrode BR1a.

And, in the embodiment of the present invention, since the common voltage line for supplying the common voltage Vcom (refer to FIG. 6) is deleted, the common voltage Vcom for forming an electric field is also applied from the data line DL. will be supplied Accordingly, not only the data voltage Vdata for expressing grayscale is applied to the data line DL, but also the common voltage Vcom is applied.

A method of driving a display device according to an embodiment of the present invention related thereto will be described later.

Additionally, in the display device 100 according to an embodiment of the present invention, various electrode patterns for preventing light leakage may be added.

Specifically, the display device 100 according to an exemplary embodiment may further include a plurality of floating electrodes Ft to overlap the data line DL.

Specifically, the plurality of floating electrodes Ft may be disposed on the same plane as the plane on which the gate line GL is formed. Accordingly, since the floating electrode Ft must be formed by excluding the intersection of the data line DL and the gate line GL, the floating electrode Ft is separated into a plurality of floating electrodes Ft to overlap the data line DL. can be

In addition, the display device 100 according to an embodiment of the present invention may further include a dummy electrode Dm in the non-display area of the first sub-pixel SPa in which the transistor TR is not formed.

The dummy electrode Dm also serves to fill the empty area of the sub-pixel, thereby preventing light leakage. Since unnecessary light does not enter the transistor TR due to the dummy electrode Dm, a phenomenon in which a photocurrent flows through the transistor TR and deterioration of image quality can be prevented.

Hereinafter, driving of the display device 100 according to an exemplary embodiment will be described with reference to FIGS. 5A to 6 .

5A and 5B are diagrams for explaining voltages applied to a first electrode and a second electrode of a display device according to an exemplary embodiment. It is a graph for explaining the voltage applied to the first electrode and the second electrode.

Specifically, in FIGS. 5A and 5B , description will be made based on the first sub-pixel SPa and the second sub-pixel SPb of the display device 100 according to an exemplary embodiment of the present invention.

Here, the transistor TR is turned on by the gate line GL of the previous stage in the first electrode E1a of the first sub-pixel SPa, so that the data voltage Vdata or the common voltage Vcom from the data line DL ) is applied, and the transistor TR is turned on by the current gate line GL to the second electrode E2a of the first sub-pixel SPa and the first electrode E1b of the second sub-pixel SPb. Accordingly, the data voltage Vdata or the common voltage Vcom is applied from the data line DL, and the transistor TR is applied to the second electrode E2b of the second sub-pixel SPb by the next gate line GL. ) is turned on, so that the data voltage Vdata or the common voltage Vcom is applied from the data line DL.

That is, it is set that the first voltage V1 is applied to the first electrode E1a of the first sub-pixel SPa during the first horizontal period H1, and the second electrode E1a of the first sub-pixel SPa E2a) and the first electrode E1b of the second sub-pixel SPb are set such that the second voltage V2 is applied during the second horizontal period H2, and the second electrode of the second sub-pixel SPb In (E2b), the operation of the first frame (Frame 1) to the fourth frame (Frame 4) will be described below by setting that the third voltage V3 is applied in the third horizontal period ( H3 ).

First, referring to the first frame (Frame 1), the common voltage Vcom is applied to the first electrode E1a of the first sub-pixel SPa through the data line DL during the first horizontal period H1. When this is applied, the first voltage V1 is polled to the common voltage Vcom, and during the second horizontal period H2, the second electrode E2a of the first sub-pixel SPa and the second sub-pixel SPb The positive data voltage Positive Vdata is applied to the first electrode E1b through the data line DL so that the second voltage V2 rises to the positive data voltage Positive Vdata, and the third horizontal period H3 ), the common voltage Vcom is applied to the second electrode E2b of the second sub-pixel SPb through the data line DL, so that the third voltage V3 rises to the common voltage Vcom.

Accordingly, as shown in FIG. 5A , from the fourth horizontal period of the first frame 1 , the first electrode E1a of the first subpixel SPa and the second electrode E1a of the second subpixel SPb are A common voltage Vcom is applied to E2b, and a positive data voltage Positive Vdata is applied to the second electrode E2a of the first sub-pixel SPa and the first electrode E1b of the second sub-pixel SPb. ) will be accepted.

Accordingly, an electric field is formed in the first electrode E1a and the second electrode E2a of the first sub-pixel SPa due to the positive data voltage Positive Vdata and the common voltage Vcom. The first sub-pixel SPa may implement grayscale, and the positive data voltage Positive Vdata and the common voltage Vcom are also applied to the first electrode E1b and the second electrode E2b of the second sub-pixel SPb. As a result, an electric field is formed and, through this, the second sub-pixel SPb may also implement grayscale.

Next, referring to the second frame Frame 2, negative data is transmitted through the data line DL to the first electrode E1a of the first sub-pixel SPa during the first horizontal period H1. The voltage Negative Vdata is applied so that the first voltage V1 is polled to the negative data voltage Negative Vdata, and the second electrode E2a of the first sub-pixel SPa during the second horizontal period H2 is applied. A common voltage Vcom is applied through the data line DL to the first electrode E1b of the second sub-pixel SPb and the second voltage V2 is polled to the common voltage Vcom, and the third horizontal During the period H3, the positive data voltage Positive Vdata is applied to the second electrode E2b of the second sub-pixel SPb through the data line DL, so that the third voltage V3 is the positive data voltage ( positive Vdata).

Accordingly, as shown in FIG. 5B , from the fourth horizontal period of the second frame Frame 2 , the first electrode E1a of the first sub-pixel SPa and the second electrode of the second sub-pixel SPb are A data voltage Vdata is applied to E2b, and a common voltage Vcom is applied to the second electrode E2a of the first sub-pixel SPa and the first electrode E1b of the second sub-pixel SPb. will become

Accordingly, an electric field is formed in the first electrode E1a and the second electrode E2a of the first sub-pixel SPa due to the negative data voltage Negative Vdata and the common voltage Vcom. The first sub-pixel SPa may implement a gray level, and a positive data voltage positive Vdata and a common voltage Vcom are applied to the first electrode E1b and the second electrode E2b of the second sub-pixel SPb. Due to this, an electric field is formed, and through this, the second sub-pixel SPb may implement grayscale.

Next, referring to the third frame Frame 3, the common voltage Vcom is applied to the first electrode E1a of the first sub-pixel SPa through the data line DL during the first horizontal period H1. ) is applied, the first voltage V1 rises to the common voltage Vcom, and the second electrode E2a and the second sub-pixel SPb of the first sub-pixel SPa during the second horizontal period H2. The negative data voltage Negative Vdata is applied to the first electrode E1b through the data line DL, the second voltage V2 is polled to the negative data voltage Negative Vdata, and the third horizontal During the period H3, the common voltage Vcom is applied to the second electrode E2b of the second sub-pixel SPb through the data line DL, so that the third voltage V3 is polled to the common voltage Vcom. .

Accordingly, as shown in FIG. 5A , from the fourth horizontal period of the first frame 1 , the first electrode E1a of the first subpixel SPa and the second electrode E1a of the second subpixel SPb are A common voltage Vcom is applied to E2b, and a negative data voltage Negative is applied to the second electrode E2a of the first sub-pixel SPa and the first electrode E1b of the second sub-pixel SPb. Vdata) is authorized.

Accordingly, an electric field is formed in the first electrode E1a and the second electrode E2a of the first sub-pixel SPa due to the negative data voltage Negative Vdata and the common voltage Vcom. The first sub-pixel SPa may implement a gray level, and the negative data voltage Negative Vdata and the common voltage Vcom are also applied to the first electrode E1b and the second electrode E2b of the second sub-pixel SPb. ), an electric field is formed, through which the second sub-pixel SPb may also implement grayscale.

Next, referring to the fourth frame (Frame 4), the positive data voltage is applied to the first electrode E1a of the first sub-pixel SPa through the data line DL during the first horizontal period H1. (Positive Vdata) is applied so that the first voltage V1 rises to a positive data voltage (Positive Vdata), and the second electrode E2a and the second electrode E2a of the first sub-pixel SPa during the second horizontal period H2 The common voltage Vcom is applied to the first electrode E1b of the two sub-pixels SPb through the data line DL, so that the second voltage V2 rises to the common voltage Vcom, and during the third horizontal period ( During H3), the negative data voltage Negative Vdata is applied to the second electrode E2b of the second sub-pixel SPb through the data line DL, so that the third voltage V3 becomes the negative data voltage ( Negative Vdata).

Accordingly, as shown in FIG. 5B , from the fourth horizontal period of the second frame Frame 2 , the first electrode E1a of the first sub-pixel SPa and the second electrode of the second sub-pixel SPb are A data voltage Vdata is applied to E2b, and a common voltage Vcom is applied to the second electrode E2a of the first sub-pixel SPa and the first electrode E1b of the second sub-pixel SPb. will become

Accordingly, an electric field is formed in the first electrode E1a and the second electrode E2a of the first sub-pixel SPa due to the positive data voltage Positive Vdata and the common voltage Vcom. One sub-pixel SPa may implement grayscale, and a negative data voltage Negative Vdata and a common voltage Vcom are applied to the first electrode E1b and the second electrode E2b of the second sub-pixel SPb. Due to this, an electric field is formed, and through this, the second sub-pixel SPb may implement grayscale.

In this way, in the second frame (Frame 2) and the fourth frame (Frame 4), the polarity of the data voltage Vdata applied to the first electrode E1a of the first sub-pixel SPa and the second sub-pixel SPb ), the polarities of the data voltages Vdata applied to the second electrode E2b are different from each other.

Specifically, in the second frame (Frame 2), the data voltage Vdata applied to the first electrode E1a of the first sub-pixel SPa is negative, and the second electrode E1a of the second sub-pixel SPb has a negative polarity. The data voltage Vdata applied to E2b) has a positive polarity, and in the fourth frame Frame 4, on the contrary, the data voltage Vdata applied to the first electrode E1a of the first sub-pixel SPa is positive. polarity, and the data voltage Vdata applied to the second electrode E2b of the second sub-pixel SPb has a negative polarity.

In this way, by changing the polarity of the data voltage Vdata of each frame, the liquid crystal is not controlled in only one electric field direction, thereby preventing the liquid crystal from being aggregated in a certain direction. Accordingly, it is possible to improve the afterimage and deterioration of the display device.

As described above, in the present invention, the first electrode of a sub-pixel and the second electrode of another adjacent sub-pixel are connected, and a data line is connected to the second electrode of another sub-pixel adjacent to the first electrode of the sub-pixel connected in this way. connected, and a data voltage or a common voltage is applied to the data line.

A general display device requires a common voltage line to apply a common voltage to each sub-pixel. In the present invention, a common voltage can be applied to the data line, so that a separate common voltage line is not required.

Accordingly, the area of the non-display area of the sub-pixel is reduced, and the aperture ratio of the sub-pixel is improved. Accordingly, there is an advantage in that the overall luminance efficiency of the sub-pixel is increased, and power consumption is also reduced.

A display device according to an embodiment of the present invention includes a plurality of sub-pixels and a plurality of data lines, each of the plurality of sub-pixels includes a first electrode and a second electrode forming an electric field with the first electrode, The first electrode of any one of the sub-pixels of , and the second electrode of the other sub-pixel adjacent to the one of the sub-pixels are electrically connected to each other, thereby improving the aperture ratio of the display device.

According to another feature of the present invention, the first electrode includes a plurality of spaced apart first branch electrodes and a first connection electrode connecting the plurality of first branch electrodes, and the second electrode alternates with the plurality of first branch electrodes. and a plurality of second branch electrodes disposed to be formed as described above and a second connection electrode connecting the plurality of second branch electrodes.

According to another feature of the present invention, the first electrode and the second electrode are disposed on the same plane.

According to another feature of the present invention, the first electrode of one sub-pixel and the second electrode of another sub-pixel adjacent to any one sub-pixel are connected to one data line.

According to another feature of the present invention, a data voltage and a common voltage are applied to each of the plurality of data lines.

According to another feature of the present invention, it further includes a plurality of floating electrodes overlapping the plurality of data lines.

According to another feature of the present invention, the plurality of sub-pixels includes a first sub-pixel and a second sub-pixel adjacent to the first sub-pixel, wherein the second electrode of the first sub-pixel and the first of the second sub-pixels are The electrodes are electrically connected.

According to another feature of the present invention, when a common voltage is applied to the first electrode of the first sub-pixel and the second electrode of the second sub-pixel, the second electrode of the first sub-pixel and the first electrode of the second sub-pixel A data voltage is applied to the electrode.

According to another feature of the present invention, when a data voltage is applied to the first electrode of the first sub-pixel and the second electrode of the second sub-pixel, the second electrode of the first sub-pixel and the first electrode of the second sub-pixel A common voltage is applied to the electrodes.

According to another feature of the present invention, the polarity of the data voltage applied to the first electrode of the first sub-pixel is different from the polarity of the data voltage applied to the second electrode of the second sub-pixel.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display device
110: display panel
120: data driving unit
130: gate driver
140: timing control
SPa, SPb: first sub-pixel, second sub-pixel
E1a, E1b: first electrode
E2a, E2b: second electrode
Ft: floating electrode
Dm: dummy electrode
CT: center electrode
TR transistor
DL: data line
GL: gate line

Claims (10)

multiple sub-pixels
multiple data lines and
a plurality of floating electrodes overlapping the plurality of data lines;
Each of the plurality of sub-pixels is
a transistor connected to the plurality of data lines, a first electrode, and a second electrode forming an electric field with the first electrode;
and a first electrode of any one sub-pixel among the plurality of sub-pixels and a second electrode of another sub-pixel adjacent to the one sub-pixel are electrically connected to each other. The method of claim 1,
the first electrode includes a plurality of spaced apart first branch electrodes and a first connection electrode connecting the plurality of first branch electrodes;
The second electrode includes a plurality of second branch electrodes alternately disposed with the plurality of first branch electrodes and a second connection electrode connecting the plurality of second branch electrodes. The method of claim 1,
and the first electrode and the second electrode are disposed on the same plane. The method of claim 1,
and a first electrode of the one sub-pixel and a second electrode of another sub-pixel adjacent to the one sub-pixel are connected to one data line. The method of claim 1,
A data voltage and a common voltage are applied to each of the plurality of data lines. The method of claim 1,
and a dummy electrode disposed in a non-display area within the plurality of sub-pixels in which the transistor is not formed. The method of claim 1,
the plurality of sub-pixels includes a first sub-pixel and a second sub-pixel adjacent to the first sub-pixel;
The second electrode of the first sub-pixel and the first electrode of the second sub-pixel are electrically connected to each other. 8. The method of claim 7,
When a common voltage is applied to the first electrode of the first sub-pixel and the second electrode of the second sub-pixel,
A data voltage is applied to the second electrode of the first sub-pixel and the first electrode of the second sub-pixel. 8. The method of claim 7,
When a data voltage is applied to the first electrode of the first sub-pixel and the second electrode of the second sub-pixel,
A common voltage is applied to the second electrode of the first sub-pixel and the first electrode of the second sub-pixel. 10. The method of claim 9,
The polarity of the data voltage applied to the first electrode of the first sub-pixel and the polarity of the data voltage applied to the second electrode of the second sub-pixel are different from each other.

Images