KR102453498B1 - A method of etching at least one of a mixed metal and dielectric layer of a semiconductor device - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention is a method for performing planar and cross-sectional etching of semiconductor devices made of multiple layers of dissimilar materials such as metals and dielectrics. The method results in the removal of multiple layers for the purpose of exposing a single layer of interest or crossing several layers to perform a variety of applications including, but not limited to, nanoprobing, circuit editing, and failure analysis. make it The method directs an ion beam towards a defined area of a semiconductor device in the presence of an etchant to remove at least a portion of the mixed metal and dielectric layer and at least one substantially smooth and planar surface of the concave in the milling area. generating wealth. The etchant used contains an optimized ratio of an oxidizing element and a reducing element so that the amount of the oxidizing element is one element greater than the amount of the reducing element.

Description

A method of etching at least one of a mixed metal and dielectric layer of a semiconductor device

The present invention relates to a method for gas-assisted etching of dissimilar materials by ion beam irradiation and applies, for example, to the uniform removal of metal and dielectric materials to create smooth and planar surfaces in semiconductor devices. It is possible.

Etching is a well-known technique in the semiconductor industry used for the removal of material from semiconductor devices. The purpose of the removal is to expand the accessibility of the area. The etching process may have two modes. The first mode is so-called planar etching or the reverse process involves thin layer-by-layer removal of a die of a semiconductor device. The second mode is called cross-sectional etching and creates a recess in the semiconductor device in which more layers of cross-section may be observed. Etching is a technique commonly employed in the semiconductor industry and also by the material analysis arm of laboratories and universities. Commercial etching may be performed by reactive ion etching, wet chemical etching or mechanical etching includes polishing or cutting. Of these, mechanical etching is the most common technique used for large-area removal of mixed or unmixed metals and dielectrics. Mechanical etching methods are very nerve-wracking, as the expected formation of a slurry is placed between the layers of the device and thus requires an additive cleaning procedure. Surfaces obtained by mechanical etching are generally non-planar surfaces with a clear slope to the surface and poor reliability in terms of localization of small structures. The growing sensitivity of semiconductor devices to this side effect increases the likelihood of failing precise defect localization, nanoprobing, C-AFM measurements, circuit edit, or any other electrical test.

Mechanical etching may be replaced with much more sophisticated advanced instruments such as focused ion beam devices or wide ion beam devices that may perform etching in a localized manner. Nearby areas are hardly affected or the effect is only in the range of a few micrometers. The ion beam device produces a stream of ions that are targeted with great accuracy to a selected area to sputter atoms from the sample. An Ion Beam (IB) changes the sample in different ways as it scans over a predetermined area, depending on the energy of the incoming ions. Ion beam devices usually employ various ions of He to Xe, distinguished by their mass and consequently their interaction with the target surface.

The material removal process is controlled as the process can be easily monitored online by collecting signals from sputtered ions using different detectors in the FIB-SEM system. To further broaden the application base of FIB-SEM systems, gas assisted etching (GAE) techniques are now widely adopted.

The "maze" geometry of conductive metal lines running through dielectric material in three-dimensionally stacked semiconductor devices makes planar and single-sided etching more difficult only when FIBs are used. The FIB interaction with the sample surface depends on the composition and/or crystallinity of the targeted surface. This results in a pre-determination of the sputtering rate for all materials using the same set of FIB conditions. This interaction can be altered when reactive molecules are introduced as an etchant into a gas or vapor formation using a gas injection system (GIS) in the work area. The basic principle of this method is to introduce a gas containing a suitable chemical formation of the desired material into the sample chamber. The injection of this advantageous chemical gas agent into the chamber during the etching of two or more dissimilar materials can enable sputtering at the same rate, resulting in a smooth, planar surface.

Two major reactions can also be observed when introducing gases in the vicinity of the sample surface in general: surface modification through etching and material deposition. Gas assisted etching can be used to alter the etching behavior of a particular material due to the presence of a gas or gaseous agent under which an ion beam enables deposition of a precursor material on a target surface. Using a reactive gas as an etchant under the influence of a beam can help increase or decrease the etch rate of some materials due to localized chemical reactions. On the one hand, when volatile species are formed, the sputtering rate is increased and less material redeposition is observed. On the other hand, a thicker layer can also be created by deposition of gas molecules on the surface and a simultaneous decrease in the sputtering rate is observed. These various applications of sputtering rates are used to perform selective or planar etching of semiconductor devices. By using a reactive etchant, ion beam etching due to the ion beam may be enhanced or reduced due to local chemical reactions.

US6900137 uses XeF ₂ to etch both organic dielectric and metal layers in a controlled manner by increasing the dwell time of the FIB.

Patent US7008803 uses a variable position endpoint detector and GAE to determine the dwell time of a single point etch to the end of the etched layer.

In patent application 2013/0118896, FIB is used for homogenization of heterogeneous materials using rotating sample stages and adjustment of FIB operating conditions during the process. This method requires precise control of the number of parameters that must be controlled during milling and the etch rate of each material present on the sample surface. The method requires generating a hierarchical circuit schematic for each sample using surface data obtained from each removed layer.

A group of etchants for GAE that results in the same etch rate of dissimilar materials by reducing the etch rate of dielectrics when compared to metallic compounds selected from the group containing acetate/nitroacetate and short chain hydrocarbons is reported in US9064811 do. The patent specifically includes methyl acetate, ethyl acetate, ethyl nitroacetate, propyl acetate, propyl nitroacetate, nitro ethyl acetate, methyl methoxyacetate or methoxy acetylchloride as agents for GAE.

The semiconductor industry is growing at a very fast pace with new challenges every day. The materials employed in constantly increasingly complex structures increase the number of transistors in a smaller area and thus require further miniaturization to reduce the size of the transistors resulting in an exponentially compressed density of the circuit. In the reference mentioned above, different methods for creating a planar surface using an ion beam device are discussed, but with respect to the structure used for the circuit as well as the increased number of materials that make up the next generation of even more semiconductor devices. There are a wide variety of etchants that can be used for etching. While many etchants may be suitable for etching a predetermined set of metal-dielectric combinations and may be more effective than using FIB alone on other combinations, undesirable side effects such as redeposition from gaseous by-products to be kept to a minimum.

Some of the etchants may be etched using conventional GAE methods. It is more effective to have a variety of etchants in the selection to select the etchant with the best performance for the method of etching dissimilar materials with approximately the same etch rate.

The method described below uses an etchant selected for semiconductor material removal from a thick layer of copper exposed immediately after de-capping to a very thin, dense layer of copper directly above the transistor contact layer (TC _L ). During etching, it is often desired that the dissimilar materials have the same etch rate. The selected etchant should contain sufficient oxidizing element to adjust the etch rate of the metal and sufficient reducing element to adjust the etch rate of the dielectric to a height at which both dissimilar materials are etched with approximately the same etch rate.

The presence of a high-energy ion beam (IB), eg a focused ion beam or a broad beam with a beam energy of at least 5 keV, together with the etchant and the semiconductor device, between the elements of the compound in the working chamber, in particular in the active ion beam region. By breaking bonds, a reactive element is created. The active ion beam region is the region in space that follows the trajectory of the ion beam and reaches the surface of the semiconductor device. This reactive element, associated with a large number of electrons produced by the interaction of the ion beam with the sample surface or etchant, may react with the constituent elements and form other molecules. In order to produce a volatile compound that supports etching, the GIS must deliver an etchant or combination of etchants containing the necessary elements to produce the targeted volatile compound. For better control of simultaneous milling of dissimilar materials containing metals and dielectrics, suitable combinations of surface composition and elements introduced by GIS must be found to allow the desired surface reaction. Elements necessary to produce volatile molecules may include carbon (C), oxygen (O), halogenated elements such as fluorine (F) and chlorine (Cl) and nitrogen (N). Simultaneous etching of the metallic constituent elements of the semiconductor device must be considered along with the etching of the dielectric, which must also be controlled to obtain the specified delayed-surface roughness. This dielectric may have a variable composition of more elements as the most common dielectrics are the SiOx type and the SixNy type. ever; Carbon is added as a popular low-k dielectric such as GaAs materials or potential substrates based on GaN materials. Metals used in semiconductor devices may be copper, cobalt, aluminum, tungsten, and tantalum. The amount of reactive molecules from dielectric milling increases as they are sputtered from the sample and ejected by ion beam interaction with the dielectric. Similar to metal etching (as described above), without the presence of complementary molecules introduced by GIS, it is difficult to control their milling rate. Thus, in order to arrive at a controlled etch rate with an approximate 1:1 ratio between all constituents of a selected sample, the etch rate of all materials with or without the addition of chemical reactions must be considered. The etchants used for GAE may contain oxidizing elements with one or several different chemical functions using nitrogen, oxygen and halogens (F, Cl) and reducing elements, preferably in the form of carbon. Nitrogen is required to produce volatile metal-nitrogen molecules, such as copper nitride. Halogen is required to produce a metal-halide or a silicon halide. Oxygen may also be used to create C-containing volatile COx molecules in low-k dielectrics. This volatile molecular formation will aid in the pumping of the chamber, thus reducing the redeposition of by-products generated during GAE using the ion beam.

The ratio of all these implanted elements must be controlled and the sample composition taken into account to reach the level of surface uniformity and roughness of the final layer. The compounds according to the invention, from which the etchant is selected, comprise a -COO-, -CON-, or -CNN- central structure in combination with other elements depending on the requirements for the oxidation/reduction ratio (o/r). Etching according to the present invention is a planar etching in which a substantially planar surface made by an ion beam is parallel to a metal or dielectric layer in a semiconductor device or a cross section in which the substantially planar surface is offset with respect to the metal or dielectric layer in the range of 10 to 170° It may be etching.

Based on this approach for the etching of dissimilar materials such as metals and dielectrics, the amount of element oxidizing (o) and element reduction (r) present in the etchant must be balanced. The best ratio for etching of dissimilar materials is determined as [o = r + 1], preferably trioxide and direductant for the most common combinations of dielectrics and metals such as silicon dioxide and copper. As the amount of reducing element in the etchant increases, it becomes more difficult to predict the amount of reactive fragments and ensure gas properties in the working chamber. The number of reducing elements in the etchant is at most three to ensure proper functioning, but also an etchant with a higher number of reducing elements may have the properties required. The reducing element in the etchant should be C and the oxidizing element should be selected from the group of F, Cl, O and N. In a preferred embodiment, the etchant may comprise a compound from the group of ammonium ethanoate, chloroacetamide, fluoroacetamide, methyl carbamate, N-nitrosodiethylamine.

In a further embodiment according to the present invention, etching of the semiconductor device may release a plurality of secondary oxidizing and reducing elements from the semiconductor device into the working chamber. These secondary oxidizing and reducing elements may contribute significantly to the etching process and as such will affect the total amount of oxidizing and reducing elements that must be introduced through the GIS during etching. If the number of secondary elements is high enough to cause elemental imbalances affecting the etching process and/or tends towards non-uniform etching of dissimilar materials, the composition of the etchant or mixture of etchants should be adjusted. Good tuning of dissimilar material etch performance is observed for etchants or mixtures of etchants where the number of elements in the etchant ranges from [o-r=-1] to [o-r=3]. If the etching of copper is faster than the dielectric, more reducing elements must be included. Likewise, if the etch of the dielectric is faster than copper, more oxidizing elements are needed. The non-uniform etching ratio may be adjusted by an etchant containing one compound from acetic acid, ethyl formate, ammonium bicarbonate, hydrazine acetate, diethyl imidodicarbonate, ammonium oxalate and water. The etching process may be monitored online or at intervals using an SEM or FIB device equipped with appropriate signal detection devices and methods.

In a preferred embodiment, the mixture of etchants comprises at least a first etchant from ammonium ethanoate, chloroacetamide, fluoroacetamide, methyl carbamate, N-nitrosodiethylamine, and acetic acid, ethyl formate, bicarbonate at least one second etchant from ammonium, hydrazine acetate, diethyl imidodicarbonate and water.

In a further embodiment according to the invention, the etchant comprises an R-CO-R central structure. R in the formula may include any element that complies with the condition of the ratio of the oxidizing element and the reducing element together with the central structure. The R-CO-R structure contains strong CO double covalent bonds and other interelement bonds with lower binding energies than CO double covalent bonds, eg CH, CC, C-NH ₂ . Molecules may also split in the gas phase by high energy collision induced dissociation (CID). In a typical CID, molecular ions are usually accelerated to high kinetic energy by a potential and then collided with a neutral molecule (often helium, nitrogen or argon). In an embodiment according to the present invention, the neutral etchant molecules collide with the ions of the high kinetic energy ion beam. Energy from the collision may be converted into internal energy that causes bond breakage and cleavage of the etchant into smaller fragments. The amount of fragments generally increases with the acceleration energy of the ion and the mass of the ion. When the energy of the ion beam is reduced to a lower energy region (< 5 keV), the amount of reactive elements is reduced and volatile molecules such as CO molecules may be generated in the working chamber. These molecules may remain intact and do not substantially contribute to inter-element reactions. When the total amount of reactive elements is decreased, the etching rate is slowed down. The slowing of the etch rate along with lower penetration of the surface of the semiconductor device may result in micro-etching of the sample surface without the need to change the etchant composition, concentration, or injection pressure. Modern ion beam devices can change the beam energy quickly, so it is possible to change very quickly between normal and very fine heterogeneous material etching. This is advantageous for debonding of a thick top metal layer of a semiconductor device with a very dense underlying semiconductor device metal layer or for better control of endpoint detection if the etch process is very fast.

For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings:
1 is a schematic diagram of a device for carrying out a preferred embodiment of the present invention;
Fig. 2 is a cross-sectional view schematically showing a portion of a typical semiconductor device;
Fig. 3 is a cross-sectional view schematically showing a portion of a semiconductor device after plane etching;
Fig. 4 is a cross-sectional view schematically showing a portion of a semiconductor device after single-sided etching;
Fig. 5 is a cross-sectional view schematically showing details of a part of a semiconductor device, using an inert ion beam;
6 is a cross-sectional view schematically showing details of a portion of a semiconductor device, using an active high energy ion beam;
7 is a cross-sectional view schematically showing details of a portion of a semiconductor device, using an active high energy ion beam while scanning;
Fig. 8 is a cross-sectional view schematically showing details of a portion of a semiconductor device after an unsuccessful etching using an etchant;
9 is a cross-sectional view schematically illustrating a portion of a semiconductor device after successful etching using a combination of an etchant and another etchant;
Fig. 10 is a schematic cross-sectional view of a portion of a semiconductor device using an active low energy ion beam;
11 is a cross-sectional view schematically illustrating a portion of a semiconductor device using an active low energy ion beam while scanning.

Embodiments of the present invention aim to expose a single layer of interest or cross several layers to perform a variety of applications including, but not limited to, nanoprobing, circuit editing, and failure analysis, including metal and A method for performing planar and single-sided etching by removing multiple layers of a dissimilar material, such as a dielectric.

A preferred embodiment of the present invention relates to a method used for etching dissimilar materials used in the production of semiconductor devices. Utilization of techniques and apparatus can be duplicated for uniform and smooth etching of copper, low-k dielectrics, GaAs, and dissimilar materials such as GaN and others. The method is flexible and can be configured alone or used in combination with other methods for improved productivity of etching or rapid techniques for probing analysis.

1 is a schematic diagram of a device 100 for etching a semiconductor device 2 . The device comprises a vacuum chamber 1 in which a semiconductor device 2 is placed on a holder 3 . The device further comprises means ( 4 ) for generating the ion beam and propagating the ion beam along the optical axis ( 5 ) towards the semiconductor device ( 2 ). The ion beam may employ a variety of ions, from light (Li) to relatively heavy Xe ions. Device 100 may further comprise SEM 6 for generating electrons and propagating electrons along SEM optical axis 7 . The SEM optical axis 7 is aimed approximately at the same area on the object as the ion beam optical axis 5 . Electrons generated by the object after interaction with the SEM 6 electrons or electrons scattered from the sample are used for monitoring the etching progress on the semiconductor device 2 surface. The device 100 further comprises a gas injection system 8 for propagating gas molecules of the etchant 9 towards the semiconductor device 2 .

2 shows a cross-sectional view of the semiconductor device 2 . The semiconductor device 2 consists of a plurality of layers. A capping layer 10 is on top of the semiconductor device 2 . The semiconductor device 2 further comprises a metal layer 11 denoted M0 to M8. Each metal layer 11 includes a metal conductor 13 (running through the metal layer 11 ) and a low-k dielectric 14 . Via layer 12, denoted V7 to VC _L , connects a metal conductor 13 from one metal layer 11 to a metal conductor 13 in the next metal layer 11 through an interconnecting conductor 15, and It is disposed between the metal layers 11 . The interconnect conductors 15 are separated within the via layer 12 by a dielectric 14 .

3 shows the results of a successful planar etch using gas assisted etch in accordance with the present invention. A part of the metal layer 11 of M8 to M1 and the via layer 12 of V7 to V0 are removed within the defined area, and a smooth surface 16 is created on the metal layer 11 (M0). The metal layer 11 in the vicinity of the flat etched box defined by the smooth planar surface 16 and walls 17 of the box is intact. The surface area of the plane has dimensions of 100×100 μm. Due to the smooth and smooth etching process, the metal conductor 13 of the metal layer 11 (M0) is accessible for observation and analysis. The removal of the metal layer 11 and the via layer 12 is a layer-by-layer process and any metal layer 11 or via layer 12 is observed according to the invention by scanning the surface of the semiconductor device 2 by means of an ion beam. and ready for analysis.

4 shows the results of a successful single-sided etch using a gas-assisted etch, in accordance with the present invention. Compared to FIG. 3 , cross-sectional etching allows viewing or analyzing a cross-sectional surface 18 that is planar intersecting more than one metal layer 11 . Using gas-assisted etching according to the present invention makes it possible to etch dissimilar materials such as metal conductors 13, dielectrics 14 and interconnect conductors 15 with the same etch rate and thus a curtain effect. effect) is minimized.

5 shows one metal layer of a semiconductor device 2 to be etched, comprising a dielectric 14 comprising an element oxidizing 19 and an element reducing 20 and a metal conductor 13 comprising a metallic element 21 ( 11) is a detailed cross section. The active region 22 of the ion beam represents the region where the etched element is first emitted and the etchant 23 molecules are first contacted with the ion beam active region 22 . 5 shows the situation of an inert ion beam, meaning that no high energy ions are present in the active region 22 . The etchant 23 contains an oxidizing (19) element and a reducing (20) element in a region close to the surface of the semiconductor device. The semiconductor device layer also includes an oxidizing element and a reducing element to complete the reaction amount. In a preferred embodiment, the etching gas is methyl carbamate with a 2:3 ratio of reducing (20) element to oxidizing (19) element. In an alternative embodiment, ammonium ethanoate, chloroacetamide, fluoroacetamide, N-nitrosodiethylamine may be used as the etchant. Etching agent 23 may be used alone or in combination with any other from this group or in combination with at least one of the group comprising acetic acid, ethyl formate, ammonium bicarbonate, hydrazine acetate, diethyl imidodicarbonate, and water. have.

6 shows, in comparison with FIG. 5 , an ion beam is activated and uses a high energy ion beam to etch the metal conductor 13 and the low-k dielectric 14 present in the metal layer 11 of the semiconductor device 2 . show the situation The ion beam has an energy of at least 5 keV, but preferably greater than 10 keV. The elements 19 , 20 , 21 from the metal layer 11 and the elements 19 , 20 of the etchant are dissociated under the effect of the ion beam and a cloud of reactive elements 19 , 20 , 21 in the active region 22 . create The etchant 23 is continuously pumped into the vicinity of the semiconductor device 2 surface during the entire etching process to help uniform etching.

7 shows an ongoing etching process under a high energy ion beam that etches larger amounts of material (both dielectric 14 and metal conductor 13). Elements 19 , 20 , 21 from both the metal layer 11 and the etchant 23 can be found to dissociate in the active region 22 of the ion beam. These dissociated elements (19, 20, 21) associate with each other to form stable volatile molecules (24, 25) formed due to the combination of element metal (21) with element oxide (19) or reducing (20) element and oxide (19) elements are exhausted due to their volatile nature. The etchant 23 adsorbed to or close to the surface of the metal layer 11 is present throughout the course of the planar etching and enters the active region 22 at every stage of the ion beam movement. In a preferred embodiment, the presence of the etchant 23 evenly spread over the complete surface of the semiconductor device 2 is very important. The presence of the etchant 23 with appropriate amounts of oxidizing and reducing elements re-reflects the surface to promote etching of the metal conductor 13 and dielectric 14 at the same etch rate and the creation of a smooth planar surface 16 . It is necessary to form volatile molecules 24 and 25 that can be evacuated instead of being deposited.

8 shows the results of a failed planar etch using gas-assisted etching of the high-density metal layer M0. A part of the metal layer 11 of M8 to M1 and the via layer 12 of V7 to V0 are removed within the defined area, and surfaces 16a and 16b are created in the metal layer 11 (M0). Dielectric 14 has a lower etch rate than metal 16 in M0, which is a layer with high metal density and ion beam etching creates a rough surface in this layer. To adjust the heterogeneous etch rate, a second etchant 23 has to be supplied and creates a mixture with the first etchant 23 . If the metal 13 has a higher etch rate compared to the dielectric 14 , a second etchant containing more reducing 20 elements must be supplied. In a preferred embodiment, the etching gas is methyl carbamate with a 2:3 ratio of reducing (20) element to oxidizing (19) element. In an alternative embodiment, ammonium ethanoate, chloroacetamide, fluoroacetamide, N-nitrosodiethylamine may be used as the first etchant.

The number of oxidizing agents in the second etchant is at most one element which is less than the number of reducing elements 20 in the second etchant 23 . If the metal 13 has a lower etch rate compared to the dielectric 14, the second etchant contains more element oxide 19 that must be supplied.

The number of oxidizing agents in the second etchant is at most three elements, which is more than the number of reducing elements 20 in the second etchant 23 .

In a preferred embodiment, this second etchant is ethyl formate (o-r=-1), diethyl imidodicarbonate (o-r=-1), acetic acid (o-r=0), hydrazine acetate (o-r=2), water (o-r) =1) or ammonium bicarbonate (o-r=3). The second etchant is supplied until the height of the surfaces 16a and 16b is reached the same as shown in FIG. 9 .

10 shows one metal layer of a semiconductor device 2 to be etched, comprising a dielectric 14 comprising an element of oxidation 19 and an element of a reducing 20 and a metal conductor 13 comprising a metallic element 21 ( 11) is a detailed cross section. Compared with FIG. 5 , the energy of the ion beam is low, less than 5 keV; This is not enough to break the strong inter-elemental bond, which creates fewer highly reactive fragments and the lower ion beam energy does not allow the ion beam ions to penetrate deeply into the metal layer 11 . This results in slower material removal from the metal layer 11 . This feature is particularly important in the highly sensitive layer in the semiconductor device 2 . A portion of the etchant 23 contains a reducing (20) element and an oxidizing (19) element, including a C-O 26 element having a double covalent bond in its structure. The etchant 23 introduced to the surface does not undergo complete dissociation and the non-dissociated volatile fragments 27 are free from any sputtered elements 19, 20, 21 present in the active region 22 of the ion beam. It is exhausted from the system without reacting.

11 shows that, in comparison with FIG. 10 , the ion beam etches the metal conductor 13 and the low-k dielectric 14 present in the metal layer 11 of the semiconductor device 2 using a low-energy ion beam while the ion beam etches the metal layer ( 11) shows the scanning situation on the surface. The non-dissociated volatile fragments 27 are continuously evacuated. On the other hand, the dissociated elements (19, 20, 21) associate with each other to form stable volatile molecules (24) formed due to the combination of the metal reducing (21) element and the oxidation (19) element or reducing (20) Elements and oxidizing (19) elements are exhausted due to their volatile nature. The depth of the etch with the etchant and ion beam less than 5 keV is tens of nanometers and the freshly etched area has minimal amount of redeposition. The uniformity of the etching is still maintained and the surface is planar and smooth and has a topographic roughness of less than 10 nm in the case of a very high sensitivity layer such as the transistor contact layer (TC _L ).

Claims (14)

A method of etching at least one of a mixed metal and dielectric layer from a region of a semiconductor device, the method comprising:
defining a region of the semiconductor device to be etched, the region comprising at least several layers of a mixed metal and dielectric comprised in the semiconductor device;
directing a first etchant towards a defined area of the semiconductor device, the first etchant forming a central structure of -C(=O)O- or -C(=O)-N- and further comprising an oxidizing element selected from the group of fluorine, chlorine, oxygen, nitrogen and a reducing element in a specific ratio, wherein the amount of the oxidizing element is one more element than the amount of the reducing element, and the amount of the reducing element is directing the first etchant towards a defined area of a semiconductor device, characterized in that at most three; and
Directing an ion beam towards the defined area of the semiconductor device in the presence of the first etchant to remove at least a portion of the mixed metal and dielectric layer and to remove at least one substantially smooth and at least one processed area on the object. A method of etching at least one of a mixed metal and dielectric layer comprising creating a recess having a planar surface.
The method of claim 1 , wherein in the first etchant, the amount of the element oxide is three. 3. The etchant of claim 1 or 2, wherein the first etchant is selected from the group consisting of ammonium ethanoate, chloroacetamide, fluoroacetamide and methyl carbamate. How to.
2. The method of claim 1, further comprising directing a second etchant towards the defined region on the semiconductor device to create a mixture with the first etchant, the second etchant being A method for etching one or more of a mixed metal and dielectric layer comprising an oxidizing element selected from the group of fluorine, chlorine, oxygen, nitrogen and a reducing element being carbon, and wherein the amount of the oxidizing element in the second etchant is at least one. .
5. The method of claim 4, wherein the amount of the oxidizing element in the second etchant minus the amount of the reducing element in the second etchant is equal to a number in the range of -1 to 3 to etch at least one of the mixed metal and dielectric layer. Way.
5. The method of claim 4, wherein the second etchant is selected from the group consisting of acetic acid, ethyl formate, ammonium bicarbonate, hydrazine acetate, and diethyl imidodicarbonate. The method of claim 1 , wherein etching the defined region of the semiconductor device using at least the first etchant is performed in two steps, the first step of the mixed metal and dielectric layer using a first beam energy. A second fine etch of at least a portion of the at least a portion of the etch and at least a portion of the mixed metal and dielectric layer that was initially etched using the first beam energy is performed using a second beam energy, wherein the first beam energy is the second beam energy. A method of etching one or more of a mixed metal and dielectric layer that is higher than the beam energy. 8. The method of claim 7, wherein the micro etch is used to etch at least a portion of the metal layer from M1 to the transistor contact layer.
The method of claim 1 , wherein the dielectric in the semiconductor device is a low-k dielectric.
The method of claim 1 , wherein the dielectric in the semiconductor device comprises at least one of SixNy, SixOy.
The method of claim 1 , wherein the substantially planar surface is parallel to a metal or dielectric layer of the semiconductor device.
The method of claim 1 , wherein the substantially planar surface is offset relative to the metal or dielectric layer of the semiconductor device within a range of 10° to 170°. The method of claim 1 , wherein the ion beam is a focused ion beam. delete

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