KR102452596B1 - Apparatus and method for diagnosing MOSFET - Google Patents

Abstract

The present invention relates to a MOSFET diagnosis apparatus and method capable of effectively diagnosing a MOSFET in the process of diagnosing whether the MOSFET is faulty. A MOSFET diagnosis apparatus according to an embodiment of the present invention is a device for diagnosing a MOSFET provided on a charge/discharge path of a cell assembly and configured to control conduction of a charge/discharge current, and is electrically connected to a gate terminal and a source terminal of the MOSFET a voltage measuring unit connected and configured to measure a measured value of a potential difference between a gate terminal and a source terminal of the MOSFET; and a processor configured to receive the potential difference measurement value from the voltage measurement unit, and to diagnose whether the MOSFET is faulty by comparing the received potential difference measurement value with a previously stored normal potential difference value.

Description

Apparatus and method for diagnosing MOSFET

The present invention relates to an apparatus and method for diagnosing a MOSFET, and more particularly, to an apparatus and method for diagnosing a MOSFET effectively in the process of diagnosing whether the MOSFET is faulty.

In recent years, as the demand for portable electronic products such as notebook computers, video cameras, and portable telephones has rapidly increased, and the development of electric vehicles, energy storage batteries, robots, satellites, etc. is in full swing, a high-performance secondary battery capable of repeatedly charging and discharging research is being actively conducted.

Currently commercialized secondary batteries include nickel-cadmium batteries, nickel-hydrogen batteries, nickel-zinc batteries, and lithium secondary batteries. Among them, lithium secondary batteries have almost no memory effect compared to nickel-based secondary batteries, so charging and discharging are free, The self-discharge rate is very low and the energy density is high, attracting attention.

Batteries are used in various fields, and fields in which batteries are recently used a lot, such as electric powered vehicles or smart grid systems, often require large capacity. In order to increase the capacity of the battery pack, there may be a method of increasing the capacity of the secondary battery, that is, the battery cell itself. has Therefore, in general, a battery pack in which a plurality of battery modules are connected in series and in parallel is widely used.

Such a battery is connected to a load or a charger to operate the load by supplying power to the load, or is charged by receiving power from the charger. That is, the battery is generally used while being electrically connected to a system such as a load or a charger. At this time, the battery and the system are connected through a line for supplying power, and a contactor or a MOSFET (MOS Field-Effect Transistor) is provided on the line between the battery and the system to perform a switching operation.

However, in the case of the related art, only whether current conduction can be adjusted using the MOSFET, and a function for diagnosing whether the MOSFET is faulty is not provided. In this case, it is impossible to diagnose whether the MOSFET is malfunctioning, so there is a problem in that energy loss according to the amount of heat generated by the MOSFET increases.

The present invention was devised under the background of the prior art as described above, and relates to an improved MOSFET diagnosis apparatus and method for effectively diagnosing a MOSFET in the process of diagnosing whether a MOSFET is faulty.

Other objects and advantages of the present invention may be understood by the following description, and will become more clearly understood by the examples of the present invention. In addition, it will be readily apparent that the objects and advantages of the present invention can be realized by means and combinations thereof indicated in the claims.

A MOSFET diagnosis apparatus according to an embodiment of the present invention for achieving the above object is an apparatus for diagnosing a MOSFET provided on a charge/discharge path of a cell assembly and configured to control conduction of a charge/discharge current. a voltage measuring unit electrically connected to the gate terminal and the source terminal, configured to measure a potential difference measurement value between the gate terminal and the source terminal of the MOSFET; and a processor configured to receive the potential difference measurement value from the voltage measurement unit, and to diagnose whether the MOSFET is faulty by comparing the received potential difference measurement value with a previously stored normal potential difference value.

Also, the MOSFET diagnosis apparatus according to an embodiment of the present invention may further include a temperature measuring unit electrically connected to the MOSFET and configured to measure a temperature of the MOSFET.

In addition, the processor receives the potential difference measurement value from the voltage measurement unit, receives the temperature of the MOSFET from the temperature measurement unit, and selects the MOSFET based on the received potential difference measurement value and the temperature of the MOSFET It may be configured to limit the amount of current flowing.

In addition, the MOSFET diagnosis apparatus according to an embodiment of the present invention uses a potential difference between a gate terminal and a source terminal of the MOSFET and the temperature of the MOSFET as input values, and a lookup table using the operating state resistance of the MOSFET as an output value. It may further include a memory device configured to pre-store.

In addition, the processor calculates a failure operating state resistance in case of a MOSFET failure based on the potential difference measurement value and the temperature of the MOSFET using the lookup table, and the MOSFET based on the normal potential difference value and the temperature of the MOSFET and may be configured to calculate a normal operating state resistance when normal.

Also, the processor may be configured to calculate a MOSFET resistance increase rate based on a ratio of the fault operating state resistance and the normal operating state resistance.

Also, the MOSFET diagnosis apparatus according to an embodiment of the present invention may further include a current measuring unit provided on the charge/discharge path and configured to measure a current flowing through the charge/discharge path.

In addition, the processor may be configured to receive the current in the steady state of the MOSFET from the current measuring unit, and calculate a maximum allowable fault current based on the current in the steady state of the MOSFET and the MOSFET resistance increase rate.

Also, the processor may be configured to limit the amount of current flowing through the MOSFET so that the maximum allowable fault current becomes a maximum allowable current of the charge/discharge path.

In addition, the BMS according to an embodiment of the present invention for achieving the above object includes a MOSFET diagnostic apparatus according to the present invention.

In addition, a battery pack according to an embodiment of the present invention for achieving the above object includes the MOSFET diagnostic apparatus according to the present invention.

In addition, a vehicle according to an embodiment of the present invention for achieving the above object includes the MOSFET diagnostic apparatus according to the present invention.

In addition, a method for diagnosing a MOSFET according to an embodiment of the present invention for achieving the above object is a method for diagnosing a MOSFET provided on a charge/discharge path of a cell assembly and configured to control conduction of charge/discharge current, the method comprising: measuring a potential difference measurement between a gate terminal and a source terminal of the MOSFET; and diagnosing whether the MOSFET is faulty by comparing the measured potential difference with a previously stored normal potential difference value.

According to one aspect of the present invention, there is an advantage in that it is possible to effectively diagnose whether the MOSFET is faulty by using the potential difference between the gate terminal and the source terminal of the MOSFET.

In particular, according to an embodiment of the present invention, by calculating the maximum allowable current of the MOSFET, an improved MOSFET diagnosis apparatus capable of limiting the amount of current flowing through the MOSFET can be provided.

In addition, the present invention may have various other effects, and these other effects of the present invention can be understood by the following description, and can be seen more clearly by the examples of the present invention.

The following drawings attached to the present specification illustrate preferred embodiments of the present invention, and serve to further understand the technical spirit of the present invention together with the detailed description of the present invention to be described later. should not be construed as being limited only to
1 is a diagram schematically showing a functional configuration of a MOSFET diagnosis apparatus according to an embodiment of the present invention.
FIG. 2 is a diagram schematically illustrating a configuration in which a MOSFET diagnostic apparatus is connected to some components of a battery pack according to an embodiment of the present invention.
3 shows a logic circuit referred to by the MOSFET diagnosis apparatus according to an embodiment of the present invention to calculate the operating state resistance of the MOSFET.
4 is a flowchart schematically illustrating a MOSFET diagnosis method according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, the terms or words used in the present specification and claims should not be construed as being limited to their ordinary or dictionary meanings, and the inventor should properly understand the concept of the term in order to best describe his invention. Based on the principle that it can be defined, it should be interpreted as meaning and concept consistent with the technical idea of the present invention.

Accordingly, the configuration shown in the embodiments and drawings described in the present specification is merely the most preferred embodiment of the present invention and does not represent all of the technical spirit of the present invention, so at the time of the present application, various It should be understood that there may be equivalents and variations.

In addition, in the description of the present invention, if it is determined that a detailed description of a related well-known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

Throughout the specification, when a part "includes" a certain element, it means that other elements may be further included, rather than excluding other elements, unless otherwise stated. In addition, a term such as 'processor' described in the specification means a unit for processing at least one function or operation, which may be implemented as hardware or software, or a combination of hardware and software.

In addition, throughout the specification, when a part is "connected" with another part, it is not only "directly connected" but also "indirectly connected" with another element interposed therebetween. include

As used herein, a secondary battery means a single, physically separable cell having a negative terminal and a positive terminal. For example, one pouch-type lithium polymer cell may be regarded as a secondary battery.

A MOSFET diagnosis apparatus according to the present invention is an apparatus for diagnosing a MOSFET. For example, the MOSFET may be provided on a charge/discharge path of the cell assembly. In addition, the MOSFET may be selectively turned on or off to control conduction of charge/discharge current. Here, one or more secondary batteries may be provided in the cell assembly. Also, the MOSFET is a field effect transistor (FET) device having gate, drain, and source terminals, and may be turned on or off depending on whether a channel is formed according to a voltage applied between the gate terminal and the source terminal. For example, the FET device may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Meanwhile, in the embodiment of FIG. 2 , the MOSFET according to an embodiment of the present invention is implemented as an N-type MOSFET, but the MOSFET is not limited to the N-type MOSFET.

1 is a diagram schematically showing a functional configuration of a MOSFET diagnostic apparatus according to an embodiment of the present invention, and FIG. 2 is a configuration in which the MOSFET diagnostic apparatus according to an embodiment of the present invention is connected to some components of a battery pack is a diagram schematically showing

1 and 2 , the MOSFET diagnostic apparatus 1 according to an embodiment of the present invention includes a voltage measuring unit 100 and a processor 200 .

The voltage measuring unit 100 may be electrically connected to the gate terminal G and the source terminal S of the MOSFET M. For example, as shown in the configuration of FIG. 2 , the voltage measuring unit 100 may be electrically connected to the gate terminal G and the source terminal S of the MOSFET M to transmit and receive electrical signals, respectively. can

Also, the voltage measuring unit 100 may be configured to measure a measured value of a potential difference between the gate terminal G and the source terminal S of the MOSFET M. More specifically, the voltage measuring unit 100 measures the potential of the gate terminal G and the potential of the source terminal S, and measures the potential difference between the gate terminal G and the source terminal S based on this. can do.

The processor 200 may be electrically connected to the voltage measuring unit 100 to transmit and receive electrical signals. Also, the processor 200 may receive a potential difference measurement value from the voltage measurement unit 100 . Also, the processor 200 may diagnose whether the MOSFET M has failed by comparing the potential difference measurement value received from the voltage measuring unit 100 with a previously stored normal potential difference value. Here, a detailed description of the failure diagnosis of the MOSFET M will be described later.

Preferably, the voltage measuring unit 100 measures the potential difference between each gate terminal (G) and the source terminal (S) at time intervals under the control of the processor 200 and receives a signal representing the magnitude of the measured voltage. It may output to the processor 200 . For example, the voltage measuring unit 100 may be implemented using a voltage measuring circuit generally used in the art.

Preferably, as shown in the configuration of FIGS. 1 and 2 , the MOSFET diagnosis apparatus 1 according to an embodiment of the present invention may further include a temperature measuring unit 300 .

The temperature measuring unit 300 may be electrically connected to the MOSFET M so as to transmit and receive electrical signals. Alternatively, the temperature measuring unit 300 may be mounted on the MOSFET M and electrically connected to the MOSFET M. Through such a configuration, the temperature measuring unit 300 may measure the temperature of the MOSFET M.

Preferably, the temperature measuring unit 300 may be electrically coupled to the processor 200 to transmit and receive electrical signals. Also, the temperature measuring unit 300 may repeatedly measure the temperature of the MOSFET M at a time interval and output a signal indicating the magnitude of the measured temperature to the processor 200 . For example, the temperature measuring unit 300 may be implemented using a thermocouple generally used in the art.

Preferably, the MOSFET diagnosis apparatus 1 according to an embodiment of the present invention may further include a current measuring unit 500 as shown in the configuration of FIGS. 1 and 2 .

The current measuring unit 500 may be provided on a charge/discharge path connected to both ends of the cell assembly 10 . More specifically, as shown in the configuration of FIG. 2 , the current measuring unit 500 according to an embodiment of the present invention may be connected to both ends of the sense resistor 510 provided on the charge/discharge path. Here, the sense resistor 510 may be electrically connected to the negative terminal of the cell assembly 10 . Also, the current measuring unit 500 may be configured to measure a current flowing through a charging/discharging path. For example, as shown in the configuration of FIG. 2 , the current measuring unit 500 according to an embodiment of the present invention measures the voltage across the sense resistor, and a charging/discharging path based on the voltage across the sense resistor. can measure the current flowing through it.

Preferably, the current measuring unit 500 may be electrically coupled to the processor 200 to transmit and receive electrical signals. In addition, the current measurement unit 500 repeatedly measures the magnitude of the charging current or the discharging current of the cell assembly 10 at time intervals under the control of the processor 200 and outputs a signal indicating the magnitude of the measured current to the processor 200 . ) can be printed. For example, the current measuring unit 500 may be implemented using a Hall sensor or a sense resistor generally used in the art. The Hall sensor or the sense resistor may be installed in a line through which a current flows.

Preferably, the MOSFET diagnosis apparatus 1 according to an embodiment of the present invention may further include a memory device 400 as shown in the configuration of FIGS. 1 and 2 .

The memory device 400 may be electrically connected to the processor 200 to transmit and receive electrical signals. Also, the memory device 400 may store in advance a normal value of the potential difference between the gate terminal G and the source terminal S of the MOSFET M. Also, the memory device 400 may store in advance a lookup table referenced by the processor 200 . In particular, the lookup table uses the potential difference between the gate terminal (G) and the source terminal (S) of the MOSFET (M) and the temperature of the MOSFET (M) as input values, and the operating state resistance of the MOSFET (M) as the output value It may be a lookup table that does

Preferably, the processor 200 according to an embodiment of the present invention may be connected to the voltage measuring unit 100 and the temperature measuring unit 300 to transmit and receive electrical signals. In addition, the processor 200 may receive the potential difference measurement value from the voltage measurement unit 100 and receive the temperature of the MOSFET M from the temperature measurement unit 300 .

Also, the processor 200 may be configured to limit the amount of current flowing through the MOSFET M based on the measured potential difference and the temperature of the MOSFET M. More specifically, the processor 200 calculates the potential difference between the gate terminal G and the source terminal S of the MOSFET M and the temperature of the MOSFET M using the lookup table received from the memory device 400 . Based on the operation state resistance of the MOSFET M can be calculated. Here, the on-state resistance of the MOSFET M may be the resistance of the MOSFET M in a state in which the MOSFET M is turned on and a current flows through the charge/discharge path.

For example, the processor 200 calculates the failure operation state resistance of the MOSFET M, which means the operation state resistance of the MOSFET M when the MOSFET fails, based on the potential difference measurement value and the temperature of the MOSFET M can do. Also, the processor 200 may calculate the normal operating state resistance of the MOSFET M, which means the operating state resistance of the MOSFET M when the MOSFET is normal, based on the potential difference normal value and the temperature of the MOSFET M. .

Preferably, the processor 200 according to an embodiment of the present invention may calculate a MOSFET resistance increase rate based on a ratio of the resistance of the MOSFET M in the faulty operation state and the resistance in the normal operation state of the MOSFET M. .

<Equation 1>

Here, R _f is the resistance of the MOSFET (M) in the fault operating state, R _n is the resistance in the normal operating state of the MOSFET (M), and a is the resistance increase rate. For example, the processor 200 may calculate a resistance increase rate of the MOSFET M based on the ratio of the fault operating state resistance and the normal operating state resistance using the operation of Equation 1 . For example, when the fault operating state resistance is 5 ohms and the normal operating state resistance is 2.5 ohms, the resistance increase rate may be 2 .

Preferably, the processor 200 according to an embodiment of the present invention receives the current in the steady state of the MOSFET from the current measuring unit 500, and the maximum allowable fault current based on the current in the steady state of the MOSFET and the increase rate of the resistance of the MOSFET can be calculated.

<Equation 2>

Here, I _f is the maximum allowable fault current, R _f is the fault operating state resistance, I _n is the steady state current, and R _n is the normal operating state resistance. For example, the processor 200 may calculate the maximum allowable amount of heat in the failure state of the MOSFET M based on the amount of heat generated in the steady state of the MOSFET M.

<Equation 3>

<Equation 4>

<Equation 5>

암페어일 수 있다.Here, I _f is the maximum allowable fault current, R _n is the normal operating state resistance of the MOSFET M, a is the resistance increase rate, and I _n is the steady state current. For example, the processor 200 may calculate the maximum allowable fault current I _f of the MOSFET M using Equations 1 to 5 above. For example, if the resistance increase rate (a) is 2 and the steady-state current (I _n ) is 5 amps, the maximum value of the maximum allowable fault current (I _f ) is

can be amperes.

Preferably, the processor 200 according to an embodiment of the present invention may limit the amount of current flowing through the MOSFET M such that the maximum allowable fault current becomes the maximum allowable current of the charge/discharge path. More specifically, the processor 200 may calculate the maximum allowable fault current and limit the amount of current flowing through the MOSFET M based on the calculated maximum allowable fault current. For example, as shown in the configuration of FIG. 2 , the processor 200 according to an embodiment of the present invention transmits a current limit request to the upper control device 50 to control the amount of current flowing through the charge/discharge path. It can be limited to a value below the maximum allowable fault current.

In addition, the processor 200 may transmit a failure state of the MOSFET M to the display to warn the user of the MOSFET failure state through the display. Here, the display may be electrically connected to the processor 200 to transmit and receive electrical signals.

On the other hand, the processor 200, in order to perform the operation as described above, the processor 200, ASIC (Application-Specific Integrated Circuit), other chipsets, logic circuits, registers, communication modems and / or data known in the art. It may be implemented in a form that selectively includes a processing device and the like.

Meanwhile, the memory device 400 is not particularly limited in its type as long as it is a storage medium capable of recording and erasing information. For example, the memory device 400 may be a RAM, a ROM, a register, a hard disk, an optical recording medium, or a magnetic recording medium. The memory device 400 may also be electrically connected to the processor 200 through, for example, a data bus, so that each can be accessed by the processor 200 . The memory device 400 may also store and/or update and/or erase and/or transmit a program including various control logic performed by the processor 200, and/or data generated when the control logic is executed. have.

The MOSFET diagnosis apparatus 1 according to the present invention may be applied to a BMS. That is, the BMS according to the present invention may include the MOSFET diagnostic apparatus 1 according to the present invention described above. In this configuration, at least some of the respective components of the MOSFET diagnostic apparatus 1 according to the present invention may be implemented by supplementing or adding functions of the configuration included in the conventional BMS. For example, the processor 200 and the memory device 400 of the MOSFET diagnostic apparatus 1 according to the present invention may be implemented as components of a Battery Management System (BMS).

Also, the MOSFET diagnosis apparatus 1 according to the present invention may be provided in a battery pack. That is, the battery pack according to the present invention may include the MOSFET diagnosis apparatus 1 according to the present invention described above. Here, the battery pack may include one or more secondary batteries, the MOSFET diagnostic device 1 , an electronic device (including a BMS, a relay, a fuse, etc.), a case, and the like.

3 shows a logic circuit referred to by the MOSFET diagnosis apparatus according to an embodiment of the present invention to calculate the operating state resistance of the MOSFET.

Referring to FIG. 3 , the processor 200 according to an embodiment of the present invention provides a faulty operation state resistance and a normal operation state resistance of the MOSFET M based on the logic circuit 250 shown in the embodiment of FIG. 3 . can be calculated. Here, the logic circuit 250 uses the potential difference (V _GS ) between the gate terminal (G) and the source terminal (S) of the MOSFET (M) and the temperature (T _M ) of the MOSFET (M) as input values, The operating state resistance (R _M ) of the MOSFET (M) may be an output value.

Preferably, the processor 200, when it is determined that the MOSFET M is faulty, the measured potential difference between the gate terminal G and the source terminal S of the MOSFET M as an input value and the MOSFET M You can input the temperature of , and calculate the resistance of the fault operating state when the MOSFET is faulty with the output value.

In addition, the processor 200 inputs the normal value of the potential difference between the gate terminal G and the source terminal S of the MOSFET M as an input value and the temperature of the MOSFET M as an input value, and the normal value when the MOSFET is normal as an output value. The operating state resistance can be calculated.

4 is a flowchart schematically illustrating a MOSFET diagnosis method according to an embodiment of the present invention. In FIG. 4 , the subject performing each step may be referred to as each component of the MOSFET diagnosis apparatus according to the present invention described above.

As shown in FIG. 4 , the voltage measuring unit may measure a potential difference measurement value between the gate terminal and the source terminal of the MOSFET in the potential difference measuring step S100 . Subsequently, in the MOSFET failure diagnosis step S110 , the processor may compare the potential difference measured value with the potential difference normal value to diagnose whether the MOSFET has failed.

Preferably, in the MOSFET fault diagnosis step S110 , the processor may limit the amount of current flowing through the MOSFET based on the measured potential difference and the temperature of the MOSFET.

Preferably, in the MOSFET failure diagnosis step ( S110 ), the processor calculates the resistance of the failure operation state when the MOSFET fails based on the potential difference measurement value and the temperature of the MOSFET, and the MOSFET based on the normal potential difference value and the temperature of the MOSFET Normal operating state resistance can be calculated.

Preferably, in the MOSFET failure diagnosis step S110 , the processor may calculate a MOSFET resistance increase rate based on a ratio of the failure operation state resistance and the normal operation state resistance.

Preferably, in the MOSFET failure diagnosis step ( S110 ), the processor calculates a maximum allowable failure current based on the MOSFET steady state current and the MOSFET resistance increase rate, and the maximum allowable failure current is the maximum allowable current of the charging/discharging path. As much as possible, the amount of current flowing through the MOSFET can be limited.

In addition, when the control logic is implemented in software, the processor may be implemented as a set of program modules. In this case, the program module may be stored in the memory device and executed by the processor.

In addition, as long as at least one or more of various control logics of the processor are combined, and the combined control logics are written in a computer-readable code system and are computer-readable, there is no particular limitation on the type. As an example, the recording medium includes at least one selected from the group consisting of a ROM, a RAM, a register, a CD-ROM, a magnetic tape, a hard disk, a floppy disk, and an optical data recording device. In addition, the code system may be distributed, stored, and executed in computers connected to a network. In addition, functional programs, codes and segments for implementing the combined control logic can be easily inferred by programmers in the art to which the present invention pertains.

As described above, although the present invention has been described with reference to limited embodiments and drawings, the present invention is not limited thereto, and the technical idea of the present invention and the following by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents of the claims to be described.

Meanwhile, although terms such as 'memory device' and 'processor' are used in this specification, it is understood by those skilled in the art that it indicates a logical unit and does not necessarily indicate a component that can be physically separated or must be physically separated. self-evident to

1: MOSFET diagnostic device
10: cell assembly
50: upper control unit
100: voltage measuring unit
200: processor
250: logic circuit
300: temperature measurement unit
400: memory device
500: current measuring unit
510: sense resistance
G: gate terminal
M: MOSFET
S: source terminal

Claims (12)

An apparatus for diagnosing a MOSFET provided on a charge/discharge path of a cell assembly and configured to control conduction of a charge/discharge current, the device comprising a drain terminal, a source terminal, and a gate terminal,
a voltage measuring unit electrically connected to the gate terminal and the source terminal of the MOSFET to measure a potential difference measurement value between the gate terminal and the source terminal of the MOSFET; and
and a processor configured to receive the potential difference measurement value from the voltage measurement unit and diagnose whether the MOSFET is faulty by comparing the received potential difference measurement value with a previously stored normal potential difference value,
The normal potential difference value is a MOSFET diagnosis apparatus, characterized in that it is a value stored in advance with respect to a potential difference between the gate terminal and the source terminal.
According to claim 1,
A temperature measuring unit electrically connected to the MOSFET and configured to measure a temperature of the MOSFET
MOSFET diagnostic device, characterized in that it further comprises.
3. The method of claim 2,
The processor receives the potential difference measurement value from the voltage measurement unit, receives the temperature of the MOSFET from the temperature measurement unit, and a current flowing through the MOSFET based on the received potential difference measurement value and the temperature of the MOSFET MOSFET diagnostic device, characterized in that configured to limit the amount of.
According to claim 1,
a memory device configured to store in advance a lookup table using a potential difference between a gate terminal and a source terminal of the MOSFET and a temperature of the MOSFET as an input value and an operating state resistance of the MOSFET as an output value
MOSFET diagnostic device, characterized in that it further comprises.
5. The method of claim 4,
The processor, using the lookup table, calculates a failure operating state resistance at the time of MOSFET failure based on the potential difference measurement value and the temperature of the MOSFET, and when the MOSFET is normal based on the normal potential difference value and the temperature of the MOSFET MOSFET diagnostic device, characterized in that configured to calculate the normal operating state resistance of.
6. The method of claim 5,
wherein the processor is configured to calculate a MOSFET resistance increase rate based on a ratio of the fault operation state resistance and the normal operation state resistance.
7. The method of claim 6,
A current measuring unit provided on the charging/discharging path to measure a current flowing through the charging/discharging path
MOSFET diagnostic device, characterized in that it further comprises.
8. The method of claim 7,
wherein the processor is configured to receive a MOSFET steady-state current from the current measuring unit and calculate a maximum allowable fault current based on the MOSFET steady-state current and the MOSFET resistance increase rate.
9. The method of claim 8,
The processor is configured to limit the amount of current flowing through the MOSFET so that the maximum allowable fault current becomes the maximum allowable current of the charging/discharging path.
10. A BMS comprising the MOSFET diagnostic device according to any one of claims 1 to 9.
10. A battery pack comprising the MOSFET diagnostic device according to any one of claims 1 to 9.
A method for diagnosing a MOSFET provided on a charge/discharge path of a cell assembly and configured to control conduction of charge/discharge current, the MOSFET including a drain terminal, a source terminal, and a gate terminal, the method comprising:
measuring a potential difference measurement value between the gate terminal and the source terminal of the MOSFET; and
Comprising the step of diagnosing whether the MOSFET is faulty by comparing the measured potential difference with a previously stored normal value of the potential difference,
The normal value of the potential difference is a value stored in advance for a potential difference between the gate terminal and the source terminal.

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