KR102446076B1 - Composition for etching and manufacturing method of semiconductor device using the same - Google Patents

Abstract

The present invention relates to an etching composition, an etching method, and a semiconductor device, wherein the etching composition includes phosphoric acid and an inorganic acid.
The etching composition enables the selective etching of the silicon nitride film and the silicon oxide film, suppresses the generation of particles due to the additive by omitting the silicon additive, improves solubility due to mixing of inorganic acids, and raises the boiling point of the solution to be heated to a high temperature make it

Description

Etching composition and method of manufacturing a semiconductor device using the same

The present invention relates to an etching composition capable of selectively etching a silicon nitride film and a silicon oxide film, and a method of manufacturing a semiconductor device including an etching process using the etching composition.

In a semiconductor manufacturing process, an oxide film such as a silicon oxide film (SiO ₂ ) and a nitride film such as a silicon nitride film (SiN _x ) are used as representative insulating films, each alone or by alternately stacking one or more layers. In addition, these oxide films and nitride films are also used as hard masks for forming conductive patterns such as metal wiring.

The wet etching process for removing the nitride layer generally includes deionized water. The deionized water is added to reduce an etch rate and prevent a change in etch selectivity for the oxide layer, but a slight change in the amount of deionized water to be supplied. There is also a problem in that defects occur in the etching removal process of the nitride film.

1A and 1B are cross-sectional views illustrating a device isolation process of a flash memory device.

First, as shown in FIG. 1A , a tunnel oxide layer 11 , a polysilicon layer 12 , a buffer oxide layer 13 , and a pad nitride layer 14 are sequentially formed on the substrate 10 , and then the polysilicon layer 12 . ), the buffer oxide layer 13 and the pad nitride layer 14 are selectively etched to form a trench. Next, after forming the SOD oxide film 15 until the trench is gap-filled, a CMP process is performed on the SOD oxide film 15 using the pad nitride film 14 as a polishing stop film.

Accordingly, there is a need for an etching composition having a high selectivity that does not have problems such as generation of particles while selectively etching a nitride film with respect to an oxide film in a semiconductor manufacturing process.

Republic of Korea Patent Publication No. 1991-0006458

The present invention enables selective etching of a silicon nitride film and a silicon oxide film, suppresses the generation of particles caused by the additive by omitting the silicon additive, improves solubility due to mixing of inorganic acids, and raises the boiling point of the solution to enable heating to a high temperature An object of the present invention is to provide an etching composition and a method of manufacturing a semiconductor device using the same.

The etching composition according to an embodiment of the present invention includes phosphoric acid and an inorganic acid.

The inorganic acid may be any one selected from the group consisting of sulfuric acid, exothermic sulfuric acid, nitric acid, silicic acid, hydrofluoric acid, boric acid, hydrochloric acid, perchloric acid, and mixtures thereof.

The inorganic acid may preferably be sulfuric acid.

The inorganic acid may have a concentration of 3 to 75% (v/v).

The etching composition may include 2 to 80 parts by weight of inorganic acid based on 100 parts by weight of phosphoric acid.

The etching composition may have a selectivity ratio of a nitride etch rate (Å/min) to an oxide etch rate (Å/min) of 40:1 to 2000:1 (nitride etch rate: oxide etch rate).

The present invention provides a method of manufacturing a semiconductor device including an etching process performed using the etching composition according to an embodiment of the present invention.

The method of manufacturing the semiconductor device further includes a subsequent process of removing particles generated in the etching process, and in the subsequent process, the particles are removed using dilute hydrofluoric acid or APM (a mixture of hydrogen peroxide and aqueous ammonia). .

The etching process may be to selectively etch the nitride layer with respect to the oxide layer, and the nitride layer etching process may be performed at a temperature of 50 to 300°C.

The present invention includes the steps of forming a nitride film on a substrate, forming a trench in the nitride film using a hard mask, forming an oxide film to fill the trench, and using the nitride film as a polishing stop film to expose the nitride film. There is provided a method of manufacturing a semiconductor device, comprising: performing a chemical mechanical planarization process until the etchant; and removing the nitride layer by a wet etching process using the etching composition.

The etching composition according to the present invention can selectively etch the silicon nitride layer and the silicon oxide layer by increasing the E/R of the silicon nitride layer and controlling the selectivity using an inorganic acid.

The etching composition according to the present invention can be selectively etched, can replace the existing silicone additive, and can suppress the generation of particles resulting from the silicone additive.

The etching composition according to the present invention is a mixture of inorganic acids and has good solubility.

The etching composition according to the present invention can be heated to a temperature higher than the boiling point of phosphoric acid alone through the boiling point increase of the solution by adding sulfuric acid.

The method of manufacturing a semiconductor device using the etching composition of the present invention can control the etching rate.

1A and 1B are cross-sectional views illustrating a device isolation process of a flash memory device according to the related art.
2A to 2C are cross-sectional views illustrating a device isolation process of a flash memory device including an etching process using an etching composition according to an embodiment of the present invention.
3A to 3F are cross-sectional views illustrating a pipe channel forming process of a flash memory device including an etching process using an etching composition according to an embodiment of the present invention.
4A and 4B are cross-sectional views illustrating a diode formation process in a phase change memory including an etching process using an etching composition according to another embodiment of the present invention.

Since the present invention can apply various transformations and can have various embodiments, specific embodiments are illustrated and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. The terms used in the present invention are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present invention, terms such as 'comprise' or 'have' are intended to designate that the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification exist, and one or more other features It is to be understood that this does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

The composition for etching a silicon oxide layer and a silicon nitride layer according to an embodiment of the present invention includes phosphoric acid and an inorganic acid.

The phosphoric acid may be used to obtain a high etch selectivity of the silicon oxide layer and the silicon nitride layer. The phosphoric acid may serve to promote etching by providing hydrogen ions in the etching composition. When phosphoric acid is used as the inorganic acid, the phosphoric acid may be 80 to 90 wt% aqueous solution of phosphoric acid. When the phosphoric acid aqueous solution is used, a high selectivity of the nitride film can be obtained.

An etching composition according to the present invention comprising a mixture of inorganic acids may have solubility advantages.

The inorganic acid may be any one selected from the group consisting of sulfuric acid, exothermic sulfuric acid, nitric acid, silicic acid, hydrofluoric acid, boric acid, hydrochloric acid, perchloric acid, and mixtures thereof.

The inorganic acid is added as an etchant for etching the nitride layer.

The inorganic acid is most preferably sulfuric acid.

In the case of adding an inorganic acid, particularly sulfuric acid, to phosphoric acid, heating to a temperature higher than the boiling point of phosphoric acid alone is possible through the boiling point increase of the solution. This enables a faster etching rate by increasing the temperature while maintaining the H ₂ O content, which is an important factor in phosphoric acid etching of the silicon nitride layer.

When sulfuric acid is added, silicon ions generated in the etching process are oxidized to silica through the oxidation action of sulfuric acid, which may cause particles more easily.

Accordingly, it is necessary to remove the particles through a subsequent process. Particles can be removed by adding particle removal processes through dilute hydrofluoric acid and APM (mixture of hydrogen peroxide and ammonia water) to remove particles.

The inorganic acid may have a concentration of 3 to 75% (v/v).

For example, sulfuric acid among the inorganic acids, if the concentration of sulfuric acid is less than 3% (v/v), the etching rate of the nitride film does not increase, so that the selectivity cannot be increased, and the excess sulfuric acid exceeds 75% (v/v) When mixed with phosphoric acid, the concentration of phosphoric acid, which is an etching element of the silicon nitride film, is reduced, and thus the etching rate of the silicon nitride film is reduced.

The etching composition may include 2 to 80 parts by weight of inorganic acid based on 100 parts by weight of phosphoric acid.

When the inorganic acid is included in an amount of less than 2 parts by weight, the nitride film may not be easily removed, there is a risk of generating particles, and when it contains more than 80 parts by weight, there may be a problem in that the nitride film is not removed.

The selectivity between the nitride etch rate (Å/min) and the oxide etch rate (Å/min) of the etching composition may be 40:1 to 2000:1 (nitride etch rate: oxide etch rate).

In etching, selection refers to the relative etch rate between two different materials. The etch selectivity of the silicon oxide layer with respect to the silicon nitride layer is a ratio of the silicon oxide layer etch rate to the silicon nitride layer etch rate, and may be calculated by Equation 1 below.

[Equation 1]

In Equation 1, A is the etching rate of the silicon nitride layer, B is the etching rate of the silicon oxide layer, and C is the selectivity.

Since the etching composition has a high etch selectivity of the nitride layer to the oxide layer as described above, the effective oxide layer height (EFH) can be easily adjusted by controlling the etching rate of the oxide layer.

When the phosphoric acid and the inorganic acid are included in an amount of 25 parts by weight based on 100 parts by weight of the phosphoric acid, the selectivity of the nitride etch rate (Å/min) and the oxide etch rate (Å/min) of the etching composition is 400: 1 or more ( nitride etch rate: oxide etch rate), and the composition is very excellent in the selective removal of the nitride film, so that the semiconductor manufacturing process requiring the selective removal of the nitride film, the device isolation process of a flash memory device, the pipe channel of the 3D flash memory device Efficiency can be improved in an etching process such as a (pipe channel) forming process and a diode forming process of a phase change memory.

The etching composition may further include a solvent of the remaining content in addition to phosphoric acid and inorganic acid. The content may include the remaining amount such that the total weight of the etching composition is 100%.

The solvent may be any one selected from the group consisting of water, alcohol, glycol ether, ether, ester, ketone, carbonate, amide, and combinations thereof.

The alcohol is methanol, ethanol, isoprotanol, n-propanol, n-hexanol, n-octanol, ethylene glycol, propylene glycol, 1,4-butanediol, 1,6-hexanediol, tetrahydrofurfuryl alcohol, and glycerin. Examples of the glycol ether include propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate, ethylene glycol monomethyl ether, ethylene glycol monomethyl ether acetate, ethylene glycol monomethyl ether propionate, and ethylene glycol monomethyl ether. butyl ether, ethylene glycol monobutyl ether acetate, and the like. Examples of the ethers include diethyl ether, tetrahydrofuran, 1,4-dioxane, and the like, and the esters include ethyl lactate, 3-methoxy and methyl propionate, methyl acetate, ethyl acetate, γ-butyrolactone, and the like, and examples of the ketone include acetone and methyl ethyl ketone, and examples of the carbonate include dimethyl carbonate, diethyl carbonate, ethylene carbonate, and propylene. carbonate and the like, and examples of the amide include N,N-dimethyl acetamide and N,N-dimethyl formamide.

The type of water is not particularly limited, but deionized water is preferable.

The etching composition may further include any additives commonly used in the art to improve etching performance. As additives, surfactants, sequestering agents, corrosion inhibitors, and the like can be used.

In addition, the etching composition may further include a surfactant if necessary in order to remove the etched residue. As the surfactant, all of an anionic surfactant, a cationic surfactant, or a nonionic surfactant may be used. Examples of the cationic surfactant include amines such as C ₈ H ₁₇ NH ₂ , and the anionic surfactant includes hydrocarbon-based carboxylic acids such as C ₈ H ₁₇ COOH, and hydrocarbons such as C ₈ H ₁₇ SO ₃ H A fluorine _- type carboxylic acid, such as a sulfonic acid and H(CF2) _6COOH , is mentioned, As a nonionic surfactant, ethers, such as polyoxyalkylene alkyl ether, are mentioned.

The surfactant may be included in an amount of 0.01 to 1 wt % based on the total amount of the etching composition. If the content of the surfactant is less than 0.01% by weight, there may be a problem that particles are generated, and if it exceeds 1% by weight, there may be a problem in process stability due to excessive bubble generation.

In the etching composition, an alkaline compound or an acid other than the fluorine compound may be further added as needed to adjust the pH. The alkaline compound may be ammonia, an amine or tetraalkyl ammonium hydroxide, or a nitrogen-containing heterocyclic compound. Examples of acids other than the fluorine compound include inorganic acids such as silicic acid, phosphoric acid, boric acid, hydrochloric acid, sulfuric acid, nitric acid and perchloric acid, or organic acids such as carboxylic acid, organic phosphorous acid and organic sulfonic acid.

The etching composition may further include corrosion inhibitors such as triazoles, imidazoles, and thiol compounds as necessary to protect metal wiring.

Since the etching composition contains phosphoric acid and inorganic acid, the etch selectivity of the nitride film to the oxide film is significantly high, and thus it can be used in the nitride film etching process.

Therefore, in the etching process, the effective oxide layer height EFH can be easily adjusted by minimizing the etching of the oxide layer. In addition, when the nitride film is selectively removed by etching, it is possible to prevent deterioration of the film quality of the oxide film or deterioration of electrical properties due to etching of the oxide film, and prevent generation of particles, thereby improving device characteristics.

The method of manufacturing a semiconductor device according to another embodiment of the present invention includes an etching process performed using the etching composition.

In one embodiment, the etching process is characterized in that the nitride film is etched, and in particular, the nitride film is selectively etched with respect to the oxide film.

The nitride film may include a silicon nitride film, for example, a SiN film, an SiON film, or the like.

In addition, the oxide film is a silicon oxide film, for example, a SOD (Spin On Dielectric) film, HDP (High Density Plasma) film, thermal oxide film, BPSG (Borophosphate Silicate Glass) film, PSG (Phospho Silicate Glass) film, BSG ( Boro Silicate Glass) film, PSZ (Polysilazane) film, FSG (Fluorinated Silicate Glass) film, LP-TEOS (Low Pressure Tetra Ethyl Ortho Silicate) film, PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate) film, HTO (High Temperature Oxide) film Film, MTO (Medium Temperature Oxide) film, USG (Undoped Silicate Glass) film, SOG (Spin On Glass) film, APL (Advanced Planarization Layer) film, ALD (Atomic Layer Deposition) film, PE-Oxide (Plasma Enhanced oxide) film , O3-TEOS (O3-Tetra Ethyl Ortho Silicate) film, and may be at least one film selected from the group consisting of combinations thereof.

The etching process using the etching composition may be performed by a wet etching method well known in the art, for example, an immersion method, a spraying method, and the like.

During the etching process, the process temperature may be in the range of 50 to 300 °C, preferably 100 to 200 °C, and the appropriate temperature may be changed as necessary in consideration of other processes and other factors.

As described above, according to the method of manufacturing a semiconductor device including an etching process performed using the etching composition, when the nitride layer and the oxide layer are alternately stacked or mixed, selective etching of the nitride layer is possible. In addition, it is possible to prevent the generation of particles, which has been a problem in the conventional etching process, thereby securing the stability and reliability of the process.

Accordingly, this method can be efficiently applied to various processes requiring selective etching of a nitride film with respect to an oxide film in a semiconductor device manufacturing process.

2A to 2C are cross-sectional views illustrating a device isolation process of a flash memory device including an etching process using an etching composition according to an embodiment of the present invention.

Referring to FIG. 2A , a tunnel oxide layer 21 , a polysilicon layer 22 , a buffer oxide layer 23 , and a pad nitride layer 24 are sequentially formed on a substrate 20 .

Subsequently, the pad nitride layer 24 , the buffer oxide layer 23 , the polysilicon layer 22 , and the tunnel oxide layer 21 are selectively etched through a photo and etching process to expose the device isolation region of the substrate 20 . .

Subsequently, the exposed substrate 20 is selectively etched using the pad nitride layer 24 as a mask to form a trench 25 having a predetermined depth from the surface.

Referring to FIG. 2B , an oxide layer 26 is formed on the entire surface of the substrate 20 by using a chemical vapor deposition (CVD) method until the trench 25 is gap-filled.

Next, a chemical mechanical polishing (CMP) process is performed on the oxide film 26 using the pad nitride film 24 as a polishing stop film.

Then, a cleaning process is performed using dry etching.

Referring to FIG. 2C , after selectively removing the pad nitride layer 24 by a wet etching process using the etching composition according to the present invention, the buffer oxide layer 23 is removed by a cleaning process. As a result, the device isolation layer 26A is formed in the field region.

As shown in FIG. 2C , in the present invention, by using an etching composition having a high etching selectivity of the nitride film to the oxide film, the etching of the oxide film gap-filled in the STI pattern is minimized and the nitride film is completely and selectively selected for a sufficient time. can be removed Accordingly, it is possible to easily control the effective oxide film height (EFH), and it is possible to prevent deterioration of electrical characteristics and generation of particles due to damage to the oxide film or etching, thereby improving device characteristics.

Although the above embodiment has been described with respect to the flash memory device, the high selectivity etch composition according to the present invention is, of course, applicable to the device isolation process of the DRAM device.

3A to 3F are cross-sectional views illustrating a channel forming process of a flash memory device including an etching process using an etching composition according to another embodiment of the present invention.

Referring to FIG. 3A , a pipe gate electrode layer 31 in which a nitride layer 32 for forming a pipe channel is buried is formed on a substrate 30 . The first and second conductive layers 31A and 31B constituting the pipe gate electrode layer 31 may include, for example, polysilicon doped with impurities.

More specifically, a first conductive film 31A is formed on the substrate 30, a nitride film is deposited on the first conductive film 31A, and the nitride film is patterned to form a nitride film 32 for pipe channel formation. After that, a second conductive film 31B is formed on the first conductive film 31A exposed by the nitride film 32 . The first and second conductive films 31A and 31B form the pipe gate electrode film 31 .

Next, a first interlayer insulating layer 33 and a first gate electrode layer 34 are alternately stacked to form a plurality of memory cells stacked vertically on the process resultant.

Hereinafter, for convenience of description, a structure in which the first interlayer insulating layer 33 and the first gate electrode layer 34 are alternately stacked will be referred to as a cell gate structure CGS.

Here, the first interlayer insulating layer 33 is for separation between the plurality of layers of memory cells, and may include, for example, an oxide layer, and the first gate electrode layer 34 is, for example, poly doped with impurities. It may contain silicone. In the present embodiment, the six-layered first gate electrode layer 34 is illustrated, but the present invention is not limited thereto.

Subsequently, the cell gate structure CGS is selectively etched to form a pair of first and second holes H1 and H2 exposing the nitride layer 32 . The first and second holes H1 and H2 are spaces for forming channels of the memory cell.

Referring to FIG. 3B , a nitride layer 35 buried in the first and second holes H1 and H2 is formed. The nitride film 35 may be damaged when the first gate electrode film 34 is exposed by the first and second holes H1 and H2 in a trench formation process (refer to FIG. 3C ) to be described later. is to prevent

Referring to FIG. 3C , the cell between the pair of first and second holes H1 and H2 is such that the plurality of layers of the first gate electrode layer 34 is separated for each of the first and second holes H1 and H2. A trench S is formed by selectively etching the gate structure CGS.

Referring to FIG. 3D , a sacrificial layer 36 buried in the trench S is formed.

Referring to FIG. 3E , a second interlayer insulating layer 37 , a second gate electrode layer 38 , and a second interlayer insulating layer 37 are sequentially formed on the process resultant to form a selection transistor. Hereinafter, for convenience of description, the stacked structure of the second interlayer insulating layer 37 , the second gate electrode layer 38 , and the second interlayer insulating layer 37 is referred to as a selection gate structure SGS.

The second interlayer insulating layer 37 may include, for example, an oxide layer, and the second gate electrode layer 38 may include, for example, polysilicon doped with impurities.

Next, the selection gate structure SGS is selectively etched to form third and fourth holes H3 and H4 exposing the nitride layer 35 buried in the pair of first and second holes H1 and H2. do. The third and fourth holes H3 and H4 are regions in which channels of the selection transistor are to be formed.

Referring to FIG. 3F , the nitride film 35 exposed by the third and fourth holes H3 and H4 and the nitride film 32 thereunder are selectively removed by a wet etching process using the etching composition according to the present invention. .

As a result of this process, a pair of cell channel holes H5 and H6 in which a channel layer of a memory cell is to be formed, and a pipe channel hole H7 disposed under the cell channel holes H5 and H6 to interconnect them are formed. At this time, by using the etching composition having a high selectivity according to the present invention, the nitride film can be completely and selectively removed for a sufficient time without loss of the oxide film, so that the pipe channel can be accurately formed without loss of the profile. In addition, it is possible to prevent the generation of particles, which has been a problem in the prior art, it is possible to secure the stability and reliability of the process.

Thereafter, a subsequent process, for example, a floating gate forming process and a control gate forming process, is performed to form a flash memory device.

4A and 4B are cross-sectional views illustrating a diode formation process in a phase change memory device including an etching process using an etching composition according to another embodiment of the present invention.

Referring to FIG. 4A , an insulating structure having an opening exposing the conductive region 41 is provided on the substrate 40 . The conductive region 41 may be, for example, an n+ impurity region.

Next, a polysilicon film 42 is formed to partially fill the opening, and then impurities are ion-implanted to form a diode.

Next, a titanium silicide layer 43 is formed on the polysilicon layer 42 . The titanium silicide film 43 may be formed by heat treatment to react with the polysilicon film 42 after forming the titanium film.

Subsequently, a titanium nitride film 44 and a nitride film 45 are sequentially formed on the titanium silicide film 43 .

Next, an oxide layer 46 is formed in an isolated space between the diodes formed by performing a dry etching process using a hard mask, and then a CMP process is performed to form a primary structure of each separated lower electrode.

Referring to FIG. 4B , a wet etching process using the etching composition according to the present invention is performed on the process result to selectively remove the upper nitride layer 45 . As described above, by using the etching composition having a high selectivity according to the present invention when removing the nitride layer, the nitride layer can be completely and selectively removed for a sufficient time without loss of the oxide layer. In addition, deterioration of electrical properties and generation of particles due to damage to the film quality of the oxide film or etching of the oxide film may be prevented, thereby improving device characteristics.

Next, titanium is deposited in the space where the nitride layer 45 is removed to form a lower electrode.

In addition to the above-described process, the method of manufacturing a semiconductor device including an etching process performed using the etching composition of the present invention is a process requiring the selective removal of a nitride film, for example, a nitride film and an oxide film are alternately stacked or mixed. If there is, it can be efficiently applied to a process requiring selective etching of the nitride film.

A semiconductor device according to another embodiment of the present invention is manufactured by an etching method using the etching composition. The type of the semiconductor device is not particularly limited in the present invention.

Hereinafter, embodiments of the present invention will be described in detail so that those of ordinary skill in the art can easily carry out the present invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[ production example One: etching Preparation of composition]

< Example 1>

An etching composition was prepared by mixing 82 g of phosphoric acid, 3 g of 3% sulfuric acid, 0.001 g of a surfactant, and the remaining amount of water.

< Example 2 to 6>

It was carried out in the same manner as in Example 1, except that the concentration of sulfuric acid was changed and added as shown in Table 1 below.

< comparative example 1>

It was carried out in the same manner as in Example 1, except that sulfuric acid was not added as shown in Table 1 below.

[ Experimental example One]

For the etching compositions prepared in Examples and Comparative Examples, the etching rate was measured according to the amount of silicon oxide contained in the etching composition after etching, and the results are summarized in Table 1 and FIG. 1 below. Specifically, when the prepared etching composition was put into a beaker and reached a temperature of 15 to 40° C., the substrate on which the silicon oxide film was formed was immersed in the heated etching composition for 20 minutes, respectively, to measure the etching rate.

SN ThOx SIN/ThoX selection ratio Bp.(C) comparative example N-phosphate 63.88 1.59 40.17 157 Example 1 N-phosphate + sulfuric acid 3% 72.47 1.60 45.30 160 Example 2 N-phosphate + sulfuric acid 5% 58.41 0.62 94.2 162 Example 3 N-phosphate + sulfuric acid 10% 52.82 0.65 81.26 164 Example 4 N-phosphate + sulfuric acid 25% 41.07 0.10 410.7 174 Example 5 N-phosphate + sulfuric acid 50% 20.9 0.01 2090 215 Example 6 N-phosphate + sulfuric acid 75% 6.63 0.00 infinity 265

Referring to Table 1, it was confirmed that the boiling point of phosphoric acid increased from 157 ° C. to 160 ° C. due to the boiling point increase when sulfuric acid was added by about 3% as shown in the evaluation result. At this time, the etching rate of the silicon nitride film was increased. It was confirmed that the effect of increasing the selectivity ratio occurred.

In addition, when 5% or more of sulfuric acid is added, the temperature is excessively increased due to the boiling point rise, and the evaluation temperature is maintained at 157 ° C. It was observed that the speed decreased. In addition, the etching rate of the silicon oxide film decreased along with the decrease in the etching rate of the silicon nitride film, and it was found that selective etching of the silicon nitride film and the silicon oxide film was possible through this.

Although the preferred embodiment of the present invention has been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims are also provided. is within the scope of the

Claims (10)

phosphoric acid and sulfuric acid;
The etching composition of the sulfuric acid concentration of 3 to 75% (v / v). delete delete delete The method of claim 1,
The etching composition is an etching composition comprising 2 to 80 parts by weight of sulfuric acid based on 100 parts by weight of phosphoric acid. The method of claim 1
The etching composition has a selectivity ratio of a nitride etch rate (Å/min) to an oxide etch rate (Å/min) of 40: 1 to 2000: 1 (nitride etch rate: oxide etch rate). A method of manufacturing a semiconductor device comprising an etching process performed using the etching composition according to claim 1 . 8. The method of claim 7,
The method of manufacturing the semiconductor device further includes a subsequent process of removing particles generated in the etching process,
In the subsequent process, the particles are removed using dilute hydrofluoric acid or APM (a mixture of hydrogen peroxide and aqueous ammonia). 8. The method of claim 7,
The etching process is to selectively etch the nitride film with respect to the oxide film, and the nitride film etching process is performed at a temperature of 50 to 300 ℃ method of manufacturing a semiconductor device. 8. The method of claim 7,
forming a nitride film on the substrate;
forming a trench in the nitride film using a hard mask;
forming an oxide film to fill the trench;
performing a chemical mechanical planarization process using the nitride film as a polishing stop film until the nitride film is exposed, and
and removing the nitride layer by a wet etching process using the etching composition.

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