KR102438494B1 - Semiconductor package and method for manufacturing thereof - Google Patents

Abstract

A semiconductor package and a method of manufacturing the same are provided. A semiconductor package according to an embodiment of the present invention includes a semiconductor chip having at least one chip pad, a mold surrounding the side and one surface of the semiconductor chip, a first pattern layer and a second pattern layer disposed on the mold, a semiconductor chip and and a coefficient of thermal expansion matching layer disposed on the other surface of the mold, and a rigidity reinforcing layer disposed on one surface of the coefficient of thermal expansion matching layer.

Description

Semiconductor package and method for manufacturing the same

The present invention relates to a semiconductor package and a method for manufacturing the same.

Recently, a panel level package (PLP), which is more advantageous than a wafer level package (WLP) in terms of production cost and efficiency, is attracting attention. WLP cuts the processed wafer on a circular substrate, puts semiconductor chips on it, and performs rewiring. On the other hand, PLP works by placing semiconductor chips on a square support substrate. Because it is a square shape, there are fewer boards discarded than a circular one. Therefore, PLP can be packaged at a lower cost compared to WLP if the yield is secured.

However, in the case of the conventional PLP or WLP, an expensive carrier and an adhesive material are used to handle the package object. In this case, in the package process, a process for attaching and removing the carrier is added. Therefore, the use of the carrier increases the production cost and time required because expensive materials and expensive equipment are required. In particular, since Turn Around Time (TAT) and Bill of Material (BOM) increase, yield loss due to carrier-related processes is caused, which causes customer dissatisfaction. Accordingly, the development of a technology to replace the carrier process is required.

In order to solve the problems of the prior art as described above, an embodiment of the present invention is to provide a semiconductor package capable of improving package productivity by omitting a separate carrier-related process and a method of manufacturing the same.

However, the problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to one aspect of the present invention for solving the above problems, the semiconductor chip provided with at least one chip pad; a mold surrounding the side surface and one surface of the semiconductor chip; a first pattern layer and a second pattern layer disposed on the mold; a coefficient of thermal expansion matching layer disposed on the other surfaces of the semiconductor chip and the mold; and a rigidity reinforcing layer disposed on one surface of the coefficient of thermal expansion matching layer.

In an embodiment, the coefficient of thermal expansion matching layer may be made of the same material as the insulating pattern of the first pattern layer and the second pattern layer.

In an embodiment, the thermal expansion coefficient matching layer may be made of the same material as the mold.

In an embodiment, the rigidity reinforcing layer may have greater strength than the entirety of the mold, the first pattern layer, and the second pattern layer.

In an embodiment, in the mold, a conductive via electrically connected to the chip pad may be disposed at a position corresponding to the chip pad.

In an embodiment, each of the first pattern layer and the second pattern layer may include a wiring pattern and an insulating pattern.

According to another aspect of the present invention, there is provided a method for manufacturing a panel comprising: arranging a plurality of semiconductor chips and then molding them with a mold material; depositing a thermal expansion coefficient matching layer on one surface of the semiconductor chip and the mold formed by molding; depositing a first pattern layer on the other surface of the mold; depositing a rigidity reinforcement layer on one surface of the coefficient of thermal expansion matching layer; and depositing a second pattern layer on one surface of the first pattern layer.

In an embodiment, the coefficient of thermal expansion matching layer may be made of the same material as the insulating pattern of the first pattern layer and the second pattern layer.

In one embodiment, the coefficient of thermal expansion matching layer may be made of the same material as the mold material.

In an embodiment, the rigidity reinforcing layer may have greater strength than the entirety of the mold, the first pattern layer, and the second pattern layer.

In an embodiment, the panelizing may include forming a conductive via electrically connected to the chip pad of the semiconductor chip at a position corresponding to the chip pad of the semiconductor chip in the mold.

In an embodiment, each of depositing the first pattern layer and depositing the second pattern layer may form a wiring pattern electrically connected to the chip pad and an insulating pattern between the wiring patterns. have.

In an embodiment, the method of manufacturing the semiconductor package may include mounting a solder ball electrically connected to the chip pad on the second pattern layer; and cutting into individual elements.

In the semiconductor package and the method for manufacturing the same according to an embodiment of the present invention, since the carrier-related process can be omitted by forming the coefficient of thermal expansion matching layer and the rigidity reinforcing layer using a deposition process, package productivity can be improved.

Further, in the present invention, by omitting a separate carrier-related process, it is possible to reduce costs due to an expensive carrier and related process equipment, thereby reducing the manufacturing cost, thereby improving economic efficiency.

In addition, the present invention reduces the load of the equipment supporting and transporting the large-area panel by reducing the overall weight of the large-area panel during the process or does not require additional equipment, so the lifespan of the process equipment is improved and the equipment cost due to the addition of the equipment can save

In addition, in the present invention, by disposing a coefficient of thermal expansion matching layer of the same or similar material as the pattern layer to face the pattern layer, the same material or similar material is disposed on the top and bottom of the large-area panel to facilitate handling of the panel itself can do it

In addition, the present invention can prevent bending of a large-area panel by disposing a coefficient of thermal expansion matching layer and a rigidity reinforcing layer to support the semiconductor chip and the pattern layer, thereby minimizing the risk of product handling.

In addition, the present invention can prevent the deformation or damage of the semiconductor package due to the bending of the large-area panel by preventing the large-area panel from bending by the thermal expansion coefficient matching layer and the rigidity reinforcing layer, so that the product reliability of the semiconductor package can be guaranteed. have.

1 is a cross-sectional view illustrating a panelized state in a method of manufacturing a semiconductor package according to an embodiment of the present invention;
2 is a cross-sectional view illustrating a state in which a thermal expansion coefficient matching layer is deposited in a method of manufacturing a semiconductor package according to an embodiment of the present invention;
3 is a cross-sectional view illustrating a state in which a first pattern layer is deposited in a method of manufacturing a semiconductor package according to an embodiment of the present invention;
4 is a cross-sectional view illustrating a state in which a rigid reinforcement layer is deposited in a method of manufacturing a semiconductor package according to an embodiment of the present invention;
5 is a cross-sectional view illustrating a state in which a second pattern layer is deposited in a method of manufacturing a semiconductor package according to an embodiment of the present invention;
6 is a cross-sectional view illustrating a state after ball mounting in a method of manufacturing a semiconductor package according to an embodiment of the present invention;
7 is a cross-sectional view showing a cutting line for a cutting process in a method of manufacturing a semiconductor package according to an embodiment of the present invention;
8 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described in detail so that those of ordinary skill in the art to which the present invention pertains can easily implement them. The present invention may be embodied in many different forms and is not limited to the embodiments described herein. In order to clearly explain the present invention in the drawings, parts irrelevant to the description are omitted, and the same reference numerals are assigned to the same or similar components throughout the specification.

The embodiments of the present invention are provided to more completely explain the present invention to those of ordinary skill in the art, and the embodiments described below may be modified in various other forms, The scope is not limited to the following examples. Rather, these examples are provided so as to more fully and complete the present invention, and to fully convey the spirit of the present invention to those skilled in the art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings schematically illustrating embodiments of the present invention. In the drawings, variations of the illustrated shape may be expected, for example depending on manufacturing technology and/or tolerances. Therefore, the embodiment of the present invention should not be construed as limited to the specific shape of the region shown in this specification, but should include, for example, a change in shape caused by manufacturing.

A method for manufacturing a semiconductor package according to the present invention includes a panelizing step, a thermal expansion coefficient matching layer deposition step, a first pattern layer deposition step, a rigid reinforcement layer deposition step, a second pattern layer deposition step, a ball mounting step, and a cutting step. .

The semiconductor package manufacturing method according to an embodiment of the present invention may be applied to WLP as well as PLP. Here, the present invention is to omit an expensive and heavy carrier, but the omission of the carrier causes warpage or thermal deformation of the large-scale panel during the process.

In order to solve this problem, in the present invention, a coefficient of thermal expansion matching layer and a rigidity reinforcing layer are disposed on the opposite side of the pattern layer with respect to the panel. In this case, since a deposition process for forming the pattern layer is used for the coefficient of thermal expansion matching layer and the rigidity reinforcing layer, a separate process is not required.

Accordingly, the semiconductor package manufacturing method can reduce the process control factor by omitting the carrier-related process, so that the process can be relatively simplified and thus the package productivity can be improved.

In addition, in the semiconductor package manufacturing method, since a separate carrier-related process is omitted, costs associated with an expensive carrier and related process equipment can be reduced, thereby reducing manufacturing cost, and thus improving economic efficiency.

In addition, the semiconductor package manufacturing method can reduce the load of equipment supporting or transporting the large-area panel by reducing the overall weight of the large-area panel during the process by omitting a relatively heavy carrier, thereby improving the lifespan of the process equipment. have. In addition, in the semiconductor package manufacturing method, it is not necessary to install special equipment to compensate for the load, so that equipment costs due to the addition of equipment can be reduced.

In the method of manufacturing a semiconductor package according to an embodiment of the present invention, first, a plurality of semiconductor chips 110 are molded into a panel.

1 is a cross-sectional view illustrating a panelized state in a method of manufacturing a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 1 , a plurality of semiconductor chips 110 are disposed on a rectangular panel (not shown). Here, the semiconductor chip 110 may include at least one chip pad 112 according to its function. For simplicity of the drawing, the semiconductor chip 110 is shown with two chip pads 112 . In addition, for the sake of simplification of the drawings, panels are omitted.

Next, the semiconductor chip 110 is molded using a mold to form a panel. Here, the molding agent may be EMC (Epoxy Molding Compound). The mold 120 may be formed to surround the side surface and one surface of the semiconductor chip 110 by using a mold material.

In FIG. 1 , one surface is a surface provided with the chip pad 112 in the semiconductor chip 110 , and is an upper surface in the longitudinal direction of the semiconductor chip 110 , and the other surface is the opposite surface of the chip pad 112 in the semiconductor chip 110 . , which means the lower surface of the semiconductor chip 110 in the longitudinal direction, and the side surface means both surfaces in the thickness direction of the semiconductor chip 110 .

At this time, a conductive via 114 is formed on one surface of the mold 120 at a position corresponding to the chip pad 112 . The conductive via 114 is for electrically connecting the chip pad 112 to the outside through a pattern layer as will be described later. That is, the conductive via 114 may be formed to be exposed through one surface (top surface in FIG. 1 ) of the mold 120 .

Next, a thermal expansion coefficient matching layer 130 is deposited on one surface of the semiconductor chip 110 and the mold 120 .

Here, in the process of forming the pattern layer as described later on the large-area panel, the warpage of the panel gradually increases due to a stress index such as a coefficient of expansion (CTE) and a modulus of elasticity (Young's Modulus). while handling is difficult.

In order to solve this problem, in the present invention, the coefficient of thermal expansion matching layer 130 and the rigidity reinforcing layer 150 are disposed to make the stress index uniform over the entire large area panel. 2 is a cross-sectional view illustrating a state in which a thermal expansion coefficient matching layer is deposited in a method of manufacturing a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 2 , a thermal expansion matching layer 130 is deposited on the semiconductor chip 110 and the other surface (top surface in FIG. 2 ) of the mold 120 by rotating the large-area panel of FIG. 1 by 180 degrees. In this case, the coefficient of thermal expansion matching layer 130 may be made of the same or similar material to the insulating patterns 144 and 164 of the first and second pattern layers 140 and 160 to be described later.

Here, since the coefficient of thermal expansion matching layer 130 is formed using the deposition process of the first pattern layer 140 and the second pattern layer 160 , an additional separate process is not required. Therefore, it is possible to reduce the cost of the additional process, so that productivity and economic efficiency can be improved.

Alternatively, the coefficient of thermal expansion matching layer 130 may be made of the same material as the mold material. In this case, the semiconductor chip 110 may be completely blocked from the outside by being surrounded by the mold 120 and the coefficient of thermal expansion matching layer 130 .

As such, by disposing the same material or similar material at the top and bottom of the large-area panel, the semiconductor package manufacturing method can reduce the coefficient of thermal expansion of the large-area panel, thereby suppressing the bending of the large-area panel, and thus the panel It can facilitate its own handling.

Next, a first pattern layer 140 is deposited on the other surface of the mold 120 .

3 is a cross-sectional view illustrating a state in which a first pattern layer is deposited in a method of manufacturing a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 3 , the first pattern layer 140 is deposited on one surface (top surface in FIG. 3 ) of the mold 120 by rotating the large-area panel of FIG. 2 by 180 degrees. In this case, the first pattern layer 140 may include a first wiring pattern 142 and a first insulating pattern 144 .

The first wiring pattern 142 may be formed to be electrically connected to the conductive via 114 exposed on the mold 120 . That is, the first wiring pattern 142 may be electrically connected to the chip pad 112 of the semiconductor chip 110 . The first wiring pattern 142 may be made of a conductive material. For example, the first wiring pattern 142 may be formed of W, Cu, Zr, Ti, Ta, Al, Ru, Pd, Pt, Co, Ni, or a combination thereof.

The first insulating pattern 144 may be formed to cover one surface of the mold 120 on which the first wiring pattern 142 is not formed. In this case, the first insulating pattern 144 may be formed to be planarized to have the same thickness as the first wiring pattern 142 .

Here, the first insulating pattern 144 may be formed of an insulating polymer, an epoxy, a silicon oxide layer, a silicon nitride layer (SiN), or a combination thereof. Also, the first insulating pattern 144 may be made of a non-photosensitive material or a photosensitive material. For example, the first insulating pattern 144 may be made of polyimide (PI).

In this case, the insulating polymer is a general-purpose polymer such as PMMA (Polymethylmethacrylate), PS (Polystylene), PBO (Polybenzoxzaoles), etc., an acrylic polymer, an imide polymer (polyimide (PI)), an aryl ether polymer, an amide polymer, and a fluorine polymer , a p-xylene-based polymer, a vinyl alcohol-based polymer, a polymer derivative having a phenol-based group, or a combination thereof.

Next, a rigidity reinforcement layer 150 is deposited on one surface of the coefficient of thermal expansion matching layer 130 .

4 is a cross-sectional view illustrating a state in which a rigid reinforcement layer is deposited in a method of manufacturing a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 4 , the rigidity reinforcing layer 150 is deposited on one surface (top surface in FIG. 4 ) of the thermal expansion coefficient matching layer 130 by rotating the large-area panel of FIG. 3 by 180 degrees. In this case, the rigidity reinforcing layer 150 may have greater strength than the entire mold 120 , the first pattern layer 140 , and the second pattern layer 160 .

That is, the rigidity reinforcing layer 150 is to suppress the degree of bending of the large-area panel according to the formation of the first pattern layer 140 and the second pattern layer 160 , and may be made of a material having high hardness. Therefore, the semiconductor package manufacturing method can improve the modulus of elasticity of the large-area panel, thereby suppressing the bending of the large-area panel.

As such, the deposition of the coefficient of thermal expansion matching layer 130 and the deposition of the rigidity enhancement layer 150 may be performed before deposition of the first pattern layer 140 and the second pattern layer 160 .

Thereby, the semiconductor package manufacturing method can make the coefficient of thermal expansion and the elastic modulus uniform over the entire large-area panel, thereby suppressing the bending of the large-area panel, and thus minimizing the risk to the handling of the product during the packaging process.

In addition, the semiconductor package manufacturing method can minimize the deformation or damage of the semiconductor package finally manufactured due to the bending of the large-area panel, so that the product reliability of the semiconductor package can be guaranteed.

Next, a second pattern layer 160 is deposited on one surface of the first pattern layer 140 .

5 is a cross-sectional view illustrating a state in which a second pattern layer is deposited in a method of manufacturing a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 5 , the second pattern layer 160 is deposited on one surface (top surface in FIG. 5 ) of the first pattern layer 140 by rotating the large-area panel of FIG. 4 by 180 degrees. In this case, the second pattern layer 160 may include a second wiring pattern 162 and a second insulating pattern 164 .

The second wiring pattern 162 may be formed to be electrically connected to the first wiring pattern 142 exposed on the first pattern layer 140 . The second wiring pattern 162 may be made of the same material as the first wiring pattern 142 .

The second insulating pattern 164 may be formed to cover one surface of the first pattern layer 140 on which the second wiring pattern 162 is not formed. In this case, the second insulating pattern 164 may be formed to be planarized to have the same thickness as the second wiring pattern 162 . The second insulating pattern 164 may be made of the same material as the first insulating pattern 144 .

Next, the solder balls 170 are mounted on the second pattern layer 160 .

6 is a cross-sectional view illustrating a state after ball mounting in a method of manufacturing a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 6 , a solder ball 170 is mounted on the second wiring pattern 162 of the second pattern layer 160 . The solder ball 170 may be electrically connected to the chip pad 112 of the semiconductor chip 110 through the first pattern layer 140 and the second pattern layer 160 . That is, the solder ball 170 may be an external terminal of the semiconductor package.

Here, for the sake of simplification of the drawings, one solder ball 170 is provided, but may be provided according to the number of chip pads 112 of the semiconductor chip 110 .

In this case, the solder ball 170 may be formed on the under bump metallurgy (UBM) layer 172 . The UBM layer 172 may be formed to be exposed to the outside on the second wiring pattern 162 . That is, the UBM layer 172 electrically connects the solder ball 170 and the second wiring pattern 162 .

Here, the solder ball 170 may include Sn, Au, Ag, Ni, In, Bi, Sb, Cu, Zn, Pb, or a combination thereof, but is not limited thereto. For example, the solder ball 170 may be formed of a Sn-Ag-Cu (SAC) series.

Next, the large-area panel is cut into individual elements.

7 is a cross-sectional view illustrating a cutting line for a cutting process in a method of manufacturing a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 7 , a large-area panel is cut based on a cutting line (X). Here, the cutting line X is a line indicating a unit area for dividing the semiconductor chip 110 into a single product in the large-area panel.

The semiconductor package 100 of an individual device may be manufactured by such a process.

8 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 8 , the semiconductor package 100 includes a semiconductor chip 110 , a mold 120 , a coefficient of thermal expansion matching layer 130 , a first pattern layer 140 , a rigidity reinforcement layer 150 , and a second pattern layer. 160 and a ball 170 .

The semiconductor package 100 may be a fan-out panel wafer level package (FOPLP). Although only one solder ball 170 is illustrated in the drawing, the number of balls 170 may correspond to the number of chip pads 112 of the semiconductor chip 110 included in the semiconductor package 100 .

The semiconductor chip 110 may be a memory semiconductor chip or a logic chip. Also, the semiconductor chip 110 may include various types of individual devices. In this case, the semiconductor chip 110 may include at least a chip pad 112 .

The mold 120 surrounds both sides and one surface (the upper surface in the drawing) of the semiconductor chip 110 , that is, the mold 120 is the semiconductor chip 110 except for the other surface (the lower surface in FIG. 8 ) of the semiconductor chip 110 . It surrounds the perimeter of. In this case, the mold 120 may be made of EMC.

Here, the conductive via 114 may be disposed in the mold 120 at a position corresponding to the chip pad 112 of the semiconductor chip 110 . Here, the conductive via 114 is for electrically connecting the chip pad 112 to the solder ball 170 .

The coefficient of thermal expansion matching layer 130 may be disposed on the other surface (lower surface in FIG. 8 ) of the semiconductor chip 110 and the mold 120 . Here, the coefficient of thermal expansion matching layer 130 may be made of the same or similar material to the insulating patterns 144 and 164 of the first pattern layer 140 and the second pattern layer 160 . Alternatively, the coefficient of thermal expansion matching layer 130 may be made of the same material as the mold 120 .

The rigidity reinforcing layer 150 may be disposed on one surface (lower surface in FIG. 8 ) of the coefficient of thermal expansion matching layer 130 . In this case, the rigidity reinforcing layer 150 may have greater strength than the entire mold 120 , the first pattern layer 140 , and the second pattern layer 160 .

The first pattern layer 140 and the second pattern layer 160 may be a redistribution layer (RDL).

The first pattern layer 140 may be disposed on the mold 120 . Here, the first pattern layer 140 may include a first wiring pattern 142 and a first insulating pattern 144 .

The first wiring pattern 142 may be electrically connected to the conductive via 114 provided on the mold 120 . That is, the first wiring pattern 142 may be electrically connected to the chip pad 112 of the semiconductor chip 110 through the conductive via 114 . The first wiring pattern 142 may be made of a conductive material.

The first insulating pattern 144 may be disposed to cover one surface of the mold 120 on which the first wiring pattern 142 is not provided. In this case, the first insulating pattern 144 may be provided to have the same thickness as the first wiring pattern 142 .

The second pattern layer 160 may be disposed on the first pattern layer 140 . Here, the second pattern layer 160 may include a second wiring pattern 162 and a second insulating pattern 164 .

The second wiring pattern 162 may be provided to be electrically connected to the first wiring pattern 142 of the first pattern layer 140 . The second wiring pattern 162 may be made of the same material as the first wiring pattern 142 .

The second insulating pattern 164 may be disposed to cover one surface of the first pattern layer 140 on which the second wiring pattern 162 is not provided. In this case, the second insulating pattern 164 may be provided to have the same thickness as the second wiring pattern 162 . The second insulating pattern 164 may be made of the same material as the first insulating pattern 144 .

The solder ball 170 may be provided on the second wiring pattern 162 . In this case, the solder ball 170 may be provided through the UBM layer 172 . The UBM layer 172 may be provided on the second wiring pattern 162 . That is, the UBM layer 172 electrically connects the solder ball 170 and the second wiring pattern 162 .

Although one embodiment of the present invention has been described above, the spirit of the present invention is not limited to the embodiments presented herein, and those skilled in the art who understand the spirit of the present invention can add components within the scope of the same spirit. , changes, deletions, additions, etc. may easily suggest other embodiments, but this will also fall within the scope of the present invention.

100: semiconductor package 110: semiconductor chip
112: chip pad 114: conductive via
120: mold 130: thermal expansion coefficient matching layer
140: first pattern layer 142: first wiring pattern
144: first insulating pattern 150: rigid reinforcement layer
160: second pattern layer 162: second wiring pattern
164: second insulating pattern 170: ball

Claims (15)

a semiconductor chip provided with at least one chip pad;
a mold surrounding the side surface and one surface of the semiconductor chip;
a first pattern layer and a second pattern layer disposed on one surface of the mold and including a wiring pattern and an insulating pattern, respectively;
It is disposed on the other surface of the semiconductor chip and the mold, and is made of a material having the same coefficient of thermal expansion as that of the insulating pattern of the first and second pattern layers, and is deposited before the first and second pattern layers. coefficient of thermal expansion matching layer; and
It is disposed on one surface of the coefficient of thermal expansion matching layer, has greater strength than the entirety of the mold, the first pattern layer and the second pattern layer, and is deposited between the first pattern layer and the second pattern layer. floor;
including,
A semiconductor package in which a layer made of a material having the same coefficient of thermal expansion is formed on one surface and the other surface of the mold to prevent distortion due to a difference in coefficient of thermal expansion between one surface and the other surface of the mold.
delete delete delete According to claim 1,
In the mold, a conductive via electrically connected to the chip pad is disposed at a position corresponding to the chip pad. delete A method of manufacturing a semiconductor package for manufacturing the semiconductor package of any one of claims 1 and 5, comprising:
forming a panel by arranging a plurality of semiconductor chips and then molding with a mold;
depositing a thermal expansion matching layer made of a material having the same thermal expansion coefficient as that of the insulating pattern of the first pattern layer and the second pattern layer on one surface of the semiconductor chip and the mold formed by molding;
depositing the first pattern layer on the other surface of the mold;
depositing a rigidity reinforcing layer having greater strength than the entirety of the mold, the first pattern layer and the second pattern layer on one surface of the thermal expansion coefficient matching layer; and
depositing the second pattern layer on one surface of the first pattern layer;
Including, a layer made of a material having the same coefficient of thermal expansion is formed on one surface and the other surface of the mold to prevent distortion due to a difference in coefficient of thermal expansion between one surface and the other surface of the mold.
delete delete delete 8. The method of claim 7,
The panelizing may include forming a conductive via electrically connected to the chip pad at a position corresponding to the chip pad of the semiconductor chip in the mold. 8. The method of claim 7,
Depositing the first pattern layer and depositing the second pattern layer each form a wiring pattern electrically connected to the chip pad of the semiconductor chip and form an insulating pattern between the wiring patterns. manufacturing method. 8. The method of claim 7,
mounting a solder ball electrically connected to a chip pad of the semiconductor chip on the second pattern layer; and
Method of manufacturing a semiconductor package further comprising the step of cutting into individual elements. a semiconductor chip provided with at least one chip pad;
a mold surrounding the side and one surface of the semiconductor chip;
a first pattern layer and a second pattern layer disposed on one surface of the mold and each including a wiring pattern and an insulating pattern;
It is disposed on the other surface of the semiconductor chip and the mold, and the ratio of the coefficient of thermal expansion between the insulating pattern of the first pattern layer and the second pattern layer is in the range of 0.8 to 1.2, and the first pattern layer and the second pattern layer are made of a material. a coefficient of thermal expansion matching layer deposited before the pattern layer; and
It is disposed on one surface of the coefficient of thermal expansion matching layer, has greater strength than the entirety of the mold, the first pattern layer and the second pattern layer, and is deposited between the first pattern layer and the second pattern layer. floor;
Including, a layer made of a material having the same coefficient of thermal expansion is formed on one surface and the other surface of the mold to prevent distortion due to a difference in coefficient of thermal expansion between one surface and the other surface of the mold. A semiconductor package manufacturing method for manufacturing the semiconductor package of claim 14,
forming a panel by arranging a plurality of semiconductor chips and then molding with a mold;
depositing a coefficient of thermal expansion matching layer made of a material having a ratio of a coefficient of thermal expansion between the insulating pattern of the first pattern layer and the second pattern layer on one surface of the semiconductor chip and the mold formed by molding;
depositing the first pattern layer on the other surface of the mold;
depositing a rigidity reinforcing layer having greater strength than the entirety of the mold, the first pattern layer and the second pattern layer on one surface of the thermal expansion coefficient matching layer; and
depositing the second pattern layer on one surface of the first pattern layer;
Including, a layer made of a material having the same coefficient of thermal expansion is formed on one surface and the other surface of the mold to prevent distortion due to a difference in coefficient of thermal expansion between one surface and the other surface of the mold.

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