KR102436531B1 - A pixel circuit of a display panel and a display apparatus - Google Patents

Abstract

A pixel circuit of a display panel is disclosed. The pixel circuit includes a light emitting device that emits light according to a driving current, and a driving transistor connected to the light emitting device, and provides a driving current of different amplitude to the light emitting device according to the magnitude of a voltage applied to a gate terminal of the driving transistor. a current source, an amplitude setting circuit for applying voltages of different magnitudes to the gate terminal of the driving transistor, and a pulse width control circuit for controlling the duration of the driving current by controlling the voltage applied to the gate terminal of the driving transistor include

Description

A pixel circuit of a display panel and a display device

The present disclosure relates to a pixel circuit and a display device of a display panel, and more particularly, to a pixel circuit and a display device of a display panel that express grayscale according to the amplitude and duration of a driving current.

In the conventional LED (Light Emitting Diode) display panel, PM (Passive Matrix) driving has been the mainstream, but AM (Active Matrix) driving is required for low power consumption. Recently, an AM driving circuit has been applied to OLED (Organic Light Emitting Diode) display panels. However, unlike OLEDs, in the case of LEDs, color shift according to the deviation of the forward voltage (Vf) between LEDs or the size of the driving current is higher than that of OLEDs. It is difficult to apply the AM driving circuit applied to the cursor OLED display to the LED display as it is.
Specifically, a PAM (Pulse Amplitude Modulation) driving method in which the amplitude of the driving current is different for each gradation for gradation expression is widely used in OLED displays. This greatly varying color shift problem occurs.
In addition, in the PWM (Pulse Width Modulation) driving method in which the pulse width (or duty ratio) of the driving current is varied according to the gray level, the conventional PWM driving circuit drives the TFT (Thin Film Transistor) in a linear operation region, so that the There is a problem in that a luminance difference according to a forward voltage deviation is greatly generated. In particular, in the case of the digital PWM method, since grayscales are expressed using the subfield method, there is a limit to the number of grayscales that can be expressed, and a pseudo contour problem occurs.
Accordingly, there is a need for a low-power AM driving circuit having high luminance uniformity and low color shift.

SUMMARY The present disclosure has been made in accordance with the above-described problems, and an object of the present disclosure is to provide a pixel circuit and a display device of a display panel having high luminance uniformity and low color shift during driving.

A pixel circuit of a display panel according to an embodiment of the present invention for achieving the above object includes a light emitting device that emits light according to a driving current, a driving transistor connected to the light emitting device, and a gate terminal of the driving transistor. A current source providing driving currents of different amplitudes to the light emitting element according to the magnitude of the voltage applied to the light emitting device, an amplitude setting circuit for applying voltages of different amplitudes to the gate terminals of the driving transistors, and applied to the gate terminals of the driving transistors and a pulse width control circuit for controlling the duration of the driving current by controlling the applied voltage.
Also, in the amplitude setting circuit, a first capacitor having one end connected to the first end of the driving transistor and a first end commonly connected to the other end of the first capacitor and a gate terminal of the driving transistor, and a second end It may include a first transistor receiving the amplitude setting voltage.
In addition, the amplitude setting circuit is configured to charge the amplitude setting voltage to the first capacitor while the first transistor is turned on according to a first enable signal input to the gate terminal of the first transistor, and to the first capacitor. The charged voltage may be applied to the gate terminal of the driving transistor.
In addition, when a driving voltage is applied to the current source while the voltage charged in the first capacitor is applied to the gate terminal of the driving transistor, the current source has an amplitude corresponding to the magnitude of the voltage charged in the first capacitor. A driving current may be provided to the light emitting device.
Also, in the amplitude setting circuit, a second transistor having a first end connected to a second end of the driving transistor, a gate terminal connected to a gate terminal of the first transistor, and a second end receiving an amplitude setting current. and charging the first capacitor with a voltage corresponding to the amplitude setting current while the first and second transistors are turned on according to a first enable signal input to the gate terminal of the first transistor, and The voltage charged in the first capacitor may be applied to the gate terminal of the driving transistor.
The pulse width control circuit may include an inverter having an output terminal connected to a gate terminal of the driving transistor, and when a first voltage applied to an input terminal of the inverter changes linearly and reaches a preset threshold voltage, the The output terminal voltage of the inverter may be the ground voltage or the driving voltage of the current source to control the duration of the driving current.
In addition, the driving current may continue from a point in time when the driving voltage is applied to the current source until a point in time when an output terminal voltage of the inverter becomes the ground voltage or the driving voltage.
In addition, the pulse width control circuit includes a switching element connected between an input terminal and an output terminal of the inverter, and a second capacitor having one end connected to the input terminal of the inverter, and setting a pulse width at the other end of the second capacitor When the switching element is turned on while the voltage is input, the input terminal of the inverter is set to the preset threshold voltage while the switching element is turned on, and when the input of the pulse width setting voltage is completed, the input terminal voltage of the inverter is The first voltage may be set at a preset threshold voltage.
Also, the first voltage may be a difference value between the preset threshold voltage and the pulse width setting voltage.
Also, in the pulse width control circuit, as the driving voltage is applied to the current source and a linear change voltage is input to the other end of the second capacitor, the first voltage may be linearly changed.
In addition, the inverter and the switching element are an N-channel Metal Oxide Semiconductor Field Effect Transistor (NMOSFET), and in the inverter, a drain terminal is connected to a gate terminal of the driving transistor, and a gate terminal is one of the second capacitors. terminal, the source terminal is connected to the ground, the switching element has a drain terminal commonly connected to a gate terminal of the inverter and one end of the second capacitor, and a source terminal is connected to the drain terminal of the inverter and the driving transistor It is commonly connected to a gate terminal, and when the first voltage applied to the gate terminal of the inverter increases linearly to reach the preset threshold voltage, the drain terminal voltage of the inverter may become the ground voltage.
In addition, the pulse width control circuit may include, when a second enable signal is input to the gate terminal of the switching element while a pulse width setting voltage of a second voltage is input to the other terminal of the second capacitor, the second enable signal While the switching element is turned on according to a signal, the voltage of the gate terminal of the inverter is set to the preset threshold voltage, and as the pulse width set voltage drops from the second voltage to 0, the gate terminal voltage of the inverter is It may fall from the set preset threshold voltage to the first voltage.
In addition, the inverter and the switching element are a P-channel Metal Oxide Semiconductor Field Effect Transistor (PMOSFET), and in the inverter, a drain terminal is connected to a gate terminal of the driving transistor, and a gate terminal is one of the second capacitors. is connected to a terminal, a source terminal is connected to a driving voltage input terminal of the current source, and the switching element has a source terminal commonly connected to a gate terminal of the inverter and one end of the second capacitor, and a drain terminal is connected to a drain terminal of the inverter and a gate terminal of the driving transistor, and when the first voltage applied to the gate terminal of the inverter linearly decreases to reach the preset threshold voltage, the drain terminal voltage of the inverter is the driving voltage of the current source this can be
In addition, the pulse width control circuit may include, when a third enable signal is input to a gate terminal of the switching element while a pulse width setting voltage of a third voltage is input to the other terminal of the second capacitor, the third enable signal While the switching element is turned on according to a signal, the voltage of the gate terminal of the inverter is set to the preset threshold voltage, and as the pulse width setting voltage rises from the third voltage to 0, the gate terminal voltage of the inverter is It may rise from the set preset threshold voltage to the first voltage.
In addition, the pulse width control circuit includes a Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOSFET) inverter having an output terminal connected to an input terminal of the inverter, a third capacitor having one end connected to an input terminal of the CMOSFET inverter, and an input terminal of a single CMOSFET inverter and a switching element connected between an output terminal, wherein when the switching element is turned on while a pulse width set voltage is input to the other terminal of the third capacitor, the input terminal of the inverter is turned on to the preset voltage while the switching element is turned on is set, and when the input of the pulse width set voltage is completed, the input terminal voltage of the inverter may be the first voltage at the set preset threshold voltage.
In addition, an amplitude setting circuit for applying voltages of different magnitudes to the gate terminal of the driving transistor and a third transistor electrically separating the amplitude setting circuit and the pulse width control circuit until the driving voltage is applied to the current source may include
In addition, the driving transistor may operate in a saturation region of an operating region of the driving transistor.
In addition, the light emitting device may be a light emitting diode (LED) or an organic light emitting diode (OLED).
Meanwhile, the display device according to an embodiment of the present disclosure includes a plurality of pixel circuits, and is applied to a display panel for displaying an image, a panel driver for driving the display panel, and a light emitting device included in the plurality of pixel circuits. and a processor for expressing the grayscale of the image based on at least one of an amplitude and a duration of a driving current, wherein each of the plurality of pixel circuits includes a light emitting device that emits light according to the driving current and is connected to the light emitting device a driving transistor comprising a current source providing a driving current having a different amplitude to the light emitting device according to the magnitude of a voltage applied to the gate terminal of the driving transistor, and controlling the voltage applied to the gate terminal of the driving transistor to control the driving current includes a pulse width control circuit that controls the duration of

As described above, according to various embodiments of the present disclosure, it is possible to provide a pixel circuit and a display device of a display panel having high luminance uniformity and low color shift.

1 is a block diagram of a pixel circuit according to an embodiment of the present disclosure;
2A and 2B are circuit diagrams schematically illustrating a pixel circuit according to an embodiment of the present disclosure;
3A and 3B are diagrams for explaining the operation of a pixel circuit when a driving transistor included in a current source is an NMOSFET or a PMOSFET;
4A is a circuit diagram illustrating a detailed configuration of a pixel circuit according to an embodiment of the present disclosure;
4B and 4C are a timing diagram and a circuit diagram for explaining a detailed operation of a pixel circuit according to an embodiment of the present disclosure;
4D is a timing diagram for various data signals and control signals input to a display panel including the pixel circuit of FIG. 4A;
5A is a circuit diagram of a pixel circuit according to another embodiment of the present disclosure;
5B is a timing diagram of various data signals and control signals input to a display panel composed of pixel circuits such as the pixel circuit of FIG. 5A;
6 is a circuit diagram of a pixel circuit according to another embodiment of the present disclosure;
7 is a circuit diagram of a pixel circuit according to another embodiment of the present disclosure;
8A, 8B, and 9 are circuit diagrams and timing diagrams for explaining various embodiments in which all transistors included in a pixel circuit are PMOSFETs according to an embodiment of the present disclosure;
10A and 10B are exemplary views in which a compensation circuit is applied to a pixel circuit according to an embodiment of the present disclosure;
11 is a block diagram of a display device according to an embodiment of the present disclosure;
12 is a flowchart illustrating a method of driving a display apparatus according to an embodiment of the present disclosure; and
13 is a conceptual diagram for comparing a pixel circuit according to an embodiment of the present disclosure and a prior art.

In describing the present disclosure, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present disclosure, the detailed description thereof will be omitted. In addition, the suffix "part" for the components used in the following description is given or mixed in consideration of only the ease of writing the specification, and does not have a meaning or role distinct from each other by itself.
The terms used herein are used to describe the embodiments, and are not intended to limit and/or limit the present disclosure. The singular expression includes the plural expression unless the context clearly dictates otherwise.
In this specification, terms such as 'comprising' or 'having' are intended to designate that the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification exist, but one or more other features It is to be understood that this does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.
In addition, in an embodiment of the present disclosure, when a part is connected to another part, this includes not only direct connection but also indirect connection through another medium. In addition, the meaning that a certain part includes a certain component means that other components may be further included without excluding other components unless otherwise stated.
1 is a block diagram of a pixel circuit according to an exemplary embodiment. In general, a display device includes a display panel, and the display panel includes a plurality of pixels. In this case, each of the plurality of pixels included in the display panel may be implemented as a light emitting device and a peripheral circuit for driving the light emitting device for its operation. Referring to FIG. 11 , in various embodiments of the present disclosure, a pixel circuit 100 refers to a circuit constituting each of a plurality of pixels of a display panel 500 .
Referring to FIG. 1 , the pixel circuit 100 includes an amplitude setting circuit 110 , a current source 120 , a light emitting device 130 , and a pulse width control circuit 140 .
The light emitting device 130 emits light according to a driving current provided by the current source 120 . Specifically, the light emitting device 130 may emit light with different luminance according to the amplitude of the driving current provided by the current source 120 or the pulse width of the driving current. Here, the pulse width of the driving current may be expressed as a duty ratio of the driving current or a driving time of the driving current (Duration).
For example, the light emitting device 130 may emit light with a higher luminance as the amplitude of the driving current increases, and may emit light with a higher luminance as the pulse width is longer (ie, the duty ratio is higher or the driving time is longer). It is not limited.
Meanwhile, the light emitting device 130 may be a Light Emitting Diode (LED) or an Organic Light Emitting Diode (OLED).
The current source 120 provides a driving current to the light emitting device 130 . In particular, the current source 120 includes driving transistors 125-1 and 125-2 connected to the light emitting device 130 as shown in FIGS. 2A and 2B, and A driving current having a different amplitude may be provided to the light emitting device according to the magnitude of the voltage applied to the gate terminal.
Specifically, the current source 120 may provide a driving current having an amplitude set through the amplitude setting circuit 110 to the light emitting device 130 , and a driving current having a pulse width set by the pulse width control circuit 140 . may be provided as the light emitting device 130 .
The amplitude setting circuit 110 may set the amplitude of the voltage to be applied to the gate terminals 125 - 1 and 125 - 2 of the driving transistor included in the current source 120 according to the amplitude data. Here, the amplitude data may be an amplitude setting voltage to be described later, but is not limited thereto.
The pulse width control circuit 140 may control the duration of the driving current by controlling the voltage applied to the gate terminals 125-1 and 125-2 of the driving transistor included in the current source 120 according to the pulse width data. have. Here, the pulse width data may be a pulse width setting voltage to be described later, but is not limited thereto.
2A and 2B are circuit diagrams schematically illustrating a pixel circuit according to an embodiment of the present disclosure. In the description of FIGS. 2A to 2B , descriptions of content overlapping with those described in FIG. 1 will be omitted.
FIG. 2A shows a pixel circuit 100-1 in which a driving transistor included in the current source 120 is an N-channel Metal Oxide Semiconductor Field Effect Transistor (NMOSFET), and FIG. 2B shows a driving transistor included in the current source 120 is a PMOSFET. A pixel circuit 100-2 that is (P-channel Metal Oxide Semiconductor Field Effect Transistor) is shown.
As shown in FIGS. 2A and 2B , the current source 120 of the pixel circuits 100-1 and 100-2) includes driving transistors 125-1 and 125-2, and the driving transistors 125-1, 125-1, It can be seen that one end of 125-2) is connected to the light emitting device 130 . For example, the driving transistors 125 - 1 and 125 - 2 , the driving voltage terminal 121 , and the ground terminal 122 may constitute the current source 120 , but the present invention is not limited thereto.
Specifically, according to FIG. 2A , when the driving transistor 125-1 is an NMOSFET, the drain terminal of the driving transistor 125-1 is a driving voltage terminal (VDD) to which the driving voltage VDD is applied through the light emitting device 130 . 121 , and the source terminal is connected to the ground terminal 122 . Accordingly, when a voltage greater than or equal to the threshold voltage is applied between the gate terminal and the source terminal of the driving transistor 125 - 1 , the driving transistor 125 - 1 conducts and is driven from the driving voltage terminal 121 to the ground terminal VSS. Current flows so that the light emitting device 130 can emit light.
Meanwhile, according to FIG. 2B , when the driving transistor 125 - 2 is a PMOSFET, the source terminal of the driving transistor 125 - 2 is connected to the driving voltage terminal 121 , and the drain terminal of the driving transistor 125 - 2 connects the light emitting device 130 . It is connected to the ground terminal 122 through the. In this case, when a voltage equal to or less than the threshold voltage is applied between the gate terminal and the source terminal of the driving transistor 125 - 2 , the driving transistor 125 - 2 conducts, and the driving voltage terminal 121 to the ground terminal 122 . ), a driving current flows so that the light emitting device 130 can emit light.
Here, the threshold voltage of the NMOSFET may have a positive value and the threshold voltage of the PMOSFET may have a negative value, but is not limited thereto. Also, the voltage VSS of the ground terminal 122 to which the source terminal of the NMOSFET or the drain terminal of the PMOSFET is connected may be an O volt voltage, but is not limited thereto. of course there is
Hereinafter, operations of the driving transistors 125 - 1 and 125 - 2 according to an embodiment of the present disclosure will be described in more detail with reference to FIGS. 3A and 3B .
FIG. 3A is a diagram for explaining a case where the driving transistor 125 - 1 included in the current source 120 is an NMOSFET.
FIG. 3A (a) illustrates the current source 120 and the light emitting device 130 of the pixel circuit 100-1 of FIG. 2A. As shown in (a) of FIG. 3A , when the driving transistor is an NMOSFET 125-1, the drain terminal of the NMOSFET 125-1 is connected to the cathode terminal of the light emitting device 130, and the source terminal is the ground. connected to terminal 122 . In addition, the anode terminal of the light emitting device 130 is connected to the driving voltage terminal 121 of the current source. Accordingly, when the NOMSFET 125-1 is turned on according to the gate terminal voltage of the NMOSFET 125-1, the current source 120 may provide the driving current I to the light emitting device.
Meanwhile, FIG. 3A (b) is a graph showing voltage-current characteristics of the NMOSFET 125-1. In (b) of FIG. 3A , the horizontal axis represents the drain-source voltage (Vds) of the NMOSFET 125-1, and the vertical axis represents the current (I) flowing from the drain terminal to the source terminal according to the drain-source voltage (Vds). indicates
As shown in (b) of FIG. 3A , in the NMOSFET 125-1, when the gate-source voltage Vgs is equal to or greater than the threshold voltage, the gate-source voltage Vgs increases (that is, at V ₀ ). As it goes to V ₃ ), more current I flows. Accordingly, the current source 120 may provide a driving current having a different amplitude to the light emitting device 130 according to the magnitude of the voltage applied to the gate terminal of the driving transistor 125 - 1 .
Also, the NMOSFET 125 - 1 may operate in a linear region or a saturation region according to a drain-source voltage Vds for each gate-source voltage Vgs equal to or greater than a threshold voltage. Here, the linear region is an operation region in which the current I flowing from the drain terminal to the source terminal increases as the drain-source voltage Vds increases, and the saturation region is the drain irrespective of the change in the drain-source voltage Vds. The current (I) flowing from the terminal to the source terminal is a constant operating region. That is, as shown in (b) of FIG. 3A , the NMOSFET 125-1 has a linear region and a saturation region when Vgs is V ₀ to V ₃ , respectively.
Meanwhile, the driving voltage VDD applied to the driving voltage terminal 121 is distributed between the NMOSFET 125 - 1 and the light emitting device 130 as Vled and Vds as shown in (a) of FIG. 3A . Here, Vds is the voltage between the drain-source terminals of the NMOSFET 125-1, and Vled is the forward voltage Vf of the light emitting device 130, that is, a voltage required for the light emitting device 130 to emit light.
As shown in (b) of FIG. 3A , the forward voltage Vf of the light emitting device may have a deviation for each light emitting device. Due to this variation, the light emitting device operates in the linear region of the driving transistor 125 - 1 . In this case, as the voltage distribution between Vled and Vds is changed, the driving current I is changed, so that even with the same driving voltage (VDD), a luminance deviation occurs between the light emitting devices.
However, according to an embodiment of the present disclosure, the pixel circuits 100 - 1 and 100 - 2 are amplitude setting circuits for applying voltages of different magnitudes to the gate terminals of the driving transistors 125 - 1 and 125 - 2 . Since 110 is included, the operating point of the driving transistor 125 - 1 is set through the amplitude setting circuit 110 so that the light emitting device 130 operates in the saturation region of the driving transistors 15 - 1 and 125 - 2 . can make it
That is, for example, when the pixel circuit 100 - 1 applies a voltage such as V ₂ or V ₃ to the gate terminal of the NMOSFET 125 - 1 in a situation as shown in (b) of FIG. 3A , the light emitting device are operated in the linear region of the NMOSFET 125-1. In this case, as the voltage distribution between Vled and Vds varies due to the Vf deviation between the light emitting elements, the driving current I provided to the light emitting element is changed to emit light. A luminance deviation occurs between the elements.
However, according to an exemplary embodiment of the present disclosure, the pixel circuit 100 - 1 applies the Vgs value as V ₀ or V ₁ through the amplitude setting circuit 110 , so that the light emitting device 130 becomes the NMOSFET 125 - 1 ) can be operated in the saturation region. When the NMOSFET 125-1 operates in the saturation region, since the current I is constant regardless of the change in Vds, even if the voltage distribution between Vled and Vds varies due to the Vf deviation between the light emitting devices, the light emitting device 130 Since the driving current I provided by ? is constant, the light emitting devices can emit light of a constant luminance regardless of a forward voltage deviation. Meanwhile, according to an embodiment, the driving voltage VDD applied to the current source 120 may be designed to be high so that the light emitting device 130 operates in the saturation region of the NMOSFET 125 - 1 .
Meanwhile, according to an embodiment of the present disclosure, even when the driving transistor included in the current source 120 is a PMOSFET, the pixel circuit may be designed to operate as described above with reference to FIG. 3A . Hereinafter, a case in which the driving transistor is a PMOSFET will be described with reference to FIG. 3B.
3B (a) illustrates the current source 120 and the light emitting device 130 of the pixel circuit 100 - 2 of FIG. 2B . According to an embodiment of the present disclosure, as shown in (a) of FIG. 3B , when the driving transistor is the PMOSFET 125-2, the drain terminal of the PMOSFET 125-2 is the light emitting device 130 . It is connected to the anode terminal, and the source terminal is connected to the driving voltage applying terminal 121 . Also, the cathode terminal of the light emitting device 130 is connected to the ground terminal 122 . Accordingly, the current source 120 may provide the driving current I to the light emitting device 130 when the POMSFET 125 - 2 is turned on according to the gate terminal voltage of the PMOSFET 125 - 2 .
Meanwhile, FIG. 3B (b) is a graph showing voltage-current characteristics of the PMOSFET 125-2. In (b) of FIG. 3B , the horizontal axis represents the source-drain voltage (Vsd) of the PMOSFET 125-1, and the vertical axis represents the current (I) flowing from the source terminal to the drain terminal of the PMOSFET 125-2 according to Vsd. indicates
As shown in FIG. 3B (b), the PNMOSFET 125-2 has a source-gate voltage (Vsg) and a threshold voltage (PMOSFET 125-2) has a gate-source voltage (Vgs) as a reference, Since it has a negative threshold voltage, to be precise, when it is equal to or greater than the absolute value of the threshold voltage), as the source-gate voltage Vsg increases (ie, from V ₀ to ₃ ), more current I flows. Accordingly, the current source 120 may provide a driving current having a different amplitude to the light emitting device 130 according to the magnitude of the voltage applied to the gate terminal of the driving transistor 125 - 2 .
In addition, the PMOSFET 125 - 2 may operate in a linear region or a saturation region according to the source-drain voltage Vsd for each source-gate voltage Vsg equal to or greater than the threshold voltage. Here, the linear region is an operation region in which the current I flowing from the source terminal to the drain terminal increases as the source-drain voltage Vsd increases, and the saturation region is the source irrespective of the change in the source-drain voltage Vsd. The current (I) flowing from the terminal to the drain terminal is a constant operating region. That is, as shown in (b) of FIG. 3B , the PMOSFET 125-1 has a linear region and a saturation region when Vsg is V ₀ to V ₃ , respectively.
Meanwhile, the driving voltage VDD applied to the driving voltage terminal 121 is distributed between the PMOSFET 125 - 2 and the light emitting device 130 as Vled and Vsd as shown in (a) of FIG. 3B . Here, Vsd is the voltage between the source-drain terminals of the PMOSFET 125 - 2 , and Vled is the forward voltage Vf of the light emitting device 130 , that is, a voltage required for the light emitting device 130 to emit light.
As shown in (b) of FIG. 3B , the forward voltage Vf of the light emitting device may have a deviation for each light emitting device. Due to this variation, the light emitting device operates in the linear region of the driving transistor 125 - 1 . In this case, as the voltage distribution between Vled and Vsd is changed, the driving current I is changed, resulting in a luminance deviation between the light emitting devices even for the same driving voltage (VDD).
However, according to an embodiment of the present disclosure, as described above with reference to FIG. 3A , by setting the operating point of the driving transistor 125 - 2 through the amplitude setting circuit 110 , the light emitting device 130 operates the driving transistor ( 125-2) in the saturation region. That is, according to an embodiment of the present disclosure, the pixel circuit 100-1 applies the Vsg value as V ₀ or V ₁ through the amplitude setting circuit 110 in the situation as shown in (b) of FIG. 3B , The light emitting device 130 can be operated in the saturation region of the PMOSFET 125 - 2 , so that the light emitting device 130 can emit light with a constant luminance regardless of the Vf deviation between the light emitting devices. . Meanwhile, according to an embodiment, the driving voltage VDD applied to the current source 120 may be designed to be high so that the light emitting device 130 operates in the saturation region of the PMOSFET 125 - 2 .
On the other hand, although an example in which the amplitude setting circuit 110 operates the driving transistors 125-1 and 125-2 in the saturation region has been mainly described above, the driving transistor 125- that the amplitude setting circuit 110 can set Of course, the operating points of 1 and 125-2 are not limited thereto, and the driving transistors 125-1 and 125-2 may be operated in a linear region according to an exemplary embodiment. Of course, it is also possible to set the voltage applied to the gate terminal of
Hereinafter, a detailed configuration and operation of the pixel circuit 100 - 1 according to an embodiment of the present disclosure will be described in detail with reference to FIGS. 4A to 4D . In the description of FIGS. 4A to 4D , descriptions overlapping those described above will be omitted.
4A is a circuit diagram illustrating a detailed configuration of a pixel circuit 400 according to an embodiment of the present disclosure. Referring to FIG. 4A , the pixel circuit 400 includes an amplitude setting circuit 110 , a current source 120 including a driving transistor 125 - 1 , a light emitting device 130 , a pulse width setting circuit 140 , and a transistor 150 . ) is included. Meanwhile, according to an embodiment of the present disclosure, as shown in FIG. 4A , all transistors included in the pixel circuit 400 may be configured as NMOSFETs, but the present disclosure is not limited thereto.
The amplitude setting circuit 110 has a capacitor 111 having one end connected to the source terminal of the driving transistor 125-1, the other end connected to the gate terminal of the driving transistor 125-1, and a capacitor ( The transistor 112 may include a transistor 112 commonly connected to the other end of the 111 and a gate terminal of the driving transistor 125 - 1 and receiving an amplitude set voltage Va through a drain terminal.
Here, the amplitude setting voltage Va is a data signal for setting the amplitude of the driving current Id, and the amplitude setting circuit 110 sets the amplitude through the transistor 112 according to the control signal GATE(n). The voltage Va may be received and the capacitor 111 may be charged.
In particular, according to an embodiment of the present disclosure, the amplitude setting circuit 110 of the pixel circuit 400 operates while the transistor 112 is turned on according to the control signal GATE(n) input to the gate terminal of the transistor 112 . , the amplitude setting voltage Va applied through the data signal line 410 may be charged to the capacitor 111 , and the voltage charged in the capacitor 111 may be applied to the gate terminal of the driving transistor 125 - 1 . .
Accordingly, when the driving voltage VDD is applied to the current source 120 in a state in which the voltage charged in the capacitor 111 is applied to the gate terminal of the driving transistor 125 - 1 , the pixel circuit 400 generates the capacitor 111 . ), a driving current Id having an amplitude corresponding to the magnitude of the charged voltage may be provided to the light emitting device 130 .
The transistor 150 may be turned on/off according to the control signal CGC to electrically connect/disconnect the amplitude setting circuit 110 and the pulse width control circuit 140 . According to FIG. 4A , in the transistor 150 , the drain terminal is commonly connected to the other terminal of the capacitor 111 , the gate terminal of the driving transistor 125 - 1 and the source terminal of the transistor 112 , and the source terminal is connected to the transistor ( It is commonly connected to the drain terminal of the 141 and the source terminal of the transistor 142 , and may receive the control signal CGC through the gate terminal.
Hereinafter, the configuration of the pulse width control circuit 140 will be described on the assumption that the transistor 150 is turned on, that is, the transistor 150 operates as a conducting wire.
The pulse width control circuit 140 includes an inverter whose output terminal is connected to a gate terminal of the driving transistor 125 - 1 . Here, the inverter refers to a circuit configuration in which input and output are logically inverted, and an NMOSFET or a PMOSFET may be an inverter according to a connection relationship in the circuit.
In FIG. 4A , the transistor 141 serves as the inverter. Specifically, in FIG. 4A , since the source terminal of the transistor 141 is connected to the ground terminal 122 , when a logic value 0 is applied to the gate terminal of the transistor 141 , the transistor 141 is turned off and the drain terminal is When it has a logic value 1 (voltage applied to the gate terminal of the driving transistor 125 - 1 ) and a logic value 1 is applied to the gate terminal of the transistor 141 , the transistor 141 is in an on state and the drain terminal is Since it has a logic value of 0 (ground voltage VSS), in FIG. 4A , the transistor 141 can be viewed as an inverter having a drain terminal as an output terminal and a gate terminal as an input terminal.
At this time, according to FIG. 4A , in the transistor 141 , the drain terminal is connected to the gate terminal of the driving transistor 125 - 1 , the gate terminal is connected to one end of the capacitor 143 , and as described above, the source terminal is connected to ground.
Meanwhile, the pulse width control circuit 140 may include a switching element connected between an input terminal and an output terminal of the inverter and a capacitor 143 having one end connected to an input terminal of the inverter.
Here, the switching element is turned on/off according to a control signal. In FIG. 4A , the transistor 142 becomes a switching element, and the transistor 142 may be turned on/off according to the control signal RES(n). Specifically, the transistor 142 has a drain terminal connected in common to an input terminal of the inverter (ie, a gate terminal of the transistor 141 ) and one terminal of the capacitor 143 , and a source terminal is connected to an output terminal of the inverter (ie, the transistor 141 ). drain terminal) and the gate terminal of the driving transistor 125 - 1 , and may receive the control signal RES(n) through the gate terminal.
On the other hand, the capacitor 143 has one end connected to the input terminal of the inverter (ie, the gate terminal of the transistor 141 ) and the drain terminal of the transistor 142 , and the other end is a pulse width setting voltage Vw and a linear change voltage. (Vsweep) can be input.
In this case, according to the embodiment of FIG. 4A , the pulse width setting circuit 140 may further include a transistor 144 that is turned on/off according to the control signal CIE. In the embodiment of FIG. 4A , since the pixel circuit 400 receives all of the amplitude setting voltage Va, the pulse width setting voltage Vw, and the linear change voltage Vsweep through one data signal line 410, the transistor 144 is turned on according to the control signal CIE only while the pulse width setting voltage Vw or the linear change voltage Vsweep is applied to the line 410, and to the control signal CIE while the amplitude setting voltage Va is applied. By being turned off accordingly, the pulse width control circuit 140 may receive only the pulse width set voltage Vw or the linear change voltage Vsweep through the capacitor 143 .
Here, the pulse width setting voltage Vw is a data signal for setting the pulse width of the driving current Id, and the linear change voltage Vsweep is a linear voltage applied to the gate terminal of the transistor 141 . It is a voltage that is linearly changed to change, and details about this will be described later.
Meanwhile, according to an embodiment of the present disclosure, in the pulse width control circuit 140 of the pixel circuit 400 , when a specific voltage applied to the input terminal of the inverter 141 changes linearly to reach a preset threshold voltage, Since the voltage at the output terminal of the inverter 141 becomes the ground voltage, the duration of the driving current Id may be controlled.
That is, as described above, a voltage (eg, Va) charged in the capacitor 111 by the operation of the amplitude setting circuit 110 is applied to the gate terminal of the driving transistor 125-1, and the driving voltage terminal When the driving voltage VDD is applied through 121 , the driving current Id having an amplitude corresponding to the magnitude of the voltage Va charged in the capacitor 111 starts to flow to the light emitting device 130 .
The driving current Id, which started to flow as above, flows until the output terminal voltage of the inverter 141 becomes the ground voltage. When the output terminal voltage of the inverter 141 becomes the ground voltage, the gate of the driving transistor 125-1 This is because the terminal voltage also becomes a ground voltage (assuming that the transistor 150 is in an on state), and thus the driving transistor 125 - 1 is turned off. That is, the driving current Id may continue from the time when the driving voltage VDD is applied to the current source 120 until the time when the voltage at the output terminal of the inverter 141 becomes the ground voltage. More details on this will be described later.
As a result, the pixel circuit 400 according to an embodiment of the present disclosure controls at least one of an amplitude and a pulse width of the driving current Id provided to the light emitting device 130 to emit luminance of the light emitting device 130 . can control Specifically, the pixel circuit 400 performs pulse amplitude modulation (PAM) in which the amplitude of the driving current Id is varied and the pulse width of the driving current Id according to various control signals and data signals. The luminance of the light emitting device 130 may be controlled by performing pulse width modulation (PWM). In this case, the pixel circuit 400 may perform pulse amplitude modulation (PAM) through the amplitude setting circuit 110 and pulse width modulation (PWM) through the pulse width control circuit 140 .
Hereinafter, a detailed operation of the pixel circuit 400 will be described with reference to FIGS. 4B to 4D .
4B and 4C are timing diagrams and circuit diagrams for describing a detailed operation of the pixel circuit 400 according to an exemplary embodiment of the present disclosure. Specifically, FIG. 4B shows the driving voltage VDD applied to the pixel circuit 400 , the main control signals GATE(n) and RES(n), the data signals Vw, Va, Vsweep, and the pixel circuit 400 . Changes with time of the gate terminal (point B) voltage of the driving transistor 125-1, the input terminal (ie, the gate terminal of the transistor 141) (point A) voltage of the inverter 141, and the driving current Id , and FIG. 4C shows the pixel circuit 400 in the order of ① to ④ according to the passage of time. Circle numbers ① to ④ of FIG. 4C correspond to circle numbers ① to ④ of the point A graph of FIG. 4B , respectively.
4B and 4C , according to an embodiment of the present disclosure, the pixel circuit 400 sets the amplitude and pulse width of the driving current Id according to the control signal and the data signal, and then the current source 120 ), when the driving voltage VDD is applied, the driving current Id having the set amplitude and pulse width may be provided to the light emitting device 130 .
First, as shown in FIG. 4B , a pulse width setting voltage Vw is input to the data signal line 410 , and an enable signal (reset signal, RES(n)) for turning on the transistor 142 is applied to the transistor. When input as 142, the gate terminal (hereinafter, referred to as point A) voltage of the transistor 141 is set to a preset threshold voltage Vth while the reset signal is input. In this case, the pulse width setting voltage Vw may be a value greater than or equal to a preset threshold voltage Vth, and the preset threshold voltage Vth may be a threshold voltage of the transistor 141 .
Specifically, as Vw is input, the A-point voltage rises from 0 to Vw (at this time, the transistor 144 is turned on according to the control signal CIE, and the on state is maintained until the input of Vw is completed). At this time, since Vw is greater than Vth, the transistor 141 is in an on state. Meanwhile. Since the transistor 142 is turned on when a reset signal is input while Vw is applied to the point A, as shown in (1) of FIG. 4c, the current 40 from the point A to the ground terminal 122 through the transistor 142 flows and the voltage at point A decreases. When the A-point voltage drops below Vth, the transistor 141 is turned off, so that the A-point voltage only drops from Vw to Vth. At this time, as the voltage at point A approaches Vth, the current 40 flowing to the ground terminal 122 decreases. Therefore, the voltage at point A decreases over time as shown in the graph for point A in FIG. 4B. It gradually decreases to Vth. Accordingly, before the input of the reset signal is completed, the A-point voltage is set to Vth.
On the other hand, although FIG. 4B shows that Vw and the reset signal are input at the same time, since the voltage at point A starts to drop from the time when the reset signal is input, the time at which Vw is input is slightly earlier than the time at which the reset signal is input. desirable. However, it is not necessarily limited thereto.
In addition, although it has been described above that the voltage at point A before Vw is input is 0 as an example, the present invention is not limited thereto, and according to embodiments, an arbitrary voltage may be applied to point A before Vw is input. In this case, as Vw is input, the point A voltage rises further by Vw from the above arbitrary voltage. Even in this case, the point A voltage drops to Vth before the input of the reset signal is completed.
Referring to FIG. 4B , even after the input of the reset signal is completed and the voltage at point A is set to Vth, the input of Vw is maintained for a predetermined time. Therefore, since the voltage at point A is set to Vth, a voltage of Vw-Vth is maintained between both ends of the capacitor 143 as shown in (1) of FIG. 4C.
Meanwhile, according to FIG. 4B , the input of the reset signal is completed, and the input of Vw is completed as Vw becomes 0 after a certain period of time. At this time, since the voltage of Vw-Vth is maintained between both ends of the capacitor 143, point A The voltage of is a voltage that is lowered by Vw from the set Vth, that is, Vth-Vw. ② in FIG. 4C shows this.
As described above, when the voltage at the point A becomes Vth-Vw, the pulse width setting is completed, and the Vth-Vw voltage at the point A is maintained until a linear change voltage is applied together with the driving voltage VDD thereafter.
Meanwhile, according to FIG. 4B , the amplitude of the driving current is set after the pulse width setting of the driving current is completed as described above. Specifically, according to an embodiment of the present disclosure, the amplitude setting circuit 110 may generate an amplitude setting voltage ( Va) may be charged in the capacitor 111 , and the voltage charged in the capacitor 111 may be applied to the gate terminal of the driving transistor 125 - 1 .
That is, as shown in FIG. 4B , when Va is input to the data signal line 410 and an enable signal (gate signal, GATE(n)) for turning on the transistor 112 is input to the transistor 112 , , Va is charged in the capacitor 111 while the transistor 112 is on. At this time, it goes without saying that the transistor 144 is turned off according to the control signal CIE so that Va is not applied to the pulse width setting circuit 140 while Va is applied. Accordingly, Va is applied to the gate terminal (hereinafter, referred to as point B) of the driving transistor 125-1, and when the voltage at point B becomes Va, the pulse amplitude setting is completed.
On the other hand, when the driving voltage VDD is applied to the driving voltage terminal 121 of the current source 120 while the voltage charged in the capacitor 111 is applied to the gate terminal of the driving transistor 125-1 as described above, A driving current Id having an amplitude corresponding to the voltage applied to the gate terminal of the driving transistor 125 - 1 flows to the light emitting device 130 .
3 of FIG. 4C shows that the transistor 112 is turned on according to the gate signal, the capacitor is charged with the amplitude set voltage, and then, as the driving voltage VDD is applied to the current source 120 , the driving current having an amplitude corresponding to the amplitude set voltage is applied. It shows that (Id) starts to flow into the light emitting element 130 .
Meanwhile, according to an embodiment of the present disclosure, the driving voltage VDD is applied to the current source 120 to provide the driving current Id to the light emitting device 130 , and at the same time, the amplitude setting circuit 140 has a linear change voltage (Vsweep) is applied.
Specifically, as shown in FIG. 4B , it can be seen that the driving voltage VDD is applied to the current source 120 and the linear change voltage Vsweep is applied to the data signal line 410 at the same time. At this time, it goes without saying that the transistor 144 must be turned on according to the control signal CIE in order for Vsweep to be applied to the amplitude setting circuit 140 .
Since a voltage of Vw-Vth is maintained at both ends of the capacitor 143 , when the linear change voltage Vsweep is applied to one end of the capacitor 143 , the voltage at the other end of the capacitor 143 , that is, point A is Vth With -Vw as the starting point, it changes with the same slope as the linear change slope of Vsweep.
Since the transistor 141 is turned off until the voltage at point A reaches Vth according to the change, the voltage Va charged in the capacitor 111 is continuously applied to point B, so the driving current Id is maintained. do.
However, when the voltage at point A changes to Vth according to the linear change voltage Vsweep, the transistor 141 is in an on state. Since the source terminal of the transistor 141 is connected to the ground terminal 122, the transistor ( When the 141 is turned on, the drain terminal voltage and the B point voltage of the transistor 141 also become the ground voltage VSS.
As described above, point B is the gate terminal of the driving transistor 125-1 included in the current source 120, and the source terminal of the driving transistor 125-1 is connected to the ground terminal 122, so the point B is When the voltage becomes the ground voltage VSS, the gate-source voltage difference of the driving transistor 125-1 becomes 0, and the driving transistor 125-1 operates even while the driving voltage VDD is being applied to the drain terminal. In the OFF state, the driving current Id no longer flows to the light emitting device 130 .
④ of FIG. 4C shows that, as the linear change voltage is applied to the pulse width control circuit 140 , the A-point voltage reaches the threshold voltage Vth of the transistor 141 , and the B-point voltage becomes ground, and the current source 120 is The driving current Id is blocked while the driving voltage VDD is being applied.
The contents will be described again with reference to FIG. 4B as follows. That is, the driving current Id starts to flow with an amplitude corresponding to the amplitude set voltage Va from the point in time when the driving voltage VDD is applied to the current source 120 , and the current width is controlled at the same time as the driving voltage VDD is applied. According to the linear increase voltage Vsweep applied to the circuit 140, when the point A voltage increases linearly from Vth-Vw to Vth, the output terminal voltage of the inverter 141 (or the drain terminal voltage of the transistor 141 or The gate terminal voltage of the driving transistor 125 - 1 becomes the ground voltage, and the driving current Id stops flowing. Consequently, the driving current Id flows from the time when the driving voltage VDD is applied to the time when the output terminal voltage of the inverter 141 becomes the ground voltage (the time when the point A voltage becomes the threshold voltage of the transistor 141). do.
Looking at this, it can be expected that the time during which the driving current Id is maintained (in other words, the duty ratio of the driving current Id or the pulse width of the driving current Id) varies according to the pulse width setting voltage Vw. have. In the example of FIG. 4B , it can be expected that as the Vw value increases, the holding time of the driving current Id becomes longer, and as the Vw value decreases, the holding time of the driving current Id becomes shorter.
Specifically, according to an embodiment of the present disclosure, since the rate of change (or slope) of the linear change voltage Vsweep is constant regardless of the magnitude of the pulse width set voltage Vw, if the Vw value is When it becomes smaller than the example, the voltage at point A falls less than Vth-Vw shown in ② of FIG. 4B as the input of Vw is completed, and therefore, when the linearly increasing voltage Vsweep is applied thereafter, in the case of FIG. 4B Vth is reached faster. This means that the output terminal voltage of the inverter 141 becomes the ground voltage faster than in the case of FIG. 4B , and consequently, the holding time of the driving current Id is shorter than in the case of FIG. 4B , the pulse width is reduced, and the duty ratio is will be lowered
On the other hand, if the Vw value becomes larger than the example shown in FIG. 4B, the voltage at point A drops much more than Vth-Vw shown in ② of FIG. 4B, and therefore, when a linearly increasing voltage Vsweep is applied, FIG. Vth is reached later than in the case of 4b. This means that the voltage at the output terminal of the inverter 141 becomes the ground voltage later than in the case of FIG. 4B , and as a result, the holding time of the driving current Id becomes longer than in the case of FIG. 4B , the pulse width increases, and the duty ratio is will rise
At this time, if, for example, in FIG. 4B , the slope of the linear increase voltage Vsweep, that is, the increase rate is S [Volt/sec], the holding time Td of the driving current Id is {Vth-(Vth-Vw) }/S [seconds] or Vw/S [seconds].
FIG. 4D is a timing diagram of various data signals and control signals input to the display panel 500 including the pixel circuit 400 of FIG. 4A . As described above, the pixel circuit 400 constitutes each pixel of the display panel 500 and may be driven by the panel driver 200 driving the display panel 500 (refer to FIG. 11 ). In FIG. 4D , in the display panel 500 including the pixel circuits 400 as shown in FIG. 4A , the amplitude and pulse width of the driving current Id are set for all the pixel circuits constituting the display panel 500 . and a driving current Id corresponding to the set amplitude and pulse width is provided to the light emitting device 130 to show a period in which one image frame is displayed.
Specifically, FIG. 4D shows various control signals (CIE, CGC, RES(n), GATE(n)) and data signals (CIE, CGC, RES(n), GATE(n)) provided by the panel driver 200 to each pixel circuit of the display panel 500 during one cycle. The driving timings of Va, Vw, and Vsweep) are shown separately for each section. Meanwhile, specific details of the panel driver 200 will be described later with reference to FIG. 11 , and here, timings of various data signals and control signals provided by the panel driver 200 will be described. In this case, it is assumed that the display panel 500 includes pixel circuits arranged in a matrix having n rows and m columns.
Referring to FIG. 4D , the control signal CIE controls on/off of the transistor 144 included in each pixel circuit of the display panel 500 . As described above, the transistor 144 operates the pulse width control circuit 140 when the data signals Va, Vw, and Vsweep are applied to the pixel circuit 400 through one data signal line 410 . Only the data signal necessary for the pulse width is applied to the pulse width control circuit 140 .
Specifically, since the data signals necessary for the operation of the pulse width control circuit 140 are the pulse width setting voltage Vw and the linear change voltage Vsweep, the control signal CIE is the display panel 500 as shown in FIG. 4D . The transistor 144 is turned on only during the period in which Vw and Vsweep are applied to the data signal line 410 in the driving period of can do.
Meanwhile, during the amplitude setting period in which Va is applied to the data signal line 410 , the control signal CIE turns off the transistor 144 to prevent Va from being input to the pulse width control circuit 140 . In the amplitude setting section, as shown in FIG. 4d , the transistor 112 of the amplitude setting circuit 110 is turned on according to the control signal Gate(n), and receives the amplitude setting voltage Va and is applied to the capacitor 111. will be charged
The control signal CGC controls on/off of the transistor 150 included in each pixel circuit of the display panel 500 . As described above, the transistor 150 serves to electrically connect or disconnect the amplitude setting circuit 110 and the pulse width control circuit 140 . In the pulse width setting section in which the pulse width of the driving current Id is set, the pulse width setting circuit 140 is connected to the gate terminal of the amplitude setting circuit 110 or the driving transistor 125-1 to perform the above-described operation. it shouldn't be Accordingly, the control signal CGC turns off the transistor 150 during the pulse width setting period, as shown in FIG. 4D .
Meanwhile, since the pulse width control circuit 140 controls the holding time of the driving current Id, when the driving current Id starts to flow according to the application of the driving voltage VDD, the gate of the driving transistor 125 - 1 must be connected to the terminal. Therefore, it can be seen that the control signal CGC turns on the transistor 150 in the light emission period, as shown in FIG. 4D . Meanwhile, although FIG. 4 illustrates an example in which the control signal CGC turns on the transistor 150 immediately after the pulse width setting period, the present invention is not limited thereto, and the transistor 150 may be turned on only during the light emission period.
The control signals RES(1) to RES(n) are control signals sequentially provided to n rows in the display panel 500 having pixel circuits arranged in n rows and m columns, m included in the selected row. While the pulse width setting voltage Vw is applied to each of the m pixel circuits, the switching element (ie, the transistor 142) of each pulse width control circuit 140 included in each of the m pixel circuits is turned on to turn on the input of the inverter. , by shorting the output terminal (ie, the gate terminal and the drain terminal of the transistor 141 ), a specific voltage (ie, the threshold voltage Vth of the transistor 141 ) is applied to the input terminal of the inverter.
Control signals GATE(1) to GATE(n) are also control signals sequentially provided to n rows in the display panel 500 having pixel circuits arranged in n rows and m columns, and m included in the selected row While the amplitude setting voltage Va is applied to each of the m pixel circuits, the amplitude setting voltage applied by turning on the transistor 112 of the amplitude setting circuit 110 included in each of the m pixel circuits is charged in the capacitor 111 . make it possible
The amplitude setting voltage Va is a data signal for setting the amplitude of the driving current Id to be provided to the light emitting device 130 of each of the plurality of pixel circuits constituting the display panel 500 in order to display an image frame. , and the pulse width setting voltage Vw sets a pulse width of a driving current Id to be provided to the light emitting device 130 of each of the plurality of pixel circuits constituting the display panel 500 to display an image frame. data signal for The amplitude setting voltage Va and the pulse width setting voltage Vw may be voltages having different magnitudes according to the brightness values of each pixel constituting the image frame.
The linear increase voltage Vsweep is a voltage that has a predetermined slope and increases linearly, and is simultaneously applied to the pulse width control circuit 140 of each of the plurality of pixel circuits constituting the display panel 500 during the light emission period to emit light. A pulse width of the driving current Id to be provided to the device 130 is controlled. Specific details of controlling the pulse width of the driving current Id through the linear increase voltage Vsweep are the same as described above.
The driving voltage VDD is a voltage that is simultaneously applied to the current sources 120 included in each of the plurality of pixel circuits constituting the display panel 500 during the light emission period, and is a driving current Id having a set amplitude and pulse width. is simultaneously provided to the light emitting device 130 of each of the plurality of pixel circuits, and accordingly, the light emitting device 130 emits light with a corresponding luminance to display an image frame.
An example in which the pulse width of the driving current Id is first set and the amplitude is set has been described in FIGS. 4A to 4D . However, the order of setting the pulse width and the amplitude is not necessarily limited thereto, and according to an embodiment, of course, the amplitude may be set first and the pulse width may be set.
Meanwhile, content that does not contradict the pixel circuit 400 described above with reference to FIGS. 4A to 4D may be directly applied to other embodiments of the pixel circuit described below. Accordingly, in the following description, portions that are contradictory or different from the pixel circuit 400 described above with reference to FIGS. 4A to 4D will be mainly described.
5A is a circuit diagram of a pixel circuit 400 ′ according to another exemplary embodiment. As shown in FIG. 5A , the pixel circuit 400 ′ has the same configuration as the pixel circuit 400 of FIG. 4A . However, the only difference is that there are two data signal lines 410 - 1 and 410 - 2 , and accordingly, there is no transistor 144 included in the pulse width control circuit 140 of FIG. 4A .
Unlike the pixel circuit 400 , the pixel circuit 400 ′ has a pulse width setting voltage Vw required for the operation of the pulse width setting circuit 140-1 through one data signal line 410-1 and The linear increasing voltage Vsweep is applied to the pulse width setting circuit 140-1, and separately from this, the amplitude setting voltage Va is applied to the amplitude setting circuit 110 through another data signal line 410-2. Since all data signals are applied through one data signal line 410 like the transistor 144 included in the pulse width control circuit 140 of FIG. 4A , there is no need to distinguish and receive the data signals. . Due to the difference in configuration from the pixel circuit 400 , the pulse width setting and the amplitude setting may be simultaneously performed in the pixel circuit 400 ′.
FIG. 5B illustrates timings of various data signals and control signals input to the display panel 500 including pixel circuits such as the pixel circuit 400' of FIG. 5A. Referring to FIG. 5B , it can be seen that, unlike FIG. 4D , the pulse width setting and the amplitude setting of the driving current Id can be simultaneously made.
6 is a circuit diagram of a pixel circuit according to still another exemplary embodiment. As shown in FIG. 6 , the configuration of the pixel circuit 600 is substantially the same as that of the pixel circuit 400 ′ of FIG. 5A . However, there is a difference in that a so-called current programming method is used to set the amplitude of the driving current Id.
In the amplitude setting of the driving current Id, the voltage programming method receives a voltage (amplitude setting voltage, Va) applied to the gate terminal of the driving transistor 125 - 1 directly through the data signal line to receive the capacitor 111 . On the other hand, in the current programming method, in order to charge the voltage (amplitude setting voltage, Va) applied to the gate terminal of the driving transistor 125-1 to the capacitor 111, the amplitude setting voltage Va By flowing the corresponding current Ia from the drain terminal of the driving transistor 125-1 to the source terminal, the amplitude setting voltage Va induced in the gate terminal of the driving transistor 125-1 is charged in the capacitor 111. way to do it
To this end, in addition to the amplitude setting circuit 110 of the pixel circuit 400 ′ of FIG. 5A , the amplitude setting circuit 110 - 1 of the pixel circuit 600 , as shown in FIG. 6 , a data signal line ( The transistor 113 may further include a transistor 113 that receives the amplitude setting current Ia through 410-2 and transmits it to the drain terminal of the driving transistor 125-1. At this time, the drain terminal of the transistor 113 is connected to the data signal line 410-2 to receive the amplitude setting current Ia, the source terminal is connected to the drain terminal of the driving transistor 125-1, and the gate terminal may be commonly connected to the gate terminal of the transistor 112 to receive the control signal GATE(n).
Accordingly, according to the amplitude setting circuit 110 - 1 of the pixel circuit 600 , in the amplitude setting period, as the transistor 112 and the transistor 113 are turned on according to the control signal GATE(n), the data signal line ( 410-2) flows from the drain terminal of the driving current Id to the source terminal, and at this time, the voltage applied to the gate terminal of the driving transistor 125-1 is applied to the capacitor 111. By charging to , the amplitude of the driving current Id can be set. Since the operation after the amplitude setting is the same as the pixel circuits 400 and 400' described above, a redundant description thereof will be omitted.
7 is a circuit diagram of a pixel circuit according to still another exemplary embodiment of the present disclosure. The pixel circuit 700 of FIG. 7 has the same configuration and operation as the pixel circuit 400 of FIG. 4A . However, in that the pulse width control circuit 140 - 2 of the pixel circuit 700 includes an inverter other than the above-described inverter 141 , that is, a complementary metal oxide semiconductor field effect transistor (CMOSFET) inverter 145 . There is a difference.
Referring to FIG. 7 , the pulse width control circuit 140 - 2 of the pixel circuit 700 includes an inverter 141 having an output terminal connected to a gate terminal of the driving transistor 125 - 1 , and an output terminal 145 - 2 including an inverter ( CMOSFET inverter 145 is connected to the input terminal of 141, one end is connected to the input terminal 145-1 of the CMOSFET inverter 145, and the other end is the pulse width set voltage (Vw) and A capacitor 143 to which the linear change voltage Vsweep is input, and a switching element 142 connected between the input terminal 145-1 and the output terminal 145-2 of the CMOSFET inverter 145 are included.
Specifically, according to the pulse width control circuit 140 - 2 of the pixel circuit 700 , in the pulse width setting period, the pulse width setting voltage Vw is input to the capacitor 113 through the data signal line 410 . while the control signal RES(n) is applied to the gate terminal of the switching element 142 to turn on the switching element 142, the output terminal 145-2 of the CMOS inverter 145 while the switching element 142 is on The voltage, that is, the input terminal voltage of the inverter 141 is set to a preset threshold voltage, that is, the threshold voltage Vth of the inverter 141 .
When the input of the control signal RES(n) is completed, since a voltage of Vw-Vth is maintained in the capacitor 143 , thereafter, the input of the pulse width set voltage Vw inputted through the other end of the capacitor 143 . When this is completed, the input terminal voltage of the inverter 141 drops from Vth to Vth-Vw.
In this way, the pulse width of the driving current Id is set, and in the subsequent light emission period, the driving voltage VDD is applied to the current source 120 , and the linear change voltage Vsweep is applied to the pulse width control circuit 140-2. ), the driving current Id having a set pulse width is provided to the light emitting device 130 . Since the operation of the current width setting circuit 110 or the operation of the pulse width setting circuit 140 - 2 after the pulse width setting is the same as described in the pixel circuits 400 and 400 ′, , redundant descriptions are omitted.
Hereinafter, an embodiment in which all transistors included in the pixel circuit are implemented as PMOSFETs will be described with reference to FIGS. 8A, 8B, and 9 .
8A is a circuit diagram illustrating a detailed configuration of a pixel circuit 800 according to an exemplary embodiment of the present disclosure. Referring to FIG. 8A , the pixel circuit 800 includes an amplitude setting circuit 110 , a current source 120 including a driving transistor 125 - 2 , a light emitting device 130 , a pulse width setting circuit 140 , and a transistor 150 . ') is included.
The amplitude setting circuit 110 has a capacitor 111 ′ having one end connected to the source terminal of the driving transistor 125-2, the other end connected to the gate terminal of the driving transistor 125-2, and a capacitor having a drain terminal. It may include a transistor 112 ′ that is commonly connected to the other end of 111 ′ and the gate terminal of the driving transistor 125 - 2 and receives an amplitude setting voltage Va through a source terminal. The amplitude setting circuit 110 may turn on the transistor 112 ′ according to the control signal GATE(n) to receive the amplitude setting voltage Va and charge the capacitor 111 ′.
Specifically, the amplitude setting circuit 110 of the pixel circuit 800 operates the data signal line 410 while the transistor 112 ′ is turned on according to the control signal GATE(n) input to the gate terminal of the transistor 112 ′. ) may be charged to the capacitor 111 ′, and the voltage charged in the capacitor 111 ′ may be applied to the gate terminal of the driving transistor 125 - 2 .
Accordingly, when the driving voltage VDD is applied to the current source 120 while the voltage charged in the capacitor 111 ′ is applied to the gate terminal of the driving transistor 125 - 2 , the pixel circuit 800 generates the capacitor ( A driving current Id having an amplitude corresponding to the magnitude of the voltage charged to 111 ′ may be provided to the light emitting device 130 .
The transistor 150 ′ may be turned on/off according to the control signal CGC to electrically connect/disconnect the amplitude setting circuit 110 and the pulse width control circuit 140 . 8A, the drain terminal of the transistor 150' is commonly connected to the other terminal of the capacitor 111', the gate terminal of the driving transistor 125-2, and the drain terminal of the transistor 112', and the source terminal is commonly connected to the drain terminal of the transistor 141' and the drain terminal of the transistor 142', and may receive the control signal CGC through the gate terminal. Hereinafter, the configuration of the pulse width control circuit 140 will be described on the assumption that the transistor 150 is turned on, that is, the transistor 150 operates as a conducting wire.
The pulse width control circuit 140 includes an inverter whose output terminal is connected to a gate terminal of the driving transistor 125 - 2 . In FIG. 8A , the transistor 141' is an inverter. Specifically, in FIG. 8A , since the source terminal of the transistor 141', which is a PMOSFET, is connected to the driving voltage terminal 121, when a logic value 1 is applied to the gate terminal of the transistor 141', the transistor 141' is turned off. state, the drain terminal has a logic value 0, and when a logic value 1 is applied to the gate terminal of the transistor 141 ′, the transistor 141 ′ is turned on and the drain terminal has a logic value 1 (driving voltage VDD). )), the transistor 141' in FIG. 8A can be viewed as an inverter having a drain terminal as an output terminal and a gate terminal as an input terminal. At this time, according to FIG. 8A , the drain terminal of the transistor 141' is connected to the gate terminal of the driving transistor 125-2, the gate terminal is connected to one end of the capacitor 143', and as described above, the source A terminal is connected to the driving voltage terminal 121 .
Meanwhile, the pulse width control circuit 140 may include a switching element connected between an input terminal and an output terminal of the inverter and a capacitor 143 ′ having one end connected to the input terminal of the inverter. Here, the switching element is configured to be turned on/off according to a control signal. In FIG. 8A , the transistor 142 ′ serves as a switching element, and the transistor 142 ′ may be turned on/off according to the control signal RES(n). .
Specifically, the transistor 142' has a source terminal commonly connected to an input terminal of the inverter (ie, a gate terminal of the transistor 141') and one terminal of the capacitor 143', and a drain terminal is connected to an output terminal of the inverter (ie, a transistor). The drain terminal of 141 ′) and the gate terminal of the driving transistor 125 - 2 are commonly connected, and the control signal RES(n) may be input through the gate terminal. The capacitor 143' has one end connected to the input terminal of the inverter (ie, the gate terminal of the transistor 141) and the source terminal of the transistor 142', and the other end is a pulse width setting voltage Vw and a linear change voltage. (Vsweep) can be input.
In this case, according to the embodiment of FIG. 8A , the pulse width setting circuit 140 may further include a transistor 144 ′ that is turned on/off according to the control signal CIE. In the embodiment of FIG. 8A , the pixel circuit 800 receives all of the amplitude setting voltage Va, the pulse width setting voltage Vw, and the linear change voltage Vsweep through one data signal line 410, so that the transistor 144' is turned on according to the control signal CIE only while the pulse width setting voltage Vw or the linear change voltage Vsweep is applied to the line 410, and the control signal CIE while the amplitude setting voltage Va is applied By turning off according to , the pulse width control circuit 140 can receive only the pulse width set voltage Vw or the linear change voltage Vsweep through the capacitor 143'.
Meanwhile, according to an embodiment of the present disclosure, in the pulse width control circuit 140 of the pixel circuit 800 , a specific voltage applied to the input terminal (point A) of the inverter 141 ′ is linearly changed to a preset threshold voltage. , the output terminal voltage of the inverter 141 ′ becomes the driving voltage VDD of the current source 120 , thereby controlling the duration of the driving current Id.
That is, as described above, a voltage (eg, Va) charged in the capacitor 111 ′ by the operation of the amplitude setting circuit 110 is applied to the gate terminal (point B) of the driving transistor 125 - 2 . When the driving voltage VDD is applied through the driving voltage terminal 121 , the driving current Id having an amplitude corresponding to the magnitude of the voltage Va charged in the capacitor 111 is transmitted to the light emitting device 130 . starts to flow
The driving current Id, which started to flow as above, flows until the output terminal voltage of the inverter 141' becomes the driving voltage VDD of the current source 120. The output terminal voltage of the inverter 141' is the driving voltage VDD. In this case, since the voltage at the gate terminal (point B) of the driving transistor 125-2 also becomes the driving voltage VDD (assuming that the transistor 150' is in an on state), the driving transistor 125-2 is turned off. because it becomes That is, the driving current Id may continue from the point in time when the driving voltage VDD is applied to the current source 120 until the time when the voltage at the output terminal of the inverter 141 ′ becomes the driving voltage VDD.
As such, in the pixel circuit 800 according to an exemplary embodiment of the present disclosure, the amplitude and the driving current Id provided to the light emitting device 130 according to the amplitude setting voltage Va and the pulse width setting voltage Vw; By controlling at least one of the pulse widths (ie, by performing pulse amplitude modulation (PAM) and pulse width modulation (PWM)), the luminance of the light emitting device 130 may be controlled.
Meanwhile, since all transistors included in the pixel circuit 800 are implemented as PMOSFETs, control signals CIE, CGC, and RES(n) input to the pixel circuit 400 of FIG. 4A in which all included transistors are implemented as NMOSFETs , GATE(n)) and the data signals Vw, Va, and Vsweep are inputted in an inverted form.
8B is a timing diagram for explaining a specific operation of the pixel circuit 800 . Specifically, FIG. 8B shows a driving voltage VDD applied to the pixel circuit 800 , main control signals GATE(n), RES(n), data signals Vw, Va, Vsweep, and the pixel circuit 800 . At the time of the gate terminal (point B) voltage of the driving transistor 125-2, the input terminal of the inverter 141' (ie, the gate terminal of the transistor 141') (point A) voltage and the driving current Id It shows the changes that follow.
As shown in FIG. 8B , the pixel circuit 800 sets the amplitude and pulse width of the driving current Id according to the control signal and the data signal, and then, when the driving voltage VDD is applied to the current source 120 , The driving current Id having the set amplitude and pulse width may be provided to the light emitting device 130 .
Specifically, first, as shown in FIG. 8B , a pulse width setting voltage Vw is input to the data signal line 410 and an enable signal (reset signal, RES(n) for turning on the transistor 142 ′). )) is input to the transistor 142', the gate terminal (hereinafter, referred to as point A) voltage of the transistor 141' is set to a preset threshold voltage Vth while the reset signal is input. In this case, the preset threshold voltage Vth may be the threshold voltage of the transistor 141 ′.
Specifically, as Vw is input, the voltage at point A drops from 0 to Vw. (At this time, the transistor 144' is turned on according to the control signal CIE, and the on state is maintained until the input of Vw is completed). At this time, since Vw is a voltage lower than Vth, the transistor 141' is in an on state. Meanwhile. When a reset signal is inputted while Vw is applied to point A, the transistor 142' is turned on, so that a current flows from point A through the transistor 142', thereby increasing the voltage at point A. When the point A voltage rises to Vth, the transistor 141' is turned off, so that the point A voltage rises only from Vw to Vth. At this time, as the voltage at point A approaches Vth, the current flowing through the transistor 120 ′ decreases. Therefore, the voltage at point A gradually rises to Vth over time. Accordingly, before the input of the reset signal is completed, the A-point voltage is set to Vth.
On the other hand, although FIG. 8B shows that Vw and the reset signal are input at the same time, since the voltage at point A starts to drop from the time when the reset signal is input, the timing at which Vw is input is slightly earlier than the timing at which the reset signal is input. desirable. However, it is not necessarily limited thereto.
In addition, although it has been described above that the voltage at point A before Vw is input is 0 as an example, the present invention is not limited thereto, and according to embodiments, an arbitrary voltage may be applied to point A before Vw is input. In this case, as Vw is input, the point A voltage further drops by Vw from the above arbitrary voltage. Even in this case, the point A voltage drops to Vth before the input of the reset signal is completed.
Referring to FIG. 8B , even after the input of the reset signal is completed and the voltage at point A is set to Vth, the input of Vw is maintained for a predetermined time. Accordingly, since the voltage at point A is set to Vth, a voltage of Vw-Vth is maintained between both ends of the capacitor 143'.
Meanwhile, according to FIG. 8B , the input of the reset signal is completed, and the input of Vw is completed as Vw becomes 0 after a certain period of time. At this time, since the voltage of Vw-Vth is maintained between both ends of the capacitor 143', A The voltage at the point becomes a voltage that is lowered by Vw from the set Vth, that is, Vth-Vw.
As described above, when the voltage at the point A becomes Vth-Vw, the pulse width setting is completed, and the Vth-Vw voltage at the point A is maintained until a linear change voltage is applied together with the driving voltage VDD thereafter.
Meanwhile, according to FIG. 8B, after the pulse width setting of the driving current is completed as described above, the amplitude of the driving current is set. Specifically, according to an embodiment of the present disclosure, the amplitude setting circuit 110 sets the amplitude while the transistor 112 ′ is turned on according to the gate signal GATE(n) input to the gate terminal of the transistor 112 ′. The voltage Va may be charged in the capacitor 111 ′, and the voltage charged in the capacitor 111 ′ may be applied to the gate terminal of the driving transistor 125 - 2 .
That is, as shown in FIG. 8B , Va is input to the data signal line 410 , and an enable signal (gate signal, GATE(n)) for turning on the transistor 112' is transmitted to the transistor 112'. Upon input, Va is charged to the capacitor 111' while the transistor 112' is on. In this case, it goes without saying that the transistor 144 ′ is turned off according to the control signal CIE so that Va is not applied to the pulse width setting circuit 140 while Va is applied. Accordingly, Va is applied to the gate terminal (hereinafter, referred to as point B) of the driving transistor 125 - 2 , and when the voltage at point B becomes Va, the pulse amplitude setting is completed.
Meanwhile, when the driving voltage VDD is applied to the driving voltage terminal 121 of the current source 120 while the voltage charged in the capacitor 111 ′ is applied to the gate terminal of the driving transistor 125 - 2 as described above, , a driving current Id having an amplitude corresponding to the voltage applied to the gate terminal of the driving transistor 125 - 2 flows to the light emitting device 130 .
Meanwhile, according to an embodiment of the present disclosure, the driving voltage VDD is applied to the current source 120 to provide the driving current Id to the light emitting device 130 , and at the same time, the amplitude setting circuit 140 has a linear change voltage (Vsweep) is applied.
Specifically, as shown in FIG. 8B , it can be seen that the driving voltage VDD is applied to the current source 120 and the linear change voltage Vsweep is applied to the data signal line 410 at the same time. At this time, it goes without saying that the transistor 144 must be turned on according to the control signal CIE in order for Vsweep to be applied to the amplitude setting circuit 140 .
Since a voltage of Vw-Vth is maintained at both ends of the capacitor 143', when the linear change voltage Vsweep is applied to one end of the capacitor 143', the other end of the capacitor 143', that is, the point A The voltage changes with the same slope as the linear change slope of Vsweep with Vth-Vw as the starting point. According to the change, since the transistor 141' is turned off until the voltage at point A reaches Vth, the voltage Va charged in the capacitor 111 is continuously applied to point B, and the driving current Id is maintained. do.
However, when the voltage at point A is changed to Vth according to the linear change voltage Vsweep, the transistor 141 ′ is in an on state, and the source terminal of the transistor 141 ′ is connected to the driving voltage VDD terminal 121 . Since they are connected, when the transistor 141' is turned on, the drain terminal voltage and the B point voltage of the transistor 141' also become the driving voltage VDD.
As described above, point B is the gate terminal of the driving transistor 125 - 2 included in the current source 120 , and the source terminal of the driving transistor 125 - 2 is connected to the driving voltage terminal 121 , so point B When the voltage of the driving transistor 125-2 becomes the driving voltage VDD, the voltage difference between the gate and the source of the driving transistor 125-2 becomes 0, and the driving transistor 125-2 is in the middle of the driving voltage VDD being applied to the source terminal. Even if it is turned off, the driving current Id no longer flows to the light emitting device 130 .
The contents will be described again with reference to FIG. 8B as follows. That is, the driving current Id starts to flow with an amplitude corresponding to the amplitude set voltage Va from the point in time when the driving voltage VDD is applied to the current source 120 , and the current width is controlled at the same time as the driving voltage VDD is applied. When the A-point voltage decreases linearly from Vth-Vw to Vth according to the linear decreasing voltage Vsweep applied to the circuit 140 , the output terminal voltage of the inverter 141 ′ (or the drain terminal of the transistor 141 ′) The voltage or the gate terminal voltage of the driving transistor 125 - 2 becomes the driving voltage VDD, and the driving current Id stops flowing. As a result, the driving current Id is determined from the time when the driving voltage VDD is applied to the time when the output terminal voltage of the inverter 141 ′ becomes the driving voltage VDD (the point A voltage is the threshold voltage of the transistor 141 ′). until the point in time).
Looking at this, it can be expected that the time during which the driving current Id is maintained (in other words, the duty ratio of the driving current Id or the pulse width of the driving current Id) varies according to the pulse width setting voltage Vw. have. In the example of FIG. 8B , it can be expected that as the Vw value increases, the holding time of the driving current Id becomes longer, and as the Vw value decreases, the holding time of the driving current Id becomes shorter.
Specifically, according to an embodiment of the present disclosure, since the rate of change (or slope) of the linear change voltage Vsweep is constant regardless of the magnitude of the pulse width set voltage Vw, if the absolute value of Vw is When it becomes smaller than the illustrated example, the voltage at point A rises less than Vth-Vw shown in FIG. 8B as the input of Vw is completed. Therefore, when the linear decreasing voltage Vsweep is applied thereafter, Vth is reached sooner than in the case of This means that the output terminal voltage of the inverter 141' becomes the driving voltage VDD faster than in the case of FIG. 8B, and consequently, the holding time of the driving current Id is shorter than in the case of FIG. 8B, and the pulse width is reduced. , the duty ratio is lowered.
On the other hand, if the absolute value of Vw becomes larger than the example shown in FIG. 8B, the voltage at point A rises much more than Vth-Vw shown in FIG. Vth is reached later than in the case of FIG. 8B. This means that the output terminal voltage of the inverter 141 ′ becomes the driving voltage VDD later than in the case of FIG. 8B , and as a result, the holding time of the driving current Id becomes longer than in the case of FIG. 8B , and the pulse width increases. , the duty ratio is increased.
At this time, in FIG. 8B , for example, if the slope of the linear decrease voltage Vsweep, that is, the decrease rate is S [Volt/sec], the holding time Td of the driving current Id is {Vth-(Vth-Vw) }/S [seconds] or Vw/S [seconds].
9 is a circuit diagram of a pixel circuit 900 according to another exemplary embodiment. As shown in FIG. 9 , the pixel circuit 900 has the same configuration as the pixel circuit 800 of FIG. 8A . However, the only difference is that there are two data signal lines 410-1 and 410-2, and accordingly, the transistor 144' included in the pulse width control circuit 140 of FIG. 8A is not required. .
In the pixel circuit 900 , unlike the pixel circuit 800 , a pulse width setting voltage Vw and a linearly increasing voltage required for the operation of the pulse width setting circuit 140 through one data signal line 410 - 1 . (Vsweep) is applied to the pulse width setting circuit 140, and separately from this, the amplitude setting voltage Va is applied to the amplitude setting circuit 110 through another data signal line 410-2. Like the transistor 144 ′ included in the pulse width control circuit 140 of , since all data signals are applied through one data signal line 410 , a configuration for receiving input separately is unnecessary. Due to the difference in configuration with the pixel circuit 800 , in the pixel circuit 900 , the pulse width setting and the amplitude setting can be simultaneously made, unlike that illustrated in FIG. 8B .
Meanwhile, although not shown in the drawings, it goes without saying that the PMOSFET pixel circuits 800 and 900 may also use a current programming method to set the amplitude of the driving current Id, like the aforementioned NMOSFET pixel circuit.
10A and 10B are exemplary diagrams in which a compensation circuit is applied to the pixel circuit 400 according to an embodiment of the present disclosure. In general, even in a TFT (Thin Film Transistor) circuit constituting the same display panel, a deviation may exist in the threshold voltage (Vth) or mobility (μ) of each transistor included in the TFT circuit. Specifically, in the case of a-SI (Amorphous Silicon), the threshold voltage (Vth) of the transistors may change over time, and in the case of LTPS (Low Temperature Poly Silicon), the threshold voltage (Vth) or mobility ( μ) may be different. Since this difference causes a decrease in luminance uniformity of the display panel, it is necessary to correct the deviation of the threshold voltage (Vth) and mobility (μ) between transistors of the TFT through a compensation circuit.
10A is an exemplary diagram in which the compensation circuit 1000 is applied to the pixel circuit 400 - 1 according to an embodiment of the present disclosure. Referring to FIG. 10A , the pixel circuit 400 - 1 includes a current source 120 including a driving transistor 125 - 1 , a light emitting device 130 , an amplitude setting circuit 110 - 1 , and a pulse width control circuit 140 . includes In this case, the configuration and operation of the pulse width control circuit 140 of the pixel circuit 400 - 1 is the same as that of the pulse width control circuit 140 of the pixel circuit 400 of FIG. 4A , and thus a redundant description thereof will be omitted.
Meanwhile, the amplitude setting circuit 110 - 1 of the pixel circuit 400 - 1 has the same configuration as the amplitude setting circuit 110 - 1 of the pixel circuit 600 of FIG. 6 , but is connected to the compensation circuit 1000 . Since the connection relationship and operation with the outside are different, the description will be focused on these differences.
In the amplitude setting circuit 110-1 of the pixel circuit 600 of FIG. 6, the drain terminal of the transistor 113 is connected to the data signal line 410-2, and the amplitude of the driving current Id is In order to set , it is turned on according to the control signal GATE(n) and receives the amplitude setting current Ia as input.
In contrast, the amplitude setting circuit 110 - 1 of the pixel circuit 400 - 1 shown in FIG. 8 applies the amplitude setting voltage Va applied to one data signal line 410 through the transistor 112 . It operates by a voltage programming method that receives an input and applies a voltage to the gate terminal of the driving transistor 125 - 1 , and the transistor 113 is used to detect the driving current Id.
Specifically, the transistor 113 has a drain terminal connected to the current detection unit 1030 of the compensation circuit 1000 , a source terminal connected to the drain terminal of the driving transistor 125 - 1 , and input through a gate terminal. It is turned on according to the control signal SENS(n) so that the current detection unit 1030 can detect the current Isens flowing through the driving transistor 125 - 1 .
More specifically, before the pixel circuit 400 - 1 starts the amplitude setting and pulse width setting operations to display the image frame, the compensation circuit 1000 first performs a specific voltage Vx through the D/A converter 1020 . ) is applied to the gate terminal of the driving transistor 125-1 (at this time, the transistor 112 is turned on according to the control signal GATE(n)), and accordingly, the driving transistor 125-1 is passed through the current detection unit 1030. is detected (at this time, the transistor 113 is turned on according to the control signal SENS(n)).
The compensating unit 1010 of the compensating circuit 1000 uses the current value detected by the current detecting unit 1030 to correct input image data and then provides the corrected data to the D/A converter 1020 , , the D/A converter 1020 applies the corrected image data to the data signal line 410 in order.
The pixel circuit 400 - 1 performs pulse width setting and amplitude setting operations according to the corrected Vw or Va, so that an image frame in which the deviation between transistors is compensated can be displayed.
Meanwhile, the compensation circuit 1000 may include a compensation unit 1010 , a D/A converter 1020 , and a current detection unit 1030 as shown in FIG. 10A .
The correction unit 1010 may correct input image data using the detected current value provided by the current detection unit 1030 . For example, the compensator 1010 compares data regarding a current value to flow through the driving transistor 125 - 1 corresponding to the specific voltage Vx with a current value detected by the current detector 1030 , and according to the comparison result, You may be able to correct the image data.
At this time, the data related to the current value corresponding to the specific voltage may be stored in various memories (not shown) inside or outside the compensation circuit 1000 in the form of a lookup table, etc. It will be possible to obtain and use the data stored in the city). However, the example in which the correction unit 1010 corrects the image data using the detected current value is not limited thereto.
To this end, the compensator 1010 may be implemented with various processors or FPGAs (Field-Programmable Gate Array), but is not limited thereto.
The D/A converter 1020 converts the amplitude setting voltage Va and the pulse width setting voltage Vw of the driving current Id corresponding to the image data or the image data corrected by the correction unit 1010 to the data signal line ( 410) can be applied. Also, the D/A converter 1020 may apply a specific voltage Vx to the data signal line 410 for detecting a current flowing through the driving transistor 125 - 1 for image data correction. In this case, the operation of the D/A converter 1020 may be controlled by the compensator 1010, but is not limited thereto, and may be controlled by an external processor.
The current detector 1030 may be connected to the transistor 113 to detect a current flowing through the driving transistor 125 - 1 . To this end, the current detection unit 1030 may be implemented in various ways according to the current detection method. For example, when detecting the current by measuring the voltage applied across the resistor, it may include a resistor, and may include a resistor at both ends of the capacitor. When the current is detected by measuring the change rate of the applied voltage, it may be implemented including an operational amplifier (OP-AMP) and a capacitor, but is not limited thereto.
Meanwhile, each of the components of the above-described compensation circuit 1000 may be included in a source driver for driving the display panel, but is not limited thereto. For example, when an external processor performs the operation of the compensator 1010, the D/A converter 1020 and the current detector 1030 are included in the source driver, and the compensator 1010 uses an external processor. may be implemented as
10B is an exemplary diagram in which the compensation circuit 1000 ′ is applied to the pixel circuit 400 - 2 according to another embodiment of the present disclosure. The pixel circuit 400 - 2 of FIG. 10B has the same configuration as the pixel circuit 400 - 1 of FIG. 10A . However, the pixel circuit 400-2 may apply various data signals Vw, Va, and Vsweep through one data signal line 410 and sense a current flowing through the driving transistor 125-1. have.
To this end, the compensation circuit 1000 ′ may further include a switch 1040 in addition to the compensator 1010 , the D/A converter 1020 , and the current detection unit 1030 . The switch 1040 is controlled on/off by a processor external to the compensator 1010 or the compensation circuit 1000' to apply the data at a time to apply the data Vw, Va, and Vsweep, and to apply the current Isens. ) may be switched to detect a current flowing through the driving transistor 125 - 1 at a time to detect it. Other operations are the same as those described above in the pixel circuit 400 - 1 of FIG. 10A , and thus a redundant description will be omitted.
Meanwhile, although the compensation circuits 1000 and 1000 ′ are applied to the pixel circuits 400 - 1 and 400 - 2 as an example through FIGS. 10A and 10B , the threshold voltage Vth between the transistors included in the display panel has been described. ) or the configuration for compensating for the deviation of the mobility μ is not limited thereto, and the compensation circuits 1000 and 1000' are also shown in the other pixel circuits 400', 600, 700, 800, and 900 described above. Of course, it can be applied similarly to 10a and 10b.
11 is a block diagram of a display apparatus 2000 according to an embodiment of the present disclosure. According to FIG. 11 , the display apparatus 2000 includes a display panel 500 , a panel driver 200 , and a processor 300 .
The display panel 500 includes a plurality of pixel circuits 100 . Here, the pixel circuit 100 may be any of the pixel circuits 400 , 400 ′ 600 , 700 , 800 , 900 , 400 - 1 and 400 - 2 described above.
Specifically, the display panel 500 may be formed such that the gate lines G1 to Gn and the data lines D1 to Dm cross each other, and the pixel circuit 100 may be formed in a region provided at the intersection. For example, each of the plurality of pixel circuits 100 may be configured such that adjacent R, G, and B sub-pixels form one pixel, but is not limited thereto.
Meanwhile, in FIG. 11 , for convenience of illustration, the gate signal lines G1 to Gn and the data driver for applying a control signal from the gate driver 230 to each pixel circuit 100 included in the display panel 500 are shown. Although only one data signal line D1 to Dm for applying a data signal from 220 to each pixel circuit 100 is illustrated, other data signal lines or control signal lines are used according to the above-described various pixel circuit embodiments. Of course, more may be included.
For example, the embodiment (400', 900) in which the Vw and Vsweep signals for setting the pulse width and the Va signal for setting the amplitude are separated and applied to a separate data signal line (400', 900) or the embodiment in which the amplitude is set by the current programming method In an embodiment to which 600 and the compensation circuits 1000 and 1000 ′ are applied, two data signal lines D1 to Dm may be provided 410 - 1 and 410 - 2 . In addition, according to various embodiments of the present disclosure, since the control signals GATE(n) and RES(n) must be applied to the pixel circuit to set the amplitude and pulse width of the driving current Id, the gate signal line G1 to Gn) may also be two.
The panel driver 200 drives the display panel 500 , more specifically, each of the plurality of pixel circuits 100 , under the control of the processor 300 , the timing controller 210 , the data driver 220 , and the gate A driving unit 230 may be included.
The timing controller 210 receives an input signal IS, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a main clock signal MCLK from the outside, such as an image data signal, a scan control signal, a data control signal, A light emission control signal may be generated and provided to the display panel 500 , the data driver 220 , the gate driver 230 , and the like.
In particular, the timing controller 210 transmits the control signal CGC to the transistor 150, 150 ′, and the control signal CIE may be applied to the transistors 144 and 144 ′ of the pixel circuits 400 , 800 , 400 - 1 and 400 - 2 .
The data driver 220 (or source driver) is a means for generating a data signal, and receives image data of R/G/B component from the processor 300 and generates a data signal. Also, the data driver 220 may apply the generated various data signals to the display panel 500 .
In particular, although not clearly shown in FIG. 11 , the data driver 220 includes an amplitude setting voltage, a pulse width setting voltage, and a linear A specific voltage Vx applied to the gate terminals of the driving transistors 125-1 and 125-2 to detect the change voltages Va, Vw, and Vsweep and the current flowing through the driving transistors 125-1 and 125-2. ) through the data signal lines 410 , 410 - 1 and 410 - 2 included in the display panel 500 , respectively, through the pixel circuits 400 , 400 ′ 600 , 700 , 800 , 900 , 400 - 1 and 400 - 2 . ) can be approved.
The gate driver 230 (or gate driver) is a means for generating various control signals such as a gate signal (in other words, a scan signal) (GATE(n)), a reset signal (RES(n)), and SENS(n), The generated various control signals are transmitted to a specific row of the display panel 500 .
In particular, a data signal (eg, an amplitude setting voltage Va) output from the data driver 220 may be transmitted to the pixel circuit 100 to which the gate signal GATE(n) is transmitted. In addition, the input terminal voltage (point A voltage) of the inverters 141 and 141 ′ of the pixel circuit 100 to which the reset signal RES(n) is transmitted is a predetermined voltage (eg, when the inverter is a MOSFET, the MOSFET threshold voltage of ). In addition, in the pixel circuit 100 to which the control signal SENS(n) signal is transmitted, the current detector 1030 of the compensation circuits 1000 and 1000 ′ may have a current flowing through the driving transistor 125 of the current source 120 . let it be
Also, the gate driver 230 may apply the driving voltage VDD to the driving voltage terminal 121 of the pixel circuit 100 according to an embodiment.
Meanwhile, under the control of the processor 300 , the panel driver 200 performs pulse width modulation (PWM) in which the duty ratio of the driving current Id is variable and amplitude modulation (PAM) in which the amplitude of the driving current Id is variable. At least one may be used to control the luminance of the light emitting unit 130 , that is, the LED element. Here, the LED is described as a concept including an OLED. In addition, the pulse width modulation signal PWM controls a ratio of turning on and off of the light sources, and the duty ratio % is determined according to a dimming value input from the processor 300 .
The panel driving unit 200 may be implemented with a plurality of LED driving modules. In some cases, each of the plurality of LED driving modules may be implemented to include a subprocessor for controlling the operation of each pixel circuit 100 and a driving module for driving each display module according to the control of the subprocessor. In this case, each sub-processor and the driving module may be implemented as hardware, software, firmware, or an integrated chip (IC). According to an embodiment, each subprocessor may be implemented as a separate semiconductor IC.
Meanwhile, each of the plurality of LED driving modules may include at least one LED driver for controlling a current applied to the LED device. The LED driver may be provided in each of the plurality of LED regions including the plurality of LED elements. Here, the LED area may be a smaller area than the above-described LED module. For example, one LED module may be divided into a plurality of LED regions including a predetermined number of LED elements, and an LED driver may be provided in each of the plurality of LED regions. In this case, current control for each region is possible. However, the present invention is not limited thereto, and the LED driver may be provided in units of LED modules.
According to an embodiment, the LED driver may be disposed at a rear end of a power supply to receive a voltage from the power supply. However, according to another embodiment, a voltage may be applied from a separate power supply device. Alternatively, it is also possible to be implemented in the form of a module in which the SMPS and the LED driver are integrated into one.
The LED driver according to various embodiments of the present disclosure may use the PAM and PWM methods together, and through this, various gray levels of an image may be expressed.
The processor 300 controls the overall operation of the display apparatus 2000, and in particular, controls the panel driver 200 to drive the display panel 500, thereby 800, 900, 400-1, 400-2) may be performed. To this end, the processor 300 includes at least one of a central processing unit (CPU), a micro-controller, an application processor (AP), or a communication processor (CP), an ARM processor. can be implemented as
Specifically, according to an embodiment of the present disclosure, the processor 300 sets the pulse width of the driving current Id according to the pulse width setting voltage Vw, and the driving current ( The panel driver 200 may be controlled to set the amplitude of Id). In this case, when the display panel 500 includes n rows and m columns, the processor 300 may control the panel driver 200 to set the amplitude or pulse width of the driving current Id in units of rows.
Thereafter, the processor 300 simultaneously applies the driving voltage VDD to the current sources 120 of the plurality of pixel circuits 100 included in the display panel 500 , and controls the pulse width of each of the plurality of pixel circuits 100 . By controlling the panel driver 300 to apply the linear change voltage Vsweep to the circuit 140 , an image may be displayed.
At this time, the processor 300 controls the panel driver 200 to control the operation of each pixel circuit 100 included in the display panel 500 as described above with reference to FIGS. 1 to 10 , A duplicate description will be omitted.
12 is a flowchart illustrating a method of driving the display apparatus 2000 according to an embodiment of the present disclosure. 12 , the display apparatus 2000 may set the pulse width and amplitude of the driving current Id for driving the light emitting device 130 of each of the plurality of pixel circuits 100 included in the display panel 500 . There is (S1210). In this case, when the display panel 500 is configured with n rows and m columns, the display apparatus 2000 may simultaneously set the amplitude or pulse width of the driving current Id in row units, but is not limited thereto.
Meanwhile, the type of the light emitting device 130 included in the pixel circuit 100 may be an LED or an OLED, but is not limited thereto. In addition, the pixel circuit 100 may be composed of a TFT, and in this case, the channel material of the TFT may be an oxide or an organic material.
Also, according to an embodiment of the present disclosure, a transistor constituting the pixel circuit 100 may be formed of only an NMOSFET or only a PMOSFET. However, the present invention is not limited thereto, and the pixel circuit 100 may be implemented including a CMOSFET.
In addition, according to an embodiment of the present disclosure, when there is only one data signal line 410 , the pulse width and amplitude should be set at different times, but according to another embodiment, the data signal lines 410 - 1 and 410 . When there are two -2), pulse width setting and amplitude setting may be made at the same time.
Meanwhile, the amplitude setting of the driving current may be performed by a voltage program method, but may also be performed by a current program method according to an exemplary embodiment. Also, according to an embodiment, when the display panel 500 is configured by applying the compensation circuit 1000 to the pixel circuit 100 , the display device 2000 may display an amplitude setting voltage corrected through the compensation circuit 1000 . By setting the amplitude and pulse width of the driving current Id using (Va) and the pulse width setting voltage (Vw), the deviation of the threshold voltage (Vth) and mobility (μ) between transistors of the TFT is reduced, resulting in uniform luminance can elevate the
On the other hand, the display device 2000 applies the driving voltage VDD and the linear change voltage Vsweep to each pixel circuit 100 when both the amplitude and the pulse width of the driving current Id are set as described above. A frame may be displayed (S1220).
Specifically, when the driving voltage VDD is applied to the current source 120 of each pixel circuit 1000 , the light emitting device 130 of each pixel circuit 100 operates according to the driving current Id having the amplitude set as above. Light starts to emit, and when the gate terminal voltage of the driving transistor 125 becomes a ground voltage (when the driving transistor 125 - 1 is an NMOSFET) or the driving voltage VDD according to the linear change voltage, (the driving transistor 125 ) When -2) is a PMOSFET), it is possible to display images of various grayscales by stopping light emission. Other details are the same as those described above with reference to FIGS. 1 to 10 , and thus a redundant description thereof will be omitted.
13 is a conceptual diagram for comparing a pixel circuit according to an embodiment of the present disclosure and a prior art. 13A and 13B illustrate a prior art, and FIG. 13C illustrates a pixel circuit according to an exemplary embodiment of the present disclosure.
13 (a) is a method of directly controlling the light emitting device through the output terminal of the inverter. In this case, since the driving transistor of the light emitting device operates in the linear operation region, the deviation of the driving current according to the deviation of the forward voltage Vf between the light emitting devices is large, so that the uniformity of the luminance is lowered.
On the other hand, (b) of Figure 13 is a method of controlling a switch positioned between the current source and the light emitting element through the output terminal of the inverter. In this case, since the inverter is implemented as a CMOSFET, an oxide cannot be used as a channel material of the TFT, so the manufacturing process is limited, and unnecessary reactive power consumption occurs in the series switch.
On the other hand, if the method of directly controlling the current source 120 as the output terminal of the inverter is taken according to an embodiment of the present disclosure, as shown in FIG. 13C , using any one type of MOSFET such as an NMOSFET or a PMOSFET Since it is possible to configure the TFT, the production cost can be reduced and the yield can be improved compared to the prior art that necessarily requires a CMOSFET (of course, the pixel circuit according to the present disclosure can also be implemented with a CMOSFET (refer to FIG. 7)) .
In addition, since there is no need for a separate switch between the current source 120 and the light emitting device 130, unnecessary consumption of reactive power can be prevented.
In addition, since the amplitude setting circuit (PAM circuit) is used as a hybrid with the pulse width control circuit (PWM circuit), it is possible to control the driving transistor to operate in the saturation region by setting the operating point through the amplitude setting circuit, Even if there is a deviation of the forward voltage (Vf) between the (130), it is possible to reduce the luminance deviation.
Meanwhile, the operation of the processor 300 of the display apparatus 2000 or the method of driving the display apparatus 2000 according to the above-described various embodiments may be generated by software and mounted on the display apparatus.
For example, setting the pulse width and amplitude of the driving current Id for driving the light emitting device 130 of each of the plurality of pixel circuits 100 included in the display panel 500 and each pixel circuit 100 ) by applying a driving voltage (VDD) and a linear change voltage (Vsweep) to a non-transitory computer readable medium in which a program for performing a driving method of a display device comprising the step of displaying an image is stored (non-transitory computer readable medium) can be installed.
Here, the non-transitory readable medium refers to a medium that stores data semi-permanently, rather than a medium that stores data for a short moment, such as a register, a cache, a memory, and the like, and can be read by a device. Specifically, the above-described various middleware or programs may be provided by being stored in a non-transitory readable medium such as a CD, DVD, hard disk, Blu-ray disk, USB, memory card, ROM, and the like.
In addition, although preferred embodiments of the present disclosure have been illustrated and described above, the present disclosure is not limited to the specific embodiments described above, and the technical field to which the disclosure belongs without departing from the gist of the present disclosure as claimed in the claims In addition, various modifications are possible by those of ordinary skill in the art, and these modifications should not be individually understood from the technical spirit or perspective of the present disclosure.

100: pixel circuit 110: amplitude setting circuit
120: current source 130: light emitting element
140: pulse width control circuit

Claims (19)

In the pixel circuit of a display panel,
a light emitting device that emits light according to a driving current;
a current source including a driving transistor connected to the light emitting device and providing a driving current having an amplitude based on a magnitude of an amplitude set voltage applied to a gate terminal of the driving transistor to the light emitting device;
a pulse amplitude modulation (PAM) circuit for applying the amplitude setting voltage applied through a data line to a gate terminal of the driving transistor;
a pulse width modulation (PWM) circuit for controlling a pulse width of the driving current based on a magnitude of a pulse width setting voltage applied through the data line; and
a third transistor electrically separating the PAM circuit and the PWM circuit until a driving voltage is applied to the current source; and
The light emitting device is an LED (Light Emitting Diode), not an OLED (Organic Light Emitting Diode),
The PWM circuit is
an inverter having an output terminal connected to a gate terminal of the driving transistor; and
When the first voltage applied to the input terminal of the inverter changes linearly and reaches a preset threshold voltage, the output terminal voltage of the inverter becomes the ground voltage or the driving voltage of the current source to control the pulse width of the driving current,
The PWM circuit is
a switching element connected between an input terminal and an output terminal of the inverter; and
A second capacitor having one end connected to the input terminal of the inverter; further comprising,
When the switching element is turned on while the pulse width setting voltage is input to the other terminal of the second capacitor, the input terminal of the inverter is set to the preset threshold voltage while the switching element is turned on,
When the input of the pulse width set voltage is completed, the input terminal voltage of the inverter becomes the first voltage at the set preset threshold voltage. The method of claim 1,
The PAM circuit is
a first capacitor having one end connected to the first end of the driving transistor; and
and a first transistor having a first terminal commonly connected to the other terminal of the first capacitor and a gate terminal of the driving transistor, and a second terminal receiving the amplitude setting voltage. 3. The method of claim 2,
The PAM circuit is
The amplitude setting voltage is charged to the first capacitor while the first transistor is turned on according to a first enable signal input to the gate terminal of the first transistor, and the voltage charged in the first capacitor is applied to the driving transistor. A pixel circuit characterized in that applied to the gate terminal. 4. The method of claim 3,
The current source is
When a driving voltage is applied to the current source while the voltage charged in the first capacitor is applied to the gate terminal of the driving transistor, a driving current having an amplitude corresponding to the voltage charged in the first capacitor is generated in the light emitting device Pixel circuit, characterized in that provided as. 3. The method of claim 2,
The PAM circuit is
a second transistor having a first end connected to a second end of the driving transistor, a gate terminal connected to a gate terminal of the first transistor, and a second end receiving an amplitude setting current;
A voltage corresponding to the amplitude setting current is charged to the first capacitor while the first and second transistors are turned on according to a first enable signal input to the gate terminal of the first transistor, and the first capacitor is charged The pixel circuit according to claim 1, wherein the applied voltage is applied to the gate terminal of the driving transistor. delete The method of claim 1,
The driving current is
The pixel circuit, characterized in that it continues from a point in time when the driving voltage is applied to the current source until a point in time when the voltage at an output terminal of the inverter becomes the ground voltage or the driving voltage. delete The method of claim 1,
The first voltage is
and a difference value between the preset threshold voltage and the pulse width set voltage. The method of claim 1,
The PWM circuit is
The first voltage is linearly changed as the driving voltage is applied to the current source and a linear change voltage is input to the other end of the second capacitor. The method of claim 1,
The inverter and the switching element are N-channel Metal Oxide Semiconductor Field Effect Transistor (NMOSFET),
In the inverter, a drain terminal is connected to a gate terminal of the driving transistor, a gate terminal is connected to one end of the second capacitor, and a source terminal is connected to a ground,
In the switching element, a drain terminal is commonly connected to a gate terminal of the inverter and one end of the second capacitor, and a source terminal is commonly connected to a drain terminal of the inverter and a gate terminal of the driving transistor,
When the first voltage applied to the gate terminal of the inverter increases linearly to reach the preset threshold voltage, the drain terminal voltage of the inverter becomes the ground voltage. ◈Claim 12 was abandoned when paying the registration fee.◈ 12. The method of claim 11,
The PWM circuit is
When a second enable signal is input to the gate terminal of the switching element while a pulse width setting voltage of a second voltage is input to the other end of the second capacitor, while the switching element is turned on according to the second enable signal , the voltage of the gate terminal of the inverter is set to the preset threshold voltage,
The pixel circuit of claim 1, wherein the gate terminal voltage of the inverter drops from the set preset threshold voltage to the first voltage as the pulse width set voltage drops from the second voltage to 0. ◈Claim 13 was abandoned when paying the registration fee.◈ The method of claim 1,
The inverter and the switching element are a P-channel Metal Oxide Semiconductor Field Effect Transistor (PMOSFET),
In the inverter, a drain terminal is connected to a gate terminal of the driving transistor, a gate terminal is connected to one end of the second capacitor, and a source terminal is connected to a driving voltage input terminal of the current source,
In the switching element, a source terminal is commonly connected to a gate terminal of the inverter and one end of the second capacitor, and a drain terminal is commonly connected to a drain terminal of the inverter and a gate terminal of the driving transistor,
When the first voltage applied to the gate terminal of the inverter decreases linearly to reach the preset threshold voltage, the drain terminal voltage of the inverter becomes the driving voltage of the current source. ◈Claim 14 was abandoned at the time of payment of the registration fee.◈ 14. The method of claim 13,
The PWM circuit is
When a third enable signal is input to the gate terminal of the switching element while a pulse width setting voltage of a third voltage is input to the other end of the second capacitor, while the switching element is turned on according to the third enable signal , the voltage of the gate terminal of the inverter is set to the preset threshold voltage,
The pixel circuit of claim 1, wherein the gate terminal voltage of the inverter rises from the set preset threshold voltage to the first voltage as the pulse width set voltage rises from the third voltage to zero. ◈Claim 15 was abandoned when paying the registration fee.◈ The method of claim 1,
The PWM circuit is
a Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOSFET) inverter having an output terminal connected to an input terminal of the inverter;
a third capacitor having one end connected to the input terminal of the CMOSFET inverter; and
a switching element connected between an input terminal and an output terminal of a single CMOSFET inverter; including,
When the switching element is turned on while the pulse width setting voltage is input to the other terminal of the third capacitor, the input terminal of the inverter is set to the preset voltage while the switching element is turned on,
When the input of the pulse width set voltage is completed, the input terminal voltage of the inverter becomes the first voltage at the set preset threshold voltage. delete ◈Claim 17 was abandoned when paying the registration fee.◈ The method of claim 1,
The driving transistor is
The pixel circuit, characterized in that it operates in a saturation region of the operating region of the driving transistor. delete In the display device,
a display panel including a plurality of pixel circuits for displaying an image;
a panel driver for driving the display panel; and
a processor configured to express the grayscale of the image based on at least one of an amplitude and a pulse width of a driving current applied to a light emitting device included in the plurality of pixel circuits;
Each of the plurality of pixel circuits,
a light emitting device that emits light according to the driving current;
a current source including a driving transistor connected to the light emitting device and providing a driving current having an amplitude based on a magnitude of an amplitude set voltage applied to a gate terminal of the driving transistor to the light emitting device;
a pulse amplitude modulation (PAM) circuit for applying the amplitude setting voltage applied through a data line to a gate terminal of the driving transistor;
a pulse width modulation (PWM) circuit for controlling a pulse width of the driving current based on a magnitude of a pulse width setting voltage applied through the data line; and
a transistor for electrically separating the PAM circuit and the PWM circuit until a driving voltage is applied to the current source;
The light emitting device is an LED (Light Emitting Diode), not an OLED (Organic Light Emitting Diode),
The PWM circuit is
an inverter having an output terminal connected to a gate terminal of the driving transistor; and
When the first voltage applied to the input terminal of the inverter changes linearly and reaches a preset threshold voltage, the output terminal voltage of the inverter becomes the ground voltage or the driving voltage of the current source to control the pulse width of the driving current,
The PWM circuit is
a switching element connected between an input terminal and an output terminal of the inverter; and
Further comprising; a capacitor having one end connected to the input terminal of the inverter;
When the switching element is turned on while the pulse width set voltage is input to the other terminal of the capacitor, the input terminal of the inverter is set to the preset threshold voltage while the switching element is turned on,
When the input of the pulse width set voltage is completed, the input terminal voltage of the inverter becomes the first voltage at the set preset threshold voltage.

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