KR102430809B1 - Double sided display - Google Patents

Abstract

The present invention relates to a double-sided display, comprising: a first data driver connected to one end of data lines to apply a data signal of a first image to the data lines; and a second data driver for applying a data signal of two images. The first data driver supplies a first pixel data signal of the first image to a first data line, and supplies an n-th pixel data signal of the first image to an n-th data line. The second data driver supplies a first pixel data signal of the second image to the n-th data line and supplies an n-th pixel data signal of the second image to the first data line.

Description

Double-sided display {DOUBLE SIDED DISPLAY}

The present invention relates to a double-sided display capable of displaying an image on the front and rear surfaces of a display panel.

The double-sided display displays an image on each of the front and rear surfaces of the display panel. In order to simplify the driving circuits of the pixel array formed on the front side and the pixel array formed on the rear side in the double-sided display, a common driving circuit may drive the front pixel array and the rear pixel array. However, this method has a problem in that an image inverted left and right is output on either one of the front and rear surfaces of the display panel.

The present invention provides a double-sided display capable of displaying an image without left-right inversion on each of both surfaces of a display panel.

The double-sided display of the present invention includes a display panel in which n (n is a positive integer of 2 or more) data lines and m (m is a positive integer of 2 or more) gate lines are intersected and a plurality of sub-pixels are disposed, a first data driver connected to one end to apply a data signal of a first image to the data lines, a second data driver connected to the other end of the data lines to apply a data signal of a second image to the data lines; and a gate driver connected to the gate lines to sequentially supply a gate signal to the gate lines. Each of the sub-pixels includes a first light emitting part that emits light through the front surface of the display panel, and a second light emitting part that emits light through a rear surface of the display panel. The first data driver supplies a first pixel data signal of the first image to a first data line, and supplies an n-th pixel data signal of the first image to an n-th data line. The second data driver supplies a first pixel data signal of the second image to the n-th data line and supplies an n-th pixel data signal of the second image to the first data line.

The first light emitting unit and the second light emitting unit share a data line and a gate line.

The light emitted from the first light emitting part is reflected on the first anode electrode and passes through the first cathode electrode, and the light emitted from the second light emitting part is reflected on the second cathode electrode and passes through the second anode electrode.

The first and second light emitting units are driven simultaneously or alternately at a predetermined time period.

Each of the sub-pixels is configured to drive the first and second light emitting devices according to a first light emitting device emitting light from the first light emitting unit, a second light emitting device emitting light from the second light emitting unit, and a gate-source voltage. and a driving element, and a capacitor for charging a gate-source voltage of the driving element.

Each of the sub-pixels is turned on in response to a scan signal applied through a first gate line to a first switch element connecting the gate of the driving element to a data line, and a sensing signal applied through a second gate line. It further includes a second switch element that is turned on accordingly to connect the sensing line to the source of the driving element.

Each of the sub-pixels includes a third switch element for switching a current path between the driving element and the first light emitting element in response to a first emission control signal, and a third switch element for switching between the driving element and the second light emitting element in response to a second emission control signal A fourth switch element for switching a current path between the two light emitting elements is further provided.

Each of the sub-pixels is configured to drive the first and second light emitting devices according to a first light emitting device emitting light from the first light emitting unit, a second light emitting device emitting light from the second light emitting unit, and a gate-source voltage. A driving device, a capacitor for charging a gate-source voltage of the driving device, a first switch device that is turned on according to a scan signal applied through a gate line to connect the gate of the driving device to a data line;

a third switch element for switching a current path between the driving element and the first light emitting element in response to a first light emission control signal, and a current between the driving element and the second light emitting element in response to a second light emission control signal A fourth switch element for switching the path is further provided.

The double-sided display of the present invention includes a display panel in which n data lines, m (m is a positive integer greater than or equal to 2) gate lines, and a plurality of sub-pixels are disposed, and one end of the data lines is connected to the data lines. and a data driver for applying a data signal of a first image or a data signal of a second image, and a gate driver connected to the gate lines to sequentially supply a gate signal to the gate lines. Each of the sub-pixels includes a first light emitting unit emitting light through the front surface of the display panel, and a second light emitting unit emitting light through the rear surface of the display panel. The data driver supplies a data signal representing at least a portion of the first image to the n data lines during a first display period. The data driver supplies a data signal representing at least a portion of the second image to the n data lines during a second display period.

The present invention connects a data driver to both ends of data lines of a double-sided display, supplies a first pixel data signal of a first image to a first data line, and supplies a first pixel data signal of a second image to an n-th data line do. As a result, the present invention can display an image without left and right inversion on both sides of the double-sided display.

1 is a block diagram showing a double-sided display according to an embodiment of the present invention.
2 is a circuit diagram illustrating a pixel circuit and a sensing path connected to the pixel circuit.
3A and 3B are waveform diagrams showing a scan signal, a sensing signal, and a data voltage.
4 is a diagram illustrating a power-on sequence, a display driving period, and a power-off sequence.
5 is a diagram illustrating in detail an active section and a vertical blank section.
6 is a plan view illustrating integrated circuits of a data driver connected to a display panel.
7 is a cross-sectional view illustrating a cross-sectional structure of a sub-pixel.
8 to 10 are circuit diagrams illustrating a pixel circuit according to an embodiment of the present invention.
11 is a waveform diagram showing the light emission control signal and the on/off time of the light emitting device shown in FIGS. 9 and 10 .

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present invention to be complete, and those of ordinary skill in the art to which the present invention pertains It is provided to fully understand the scope of the invention, and the present invention is only defined by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiment of the present invention are exemplary, the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When "includes", "includes", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, it may be interpreted as the plural unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship between the two components is described as 'on One or more other elements may be interposed between those elements in which 'directly' or 'directly' are not used.

The first, second, etc. may be used to distinguish the components, but the functions or structures of these components are not limited to the ordinal number or component name attached to the front of the component.

The following embodiments can be partially or wholly combined or combined with each other, and technically various interlocking and driving are possible. Each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship.

The double-sided display of the present invention is implemented based on an electroluminescent display. The electroluminescent display is divided into an inorganic light emitting display and an organic light emitting display according to the material of the light emitting layer. An active matrix type organic light emitting diode display may include an organic light emitting diode (hereinafter, referred to as “OLED”) as a light emitting device.

The sub-pixels of the organic light emitting diode display include an OLED and a driving element for driving the OLED by supplying a current to the OLED according to a gate-source voltage. The driving element may be implemented as a transistor. The driving element drives the OLED by controlling the current flowing to the OLED according to the gate-source voltage. An OLED of an organic light emitting display device includes an anode and a cathode, and an organic compound layer formed between the electrodes. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL). When a current flows in the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light emitting layer (EML) to form excitons, and as a result, the light emitting layer (EML) generates visible light.

The electrical characteristics of the pixel, such as the threshold voltage (Vth) of the driving element, the electron mobility (μ) of the driving element, and the threshold voltage of the OLED, are factors that determine the driving current of the OLED, so it should be the same in all pixels. do. However, electrical characteristics may vary between pixels due to various causes, such as process variations and changes over time. This deviation of the electrical characteristics of the pixel causes deterioration of image quality and shortened lifespan.

An internal compensation method and an external compensation method may be applied to compensate for the deviation in electrical characteristics of the driving element. The internal compensation method automatically compensates for a deviation in electrical characteristics of the driving device between pixels in real time by using a gate-source voltage of the driving device that varies according to the electrical characteristics of the driving device. The external compensation method compensates for variations in electrical characteristics of the driving element between pixels by sensing a voltage of a pixel that changes according to the electrical characteristics of the driving element, and modulating input image data in an external circuit based on the sensed voltage.

In the double-sided display of the present invention, the pixel circuit includes a driving element and a switch element. The driving element and the switch element may be implemented by at least one of an n-type transistor (NMOS) and a p-type transistor (PMOS). The transistor may be implemented as an oxide transistor having an oxide semiconductor pattern or an LTPS transistor having a low temperature poly-silicon (LTPS) semiconductor pattern. A transistor is a three-electrode device including a gate, a source, and a drain. The transistor may be implemented as a thin film transistor (TFT) on the display panel 100 . The source is an electrode that supplies a carrier to the transistor. In the transistor, carriers begin to flow from the source. The drain is an electrode through which carriers exit the TFT. In a transistor, the flow of carriers flows from source to drain. In the case of an n-type transistor (NMOS), since carriers are electrons, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type transistor (NMOS), the direction of current flows from the drain to the source. In the case of a p-type transistor (PMOS), since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type transistor (PMOS), since holes flow from the source to the drain, current flows from the source to the drain. Therefore, it should be noted that the source and drain of the transistor are not fixed because the source and drain can be changed according to the applied voltage. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal of the TFT used as the switch element swings between a gate on voltage and a gate off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the TFT, and the gate-off voltage is set to a voltage lower than the threshold voltage of the TFT. The TFT is turned on in response to a gate-on voltage, while turned-off in response to a gate-off voltage. In the case of NMOS, the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL). In the case of the PMOS, the gate-on voltage may be a gate low voltage VGL, and the gate-off voltage may be a gate high voltage VGH.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a double-sided display according to an embodiment of the present invention. 2 is a circuit diagram illustrating a pixel circuit and a sensing path connected to the pixel circuit.

1 and 2 , a double-sided display according to an embodiment of the present invention includes a display panel 100 and a display panel driving circuit.

The screen of the display panel 100 includes an active area AA for displaying an input image. A pixel array is disposed in the active area AA. The pixel array includes a plurality of data lines 102 , a plurality of gate lines 104 intersecting the data lines 102 , and pixels arranged in a matrix form.

Each of the pixels may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to implement color. Each of the pixels may further include a white sub-pixel. Each of the sub-pixels 101 includes a pixel circuit as shown in FIGS. 7 to 10 .

Each of the sub-pixels 101 includes a first light emitting part 101T and a second light emitting part 101B. The first light emitting unit 101T and the second light emitting unit 101B share the data line 102 and the gate line 104 . Each of the first light emitting unit 101T and the second light emitting unit 101B includes a separate light emitting device. The first light emitting part 101T displays a first image on the front surface of the display panel 101 including a top emission area emitting light toward the front surface of the display panel 101 . The second light emitting part 101B displays a second image on the rear surface of the display panel 101 including a bottom emission area emitting light toward the rear surface of the display panel 101 . To this end, the front and rear surfaces of the display panel 100 are formed of a transparent substrate through which light can pass. Accordingly, the double-sided display of the present invention may operate as a transparent display in which an image is displayed on each of the front and rear surfaces of the display panel 100 , and the user can see the background or the real thing outside the display panel 100 .

Touch sensors may be disposed on the display panel 100 . The touch input may be sensed using separate touch sensors or may be sensed through pixels. The touch sensors may be implemented as in-cell type touch sensors disposed on the screen of a display panel or embedded in a pixel array as an on-cell type or an add-on type. can

The display panel driving circuit includes data drivers 110T and 110B and a gate driver 120 . A demultiplexer (not shown) may be disposed between the data drivers 110T and 110B and the data lines 102 .

The display panel driving circuit may further include a touch sensor driver for driving the touch sensors. The touch sensor driver is omitted from FIG. 1 . In a mobile device or a wearable device, the display panel driving circuit, the timing controller 130 and the power circuit may be integrated into one integrated circuit.

The display panel driving circuit displays the input image on the screen by writing the data of the input image to the pixels of the display panel 100 under the control of a timing controller (TCON) 130 during the display driving period.

The display driving period may be divided into a double-sided display mode in which an image is displayed on both the front and rear surfaces of the display panel 100 and a single-sided display mode in which an image is displayed on either one of the front and rear surfaces of the display panel 100 . In the double-sided display mode, the first and second data drivers 110T and 110B alternately apply the data signal of the input image to the data lines 102 at a predetermined time period to drive the data lines 102 . In the case of the pixel circuit shown in FIG. 8 in the double-sided display mode, the first and second light emitting units 101T and 101B may be driven simultaneously. In the case of the pixel circuit shown in FIGS. 9 and 10 in the double-sided display mode, the first and second light emitting units 101T and 101B may be alternately driven at a predetermined time period.

In the single-sided display mode, only one of the first and second data drivers 110T and 110B is enabled to supply data signals to the data lines 102 . The first data driver 110T is connected to one end of the data lines 102 , and the second data driver 110B is connected to the other end of the data lines 102 . Each of the data lines is not separated between the first data driver 110T and the second data driver 110B, but is connected to the data drivers 110T and 110B. In the single-sided display mode, only one of the first and second light emitting units 101T and 101B is driven.

The first data driver 110T converts the pixel data of the first image to be displayed on the first light emitting unit 101T of the sub-pixel 101 into a data signal Vdata, and outputs the converted pixel data to the data lines 102 . As shown in FIG. 2 , the first data driving unit 110T includes pixel data (digital data) of the first image received from the timing controller 130 using a digital to analog converter (hereinafter referred to as DAC). ) to a gamma compensation voltage to generate a data signal Vdata.

The second data driver 110B converts the voltage of the pixel data signal Vdata of the second image to be displayed on the second light emitting unit 101B of the sub-pixel 101 into a voltage and outputs the converted voltage to the data lines 102 . The second data driver 110B converts the pixel data of the second image received from the timing controller 130 into a gamma compensation voltage using the DAC to generate the data signal Vdata. The second image may be the same image as the first image or a different image.

The demultiplexer distributes the data signal Vdata output from the first and second data drivers 110T and 110B to the data lines 102 using a plurality of switch elements. Since one channel of the first and second data drivers 110T and 110B is time-divisionally connected to the plurality of data lines 102 by the demultiplexer, the number of data lines 102 may be reduced.

The gate driver 120 may be implemented as a gate in panel (GIP) circuit that is directly formed on a bezel area of the display panel 100 together with the TFT array of the active area AA. The gate driver 120 outputs a gate signal to the gate lines 104 under the control of the timing controller 130 . The gate driver 120 may sequentially supply the gate signals to the gate lines 104 by shifting the gate signals using a shift register. The gate signal may include a scan signal SCAN and a sensing signal SENSE, but is not limited thereto. The scan signal SCAN is applied to the sub-pixels 101 through the first gate line 1041 , and the sensing signal SENSE is applied to the sub-pixels 101 through the second gate line 1042 .

The scan signal SCAN controls a switch element connected between the data line 102 and the gate of the driving element of the sub-pixel 101 to select pixels to which the data signal is applied. The sensing signal SENSE controls a switch element for connecting the sub-pixel 100 to the sensing line 103 shown in FIG. 2 . The sensing signal SECSE selects pixels in which electrical characteristics of the driving element DT are sensed. Here, the electrical characteristics of the driving element include at least one of a mobility (μ) and a threshold voltage (Vth).

The scan signal SCAN and the sensing signal SENSE are synchronized with the data signal Vdata as shown in FIGS. 3A and 3B . During the active period AT, pulses of the scan signal SCAN and the sensing signal SENSE are generated as a gate-on voltage for one horizontal period 1HT. One horizontal period 1HT is a time required for data to be written in pixels arranged in one line of the display panel 100 . The data drivers 110T and 110B simultaneously output the data signal Vdata corresponding to one line of data of the display panel 100 to the data lines 102 in one horizontal period 1HT.

In the sensing mode for sensing the electrical characteristics of the sub-pixel through the sensing line 103, the pulses of the scan signal SCAN and the sensing signal SENSE are generated as a gate-on voltage for a long time (T) of several msec to several tens of msec. do.

One frame period of the double-sided display is divided into an active period (AT) and a vertical blank (VB). The active period AT is a time during which data of one frame is written to all pixels on the screen. The vertical blank period VB is allocated for a predetermined time between the N-1 th active period and the N th active period. During the vertical blank period VB, next frame data (N-th frame data) is not received by the timing controller 130 .

The sensing mode is divided into before product shipment and after product shipment. After the threshold voltage of the driving device is sensed in each of the sub-pixels 101 through a sensing path connected to the pixels before product shipment, the threshold voltage deviation in all sub-pixels is compensated based on the sensing result. In addition, the mobility of the driving element is sensed in each of the sub-pixels to compensate for the mobility deviation.

After product shipment, the sensing mode may be performed in a power ON sequence, a vertical blank period (VB), and a power OFF sequence. In the power-off sequence, the display panel driving circuit and the sensing path are further driven for a preset delay time after receiving the power-off signal to sense the threshold voltage Vth of the driving device in each of the sub-pixels.

The timing controller 130 receives digital video data DATA of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The host system may be any one of a television (Television) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

The timing controller 130 may adjust the frame rate to a frequency greater than or equal to the input frame frequency. For example, the timing controller 130 multiplies the input frame frequency by i and sets the frame frequency×i (i is a positive integer greater than 0) Hz to the operation timing of the display panel drivers 110T, 110B, and 120 can be controlled. The frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase-Alternating Line) scheme.

The timing controller 130 includes a data timing control signal for controlling the operation timing of the data drivers 110T and 110B based on the timing signals Vsync, Hsync, and DE received from the host system, and the operation timing of the gate driver 120 . The operation timing of the display panel driving circuits 110T, 110B, and 120 is controlled by generating a gate timing control signal for controlling the . The voltage level of the gate timing control signal output from the timing controller 130 may be converted into a gate-on voltage and a gate-off voltage through a level shifter (not shown) and supplied to the gate driver 120 . The level shifter converts a low level voltage of the gate timing control signal into a gate low voltage VGL, and converts a high level voltage of the gate timing control signal into a gate high voltage VGH. .

Referring to FIG. 2 , a sensing path may be connected to a sub-pixel. The sensing path may include a sensing line 103 , an analog-to-digital converter (hereinafter referred to as “ADC”), and switch elements M1 and M2, and the like. The sensing path may sense the source voltage of the driving device to sense electrical characteristics of the driving device. The switch element M1 initializes the source voltage of the driving element to the reference voltage Vref by supplying a predetermined reference voltage Vref to the sensing line 103 . The switch element M2 is turned on after the switch element M1 is turned off to supply the source voltage of the driving element to the ADC. The ADC converts the analog sensing voltage into digital sensing data and transmits it to the compensator 131 . A method of sensing the threshold voltage of the driving element DT through the sensing path or a method of sensing the mobility of the driving element through the sensing path may use a known sensing method. The ADC may be integrated in an integrated circuit (IC) of the data drivers 110T and 110B together with the DAC.

The compensation unit 131 stores compensation values for compensating for the threshold voltage Vth and the mobility μ of the driving element in each of the sub-pixels. The compensator 131 selects a preset compensation value according to the digital sensing data received through the ADC and compensates the pixel data by adding or multiplying the compensation value to the pixel data (digital data) of the input image. The compensated pixel data is transmitted to the data drivers 110T and 110B, converted into a voltage of the data signal Vdata by the DAC of the data driver 110 , and supplied to the data line 102 . The driving element of the pixel circuit is driven by the voltage of the data signal Vdata supplied through the data line 102 to generate a current. A current flowing through the driving element DT to the OLED, which is the light emitting element, is determined according to the gate-source voltage Vgs of the driving element DT. The compensator 131 may be implemented as an arithmetic circuit in the timing controller 130 .

Figure 4 is a view showing a power on sequence (Power ON sequence), a display driving period, and a power OFF sequence (Power OFF sequence). Figure 5 shows the active period (AT) and the vertical blank period (VB) in detail drawing is given.

4 and 5 , the power-on sequence ON starts after the display power is turned on. In the power-on sequence 0N, driving voltages of the display panel driving circuit and the display panel 100 are generated, and the display panel driving circuit is initialized. The mobility of the driving element DT is sensed in the vertical blank section VB of the power-on sequence 0N and the display driving period, and the mobility deviation of the driving element DT is determined by a mobility compensation value selected according to the sensed value. compensated A mobility compensation value may be updated based on a result of sensing the mobility of the driving element DT. During the display driving period, pixel data written to the pixels is updated every frame period to display an image on the screen.

The power-off sequence OFF starts after an off signal of the display power is received. In the power-off sequence OFF, the threshold voltage Vth of each of the sub-pixels is sensed during a delay time during which the display panel driving circuit and the sensing path are additionally driven. The threshold voltage compensation value may be updated based on the sensing result of the threshold voltage sensed in real time in the power-off sequence.

The vertical synchronization signal Vsync defines one frame period. The horizontal synchronization signal Hsync defines one horizontal time period. The data enable signal DE defines an effective data section including pixel data to be displayed on the screen.

The data enable signal DE is synchronized with valid data to be displayed on the pixel array of the display panel 100 . One pulse period of the data enable signal DE is one horizontal period, and a high logic period of the data enable signal DE indicates a data input timing of one pixel line. One horizontal period is a time required to write data to pixels of one pixel line in the display panel 100 .

The timing controller 130 receives the data enable signal DE and the data of the input image during the vertical active period AT. There is no data enable signal DE and no data of the input image in the vertical blank section VB. During the active period AT, data corresponding to one frame to be written in all pixels is received by the timing controller 130 . One frame period is the sum of the active periods AT and the vertical blank period VB.

As can be seen from the data enable signal DE, input data is not received by the display device during the vertical blank period VB. The vertical blank section VB includes a vertical sync time (VS), a vertical front porch (FP), and a vertical back porch (BP).

In the double-sided display according to the embodiment of the present invention, in the double-sided display mode, the first and second data drivers 110T and 110B are alternately driven to time-divide the data signals of the first and second images to the data lines 102 . can supply For example, after the first data driver 110T supplies a data signal representing at least a portion of the first image to the data lines 102 during the first display period, the second data driver 110B performs the second display. During the period, a data signal representing at least a portion of the second image may be supplied to the data lines 102 .

In the double-sided display according to another embodiment of the present invention, any one of the first and second data drivers 110T and 110B time-divisions the data signals of the first and second images to the data lines 102 in the double-sided display mode. can supply For example, the first data driver 110T supplies a data signal representing at least a portion of the first image to the data lines 102 during the first display period, and then supplies at least a portion of the second image during the second display period. A data signal representing ? may be supplied to the data lines 102 .

The first display period may be a period in which the first image is displayed through the first light emitting units 101T of the sub-pixels. The second display period may be a period in which a second image is displayed through the second light emitting units 101B of the sub-pixels. The first display period and the second display period may be alternately allocated so that the first and second light emitting units 101T and 101B may be time-division driven. The first and second display periods may be appropriately selected in consideration of flicker, an afterimage, and the like. For example, each of the first and second display periods may be one frame period, a time less than one frame period, and N (N is a positive integer greater than 0) horizontal period. The time less than 1 frame period may be 1/2 frame period. The N horizontal period may be 1 horizontal period.

The double-sided display of the present invention may be driven by time-dividing the first light emitting unit 101T and the second light emitting unit 101B in the double-sided display mode. The first light emitting unit 101T and the second light emitting unit 101B may be alternately driven in units of one frame period. In this case, when the frame frequency of the double-sided display is 120 Hz, each of the first light emitting unit 101T and the second light emitting unit 101B is driven at 60 Hz. The first light emitting unit 101T may be driven in the odd-numbered frame periods FR1 and FR3 in FIG. 4 to display pixel data of the first image. The second light emitting unit 101B may be driven in even-th frame periods FR2 and FR4 in FIG. 4 to display pixel data of the second image. When the frame frequency is 120 Hz, one frame period is 1/120 sec.

In the double-sided display of the present invention, one of the first light emitting unit 101T and the second light emitting unit 101B is driven and the other is not driven in each frame period in the single-sided display mode. Light passes through the light emitting unit that is not driven, so that an object outside the display panel can be seen through the light emitting unit.

6 is a plan view illustrating integrated circuits of the data drivers 110T and 110B connected to the display panel 100 .

Referring to FIG. 6 , the first data driver 110T may be disposed on the top of the display panel 100 to be connected to one end of the data lines 102 . The second data driver 110B may be disposed at the lower end of the display panel 100 to be connected to the other end of the data lines 102 .

The first data driver 110T includes one or more source drive integrated circuits (ICs) SICT1 and a source printed circuit board (SPCBT). The second data driver 110B includes one or more source drive integrated circuits (ICs) SICB1 and source printed circuit boards (PCBs) SPCBB.

Each of the source drive ICs SICT1 and SICB1 may be mounted on a Chip On Film (COF). An input terminal of the COF is connected to output terminals of the source PCB (SPCBT), and an output terminal of the COF is connected to a data pad of the display panel 100 . The COF may be adhered to the substrate of the display panel 100 through an anisotropic conductive film (ACF). The source PCBs SPCBT and SPCBB include wires connecting the timing controller 130 and the source drive ICs SICT1 and SICB1.

The first data driver 110T supplies the first pixel data signal DATAT1 to the first data line disposed on the leftmost side of the display panel 100 , and nth (n is a positive integer greater than or equal to 2), which is the last pixel data. ) The pixel data signal DATATn is supplied to the n-th data line disposed on the rightmost side of the display panel 100 .

The second data driver 110B supplies the first pixel data signal DATAB1 to the n-th data line disposed on the rightmost side of the display panel 100 , and displays the n-th pixel data signal DATABn, which is the last pixel data. It is supplied to the first data line disposed on the leftmost side on the panel 100 . The arrangement and order of the data signals output to the first and second data drivers 110T and 110B are controlled by the timing controller 130 . Accordingly, since the double-sided display of the present invention controls the pixel data order of images to be displayed on the front and rear surfaces of the display panel 100 in opposite directions, images are displayed normally without left and right inversions on both the front and rear surfaces of the display panel 100 . can be displayed

In FIG. 6 , “SICT1” is a first source drive IC of the first data driver 110T for supplying the first pixel data signal DATAT1 to the first data line. Due to the first source drive IC SICT1 , the first pixel data DATAT1 of the first image is written in the leftmost sub-pixel 100 of the display panel 100 every horizontal period. “SICB1” is the first source drive IC of the second data driver 110B for supplying the first pixel data signal DATAB1 to the n-th data line. Due to the first source drive IC SICB1 , the first pixel data DATAB1 of the second image is written in the rightmost sub-pixel 100 of the display panel 100 every horizontal period. Accordingly, in the first image displayed on the front surface of the display panel 100 and the second image displayed on the rear surface of the display panel 100 , the positions of sub-pixels in which the first pixel data are written are opposite to each other on the display panel 100 . to be.

7 is a cross-sectional view illustrating a cross-sectional structure of the sub-pixel 101 .

Referring to FIG. 7 , each of the sub-pixels 101 is divided into a first light emitting part 101T and a second light emitting part 101B. The first light emitting part 101T includes a first light emitting device OLED1 having a top emission structure that irradiates light toward the front side of the display panel 100 . The second light emitting unit 101B includes a second light emitting device OLED2 having a bottom emission structure that irradiates light toward the rear surface of the display panel 100 .

Each of the sub-pixels 101 includes a driving element DT1, one or more switch elements, and a capacitor. In FIG. 7 , some switch elements and capacitors are omitted. The first light emitting unit 101T and the second light emitting unit 101B share the data line 102 and the gate line 104 , and share the driving device DT. Accordingly, the first light emitting device OLED1 and the second light emitting device OLED2 are driven by one driving device DT.

Each of the first light emitting unit 101T and the second light emitting unit 101B includes a separate light emitting device. The first light emitting part 101T displays a first image on the front surface of the display panel 101 including a top emission area emitting light toward the front surface of the display panel 101 . The second light emitting part 101B displays a second image on the rear surface of the display panel 101 including a bottom emission area emitting light toward the rear surface of the display panel 101 .

Looking at the cross-sectional structure of the sub-pixel 101 , a first metal pattern is formed on the first transparent substrate GLS1 . The first metal pattern may be formed of a double metal layer in which copper (Cu) and motitanium alloy (MoTi) are stacked. The first metal pattern includes a light blocking metal pattern LS1 and a VSS auxiliary electrode LS2. The light blocking metal pattern LS1 blocks light irradiated to the semiconductor pattern of the driving element DT to prevent leakage current and threshold voltage shift of the driving element DT generated when the semiconductor pattern ACT1 is exposed to light. do. The low potential power voltage VSS is applied to the VSS auxiliary electrode LS2. The low-potential power voltage VSS is supplied to the sub-pixels 101 through the VSS auxiliary electrode LS2 . In FIG. 7 , “LS3” is a metal pattern that may be simultaneously formed with the first metal pattern on the pad area of the display panel 100 . The metal pattern LS3 may be omitted. The pad area includes a data pad area in which a data pad connected to a data line is disposed and a data pad area in which a data pad connected to a gate line is disposed. 7 shows a portion of the gate pad region.

The buffer layer BUF is formed on the first transparent substrate GLS1 to cover the first metal patterns LS1 , LS2 , and LS3 with an insulating material such as silicon oxide (SiO2). A driving element DT and a switch element S32 are formed on the buffer film BUF. The semiconductor patterns ACT1 and ACT2 of the driving element DT and the switch element S32 are formed on the buffer layer BUF. In the case of an oxide semiconductor, the semiconductor pattern may be formed of indium gallium zinc oxide (IGZO).

A gate insulating pattern is formed of an insulating material such as silicon oxide (SiO2) on the buffer layer BUF. The gate insulating pattern includes a first gate insulating pattern GI1 formed on the first semiconductor pattern ACT1 and a second gate insulating pattern GI2 formed on the second semiconductor pattern ACT2 . The gate insulating patterns GI1 and GI2 mask the channel region when impurity ions are doped into the source and drain regions of the semiconductor patterns ACT1 and ACT2 . The gate insulating pattern further includes an insulating pattern GI3 formed on the pad region.

A second metal pattern is formed on the gate insulating patterns GI1 , GI2 , and GI3 . The second metal pattern is formed of copper (Cu), and includes the gate line 104 , the gate electrode GE1 of the driving device DT, the gate electrode GE2 of the switch device S32 , and the lower electrode GE3 on the pad region. ) is included. The lower electrode GE3 may be connected to the gate line 104 .

The interlayer insulating layer ILD is an insulating layer formed of an insulating material such as silicon oxide (SiO2) to cover the second metal patterns GE1, GE2, and GE3. A plurality of contact holes are formed in the interlayer insulating layer ILD. The first contact hole exposes the drain region of the first semiconductor pattern ACT1 and the second contact hole exposes the source region of the first semiconductor pattern ACT. The third contact hole exposes a drain region of the switch element S32. The fourth contact hole exposes the lower electrode GE3 of the pad area.

A third metal pattern is formed on the interlayer insulating layer ILD. The third metal pattern may be formed of a double metal layer formed of a motitanium alloy (MoTi) and copper (Cu). The third metal pattern includes a first electrode SD1 of the driving element DT and a second electrode SD2 of the driving element DT. The second electrode SD2 of the driving element DT is integrated with the first electrode of the switch element S32 . The third metal pattern further includes an electrode SD3 connected to the VSS auxiliary electrode LS2 and an electrode SD4 connected to the lower electrode GE3 of the pad region.

The passivation layer PAS is an insulating layer formed of an insulating material such as silicon oxide (SiO2) to cover the third metal patterns SD1, SD2, and SD3. The color filter CFB of the second light emitting part 101B is formed on the passivation layer PAS. The color filter CFB includes a red color filter through which red light is transmitted, a green color filter through which exposure light is transmitted, and a blue color filter through which blue light is transmitted. Light from the second light emitting device OLED2 travels toward the rear surface of the display panel 100 through the color filter CFB.

The planarization layer OC is formed of an insulating material such as acrylic photosensitive resin PAC to cover the color filter CFB. Contact holes passing through the planarization layer PAC and the passivation layer PAS are formed. The electrode SD3 connected to the VSS auxiliary electrode LS3 is exposed through the first contact hole penetrating the planarization layer PAC and the passivation layer PAS. A source region of the second semiconductor pattern ACT2 is exposed through a second contact hole penetrating the planarization layer PAC and the passivation layer PAS. The electrode SD4 of the pad region is exposed through the third contact hole penetrating the passivation layer PAS.

The first anode electrode pattern is formed on the planarization layer OC by stacking indium tin oxide (ITO), motitanium alloy (MoTi), and indium tin oxide (ITO). The first anode electrode pattern includes a first anode electrode ANO1 , a VSS upper electrode VSSE, and a pad electrode PAD. The first anode electrode ANO1 is an anode electrode of the first light emitting device OLED1 formed in the first light emitting part 101T. The first anode electrode ANO1 may contact the source region of the second semiconductor pattern ACT2 through a second contact hole penetrating the planarization layer OC and the passivation layer PAS. The VSS upper electrode VSSE is in contact with the VSS auxiliary electrode LS3 through a first contact hole penetrating the planarization layer PAC and the passivation layer PAS. The pad electrode PAD contacts the electrode SD4 in the pad area through a third contact hole penetrating the passivation layer PAS.

The second anode electrode pattern is formed on the planarization layer OC using a transparent electrode material such as indium tin oxide (ITO). The second anode electrode pattern includes a second anode electrode ANO2. The second anode electrode ANO2 is an anode electrode of the second light emitting device OLED2 formed in the second light emitting part 101B separated from the first anode electrode ANO1 .

The bank pattern (BNK) may be formed of polyimide (PI) covering the anode electrode patterns. The bank pattern BNK divides the first light emitting part 101T and the second light emitting part 101B. The bank pattern separates the first anode electrode ANO1 and the organic compound layer EL at the boundary between the light emitting units 101T and 101B.

The organic compound layer EL is shared by the first light emitting part 101T and the second light emitting part 101B. The organic compound layer EL may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL).

The first cathode electrode CAT1 is formed of a transparent electrode material such as indium zinc oxide (IZO) and is formed on the first light emitting part 101T and the second light emitting part 101B to form the first light emitting part 101T. is the cathode electrode of The second cathode electrode CAT2 is a cathode electrode of the second light emitting device OLED2 formed of a metal material such as aluminum (Al).

Light emitted from the first light emitting device OLED1 is reflected on the first anode electrode ANO1 having high reflectivity, passes through the transparent first cathode electrode CAT1 , and travels toward the front side of the display panel 100 . Light emitted from the second light emitting device OLED2 is reflected on the second cathode electrode CAT2 having high reflectivity, passes through the transparent second anode electrode ANO1 , and travels toward the rear surface of the display panel 100 .

A color filter CFT and a black matrix pattern BM are formed on the second transparent substrate GLS2 to face the first light emitting part 101T. Light from the first light emitting device OLED1 travels toward the front side of the display panel 100 through the color filter CFT. The color filter CFT includes a red color filter through which red light is transmitted, a green color filter through which exposure light is transmitted, and a blue color filter through which blue light is transmitted.

The TFT and light emitting device array formed on the first transparent substrate GLS1 and the color filter array formed on the second transparent substrate GLS2 are bonded through a face seal including a transparent adhesive. The face seal is a transparent adhesive with high transmittance. After this bonding process, the electrode SD3 connected to the VSS auxiliary electrode LS2 may be completely connected to the VSS upper electrode VSSE through a laser welding process.

8 to 10 are circuit diagrams illustrating a pixel circuit according to an embodiment of the present invention.

Referring to FIG. 8 , the pixel circuit includes first and second light emitting devices OLED1 and OLED2, a driving device DT for driving the first and second light emitting devices OLED1 and OLED2, and a plurality of switch devices ( S1 and S2), and a capacitor Cst. The driving element DT and the switch elements are exemplified as an n-type transistor NMOS in FIG. 8 , but are not limited thereto.

The first light emitting device OLED1 is formed in the first light emitting part 101T. The second light emitting element OLED2 is formed in the second light emitting part 101B. The light emitting devices OLED1 and OLED2 emit light with a current generated according to the gate-source voltage Vgs of the driving device DT that varies according to the data signal Vdata. The light emitting devices OLED1 and OLED2 include an organic compound layer EL formed between the anode electrodes ANO1 and ANO2 and the cathode electrodes CAT1 and CAT as shown in FIG. 7 . Anode electrodes of the light emitting elements OLED1 and OLED2 are connected to the driving element DT and the capacitor Cst via the second node n2 . In addition, anode electrodes of the light emitting elements OLED1 and OLED2 are connected to the second switch element S2 through the second node n2 .

The first switch element S1 is turned on according to the scan signal SCAN to supply the data signal Vdata to the gate of the driving element DT connected to the first node n1. The first switch element S1 has a gate connected to the first gate line 1041 to which the scan signal SCAN is applied, a first electrode connected to the data line 102 , and a second electrode connected to the first node n1 . includes

The second switch element S2 is turned on according to the sensing signal SENSE to supply the reference voltage Vref to the second node n2. The second switch element S2 includes a gate connected to the second gate line 1042 to which the sensing signal SENSE is applied, a first electrode connected to the sensing line 103 to which the reference voltage Vref is applied, and a second node. and a second electrode connected to (n2). The external compensation method senses the source voltage of the second node, that is, the driving element DT, through the second switch element S2 and the sensing line 103 when the second switch element S2 is turned on, and the sensing result modulates the pixel data of the input image based on

The driving device DT controls current flowing to the first and second light emitting devices OLED1 and OLED2 according to the gate-source voltage Vgs and drives the light emitting devices OLED1 and OLED2. The driving device DT includes a gate connected to the first node n1 , a first electrode to which the pixel driving voltage VDD is supplied, and anode electrodes of the light emitting devices OLED1 and OLED2 through the second node n2 . a second electrode connected to the The capacitor Cst is connected between the first node n1 and the second node n2 to charge the gate-source voltage Vgs of the driving device DT.

In the pixel circuit shown in FIG. 8 , the light emitting devices OLED1 and OLED2 of the first and second light emitting units 101T and 101B are simultaneously driven to simultaneously display the same image on the front and rear surfaces of the display panel 100 . can

It is an example in which switch elements for switching the emission time are added to the pixel circuit shown in FIGS. 9 and 10 . 10 shows a pixel circuit to which an external compensation method is not applied. In the pixel circuit shown in FIG. 10 , the second switch element S2 and the sensing line 103 are omitted. In the description of the pixel circuit illustrated in FIGS. 9 and 10 , the same reference numerals are assigned to the same components as those of the pixel circuit illustrated in FIG. 8 , and detailed description thereof will be omitted.

9 and 10 , the pixel circuit further includes third and fourth switch elements S31 and S32.

The third switch device S31 is disposed between the driving device DT and the first light emitting device OLED1 and is turned on according to the gate-on voltage of the first light emission control signal EMT to turn on the driving device. A current path is formed between the DT and the first light emitting device OLED1. The third switch element S31 is turned off when the voltage of the first light emission control signal EMT is the gate-off voltage to block a current path between the driving element DT and the first light emitting element OLED1 .

The fourth switch element S32 is disposed between the driving element DT and the second light emitting element OLED2 and is turned on according to the gate-on voltage of the second light emission control signal EMB, so that the driving element DT and the second light emitting element S32 are turned on. A current path is formed between the two light emitting devices OLED2. The fourth switch element S32 is turned off when the voltage of the second light emission control signal EMB is the gate-off voltage to block a current path between the driving element DT and the second light emitting element OLED2 .

In the double-sided display mode, when the third and fourth switch elements S31 and S32 are alternately turned on in a predetermined time period, for example, one frame period period, the first and second light emitting elements as shown in FIG. (OLED1, OLED2) may be alternately turned on to emit light.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 101: sub-pixel
101T: first light emitting unit 101B: second light emitting unit
110T, 110B: data driver 120: gate driver
130: timing controller 131: compensation unit
DT: drive element S1 to S32: switch element

Claims (10)

a display panel in which n (n is a positive integer equal to or greater than 2) data lines and m (m is a positive integer equal to or greater than 2) gate lines are crossed and a plurality of sub-pixels are disposed;
a first data driver connected to one end of the data lines to apply a data signal of a first image to the data lines;
a second data driver connected to the other end of the data lines to apply a data signal of a second image to the data lines; and
a gate driver connected to the gate lines to sequentially supply a gate signal to the gate lines;
Each of the sub-pixels is
a first light emitting unit emitting light through the front surface of the display panel, and a second light emitting unit emitting light through a rear surface of the display panel;
the first data driver supplies a first pixel data signal of the first image to a first data line, and supplies an n-th pixel data signal of the first image to an n-th data line;
The second data driver supplies a first pixel data signal of the second image to the n-th data line and supplies an n-th pixel data signal of the second image to the first data line. The method of claim 1,
The first light emitting unit and the second light emitting unit,
Double-sided display sharing data line and gate line. a display panel in which n (n is a positive integer equal to or greater than 2) data lines and m (m is a positive integer equal to or greater than 2) gate lines are crossed and a plurality of sub-pixels are disposed;
a first data driver connected to one end of the data lines to apply a data signal of a first image to the data lines;
a second data driver connected to the other end of the data lines to apply a data signal of a second image to the data lines; and
a gate driver connected to the gate lines to sequentially supply a gate signal to the gate lines;
Each of the sub-pixels is
a first light emitting unit emitting light through the front surface of the display panel, and a second light emitting unit emitting light through a rear surface of the display panel;
the first data driver supplies a first pixel data signal of the first image to a first data line, and supplies an n-th pixel data signal of the first image to an n-th data line;
the second data driver supplies a first pixel data signal of the second image to the n-th data line, and supplies an n-th pixel data signal of the second image to the first data line;
The first light emitting unit and the second light emitting unit share a data line and a gate line,
The light emitted from the first light emitting unit is reflected on the first anode electrode and passes through the first cathode electrode,
A double-sided display in which the light emitted from the second light emitting unit is reflected on the second cathode electrode and passes through the second anode electrode. 4. The method of claim 3,
A double-sided display in which the first and second light emitting units are driven simultaneously or alternately at a predetermined time period. 5. The method of claim 4,
Each of the sub-pixels is
a first light emitting device emitting light from the first light emitting unit;
a second light emitting device emitting light from the second light emitting unit;
a driving device for driving the first and second light emitting devices according to a gate-source voltage; and
A double-sided display comprising a capacitor for charging a gate-source voltage of the driving element. 6. The method of claim 5,
Each of the sub-pixels,
a first switch element that is turned on according to a scan signal applied through a first gate line to connect a gate of the driving element to a data line; and
The double-sided display further comprising a second switch element that is turned on according to a sensing signal applied through a second gate line and connects the sensing line to the source of the driving element. 7. The method of claim 6,
Each of the sub-pixels,
a third switch element for switching a current path between the driving element and the first light emitting element in response to a first light emitting control signal; and
The double-sided display further comprising a fourth switch element for switching a current path between the driving element and the second light emitting element in response to a second light emission control signal. 5. The method of claim 4,
Each of the sub-pixels is
a first light emitting device emitting light from the first light emitting unit;
a second light emitting device emitting light from the second light emitting unit;
a driving device for driving the first and second light emitting devices according to a gate-source voltage;
a capacitor for charging a gate-source voltage of the driving device;
a first switch device that is turned on according to a scan signal applied through a gate line and connects a gate of the driving device to a data line;
a third switch element for switching a current path between the driving element and the first light emitting element in response to a first light emitting control signal; and
The double-sided display further comprising a fourth switch element for switching a current path between the driving element and the second light emitting element in response to a second light emission control signal. a display panel in which n (n is a positive integer of 2 or more) data lines, m (m is a positive integer of 2 or more) number of gate lines, and a plurality of sub-pixels are disposed;
a data driver connected to one end of the data lines to apply a data signal of a first image or a data signal of a second image to the data lines; and
a gate driver connected to the gate lines to sequentially supply a gate signal to the gate lines;
each of the sub-pixels includes a first light emitting unit emitting light through the front surface of the display panel, and a second light emitting unit emitting light through the rear surface of the display panel;
the data driver supplies a data signal representing at least a portion of the first image to the n data lines during a first display period;
The data driver supplies a data signal representing at least a part of the second image to the n data lines during a second display period. According to claim 1,
The display panel is a transparent double-sided display.

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