KR102423280B1 - Area-optimized design of sot-mram - Google Patents

Abstract

A SOT-MRAM area optimization technique is disclosed. A memory device according to an embodiment may include a free layer, a pinned layer, and a magnetic tunnel junction between the free layer and the pinned layer; a metal layer in contact with one side of the free layer of the magnetic tunnel junction; and a spin sink layer (SSL) formed under the metal layer, wherein a low area can be achieved by arranging a source line perpendicular to a bit line in the memory device, and the memory device for a read operation or a write operation in the device The source line configured on the device can be set to ground.

Description

SOT-MRAM area optimization technique {AREA-OPTIMIZED DESIGN OF SOT-MRAM}

The description below relates to spin orbit torque magnetoresistance random access memory.

Spin-shift torque magnetoresistive RAM (STT-MRAM) has attracted great interest in on-chip cache and embedded applications because of desirable characteristics such as non-volume, high density, and compatibility with CMOS processes. However, STT-MRAM is designed to have a common access path through a magnetic tunnel junction for read and write operations. This causes some unwanted flips during reads and negatively affects reliability, such as high stress on the tunnel junction during writes.

Recently, spin orbit torque magnetoresistive RAM (SOT-MRAM) has been proposed as another candidate for nonvolatile on-chip memory with enhanced reliability. The three-terminal structure of SOT-MRAM separates the read and write paths, so each path can be independently optimized without interfering with the other. In addition, SOT-MRAM does not require high stress conditions across the tunnel junction because SOT-induced switching is performed by spin injection from heavy metals. Due to these advantages, SOT-MRAM is emerging instead of STT-MRAM.

However, a major disadvantage of SOT-MRAM is that each cell requires two access transistors. This results in a larger bit cell area than STT-MRAM using single access transistors. Accordingly, there is a need for a technique for improving the integration density while maintaining the advantages of SOT-MRAM.

A novel structure of spin orbital torque magnetoresistive random access memory (SOT-MRAM) for area optimization can be provided.

It is possible to provide a spin orbit torque magnetoresistive random access memory (SOT-MRAM) device that routes the source line layer in a direction perpendicular to the bit line layer that can relax the minimum pitch of the cell.

A memory device comprising: a free layer, a pinned layer, and a magnetic tunnel junction between the free layer and the pinned layer; a metal layer in contact with one side of the free layer of the magnetic tunnel junction; and a spin sink layer (SSL) formed under the metal layer, wherein the source line is disposed in a direction perpendicular to the bit line in the memory device to reduce the area of the bit cell.

The memory device may arrange a source line in a vertical direction of the bit line, and set the source line disposed in a vertical direction of the bit line as a ground for a read operation or a write operation.

The memory device may include a plurality of transistors including a read access transistor coupled to a first terminal of the magnetic tunnel junction and a write access transistor coupled to a second terminal of the metal layer.

The read access transistor is coupled to a read word line at a gate side, a bit line at a drain side, and coupled to a pinned layer of the magnetic tunnel junction at a source side, and the write access transistor is coupled to a write word line at a gate side and may be connected to the bit line at the drain side and may be connected to the metal layer at the source side.

In the case of the write operation, the condition in which the bit line is deflected to a negative voltage to write the logical value 0, the condition in which the read word line is deflected to the negative voltage to write the logical value 1 in the case of the write operation, and the read operation In the case of the operation, it is possible to set a bias condition for a read operation and a write operation including a condition in which the write word line is biased to a negative voltage.

In the memory device, the write current flows from the source line to the bit line or from the bit line to the source line through the metal layer according to the set deflection condition, and the read current reads from the bit line to the source line through the magnetic tunnel junction. current can flow.

wherein the memory device includes applying a charge current to the metal layer in contact with the free layer to switch magnetization of the free layer of the magnetic tunnel junction, a spin current traversing the charge current is generated to spin in the metal layer - May lead to orbital interactions.

The memory device proposed in the embodiment may achieve a reduction in cell area compared to the conventional SOT-MRAM/STT-MRAM by changing the arrangement of the source line metal.

The memory device proposed in the embodiment may achieve lower write performance than the conventional STT-MRAM by using high spin current injection efficiency.

The memory device proposed in the embodiment can independently optimize each path due to separate read and write currents to obtain lower read power and higher read failure margin compared to STT-MRAM with a common path for read and write operations. can

The memory device proposed in the embodiment may improve the integration density while maintaining inherent advantages such as reliability and energy efficiency associated with the MTJ during a write operation.

1 is a diagram for explaining the structure of a SOT-MRAM.
2 is an example showing bit cells and bias conditions of SOT-MRAM.
3 is a diagram for explaining parameters according to a layout design rule in SOT-MRAM.
4 is an example illustrating a bit cell and a bias condition of an SOT-MRAM according to an embodiment.
5 is a diagram for explaining an example of transistor deflection in an SOT-MRAM according to an embodiment.
6 is a diagram for comparing the SOT-MRAM according to an embodiment and the conventional SOR-MRAM and STT-MRAM.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

1 is a diagram for explaining the structure of a SOT-MRAM.

The three-terminal SOT device may include a magnetic tunnel junction (MTJ), a heavy metal (HM), and a spin-sink layer (SSL) as shown in FIG. 1 . The magnetic tunnel junction MTJ may include a pinned layer (PL) and a free layer (FL) sandwiching the magnetic tunnel junction.

The magnetization of the free layer FL may be compatible with either a parallel (P) state or an antiparallel (AP) state with respect to the pinned magnetization of the pinned layer PL. In the parallel (P) state, the resistance of the magnetic tunnel junction (MTJ) is relatively lower than in the AP state, so it passes a read current through the magnetic tunnel junction (MTJ) terminal T1 and detects the magnetic tunnel junction (MTJ) resistance to beat the bit. It can function as a storage element from which information can be retrieved.

A charge current is applied to the metal layer HM in direct contact with the free layer to switch the free layer FL magnetization. It creates a spin current that crosses the charge current as shown in Fig. 1(b), leading to a spin-orbit interaction in the metal layer. The spin current injected into the upper surface of the metal layer HM exerts a spin transfer torque, causing the magnetization of the free layer FL to be switched. SOT-induced switching eliminates the reliability issues associated with oxide barriers in magnetic tunnel junctions (MTJs) because the oxide barrier is not stressed by high voltage drops. Also note that the spin current IS may be greater than the charge current IC. That is, the spin current injection efficiency can exceed 100% because one deficit flowing through the metal layer HM transfers several units of angular momentum. The spin sink layer (SSL) is attached to the bottom of the metal layer (HM) to further improve the spin current input efficiency by reducing the spin current backflow due to spin polarized electrons on the bottom surface of the metal layer (HM) and the metal layer (HM). .

As shown in FIG. 2, the bit cell of the conventional SOT-MRAM requires two types of transistors. A read access transistor coupled to terminal T1 and a write access transistor coupled to terminal T2 of the metal layer (HM). Because the read path is separate from the write path, each path can be optimized independently. To write a logical value 1 in the bit cell, the bit line BL is set to a positive value (V _W ), the source line SL is set to the ground G _ND , and the write word line WWL is set high. A write current I _W flowing from the bit line BL to the source line SL through the heavy metal HM is generated. Similarly, the logic value 0 can be created by applying the opposite voltage, that is, the positive voltage V _W to the source line SL and the ground to the bit line BL. For a read operation, the source line (SL) is set to ground (G _ND ), the bit line (BL) is connected to the current source, the read word line (RWL) is the read current (IR) and the bit line (BL). It may be designated as high to flow from to the source line SL. The sense amplifier compares the reference voltage V _REF of the reference bit line BL and the cell voltage V _READ of the bit line BL.

3 is a diagram for explaining parameters according to a layout design rule in SOT-MRAM.

The embodiment may provide a memory device for improving integration density while maintaining the advantages of SOT-MRAM. In other words, the memory device means SOT-MRAM designed with a new structure. The memory device proposed in the embodiment may include a plurality of bit lines, a plurality of source lines, a plurality of read word lines, and a plurality of write word lines. The memory device may include a magnetic tunnel junction formed between a bit line and a source line and a plurality of transistors. The magnetic tunnel junction may include a pinned layer and a free layer sandwiching the magnetic tunnel junction. The plurality of transistors may be comprised of a plurality of transistors including a read access transistor coupled to a first terminal of the magnetic tunnel junction and a write access transistor coupled to a second terminal of the metal layer. The read access transistor may be connected to the read word line at the gate side, the bit line at the drain side, and the pinned layer of the magnetic tunnel junction at the source side. The write access transistor may be coupled to the write word line at the gate side, coupled to the bit line at the drain side, and coupled to the metal layer at the source side. In other words, the magnetic tunnel junction may be connected as a pair with respect to a bit line and a source line, a read word line, and a write word line through a plurality of transistors.

The layout of the conventional SOT-MRAM cell includes two metal lines for the source line SL routed in the same direction as the bit line BL to dominate the bit cell area. An object of the present invention is to provide a structure for routing the source line (SL) layer in a direction perpendicular to the bit line (BL) layer capable of reducing the minimum pitch of the cell.

기반 규칙을 사용하여 SOR-MRAM의 레이아웃이 분석될 수 있다. 여기서,

는 최소 형상 크기의 절반을 가리킨다. 실시예에서는 금속 라인 사이의 최소 피치는 6

으로 가정하기로 한다. 배치 설계 규칙에 따른 다른 파라미터는 도 3(a)에 정의되어 있다. 참고로, 접근 트랜지스터의 폭이 작은 경우, 수평 치수는 트랜지스터 폭(W_FET)에 의해 결정되지 않는다. 오히려, 도 3(b)와 같이 금속 피치에 의해 제한될 수 있다. 특히, 동일한 칼럼의 셀들 사이에서 비트 라인(BL)과 소스 라인(SL)을 공유하기 위해서는 기존의 SOT-MRAM은 수직 방향으로 두 개의 금속 라인이 배선되어 있어, x-치수로 12

가 된다. 반대로, 트랜지스터 폭(W_FET)이 9

이상으로 증가하면 수평 치수 또한 도 3(c)와 같이 트랜지스터 폭(W_FET)에 의해 비례하여 증가한다.

The layout of the SOR-MRAM can be analyzed using the base rules. here,

denotes half of the minimum feature size. In an embodiment, the minimum pitch between metal lines is 6

to assume that Other parameters according to the layout design rule are defined in Fig. 3(a). For reference, when the width of the access transistor is small, the horizontal dimension is not determined by the transistor width (W _FET ). Rather, it may be limited by the metal pitch as shown in Fig. 3(b). In particular, in order to share the bit line BL and the source line SL between cells in the same column, in the conventional SOT-MRAM, two metal lines are wired in the vertical direction, so that the x-dimension is 12

becomes Conversely, if the transistor width (W _FET ) is 9

When it increases above the above, the horizontal dimension also increases proportionally with the transistor width (W _FET ) as shown in FIG. 3( c ).

이라고 가정하기로 한다. 이러한 가정은 SOT-MRAM이 100% 초과하는 스핀 전류 투입 효율 덕분에 작은 쓰기 전류로도 10ns 미만의 쓰기 작업을 달성할 수 있다. In the embodiment, the transistor width (W _FET ) of the conventional SOT-MRAM is the maximum required for high memory density of 9

to assume that The assumption is that SOT-MRAM can achieve write operations of less than 10ns with a small write current thanks to the spin current input efficiency exceeding 100%.

The transistor can be obtained as follows.

은 단일 핑거 액세스 트랜지스터를 사용하는 STT-MRAM의 y치수의 2배라는 점에 유의한다. 이 때문에 기존의 SOT-MRAM은 작은 트랜지스터 폭(W_FET)으로도 STT-MRAM과 비교했을 때 비트 셀 면적이 더 커질 수 있다.value of the above expression 23

Note that is twice the y-dimension of STT-MRAM using a single finger access transistor. For this reason, the conventional SOT-MRAM can have a larger bit cell area compared to the STT-MRAM even with a small transistor width (W _FET ).

4 is an example illustrating a bit cell and a bias condition of an SOT-MRAM according to an embodiment.

We propose a modified SOT-MRAM bit cell structure based on the fact that metal lines can be added in the horizontal direction without increasing the cell area to improve the integration density. The proposed structure for routing (routing) the source line SL in the horizontal direction instead of the vertical direction always sets the source line to the ground (G _ND ) as shown in FIG. 4( a ). Read and write operations are performed under the bias conditions shown in FIG. 4(b). When a value of 0 is written, the bit line BL is biased at a negative voltage (V _MINUS ) such that a current flows from the source line SL through the metal layer HM to the bit line BL.

Referring to FIG. 4(b) , the bias condition is a condition in which the bit line is deflected to a negative voltage to write a logical value 0 in the case of a write operation, and a read word line is a negative voltage in order to write a logical value 1 in the case of a write operation. In the case of a read operation and a read operation biased condition, it may be set as a bias condition for a read operation and a write operation including a condition in which a write word line is biased to a negative voltage. For example, depending on the set deflection condition, the write current flows from the source line to the bit line or from the bit line to the source line through the metal layer, and the read current flows from the bit line to the source line through the magnetic tunnel junction. will flow

5 is a diagram for explaining an example of transistor deflection in an SOT-MRAM according to an embodiment.

Applying a negative voltage to the bit line (BL) requires careful transistor bias for reliable and energy-efficient operation. First, the gate-source voltage (V _GS ) of the write access transistor selected to write the value 0 may exceed V _DD if the write word line (WWL) is biased equal to the conventional cell (write access in cell A of Figure 5). transistors). Since excessive gate-source voltage (V _GS ) causes reliability problems of the transistor such as deflection temperature instability, the structure proposed in the embodiment is lower than the nominal V _DD but positive to assert the write word line (WWL). Apply V _WWL . Note that V _WWL lower than V _DD may note the current drive strength for writing the value 1 (Fig. 5(b)). However, it is possible to achieve write operations of less than 10ns due to the high spin current input efficiency. Second, the read word line (RWL) or write word line (WWL) in the proposed scheme is biased to a negative voltage (V _MINUS ) when the associated transistor is not selected for access. Checking that V _GS is less than or equal to zero even if the voltage on the bit line BL is negative prevents the unselected transistor from passing through the leakage current (see the read access transistor in FIG. 5 ). Third, if the transistor body is set to the ground (G _ND ) as in the conventional design, the body-source voltage (V _BS ) may be positive. The body voltage is set to a negative voltage (V _MINUS ) because the positive body-source voltage (V _BS ) induces a forward-biased PN junction between the body sources, resulting in unnecessary leakage current from the unselected cells.

6 is a diagram for comparing the SOT-MRAM according to an embodiment and the conventional SOR-MRAM and STT-MRAM.

6(a) shows a conventional STT-MRAM, FIG. 6(b) shows a conventional SOT-MRAM, and FIG. 6(c) shows a SOT-MRAM proposed in the embodiment.

In order to compare the cells of the SOT-MRAM proposed in the embodiment with the cells of the existing STT-MRAM/SOT-MRAM, the following three simulation frameworks can be used. Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation solver to model magnetization dynamics, Non-Equilibrium Green's Function (NEGF) formalism to obtain magnetic tunnel junction (MTJ) resistance, and circuitry of MRAM bit cells. SPICE simulation for modeling can be used.

The LLGS equation solver determines the critical switching current of each cell based on the magnetic device parameters in Table 1.

Table 1: Parameters of the spin apparatus

The spin current input efficiency of the SOT-MRAM cell, that is, the ratio of IS to IC, can be calculated as follows.

는 실시예에서 0.3으로 가정되는 스핀 홀 각도이다. 표 1에서 A_HM(= t_HM Х W_HM)은 A_MTJ(=

Х W_MTJ Х L_MTJ)보다 작게 설계되어 471%의 높은 스핀 전류 투입 효율이 달성한다는 점에 유의한다. SPICE 회로 시뮬레이션의 경우, MTJ와 HM의 저항을 결정해야 한다. AP와 P 상태에서 MTJ의 전압 의존 저항은 NEGF 기반 전자 전송 시뮬레이션에 의해 계산되는 반면, HM의 저항은 기 설정된 실험 저항 값과 표 1의 장치 치수를 사용하여 추정한다. 또한 상용 45nm 트랜지스터 모델을 사용하여 완전한 메모리 셀 구조를 형성하고 읽기 및 쓰기 작업을 평가한다. 비교는 7ns 스위칭 시간의 동일한 조건에서 설계한 3개의 서로 다른 셀 구조, (IW - IC) / IC로 정의되는 20% 쓰기 마진, 그리고 (IC - IR) / IC로 정의된 읽기-장애 마진의 50% 초과 조건에서 수행된다.where A _MTJ (A _HM ) is the cross-sectional area of MTJ(HM),

is the spin Hall angle assumed to be 0.3 in the embodiment. In Table 1, A _HM (= t _HM Х W _HM ) is A _MTJ (=

Note that it is designed smaller than Х W _MTJ Х L _MTJ ), achieving a high spin current input efficiency of 471%. For SPICE circuit simulation, the resistances of MTJ and HM need to be determined. The voltage-dependent resistance of the MTJ in the AP and P states is calculated by NEGF-based electron transport simulation, while the resistance of the HM is estimated using the preset experimental resistance values and the device dimensions in Table 1. A commercial 45nm transistor model is also used to form a complete memory cell structure and evaluate read and write operations. A comparison is made of three different cell structures designed under the same conditions of 7 ns switching time, (IW - IC) / 20% write margin defined as IC, and 50 of the read-failure margin defined as (IC - IR) / IC. % excess condition.

(=400nm)의 트랜지스터 폭을 요구한다. 이와는 대조적으로, 기존의 SOT-MRAM은 앞에서 언급한 바와 같이 9

(=180nm) 폭으로 설계되어 있다. 상대적으로 트랜지스터 폭이 작더라도 SOT-MRAM은 동일한 7ns 스위칭 사양에 대해 V_WRITE의 낮은 값을 요구하므로 쓰기 전력도 낮아진다. 그러나 SOT-MRAM 셀 면적은 도 6과 같은 2-트랜지스터 요건 때문에 STT-MRAM 셀 면적보다 크다.The simulation results are summarized in Table 2. STT-MRAM requires 20 ns to achieve 7 ns switching time with V _WRITE not exceeding nominal V _DD (=1V).

It requires a transistor width of (=400 nm). In contrast, conventional SOT-MRAM, as mentioned earlier

(=180nm) width is designed. Even with a relatively small transistor width, SOT-MRAM requires a lower value of V _WRITE for the same 7ns switching specification, resulting in lower write power. However, the SOT-MRAM cell area is larger than the STT-MRAM cell area due to the two-transistor requirement as in FIG.

In order to solve the disadvantage of the SOT-MRAM cell area, the cell proposed in the embodiment relaxes the minimum x dimension while maintaining the y-dimension by moving the SL metal line in the horizontal direction as shown in FIG. 6(c). The proposed cell with 80nm size transistor can meet the requirement of 7ns switching time using the deflection conditions in Table 2. Compared to STT-MRAM, the cell proposed in the example exhibits 23% smaller bit cell area (due to minimum x-dimension relaxation) and 6.26 times lower write power (due to high spin input efficiency). Also, unlike the STT device, which has an oxide thickness (1.15 nm) that has a tradeoff between readability and writeability, the SOT device can optimize the oxide thickness (1.45 nm) only for read operations. Because the thick oxide layer translates into a higher resistance that requires a smaller current to generate the same BL voltage during read, the cell proposed in the embodiment has 7.69 times lower read power and 1.88 times higher read-power compared to STT-MRAM. Achieving a margin of failure.

Simulation results show that each bit cell is 42%/23% denser than conventional SOT-MRAM and STT-MRAM, respectively, when designed for 7ns switching time, 20% write margin, and greater than 50% read failure margin. can be checked

The device described above may be implemented as a hardware component, a software component, and/or a combination of the hardware component and the software component. For example, devices and components described in the embodiments may include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA). , a programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions, may be implemented using one or more general purpose or special purpose computers. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For convenience of understanding, although one processing device is sometimes described as being used, one of ordinary skill in the art will recognize that the processing device includes a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that may include For example, the processing device may include a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as parallel processors.

Software may comprise a computer program, code, instructions, or a combination of one or more of these, which configures a processing device to operate as desired or is independently or collectively processed You can command the device. The software and/or data may be any kind of machine, component, physical device, virtual equipment, computer storage medium or device, to be interpreted by or to provide instructions or data to the processing device. may be embodied in The software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored in one or more computer-readable recording media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the medium may be specially designed and configured for the embodiment, or may be known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic such as floppy disks. - includes magneto-optical media, and hardware devices specially configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like.

As described above, although the embodiments have been described with reference to the limited embodiments and drawings, various modifications and variations are possible by those skilled in the art from the above description. For example, the described techniques are performed in a different order than the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (7)

A memory device comprising:
a free layer, a pinned layer, and a magnetic tunnel junction between the free layer and the pinned layer;
a metal layer in contact with one side of the free layer of the magnetic tunnel junction; and
A spin sink layer (SSL) formed under the metal layer
including,
In the memory device, a source line is arranged in a vertical direction with a bit line based on the bit line, and the source line is routed in a horizontal direction to share it with a bit cell belonging to the same horizontal direction to reduce an area of a bit cell, and to perform a read operation Alternatively, for a write operation, the source line arranged in the vertical direction of the bit line is always set to ground, and in the case of the write operation, the bit line is deflected to a negative voltage to write a logic value of 0. In the case of a write operation, Characterized in setting bias conditions for read and write operations, including a condition in which the read word line is deflected to a negative voltage in order to write a logical value 1, and a condition in which the write word line is deflected to a negative voltage in the case of a read operation memory device. delete According to claim 1,
The memory device is
a plurality of transistors comprising a read access transistor coupled to a first terminal of the magnetic tunnel junction and a write access transistor coupled to a second terminal of the metal layer;
A memory device, characterized in that. 4. The method of claim 3,
the read access transistor is connected to a read word line at a gate side, a bit line at a drain side, and a pinned layer of the magnetic tunnel junction at a source side;
The write access transistor is connected to a write word line at a gate side, a bit line at a drain side, and connected to the metal layer at a source side.
A memory device, characterized in that. delete According to claim 1,
The memory device is
Writing a logic value of 0 biases the bit line to a negative voltage, causing current to flow from the source line through the metal layer to the bit line.
A memory device, characterized in that. According to claim 1,
The memory device is
applying a charge current to the metal layer in contact with the free layer to switch the magnetization of the free layer of the magnetic tunnel junction;
A spin current across the charge current is generated leading to spin-orbit interactions in the metal layer.
A memory device, characterized in that.

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