KR102418633B1 - A semiconductor device radiation test method, and a semiconductor device radiation test system - Google Patents

Abstract

Provided is a method for testing radiation of a semiconductor device. The system for testing radiation of a semiconductor device measures an error value of a semiconductor device to be tested by irradiating a test beam for the semiconductor device to be tested disposed on a test board. The semiconductor device to be tested includes a reference semiconductor device to be tested and a general semiconductor device to be tested. The system for testing radiation of the semiconductor device derives a reference error value of the reference semiconductor device to be tested and a reference error value of the general semiconductor device to be tested. The reference error value of the general semiconductor device to be tested may be defined as a relative ratio for the reference error value of the reference semiconductor device to be tested.

Description

A semiconductor device radiation evaluation method, and a semiconductor device radiation evaluation system {A semiconductor device radiation test method, and a semiconductor device radiation test system}

The present application relates to a radiation evaluation method of a semiconductor device and a radiation evaluation system for a semiconductor device, and more particularly, a semiconductor device for measuring an error value due to radiation of a semiconductor device under test by a radiation test beam irradiated to a test board It relates to an evaluation method and a semiconductor device evaluation system.

Semiconductor inspection equipment can be broadly classified into main tester, probe station, handler, and burn-in equipment. , component inspection equipment such as handler that evaluates the normal operation of the package at the final stage after finishing the semiconductor process, and module inspection equipment that inspects whether the module works properly in the state of a module with several semiconductor elements mounted on the PCB. can

As semiconductor devices are miniaturized, various semiconductor evaluation apparatuses are being developed.

For example, in Korean Patent Publication No. 10-1679527, a light generator for generating light irradiated to a semiconductor device, which is a device under test, and a test signal applying unit for applying a test signal for driving the semiconductor device to the semiconductor device; , a photodetector that detects reflected light reflected from the semiconductor device when the light is irradiated to the semiconductor device and outputs a detection signal; A first spectrum analyzer to measure; an analysis unit for deriving phase information of the detection signal at the predetermined frequency based on the first phase information and the second phase information, wherein the first spectrum analyzer operates the first spectrum analyzer Measures the first phase information with respect to the frequency of a reference signal, the second spectrum analyzer measures the second phase information with respect to the frequency of the reference signal for operating the second spectrum analyzer, Disclosed is a semiconductor device inspection apparatus in which the frequency and phase of a reference signal are synchronized with the frequency and phase of the reference signal of the second spectrum analyzer.

One technical problem to be solved by the present application is to provide a method for evaluating the effect of radiation particles on a semiconductor device, and an evaluation system for a semiconductor device.

Another technical problem to be solved by the present application is to provide a method for evaluating a semiconductor device for measuring an error value of a semiconductor device under test by a test beam using radiation or radiation particles irradiated to a test board, and an evaluation system for a semiconductor device there is

Another technical problem to be solved by the present application is to provide a semiconductor device evaluation method and a semiconductor device evaluation system capable of defining reference error values of a plurality of semiconductor devices under test.

Another technical problem to be solved by the present application is a method for evaluating a semiconductor device and a semiconductor device capable of minimizing an error value between an evaluation value and a dose value of a semiconductor device according to a dose difference in consideration of a dose difference according to a region of a test beam to provide an evaluation system of

The technical problem to be solved by the present application is not limited to the above.

In order to solve the above technical problem, the present application provides a method for evaluating a semiconductor device.

According to an embodiment, the method for evaluating the semiconductor device includes preparing a test board, arranging a semiconductor device under test in a test area of the test board, and using the test area of the test board, and measuring an error value of the semiconductor device under test by the test beam by irradiating a test beam, wherein the irradiating the test beam includes: a beam in the test area to which the test beam is irradiated It may include that the irradiation area is changed and the dose of the beam is not uniform.

According to an embodiment, the irradiating of the test beam may include moving the beam irradiation area from a first position of the test area to a second position of the test area.

According to an embodiment, in a state in which the irradiation direction of the test beam is fixed, the test board is moved to move the beam irradiation area from the first position to the second position.

According to an embodiment, the moving direction from the first position to the second position may include a direction perpendicular to a direction in which the test beam is irradiated left and right or up and down.

According to an exemplary embodiment, in the method for evaluating the semiconductor device, the test board moves a minute interval at a constant speed (or continuously moves), or the test board sets a predetermined interval after a reference time elapses. This may include moving.

According to an embodiment, the method for evaluating the semiconductor device may include gradually expanding or gradually decreasing the beam irradiation area according to a distance of the test board to the test beam.

In the above-described embodiment, the beam irradiation distance may be referred to as an evaluation distance, and the beam irradiation distance is a position where the dose of the test beam is measured in advance from the exit of the test beam, and an accurate dose for evaluation is known.

In order to solve the above technical problem, the present application provides an evaluation system for a semiconductor device.

According to an embodiment, in the semiconductor device evaluation system for measuring the error value of the semiconductor device under test by irradiating a test beam to the semiconductor device under test disposed on a test board, the error value of the semiconductor device under test While measuring , the beam irradiation area to which the test beam is irradiated may be changed.

According to an embodiment, the evaluation system of the semiconductor device may derive a reference error value of the semiconductor device under test from an error value measured by the semiconductor device under test while changing the beam irradiation area.

According to an embodiment, the evaluation system of the semiconductor device may derive a dose value for each irradiation area of the test beam from an error value measured by the semiconductor element under test while changing the beam irradiation area.

According to an embodiment, the beam irradiation area may continuously move, or the beam irradiation area may move after a reference time elapses.

According to an embodiment of the present application, a semiconductor device under test is disposed in a test area of a test board, a test beam is irradiated to the test area of the test board, and the semiconductor device under test is performed by the test beam An error value of can be measured.

While the error value of the semiconductor device under test is being measured, a beam irradiation area to which the test beam is irradiated may be changed, so that the test beams of substantially the same quantifiable dose are irradiated to a plurality of the semiconductor devices under test. can be Accordingly, reference error values of the plurality of semiconductor devices under test can be easily defined, and other semiconductor devices under test can be easily and with high reliability by using the plurality of semiconductor devices under test having defined reference error values. can be evaluated

In addition, a plurality of the semiconductor devices under test may be evaluated simultaneously, the evaluation time may be shortened, and the accuracy of the evaluation result may be improved.

1 is a view for explaining a system for evaluating a semiconductor device according to an embodiment of the present application.
2 is a view for explaining a dose change according to an evaluation distance of a test beam used in the evaluation system of a semiconductor device according to an embodiment of the present application.
3 is a diagram for explaining a difference in reference error values of a semiconductor device under test used in a semiconductor device evaluation system according to an embodiment of the present application.
4 is a diagram for explaining a difference in dose for each region of a test beam used in a system for evaluating a semiconductor device according to an embodiment of the present application.
5 is a view for explaining a difference in error values according to characteristics of a test beam and a semiconductor device under test used in the evaluation system of a semiconductor device according to an embodiment of the present application.
6 is a flowchart illustrating a method for evaluating a semiconductor device according to an exemplary embodiment of the present application.
7 is a view for explaining a process of changing a beam irradiation area in the system for preventing crime and evaluating a semiconductor device according to an embodiment of the present application.
8 is a view for explaining examples of arrangement of a plurality of semiconductor devices under test in a method for evaluating a semiconductor device and a system for evaluating a semiconductor device according to an embodiment of the present application.
9 is a view for explaining a process of moving a beam irradiation area in a method for evaluating a semiconductor device and a system for evaluating a semiconductor device according to an embodiment of the present application. The reference dose value for each region of the beam can be confirmed by a method of deriving the reference error value.
10 is a view for explaining a beam irradiation area and a test area in a method for evaluating a semiconductor device and a system for evaluating a semiconductor device according to an embodiment of the present application.
11 is a view for explaining a process of overlapping the beam irradiation area and the test area of FIG. 10 .
12 to 15 are graphs illustrating error values of a semiconductor device under test measured according to a method for evaluating a semiconductor device according to an embodiment of the present application.
16 is a view for explaining a step-by-step overlapping process and a scanning process in a method for evaluating a semiconductor device and a system for evaluating a semiconductor device according to an embodiment of the present application.
17 is a graph illustrating an error value for each device according to step-by-step overlap in a method for evaluating a semiconductor device and a system for evaluating a semiconductor device according to an embodiment of the present application.
18 is a view for explaining a scanning process in a method for evaluating a semiconductor device and a system for evaluating a semiconductor device according to an embodiment of the present application.
19 is a graph illustrating an error value for each device according to a scan process in a method for evaluating a semiconductor device and an evaluation system for a semiconductor device according to an embodiment of the present application.
20 and 21 are graphs for explaining the sameness of the dose of a test beam irradiated to a semiconductor device under test in a method for evaluating a semiconductor device and a system for evaluating a semiconductor device according to an embodiment of the present application.
22 is a view for explaining an internal structure of a semiconductor device under test according to an embodiment of the present application.
23 is a view for explaining a process of applying the evaluation method of a semiconductor device according to an embodiment of the present application to the semiconductor device under test having the internal structure of FIG. 22 .
24 and 25 are diagrams for explaining a system for evaluating a semiconductor device according to an embodiment of the present application.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical spirit of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed content may be thorough and complete, and the spirit of the present invention may be sufficiently conveyed to those skilled in the art.

In addition, in various embodiments of the present specification, terms such as first, second, third, etc. are used to describe various components, but these components should not be limited by these terms. These terms are only used to distinguish one component from another. Accordingly, what is referred to as a first component in one embodiment may be referred to as a second component in another embodiment. Each embodiment described and illustrated herein also includes a complementary embodiment thereof. In addition, in this specification, 'and/or' is used in the sense of including at least one of the components listed before and after.

In the specification, the singular expression includes the plural expression unless the context clearly dictates otherwise. In addition, terms such as "comprise" or "have" are intended to designate that a feature, number, step, element, or a combination thereof described in the specification exists, but one or more other features, number, step, configuration It should not be construed as excluding the possibility of the presence or addition of elements or combinations thereof. In addition, in the following description of the present invention, if it is determined that a detailed description of a related well-known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

In the present application, "beam" includes radiation and/or radiation particles, and may be interpreted as including radiation particles such as alpha particles, neutrons, protons, heavy ions, gamma rays, and X-rays, and in the present application An error occurring in a semiconductor device under test can be interpreted as a general meaning including soft errors such as single bit upset (SBU), multi bit upset (MBU), and multi cell upset (MCU) among single event upset (SEU). .

In addition, it is obvious that the subject who manufactures and sells the evaluation system of the semiconductor device described in the specification of the present application and the subject who performs the method for evaluating the semiconductor device described in the specification of the present application may be different.

In addition, the semiconductor device under test described in the specification of the present application includes SRAM, flash memory, DRAM, cache memory, logic IC, image sensor device, display device, power IC, RF IC, SSD, RRAM, PRAM, MRAM, etc. It is obvious that various analog and/or digital semiconductor devices not specified may be included.

In addition, the dose described in the present application may be interpreted as meaning including the number of particles irradiated to a given area for a unit time, or the number of particles irradiated to a unit area for a given time, including flux It is apparent to those skilled in the art that it can be interpreted in the meaning of

A general semiconductor device evaluation equipment is for evaluating various defects occurring in the production process. On the other hand, according to an embodiment of the present application, an evaluation method and an evaluation system are provided for evaluating a defect caused by radiation in a semiconductor device that passes through all evaluation processes after being produced and operates normally.

In addition, the evaluation system of a semiconductor device to be described later may further include a control area including a computer device and software in addition to the beam irradiation area.

1 is a view for explaining a system for evaluating a semiconductor device according to an embodiment of the present application.

Referring to FIG. 1 , the evaluation system of a semiconductor device according to an embodiment of the present application may include a beam irradiation region 5 and a control region 10 .

A test board 110 on which a plurality of semiconductor devices under test 120 are disposed may be provided in the beam irradiation area 5 , and the plurality of semiconductor devices under test 120 of the test board 110 may be provided. A test beam 130 may be irradiated. An error may occur in the plurality of semiconductor devices under test 120 by the test beam 130 .

The UUT motion table 5a in the beam irradiation area 5 may control the movement of the test board 110 to change the area to which the test beam 130 is irradiated, as will be described later.

The algorithm board 5b may include a UUT motion control unit, a semiconductor function control unit, an algorithm control unit, and a voltage, current, temperature, and image control unit. The algorithm board 5b may measure and count errors occurring in a plurality of the semiconductor devices under test 120, and transmit an error value to the base control system 10a of the control area 10 through a remote communication unit. can transmit, the base control system 10a through the remote communication unit, the UUT motion control unit, the semiconductor function control unit, the algorithm control unit, and the voltage, current, temperature, and image of the algorithm board 5b The control unit may control the operation.

The base analysis system 10b of the control region 10 analyzes the error values of the plurality of semiconductor devices under test 120 received from the base control system 10a, and the plurality of semiconductor devices under test A reference error value of (120) can be defined/measured/calculated.

In other words, the semiconductor device evaluation system according to the embodiment of the present application may analyze and store the evaluation result of the semiconductor device under test 120 .

In general, the dose of the test beam 130 irradiated to the semiconductor device under test 120 is different depending on the beam source, and the dose varies depending on the distance between the beam source and the semiconductor device under test 120 . A difference occurs, and a difference in dose occurs for each region within the beam irradiation region to which the test beam 130 is irradiated, and the semiconductor device under test 120 according to the irradiated dose also has a reference error value and an error rate. Therefore, it is not easy to define the reference error value of the semiconductor device under test 120 . Hereinafter, it will be described in more detail with reference to FIGS. 2 to 5 .

2 is a view for explaining a dose change according to an evaluation distance of a test beam used in an evaluation system for a semiconductor device according to an embodiment of the present application, and FIG. 3 is a view for explaining a change in dose according to an embodiment of the present application. It is a diagram for explaining the difference in the reference error value of the semiconductor device under test used, and FIG. 4 is a diagram for explaining the difference in dose for each region of the test beam used in the evaluation system of the semiconductor device according to the embodiment of the present application, 5 is a diagram for explaining a difference in error values according to characteristics of a test beam and a semiconductor device under test used in the evaluation system of a semiconductor device according to an embodiment of the present application.

Referring to FIG. 2 , a beam irradiation area 132 may be defined on the test board 110 among the overall areas to which the test beam 130 is irradiated from the beam source. However, as shown in FIG. 2 , when the test board 110 is located at a position relatively close to the beam source, and when the test board 110 is located at a position relatively far from the beam source , the beam irradiation area 132 may be different. Specifically, as shown in FIG. 2 , when the distance between the beam source and the test board 110 is relatively close, the beam irradiation area 132 is relatively narrow and a reference area of the beam irradiation area 132 is relatively small. The dose of the test beam 132 irradiated by the . On the other hand, as shown in FIG. 2 , when the distance between the beam source and the test board 110 is relatively long, the beam irradiation area 132 is relatively wide and the reference area of the beam irradiation area 132 is relatively large. The dose of the test beam 132 irradiated to the .

Referring to FIG. 3 , when a plurality of the semiconductor devices under test are disposed on the test board, each of the plurality of semiconductor devices under test may have a reference error value and an error ratio with respect to the test beam. In other words, each of the plurality of semiconductor devices under test may not have the same sensitivity to the test beam, but may be different, so that even in an environment in which the test beam of the same dose is irradiated to the plurality of semiconductor devices under test , may have different error values and error rates, respectively, as shown in FIG. 3 . FIG. 3 shows the ratio of the reference error value and the error ratio of the semiconductor device under test located at the center among the plurality of semiconductor devices under test, when it is assumed that 100 is the reference error value and the error ratio.

Referring to FIG. 4 , in a beam irradiation region to which a test beam is irradiated, a difference in dose may occur for each region. That is, as shown in FIG. 4 , a relatively dark region (a gray or black region in FIG. 4 ) is a region irradiated with a relatively small dose of the test beam, and a relatively light region (white in FIG. 4 ). A region close to ) is a region to which a relatively large dose of the test beam is irradiated.

Referring to FIG. 5 , in a case in which the plurality of semiconductor devices under test described with reference to FIG. 3 are disposed in the beam irradiation area described with reference to FIG. 4 , the difference in dose even within the beam irradiation area to which the test beam is irradiated , as well as the plurality of semiconductor devices under test also have different sensitivities to the test beam, and thus may have reference error values and error ratios.

In conclusion, the uniformity of the beam profile of the test beam is not uniform within the beam irradiation area, and a difference in dose occurs in the beam irradiation area according to the distance between the beam source and the test board, and a plurality of the A difference in sensitivity of the test semiconductor device according to the test beam occurs. For this reason, there is a limit to the accurate measurement of error values and error ratios of the plurality of semiconductor devices under test by the test beam. In order to solve these problems, reference error values and reference errors of the plurality of semiconductor devices under test We need a definition of the ratio.

6 is a flowchart illustrating a method for evaluating a semiconductor device according to an exemplary embodiment of the present application.

Referring to FIG. 6 , a test board is prepared ( S110 ), a plurality of semiconductor devices under test are disposed in a test area of the test board ( S120 ), and a test beam is irradiated to the test area of the test board to perform the test. Error values of the plurality of semiconductor devices under test by the beam may be measured ( S130 ).

In this case, the beam irradiation area in the test area to which the test beam is irradiated may be changed. In other words, the beam irradiation area in the test area may be moved, expanded, and/or reduced, so that the test beam may be irradiated with the same dose to the plurality of semiconductor devices under test, as a result, Reference error values and error ratios of the plurality of semiconductor devices under test may be checked.

In order to analyze the reference error value and the error rate, the result of the beam irradiation region in which the error value of the semiconductor device under test is measured may be transmitted to the control region 10 described with reference to FIG. 1 ( S140 ). .

Thereafter, by analyzing the measurement results in the base control system 10a and the base analysis system 10b of the control area 10 , an error rate and a dose may be analyzed. In other words, analysis of the reference error value and the error rate may be performed.

FIG. 7 is a view for explaining a process of changing a beam irradiation area in the system for preventing crime and evaluating a semiconductor device according to an embodiment of the present application.

Referring to FIG. 7 , a plurality of the semiconductor devices under test 120 may be disposed in the test region 112 of the test board 110 , and the test beam may be irradiated to the test region 112 . have.

As shown in FIG. 7 , three axes (X-axis, Y-axis, and Z-axis) may be defined, and the X-axis and the Y-axis may be parallel to the upper surface and the side surface of the test board 110 , respectively. The X axis may be parallel to the upper surface and the Y axis may be parallel to the side surface, and the Z axis may be parallel to the direction in which the test beam is irradiated to the test board 110 (that is, the evaluation distance).

According to an embodiment, the beam irradiation region may be moved from a first position of the test region 112 to a second position of the test region 112 , and the beam irradiation region may be moved from the first position to the second position. The direction may be parallel to the X-axis or parallel to the Y-axis. Specifically, in a state in which the irradiation direction of the test beam is fixed, the test board 110 may move in a direction parallel to the X-axis or in a direction parallel to the Y-axis, whereby, The beam irradiation area within the test area 112 may be moved. Alternatively, alternatively, in a state in which the test board 110 is fixed, the irradiation direction of the test beam may move in a direction parallel to the X-axis or may move in a direction parallel to the Y-axis, thereby , the beam irradiation area within the test area 112 may move. In other words, in a state in which the test board 110 is fixed, the collimator of the test beam may move in the X-axis and/or the Y-axis direction within the beam area.

Alternatively, according to another embodiment, as described above, the beam irradiation region moves from the first position of the test region 112 to the second position of the test region 112, but at the first position A direction of movement to the second position may be parallel to the Z-axis. Specifically, in a state in which the beam source irradiating the test beam is fixed, the test board 110 may move in a direction parallel to the Z-axis, and thus, the beam irradiation area within the test area 112 . This can be expanded or contracted. Alternatively, the beam source may move in a direction parallel to the Z-axis while the test board 110 is fixed, and thus, the beam irradiation area in the test area may be expanded or reduced. . In other words, for example, in the evaluation of accelerated alpha, the coin-sized AM241, which is a particle source of alpha particles, may move in the X-axis and/or Y-axis direction. That is, the distance between the beam source and the test board 110 may be adjusted, so that the beam irradiation area in the test area 112 may be changed.

8 is a view for explaining arrangement examples of a plurality of semiconductor devices under test in a method for evaluating a semiconductor device and a system for evaluating a semiconductor device according to an embodiment of the present application.

Referring to FIG. 8 , a plurality of semiconductor devices under test may be disposed in the test area 112 matching the beam irradiation area 132 . Specifically, as shown in FIG. 8A , a plurality of semiconductor devices under test may be disposed in the test area 112 divided into a plurality of grids, and in each grid. Alternatively, as shown in (b) of FIG. 8, a plurality of the semiconductor devices under test located inside the grid but on the center line centered in the X-axis direction of the test region 112, unlike in FIG. 8 (a). can be placed. Alternatively, as shown in (c) of FIG. 8 , a plurality of the semiconductor devices under test may be arranged based on a line that is located inside the grid but intersects center lines in the center of each of the X-axis and the Y-axis. .

It is obvious that, in addition to those shown in FIGS. 8A to 8C , the plurality of semiconductor devices under test may be disposed in various forms on the test board 110, and the technical idea of the present application is, The plurality of semiconductor devices under test are not limited according to the shape and shape of the plurality of semiconductor devices disposed on the test board 110 .

9 is a view for explaining a process of moving a beam irradiation area in a method for evaluating a semiconductor device and a system for evaluating a semiconductor device according to an embodiment of the present application.

Referring to FIG. 9 , a plurality of the semiconductor devices under test 120 may be disposed on the test board 110 , and a beam irradiation region 132 to which the test beam is irradiated may be provided.

In the description with reference to FIG. 9, it is described that the test board 110 is moved in a direction parallel to the X-axis of FIG. 7, but is not limited thereto, and the test board 110 in a direction parallel to the Y-axis of FIG. It is apparent to those skilled in the art that the test board 110 may be moved or the test board 110 may be moved in a direction parallel to the Z-axis of FIG. 7 . In addition, although it is described that the test board 110 is moved, it is not limited thereto, and it is obvious that the test board 110 is fixed and the beam source irradiating the test beam may be moved. Also, the test board 110 and the beam source may be moved at the same time.

Also, in the description with reference to FIG. 9 , it is apparent to those skilled in the art that the plurality of semiconductor devices under test may be disposed in a shape and arrangement different from those disposed on the test board 110 .

In addition, in the description with reference to FIG. 9 , it is described that a plurality of the semiconductor devices under test are disposed on the test board 110 , but the present invention is not limited thereto, and one semiconductor device under test is disposed on the test board 110 . It is obvious to those skilled in the art that it can be arranged. Alternatively, it is apparent to those skilled in the art that the plurality of semiconductor devices under test may be disposed on the test board 110 along the X axis, the Y axis, or the X and Y axes.

Continuing to refer to Fig. 9, as shown in Figs. 9 (a) to 9 (d), the beam irradiation area 132 is located outside the test board 110 and gradually moves while The rightmost semiconductor element under test 120 and the beam irradiation region 132 overlap, the test beam is irradiated to the rightmost semiconductor element under test 120, and in turn, the rightmost semiconductor element under test The test beam may also be irradiated to the semiconductor devices under test 120 located on the left side of the semiconductor device 120 . Finally, the leftmost semiconductor element under test 120 and the beam irradiation region 132 overlap, the test beam is irradiated to the leftmost semiconductor element under test 120 , and a plurality of the Irradiation of the test beam to the semiconductor device 120 may be terminated. 9 illustrates that the test beam is irradiated 9 times, the technical idea according to the embodiment of the present application is not limited thereto.

As described above, while the test beam is irradiated to the plurality of semiconductor devices under test 120 , that is, while the beam irradiation region 132 overlaps the plurality of semiconductor devices under test 120 , a plurality of Errors occurring in the semiconductor device under test 120 of may be measured and counted. Errors occurring in the plurality of semiconductor devices under test 120 are the algorithm board, the base control system 10a, and the base analysis system 10b of the evaluation system of the semiconductor device described with reference to FIG. 1 . can be measured, counted, and analyzed through In addition, the same effect may be realized in the evaluation of the semiconductor device through the scan process to be described later.

According to one modification, as described with reference to FIG. 9 , after the test beam is irradiated from the rightmost semiconductor device under test 120 to the leftmost semiconductor device under test 120, Again, the test beam may be irradiated again from the leftmost semiconductor device under test 120 to the rightmost semiconductor device under test 120 .

As such, when the process of irradiating the test beam to all the plurality of semiconductor devices under test 120 is defined as a unit cycle, the unit cycle may be performed once or may be performed multiple times, and may be performed once or a plurality of times. During the operation, errors occurring in the plurality of semiconductor devices under test 120 may be measured and counted.

Also, as in the above-described modified example, when the unit cycle is performed a plurality of times, directions in which the test beams move may be the same or different from each other. In other words, for example, when the unit cycle is performed twice, as described with reference to FIG. 9 , the leftmost semiconductor element 120 in the rightmost semiconductor element under test 120 . ), the test beam may be moved from the leftmost semiconductor device under test 120 to the rightmost semiconductor device under test 120 . That is, the test board 110 moves in the + direction (moving from left to right) and the - direction (moving from right to left) in the X-axis direction, so that the unit cycle may be performed.

Or, for another example, when the unit cycle is performed twice, in the first unit cycle, the test board 110 moves in the X-axis in the + direction or the - direction, and the unit in the second time In a cycle, the test board 110 may move in a + direction (moving from bottom to top) or a direction (moving from top to bottom) along the Y-axis.

Or, for another example, when the unit cycle is performed twice, in the first unit cycle, the test board 110 moves in the X-axis in the + direction or the - direction, and in the second In the unit cycle, the test board 110 may move along the Z-axis in the + direction (moving from the paper to the viewer) or the - direction (moving from the viewer to the ground).

Or, for another example, when the unit cycle is performed twice, in the first unit cycle, the test board 110 moves in the Y-axis in the + direction or the - direction, and in the second In a unit cycle, the test board 110 may move in a + direction or a - direction along the Z-axis.

As such, when the unit cycle is performed a plurality of times, directions in which the test beam is irradiated to the test board 110 in the plurality of unit cycles may be the same or different from each other.

10 is a view for explaining a beam irradiation region and a test region in a semiconductor device evaluation method and semiconductor device evaluation system according to an embodiment of the present application, and FIG. 11 is a process of overlapping the beam irradiation region and the test region of FIG. 10 . 12 to 15 are graphs illustrating an error value of a semiconductor device under test measured according to a method for evaluating a semiconductor device according to an embodiment of the present application.

Referring to FIGS. 10 and 11 , as shown in FIG. 10A , the beam irradiation area to which the test beam is irradiated may be divided into a plurality of gratings, and L1 to L5 within the beam irradiation area. Regions can be defined.

In addition, as shown in FIG. 10B , the test area of the test board may also be partitioned into a plurality of gratings to correspond to the beam irradiation area, and a plurality of the semiconductor devices under test D1 in the test area. ~D5 may be deployed.

Thereafter, as shown in FIG. 11 , the D5 overlaps the L1, and the D4, the D3, the D2, and the D1 overlap the L1, and finally the D1 overlaps the L5. , the unit cycle may end.

As described above, during the unit cycle, error values for the L1 to L5 of the D1 to D5 that are the semiconductor device under test may be measured and counted.

For example, when the difference in dose between L1 to L5 is compared with the average value of the total dose 132, it is the same as in Table 1 below, and the difference between the reference error values of D1 to D5 is < In the case of Table 2>, an error value may be measured as shown in Table 3 and FIG. 12 below.

As can be seen from <Table 3> and FIG. 12 below, the measured error value was found to have a maximum value of 121 when the D5 is located in the L3, and a minimum value of 81 when the D2 is located in the L5. appeared to have Among a plurality of error values, when 100, which is a value adjacent to the median value, is used as a reference, an error value in which the D3 is located in the L4 may be defined as the reference error value of the D3, and the D1, the D2, the D4 and the The reference error value of D5 may be defined as 105, 90, 95, and 110, which are relative ratios to the reference error value of D3 at the L4 position where the reference error value of D3 is defined.

L1 L2 L3 L4 L5 -5% +5% +10% 0% -10%

D1 D2 D3 D4 D5 105 90 100 95 110

L1 L2 L3 L4 L5 D1 99.75 110.25 115.5 105 94.5 D2 85.5 94.5 99 90 81 D3 95 105 110 100 90 D4 90.25 99.78 104.5 95 85.5 D5 104.5 115.5 121 110 99

For another example, when the difference in dose between L1 and L5 is the same as in <Table 1>, and the difference in the error value between D1 and D5 is the same as in <Table 4> below, <Table 5> > and an error value may be measured as shown in FIG. 13 .

As can be seen from <Table 5> and FIG. 13 below, the measured error value was found to have a maximum value of 121 when the D1 is located in the L3, and a minimum value of 85.5 when the D2 is located in the L5. appeared to have Among a plurality of error values, when 100, which is a value adjacent to a median value, is used as a reference, an error value in which the D4 is located in the L4 may be defined as the reference error value of the D4, and the D1, the D2, the D3 and the The reference error value of D5 may be defined as 110, 95, 105, and 107, which are relative ratios to the reference error value of D4 at the L4 position where the reference error value of D4 is defined.

D1 D2 D3 D4 D5 110 95 105 100 107

L1 L2 L3 L4 L5 D1 104.5 115.5 121 110 99 D2 90.25 99.75 104.5 95 85.5 D3 99.75 110.25 115.5 105 94.5 D4 95 105 110 100 90 D5 101.65 112.35 117.7 107 96.3

As another example, when the difference in dose between L1 to L5 is as in <Table 6> below, and the difference in error values between D1 to D5 is the same as in <Table 2>, the following <Table 6> 7> and an error value may be measured as shown in FIG. 14 .

As can be seen from <Table 7> and FIG. 14 below, the measured error value was found to have a maximum value of 121 when the D5 is located in the L4, and a minimum value of 81 when the D2 is located in the L1. appeared to have Among a plurality of error values, when 100, which is a value adjacent to a median value, is used as a reference, an error value in which the D3 is located in the L2 may be defined as the reference error value of the D3, and the D1, the D2, the D4 and the The reference error value of D5 may be defined as 105, 90, 95, and 110, which are relative ratios to the reference error value of D3 at the L2 position where the reference error value of D3 is defined.

L1 L2 L3 L4 L5 -10% 0% 7% 10% -5%

L1 L2 L3 L4 L5 D1 94.5 105 112.35 115.5 99.75 D2 81 90 96.3 99 85.5 D3 90 100 107 110 95 D4 85.5 95 101.65 104.5 90.25 D5 99 110 117.7 121 104.5

As another example, when the difference in dose between L1 to L5 is the same as in <Table 6>, and the difference in the error value between D1 to D5 is the same as in <Table 4>, the following <Table 8> > and an error value may be measured as shown in FIG. 15 .

As can be seen from <Table 8> and FIG. 15 below, the measured error value was found to have a maximum value of 121 when the D1 is located in the L4, and a minimum value of 85.5 when the D2 is located in the L1 appeared to have Among a plurality of error values, when 100, which is a value adjacent to a median value, is used as a reference, an error value in which D4 is located in L2 may be defined as the reference error value of D4, and the D1, D2, D3 and The reference error value of D5 may be defined as 110, 95, 105, and 107, which are relative ratios to the reference error value of D4 at the L2 position where the reference error value of D4 is defined.

L1 L2 L3 L4 L5 D1 99 110 117.7 121 104.5 D2 85.5 95 101.65 104.5 90.25 D3 94.5 105 112.35 115.5 99.75 D4 90 100 107 110 95 D5 96.3 107 114.49 117.7 101.65

As described above, through the unit cycle, while the test beam is irradiated to the plurality of semiconductor devices under test, error values for the plurality of semiconductor devices under test may be measured. Among the plurality of semiconductor devices under test, any one semiconductor device under test that does not have a maximum error value and a minimum error value and has a median or an error value close to the median is defined as a reference semiconductor device under test, The error value of the semiconductor device under test may be defined as a reference error value, and the reference error value of the semiconductor device under test (general semiconductor device under test) other than the reference semiconductor device under test is the reference error value of the reference semiconductor device under test. It can be defined as a ratio relative to a reference error value. In addition, as described above, the reference semiconductor device under test may be defined as any one semiconductor device under test having a median value or an error value close to the median value among the plurality of semiconductor devices under test. The test semiconductor device includes a first type general semiconductor under test having a reference error value higher than a reference error value of the reference semiconductor device under test, and a first type general semiconductor device under test having a reference error value lower than the reference error value of the reference semiconductor device under test Two-type general semiconductor devices under test may be included.

In other words, through the unit cycle, the test beam of the same dose may be irradiated to the D1 to D5, and based on the error value measured in a state in which the test beam of the same dose is irradiated, a plurality of the Reference error values for the test semiconductor device may be respectively defined. Accordingly, it is possible to minimize variations in error values due to differences in doses for each area of the irradiated test beam, thereby securing reliability of the reference error values of the plurality of semiconductor devices under test.

According to an embodiment, other statistical methods may be used, as described above. Specifically, the reference dose value is also set and applied like the reference error value setting. In this case, if both the reference error value and the reference dose value are unknown, if one of the reference values is known, there are cases where both are known, and in this case, the third It is also possible to calculate a reference error value of , and a third reference dose value. For example, if the average dose value of the beam and the error range according to the dose change are given as in the examples of FIGS. 4 to 5 , the median value of the semiconductor device under test can be calculated as in the examples of FIGS. 10 to 15 . . It has already been seen in the examples of FIGS. 10 to 15 that the median value obtained here is also proportionally changed at other locations where the dose change occurs. It can be seen that the proportional deviation of the average dose value is distributed around the median value of the semiconductor device under test, showing the proportional deviation of the error value. It is also self-evident that the dose value of the beam under test can be obtained through the same proportional relationship through the median value of the semiconductor element under test.

In the unit cycle, depending on the measurement method, the beam irradiation area and the semiconductor element under test may overlap in stages, or the beam irradiation area may move/scan at a constant speed (continuously) on the semiconductor elements under test have. Hereinafter, a step-by-step overlapping process and a scanning process will be described with reference to FIGS. 16 to 19 .

16 is a diagram for explaining a step-by-step overlapping process and a scanning process in a semiconductor device evaluation method and a semiconductor device evaluation system according to an embodiment of the present application, and FIG. 17 is a semiconductor device evaluation method according to an embodiment of the present application and a graph showing an error value for each device according to the step-by-step overlap in the evaluation system of the semiconductor device.

11, 16 and 17, as described with reference to FIG. 11, the D1 to D5, which are the semiconductor devices under test, are provided, and the beam irradiation area having the L1 to L5 is provided. can be

The test board 110 may move every time a reference time elapses. That is, the test board 110 may move stepwisely or in a steplike arrangement in a chip unit, a cell unit, or a predetermined grid unit. In other words, after the reference time elapses while the L1 overlaps the D5, the test board 110 may move. Due to the movement of the test board 110 , the L1 and the L2 overlap the D4 and the D5, respectively, and after the reference time elapses, the test board 110 may move. Due to the movement of the test board 110 , the L1 , the L2 , and the L3 overlap the D3 , the D4 , and the D5 , and after the reference time elapses, the test board 110 may move. As the test board 110 moves, the L1, the L2, the L3, and the L4 overlap the D2, the D3, the D4, and the D5, respectively, and after the reference time elapses, the test board 110 ) can be moved. As the test board 110 moves, the L1, the L2, the L3, the L4, and the L5 overlap the D1, the D2, the D3, the D4, and the D5, respectively, and the reference time has elapsed. Thereafter, the test board 110 may move. As the test board 110 moves, the L2, the L3, the L4, and the L5 overlap the D1, the D2, the D3, and the D4, respectively, and after the reference time elapses, the test board 110 ) can be moved. Due to the movement of the test board 110 , the L3 , the L4 , and the L5 overlap the D1 , the D2 , and the D3 , respectively, and the test board 110 may move after the reference time elapses. Due to the movement of the test board 110 , the L4 and L5 overlap the D1 and D2 , respectively, and after the reference time elapses, the test board 110 may move. Due to the movement of the test board 110 , the L5 overlaps the D1 and the test board 110 may move after the reference time elapses. Accordingly, the unit cycle may end.

As shown in FIG. 16 , when the width of the semiconductor device under test is defined as W _DUT and the interval between the semiconductor devices under test is defined as W _Gap , the total width W _UUT is the sum of W _DUT and W _Gap . can be defined as

In addition, when the width of the test beam is defined as W _Beam , the total width W _total through which the test beam is irradiated to the semiconductor device under test may be defined as the sum of W _UUT and W _Beam .

In addition, when the unit cycle based on the stepwise overlapping movement is performed after the reference time has elapsed, the error rate values for each position (the L1 to the L5) of the semiconductor device under test (the D1 to the D5) are shown in FIG. It may be displayed as shown. The graph of FIG. 17 is created with reference to Table 1 and the data of the graph of FIG. 12 .

In addition, it is apparent to those skilled in the art that the test beam may have various shapes, such as a square, an oval, and the like, rather than a circular shape.

18 is a diagram for explaining a scanning process in a semiconductor device evaluation method and a semiconductor device evaluation system according to an embodiment of the present application, and FIG. 19 is a semiconductor device evaluation method and a semiconductor device according to an embodiment of the present application. It is a graph showing the error value for each device according to the scan process in the evaluation system.

11, 18 and 19 , as described with reference to FIG. 11 , the D1 to D5 that are the semiconductor devices under test are provided, and the beam irradiation area having the L1 to L5 is provided can be

The test board 110 may move at a constant speed (continuously). In other words, the test board 110 may move at a constant speed, so that the D1 to D5 may overlap the L1 to L5. Specifically, as shown in FIG. 18, when the L1 starts to be positioned on the D5, it moves at a constant speed, and the L1 is positioned on the D5, the D4, the D3, the D2 and the D1, The L2 is located on the D5, the D4, the D3, the D2 and the D1 from a time point when the L1 is not located on the D5 (overlapping is finished), and the L3 is the L2 is located on the D5 From a point in time at which the overlapping is not completed (overlapping is terminated), it is sequentially positioned on the D5, the D4, the D3, the D2, and the D1, and the L4 is the time when the L3 is not positioned on the D5 (the overlapping is ended) are sequentially positioned on the D5, the D4, the D3, the D2, and the D1, and the L5 is the D5, the D4, and the D3 , may be sequentially positioned on the D2 and the D1.

As described above, when the unit cycle is performed by the scan process, the error rate values for each position (the L1 to the L5) of the semiconductor device under test (the D1 to the D5) are displayed as shown in FIG. can The graph of FIG. 19 is created with reference to the data of the graph of FIG. 12 . Also, the dose of the test beam irradiated to the semiconductor device under test may be calculated as an integral value.

20 and 21 are graphs for explaining the sameness of the dose of a test beam irradiated to a semiconductor device under test in a method for evaluating a semiconductor device and a system for evaluating a semiconductor device according to an embodiment of the present application.

Referring to FIGS. 20 and 21 , as described with reference to FIG. 11 , the D1 to D5 that are the semiconductor devices under test are provided, and the beam irradiation region having the L1 to L5 is provided, and the The test beam may be irradiated to D1 to D5.

20 and 21 , the period during which the D1 to D5 are exposed to the test beam may be the same. In other words, since the exposure times of the D1 to D5 to the test beam are the same, and all of the D1 to D5 overlap the L1 to L5, the L1 that is the beam irradiation area of the test beam Even if there is a difference in dose between ~L5, the doses of the test beams irradiated to the D1 ~ D5 located on the same X-axis may be substantially the same. That is, due to the result of the above-described step-by-step superposition process or scanning process, substantially the same dose for substantially the same time (during the same moving time) to the semiconductor device under test arranged in a direction parallel to the moving direction of the test beam may be irradiated with the test beam of , so that the accumulated dose is substantially the same.

In conclusion, in the unit cycle process in which the beam irradiation region (the L1 to the L5) to which the test beam is irradiated to the plurality of the semiconductor devices under test (the D1 to the D5) is moved and irradiated, the plurality of the The doses of the test beams irradiated to the test semiconductor may be substantially the same, and thus, the difference in error values according to the difference in doses for each area of the test beam is minimized, so that the reference of the plurality of semiconductor devices under test Reliability for error values may be improved.

That is, according to FIGS. 20 and 21 and the description referring to them, the reference error of D1 to D5 may be calculated, and the reference dose of L1 to L5 may also be calculated. If either the reference error or the reference dose is known, an unknown reference error or reference dose value can be derived. In addition, as can be seen from FIG. 21 , the reference dose value may constitute a profile of a continuous beam. In addition, the average error value of each device may be obtained from the cumulative evaluation values of D1 to D5.

22 is a view for explaining an internal structure of a semiconductor device under test according to an embodiment of the present application, and FIG. 23 is a view of a semiconductor device according to an embodiment of the present application for the semiconductor device under test having the internal structure of FIG. 22 It is a diagram for explaining the application process of the evaluation method.

22 and 23 , the D4 and D5 that are the semiconductor devices under test described with reference to FIG. 11 may be provided to overlap the beam irradiation regions L1 and L2, respectively.

As shown in FIG. 22 , D4 and D5 may include a plurality of columns. In this case, as shown in FIG. 23 , when the D5 starts to overlap with the L1, column 4 overlaps the beam irradiation area of the test beam with the L1, and then, the column 4 and column 3 overlap the L1 , then column 4, column 3, and column 2 overlap with L1, then column 4, column 3, column 2, and column 1 overlap with L1, then column 3, column 2 and column 1 When the D5 overlaps the L1, the column 2 and the column 1 overlap the L1, and the column 1 overlaps the L1, and the D5 overlaps the L1, an error value may be measured.

In other words, the test board 110 moves to correspond to the spacing of the columns of the semiconductor device under test (the D5), so that substantially the same dose is applied to each column in the semiconductor device under test (the D5). A test beam may be irradiated. In other words, the test board 110 is moved so that any one column (column 4) in the semiconductor device under test overlaps the beam irradiation area of the test beam, and after a reference time elapses, the test The test board 110 may be moved in such a way that the board 110 is moved so that columns 4 and 3 in the semiconductor device under test overlap the beam irradiation area of the test beam.

Thereafter, as the sum of the error values generated in each column, an error value in a state in which the D5 overlaps the L1 may be measured.

In addition, by using the evaluation system of the semiconductor device shown in FIGS. 24 and 25, which will be described later, the test beam can be more easily and precisely irradiated according to the column position of the memory device described with reference to FIGS. 22 and 23. Also, the profile of the test beam can be analyzed more precisely through the error rate analysis according to columns. That is, the evaluation and analysis technology applied to the semiconductor device under test is applied to the fine column structure, so that more fine and precise dose analysis and evaluation of the test beam can be performed.

24 and 25 are diagrams for explaining a system for evaluating a semiconductor device according to an embodiment of the present application.

24 and 25 , in the evaluation system of a semiconductor device according to an embodiment of the present application, a grip unit 220 for fixing the test board 110 , and a driving motor 230 for moving the grip unit 220 . and a driving gear 240 , and a control unit 210 for controlling the driving motor 230 .

The semiconductor device evaluation system of FIG. 24 may move the test board 110 in the X-axis direction, and the semiconductor device evaluation system of FIG. 25 may move the test board 110 in the Y-axis direction. have.

Accordingly, the test board 110 can be easily moved in a stable and fixed state, so that the evaluation method of the semiconductor device according to the embodiment of the present application described with reference to FIGS. 1 to 23 is easy. can be carried out

However, in addition to the method shown in FIGS. 24 and 25 , the test board 110 can move through various methods and various configurations, and the technical idea according to the embodiment of the present application is the semiconductor shown in FIGS. 24 and 25 . It is not limited to the configuration of the evaluation system of the device. That is, one driving device incorporating FIGS. 24 and 25 may be implemented, and a device movable in the Z-axis may be further implemented.

As mentioned above, although the present invention has been described in detail using preferred embodiments, the scope of the present invention is not limited to specific embodiments and should be construed according to the appended claims. In addition, those skilled in the art should understand that many modifications and variations are possible without departing from the scope of the present invention.

5: Beam irradiation area
5a: UUT motion table
5b: Algorithm Board
10: control area
10a: base control system
10b: bass analysis system
110: test board
120: semiconductor element under test
130: test beam
132: beam irradiation area

Claims (8)

preparing a test board;
disposing a semiconductor device under test in a test area of the test board;
measuring an error value of the semiconductor device under test by irradiating a test beam to the test area of the test board; and
receiving the error value of the semiconductor device under test and analyzing the error value of the device under test;
The step of irradiating the test beam,
and changing a beam irradiation area in the test area to which the test beam is irradiated.
According to claim 1,
The step of irradiating the test beam,
and moving the beam irradiation region from a first position of the test region to a second position of the test region that does not overlap the first position.
3. The method of claim 2,
and wherein the test board is moved in a state in which the irradiation direction of the test beam is fixed, and the beam irradiation area is moved from the first position to the second position.
3. The method of claim 2,
and a direction moving from the first position to the second position is perpendicular to a direction in which the test beam is irradiated.
A semiconductor device evaluation system for measuring an error value of a semiconductor device under test by irradiating a test beam with respect to a semiconductor device under test disposed on a test board, the system comprising:
The semiconductor device evaluation system irradiates the test beam to a test area in which the semiconductor device under test is disposed, and measures an error value of the semiconductor device under test by the test beam;
The evaluation system of the semiconductor device includes a base control system that receives the error value of the semiconductor device under test, and a base analysis system that analyzes the error value of the semiconductor device under test received from the base control system,
and changing a beam irradiation area to which the test beam is irradiated while measuring the error value of the semiconductor element under test.
6. The method of claim 5,
and deriving a reference error value of the semiconductor element under test from an error value measured by the semiconductor element under test while changing the beam irradiation area.
7. The method of claim 6,
and deriving a dose value for each irradiation area of the test beam from an error value measured in the semiconductor element under test while changing the beam irradiation area.
8. The method of claim 7,
an algorithm board for measuring and counting errors occurring in the semiconductor device under test;
a beam irradiation area in which the test board is disposed and the test beam is irradiated; and
The evaluation system of a semiconductor device further comprising a control region that is isolated from the beam irradiation region, to which the test beam is not irradiated.

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