KR102417730B1 - Display driving circuit and display device including the same - Google Patents

Abstract

A display driving circuit and a display device including the same are provided. The display driving circuit includes a source driver for applying source data to the display panel, a power supply unit receiving an external voltage from the power module to generate an internal voltage, and a logic unit receiving the internal voltage and controlling the source driver, the logic The unit includes a voltage variable determination logic for generating a voltage variable signal by determining whether a supply voltage including the internal voltage and the external voltage is changed, and a voltage adjustment logic for receiving the voltage variable signal and changing the supply voltage .

Description

Display driving circuit and display device including the same

The present invention relates to a display driving circuit and a display device including the same.

As the resolution of an organic light emitting mobile display increases, a gate-count of a digital logic of a display driving integrated circuit (DDI) increases and current consumption increases.

However, a user's mobile phone usage pattern is changing to low power consumption for a long time, such as an AOD mode (always-on-display mode). Therefore, the need to reduce the current consumption of digital logic is gradually increasing.

In addition, when power of the mobile phone is dynamically consumed instead of statically, efficient execution of logic operations may be implemented.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display driving circuit that improves efficiency of power consumption by applying a variable voltage.

Another object to be solved by the present invention is to provide a display device including a display driving circuit for improving efficiency of power consumption by applying a variable voltage.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A display driving circuit according to some embodiments of the present invention for solving the above problems includes a source driver that applies source data to a display panel, a power supply unit that receives an external voltage from a power module and generates an internal voltage, and receives the internal voltage , a logic unit for controlling the source driver, wherein the logic unit determines whether a supply voltage including the internal voltage and the external voltage is changed to generate a voltage variable determination logic to generate a voltage variable signal; and voltage regulation logic to receive and change the supply voltage.

A display device according to some embodiments of the present invention for solving the above other problems includes a display panel for displaying an image, a display driving circuit for driving the display panel by transmitting the image and a gate signal, and driving the display panel and the display A power module for providing an external voltage to a circuit, wherein the display driving circuit includes: a power supply unit configured to receive an external voltage from the power module and generate an internal voltage; and a logic unit for determining whether to change and changing the internal voltage and/or the external voltage.

A display driving circuit according to some embodiments of the present invention for solving the above problems includes a source driver for applying source data corresponding to image data to a display panel, a power supply unit for receiving an external voltage from a power module to generate an internal voltage, and a frame frequency a clock generator generating a clock having a voltage variable determination logic for generating a voltage variable signal by determining whether the internal voltage and/or the external voltage are changed in consideration of at least one of the frame frequencies; and the internal voltage and/or the external voltage according to the voltage variable signal It contains voltage regulation logic to change the voltage.

1 is a block diagram illustrating a display device according to some embodiments of the present invention.
FIG. 2 is a block diagram illustrating in detail the display driving circuit of FIG. 1 .
3 is a block diagram for describing the logic unit of FIG. 2 in detail.
4 is a table for explaining power consumption characteristics according to an operation mode of a display apparatus according to some embodiments of the present invention.
5 is a block diagram for describing the power supply unit of FIG. 2 in detail.
FIG. 6 is a block diagram illustrating in detail the first power supply unit of FIG. 5 .
7 is a block diagram illustrating a display driving circuit according to some embodiments of the present invention.
8 is a block diagram for describing the logic unit of FIG. 7 in detail.
9 is a block diagram illustrating a relationship between the display driving circuit and the power module of FIG. 7 .
10 is a block diagram illustrating a display driving circuit according to some embodiments of the present invention.
11 is a block diagram for describing the logic unit of FIG. 10 in detail.
12 is a block diagram illustrating a display driving circuit according to some embodiments of the present invention.
13 is a block diagram illustrating a display driving circuit according to some embodiments of the present invention.
14 is a block diagram for describing the logic unit of FIG. 13 in detail.
15 is a block diagram illustrating a display driving circuit according to some embodiments of the present invention.
16 is a block diagram for describing the logic unit of FIG. 15 in detail.
17 is a block diagram for describing the power supply unit of FIG. 15 in detail.

Hereinafter, a display apparatus according to some embodiments of the present invention will be described with reference to FIGS. 1 to 6 .

FIG. 1 is a block diagram illustrating a display device according to some embodiments of the present disclosure, and FIG. 2 is a block diagram illustrating a display driving circuit of FIG. 1 in detail. FIG. 3 is a block diagram for describing the logic unit of FIG. 2 in detail, and FIG. 4 is a table for explaining power consumption characteristics according to an operation mode of a display apparatus according to some embodiments of the present invention. FIG. 5 is a block diagram illustrating the power supply unit of FIG. 2 in detail, and FIG. 6 is a block diagram illustrating the first power supply unit of FIG. 5 in detail.

Referring to FIG. 1 , a display device according to some embodiments of the present invention includes a processor 100 , a processor interface 150 , a first display driving circuit 200 , a display panel 300 , a power module 400 , and a power supply. interface 450 .

The display device may be implemented as, for example, a portable electronic device. According to various embodiments, the first display driving circuit 200 and the display panel 300 may be implemented as a separate (or external) display device (or display module) other than the processor 100 .

The processor 100 may control the overall operation of the display device. According to an embodiment, the processor 100 may be implemented as an integrated circuit, a system on a chip, or a mobile application processor (AP). The processor 100 may transmit data to be displayed (eg, image data, video data, or still image data) to the first display driving circuit 200 . According to an embodiment, the data may be divided into source data SD units corresponding to horizontal lines (or vertical lines) of the display panel 300 .

The first display driving circuit 200 may change the data transmitted from the processor 100 to a form that can be transmitted to the display panel 300 , and transmit the changed data to the display panel 300 . The source data SD may be supplied in units of pixels.

Here, a pixel has a structure in which sub-pixels Red, Green, and Blue are arranged adjacently in relation to a designated color display, and one pixel includes RGB sub-pixels (RGB stripe layout structure) or includes RGB sub-pixels (Pentile layout structure) )can do. Here, the arrangement structure of the RGBG sub-pixels may be replaced with the arrangement structure of the RGBG sub-pixels. Alternatively, the pixel may be replaced with an RGBW sub-pixel arrangement structure. However, the present embodiment is not limited thereto.

The processor interface 150 may interface signals or data exchanged between the processor 100 and the first display driving circuit 200 . The processor interface 150 may interface line data (SD) transmitted from the processor 100 to the first display driving circuit 200 . According to an embodiment, the processor interface 150 may include a Mobile Industry Processor Interface (MIPI®) (MIPI), a Mobile Display Digital Interface (MDDI), a DisplayPort, an Embedded DisplayPort (eDP), and the like. It may be an interface related to the same serial interface.

The display panel 300 may display the source data SD by the first display driving circuit 200 . In some embodiments, the display panel 300 includes a thin film transistor-liquid crystal display (TFT-LCD) panel, a light emitting diode (LED) display panel, an organic LED (OLED) display panel, and an active matrix OLED (AMOLED) display panel. , or a flexible display panel or the like.

In the display panel 300 , for example, gate lines and source lines may be intersected in a matrix form.

Source data SD or a signal corresponding to the source data SD may be supplied to the source lines. A signal corresponding to the source data SD may be in the form of an analog voltage.

The power module 400 may manage power of the display device. According to an embodiment, the power module 400 may include a power management integrated circuit (PMIC), a charger integrated circuit (IC), or a battery or fuel gauge.

The power module 400 may have a wired and/or wireless charging method. The wireless charging method includes, for example, a magnetic resonance method, a magnetic induction method or an electromagnetic wave method, and may further include an additional circuit for wireless charging, for example, a coil loop, a resonance circuit, or a rectifier. have.

The power module 400 may receive a command from the processor 100 to supply power to each part of the display device. The power module 400 may supply power to the first display driving circuit 200 and the display panel 300 , respectively.

Specifically, the power module 400 may provide the external voltage EV to the first display driving circuit 200 . The external voltage EV may be processed and used inside the first display driving circuit 200 .

The power interface 450 may interface between the power module 400 and the first display driving circuit 200 . Specifically, the power interface 450 may transmit commands transmitted from the first display driving circuit 200 to the power module 400 . Since the power interface 450 exists separately from the processor interface 150 , the first display driving circuit 200 may be directly connected to the power module 400 without going through the processor 100 .

Referring to FIG. 2 , the first display driving circuit 200 may include a first logic unit 210 , a memory 220 , a source driver 230 , a gate driver 240 , and a first power supply unit 250 . have.

Although not shown, the first logic unit 210 is basically a memory write controller, a timing controller, a memory read controller, an image processing unit, and a source shift It may include a source shift register controller and a data shift register.

The memory write controller of the first logic unit 210 may receive the image data Image transmitted from the processor interface 150 and control an operation of writing the received image data Image to the memory 220 .

The timing controller may supply a synchronizing signal and/or a clock signal to each component (eg, the memory read controller) of the first display driving circuit 200 .

Also, the timing controller may transmit a read command for controlling a read operation of the memory 220 to the memory read controller.

The timing controller may control supply of the source data SD of the source driver 230 . Also, the timing controller may control the output of the gate signal GS of the gate driver 240 through the gate control signal Gate Ctr.

The memory read controller may perform a read operation on the image data Image stored in the memory 220 . According to an embodiment, the memory read controller may perform a read operation on all or part of the image data Image stored in the memory 220 based on a read command for the image data Image.

The memory read controller may transmit all of the image data Image read from the memory 220 or a part of the image data Image to the image processing unit.

Although the memory write controller and the memory read controller are separately described for convenience of description, they may be implemented as one memory controller.

The image processing unit may improve image quality by processing all of the image data or a part of the image data transmitted from the memory read controller. The image data Image with improved image quality may be transmitted to the timing controller as source data SD, and the timing controller may transmit the source data SD to the source driver 230 .

The source shift register controller may control a data shifting operation of the data shift register. According to an embodiment, the source shift register controller may perform control such as writing image data in the memory 220 and image preprocessing of the image processing unit in response to a command received from the processor 100 .

The data shift register may shift the image data Image transmitted through the source shift register controller, that is, the source data SD, under the control of the source shift register controller. The data shift register may sequentially transmit the shifted source data SD to the source driver 230 .

The memory 220 may store the source data SD input through the memory write controller under the control of the memory write controller. The memory 220 may operate as a buffer memory in the first display driving circuit 200 . According to an embodiment, the memory 220 may include a graphic random access memory (GRAM).

The source driver 230 may transmit the source data SD transmitted from the first logic unit 210 to the display panel 300 . According to an embodiment, the source driver 230 may include an amplifier connected for each sub-pixel (or for each channel allocated to each sub-pixel). The amplifiers included in the source driver 230 may be driven in units of pixels. For example, the amplifiers included in the source driver 230 may be grouped for each pixel (eg, RGB sub-pixels or RGB sub-pixels) configured to output a specified color (eg, white or black). The source driver 230 may share and use the amplifier output allocated to a sub-pixel designated within one pixel to at least one other sub-pixel.

The gate driver 240 may drive gate lines of the display panel 300 . That is, as the operation of pixels implemented in the display panel 300 is controlled by the source driver 230 and the gate driver 240 , the source data SD input from the processor 100 is transmitted to the display panel 300 . can be displayed.

The first power supply unit 250 may receive the external voltage EV to generate a first internal voltage IV1 and a second internal voltage IV2 . The first power unit 250 may supply the first internal voltage IV1 to the first logic unit 210 . The first power supply unit 250 may supply the second internal voltage IV2 to the memory 220 .

The first power unit 250 may receive the first voltage change signal CV1 from the first logic unit 210 . When receiving the first voltage change signal CV1 , the first power unit 250 may supply the changed first internal voltage IV1 ′ to the first logic unit 210 instead of the first internal voltage IV1 .

Referring to FIG. 3 , the first logic unit 210 may further include a voltage variable determination logic 211 and a first voltage adjustment logic 212 .

The voltage variable determination logic 211 may receive a mode signal Mode, image data Image, and a clock Clk from the processor 100 . The voltage variable determination logic 211 may determine whether it is necessary to vary the supply voltage of the first logic unit 210 using at least one of the mode signal Mode, the image data Image, and the clock Clk. In this case, the "supply voltage" may mean the first internal voltage IV1. The voltage variable determination logic 211 may generate the first voltage variable signal S1 when it is determined that the supply voltage needs to be varied.

3 and 4 , the display device may operate in a plurality of modes, each of which has a different toggle amount, a different on pixel ratio (OPR), and a different frame frequency. can have

The toggle amount may mean the total number of times of toggling because signal toggling occurs when there is a signal different from that of an adjacent pixel in the display panel 300 . That is, when the number of times when the difference in luminance between adjacent pixels is large, the toggle amount may increase. When the amount of toggles is high, more power may be required.

OPR may be a ratio of turned-on pixels among pixels of the entire display panel 300 . Naturally, the higher the OPR, the more power may be required.

For example, the A mode may have a toggle amount, an OPR, and a frame frequency of specific values as a normal mode. In contrast, the B mode may have a higher toggle amount, a higher OPR, and a higher frame frequency than the A mode. In this case, in the B mode, the operation of the display device can be performed quickly only by using a higher supply voltage. Accordingly, in this case, the voltage variable determination logic 211 may generate the first voltage variable signal S1 because it is necessary to vary the supply voltage.

Conversely, the C mode may have a lower toggle amount, a lower OPR, and a lower frame frequency compared to the A mode. In this case, in the C mode, the operation of the display device can be performed without a problem even when a lower supply voltage is used, and power consumption can be reduced. Accordingly, in this case, the voltage variable determination logic 211 may generate the first voltage variable signal S1 because it is necessary to vary the supply voltage.

The B mode and C mode are only examples of the operation mode, and characteristics of each mode are not limited thereto. Also, in each mode, each characteristic may have opposite directions. That is, there may be a mode in which the torque amount is increased but the OPR is decreased. In this case, the voltage variable determination logic 211 may comprehensively determine a plurality of characteristics to determine whether the supply voltage is variable and generate the first voltage variable signal S1 accordingly.

The C mode may be an Always-On-Display (AOD) mode. The AOD mode maintains low luminance, but the display may be always turned on. For example, the AOD mode may appear in the form of a clock or a calendar displayed on the display. However, the present embodiment is not limited thereto.

In detail, the voltage variable determination logic 211 may obtain the mode conversion information from the mode signal Mode of the processor 100 . Accordingly, the voltage variable determination logic 211 may receive the mode signal Mode and determine whether the supply voltage is variable through this. That is, the voltage variable determination logic 211 may generate the first voltage variable signal S1 according to the mode signal Mode.

Alternatively, since the voltage variable determination logic 211 receives the image data Image from the processor 100, a toggle amount directly from the image data Image, an OPR and/or an average of the most significant bit (MSB), etc. It is also possible to determine whether the supply voltage is variable by determining the characteristics of . In this case, the most significant bit may be used as a unit of brightness. That is, the value of the most significant bit may vary according to the brightness of the pixel.

At this time, the determined characteristic is not limited to the toggle amount, OPR, and/or average of the most significant bit. That is, the voltage variable determination logic 211 may generate the first voltage variable signal S1 by comprehensively determining various characteristics of the image data Image.

Alternatively, the voltage variable determination logic 211 may obtain the clock Clk from the processor 100 or another external device. Accordingly, the voltage variable determination logic 211 may determine whether the supply voltage is variable based on the frame frequency of the clock Clk. Here, the frame frequency means a speed at which the display device displays data on one screen, and display may be performed by a clock Clk having a frame frequency. That is, the voltage variable determination logic 211 may generate the first voltage variable signal S1 according to the frame frequency of the clock Clk.

As described above, the voltage variable determination logic 211 may generate the first variable voltage signal S1 using at least one of the mode signal Mode, the image data Image, and the frame frequency. That is, not only each element of the mode signal (Mode), image data (Image), and frame frequency is the basis of judgment, but two of the mode signal (Mode), image data (Image) and frame frequency are considered as factors Thus, the first voltage variable signal S1 may be generated. Of course, the voltage variable determination logic 211 may generate the first voltage variable signal S1 based on all of the mode signal Mode, the image data Image, and the frame frequency.

Referring again to FIG. 3 , the first voltage adjustment logic 212 may receive the first voltage variable signal S1 from the voltage variable determination logic 211 . The first voltage control logic 212 may generate the first voltage change signal CV1 according to the first voltage variable signal S1 .

Referring to FIG. 5 , the first power supply unit 250 may include a first sub power supply unit 251 and a second sub power unit 252 .

The first sub-power unit 251 and the second sub-power unit 252 may generate a first internal voltage IV1 and a second internal voltage IV2, respectively. Both the first sub power supply unit 251 and the second sub power supply unit 252 may receive the external voltage EV to generate the first internal voltage IV1 and the second internal voltage IV2 respectively.

The first internal voltage IV1 of the first sub power unit 251 is supplied to the first logic unit 210 , and the second internal voltage IV2 of the second sub power unit 252 is supplied to the memory 220 . can In some embodiments of the present invention, there may be further sub-power units that additionally generate internal voltages supplied to other components.

The first sub-power unit 251 may receive the first voltage change signal CV1 , and accordingly change the first internal voltage IV1 to the changed first internal voltage IV1 ′. That is, the first sub-power supply unit 251 supplies the first internal voltage IV1 to the first logic unit 210 , and transmits the first voltage change signal CV1 from the first logic unit 210 to the first voltage change signal CV1 . One internal voltage IV1 ′ may be supplied to the first logic unit 210 .

Referring to FIG. 6 , the first sub power unit 251 may include a regulator RGT and a variable resistance column Rv.

The regulator RGT may output the first internal voltage IV1 using the external voltage EV and the reference voltage Vref. The regulator RGT may output a constant voltage. In this case, the level of the output first internal voltage IV1 may be adjusted by the variable resistance column Rv.

The variable resistance column Rv may be designed to adjust a position in contact with the + terminal of the operational amplifier of the regulator RGT in the series resistor. Accordingly, the first voltage change signal CV1 may adjust a position in contact with the + terminal of the operational amplifier of the regulator RGT of the variable resistance column Rv. Accordingly, the magnitude of the first internal voltage IV1 may vary according to the ratio of the first resistor R1 to the second resistor R2 .

That is, the first voltage change signal CV1 may not be an output signal of a digital circuit but may be in the form of a mechanical manipulation of an analog circuit. That is, the first voltage control logic 212 may operate to adjust the contact point of the variable resistance column Rv, and this may be defined as the first voltage change signal CV1.

Accordingly, the output of the regulator RGT may be changed from the first internal voltage IV1 to the changed first internal voltage IV1'.

Existing display driving circuits are always driven using a constant voltage, thus consuming a constant power even when a large voltage is not required, and processing using the existing constant power even when higher performance is required through a larger voltage. carried out.

In contrast, the display device according to some embodiments of the present invention can efficiently use the voltage as the internal voltage is adjusted as described above. That is, the display driving circuit may be supplied with a higher voltage when higher performance is required with a higher voltage, and may be supplied with a lower voltage without wasting when it can be sufficiently driven with a lower voltage.

Accordingly, efficiency of voltage supply to the entire display device may be increased, and meaningless power consumption may be minimized.

Hereinafter, a display driving circuit of a display device according to some embodiments of the present invention will be described with reference to FIGS. 7 to 9 . Descriptions overlapping with the above description will be omitted or simplified.

7 is a block diagram illustrating a display driving circuit according to some embodiments of the present disclosure, and FIG. 8 is a block diagram illustrating the logic unit of FIG. 7 in detail. 9 is a block diagram illustrating a relationship between the display driving circuit and the power module of FIG. 7 .

7 and 9 , the second display driving circuit 200_1 of the display device according to some embodiments of the present invention includes a second logic unit 210_1.

The second logic unit 210_1 may transmit the second voltage change signal CV2 to the outside of the second display driving circuit 200_1 without transmitting the voltage change signal to the first power supply unit 250 . The second voltage change signal CV2 may be directly transmitted to the power module 400 of FIG. 9 . Accordingly, the power module 400 may change the external voltage EV supplied to the first power supply unit 250 into the changed external voltage EV'.

The first power unit 250 may generate the same first internal voltage IV1 by using the changed external voltage EV'. Accordingly, although the second logic unit 210_1 receives the same first internal voltage IV1 , the second display driving circuit 200_1 actually uses the changed external voltage EV′ that is changed as a whole, so power consumption may vary. have.

Referring to FIG. 8 , the second logic unit 210_1 may include a second voltage control logic 212_1 . The second voltage adjustment logic 212_1 may receive the first voltage variable signal S1 from the voltage variable determination logic 211 . When the second voltage control logic 212_1 receives the first voltage variable signal S1 , it may generate the second voltage change signal CV2 accordingly.

As described above, the second voltage change signal CV2 may be directly transmitted to the power module 400 instead of the first power supply 250 . The second voltage change signal CV2 may be a digital signal having the form of a command, but is not limited thereto.

According to the present embodiment, when the amount of current used can be reduced, the internal voltage is used the same but the external voltage is changed to be smaller to achieve lower power consumption of the entire display device.

Hereinafter, a display driving circuit of a display device according to some embodiments of the present disclosure will be described with reference to FIGS. 9, 10 and 11 . Descriptions overlapping with the above description will be omitted or simplified.

10 is a block diagram illustrating a display driving circuit according to some embodiments of the present disclosure, and FIG. 11 is a block diagram illustrating the logic unit of FIG. 10 in detail.

9, 10, and 11 , the third display driving circuit 200_2 of the display device according to some embodiments of the present invention includes a third logic unit 210_2.

The third logic unit 210_2 may transmit the first voltage change signal CV1 to the first power unit 250 . The first power supply unit 250 may change the first internal voltage IV1 to the changed first internal voltage IV1'.

The third logic unit 210_2 may also transmit the second voltage change signal CV2 to the outside of the second display driving circuit 200_1 . The second voltage change signal CV2 may be directly transmitted to the power module 400 of FIG. 9 . Accordingly, the power module 400 may change the external voltage EV supplied to the first power supply unit 250 into the changed external voltage EV'.

The first power unit 250 may generate the same first internal voltage IV1 or the changed first internal voltage IV1' by using the changed external voltage EV'. Accordingly, the power consumed by the entire third display driving circuit 200_2 changes as the external voltage EV is changed to the changed external voltage EV′, and the power consumed by the third logic unit 210_2 is also It may be changed as the first internal voltage IV1 is changed to the changed first internal voltage IV1'.

Referring to FIG. 11 , the third logic unit 210_2 may include a third voltage control logic 212_2 . The third voltage adjustment logic 212_2 may receive the first voltage variable signal S1 from the voltage variable determination logic 211 . When the third voltage control logic 212_2 receives the first voltage change signal S1 , it may generate the first voltage change signal CV1 and the second voltage change signal CV2 accordingly.

As described above, the first voltage change signal CV1 may be transmitted to the first power supply unit 250 , and the second voltage change signal CV2 may be transmitted to the power module 400 .

According to the present exemplary embodiment, the display driving circuit of the display device simultaneously controls the internal voltage and the external voltage to achieve more precise and efficient power consumption.

Hereinafter, a display driving circuit of a display device according to some embodiments of the present invention will be described with reference to FIGS. 1 and 12 . Descriptions overlapping with the above description will be omitted or simplified.

12 is a block diagram illustrating a display driving circuit according to some embodiments of the present invention.

1 and 12 , a fourth display driving circuit 200_3 of a display device according to some embodiments of the present disclosure includes a fourth logic unit 210_3 and a clock generation unit 260 .

The clock generator 260 may generate a clock Clk used in the fourth display driving circuit 200_3 . The clock generator 260 may supply the clock Clk having the frame frequency to the fourth logic unit 210_3 .

The fourth logic unit 210_3 may transmit the time control signal Time Ctr to the clock generation unit 260 . The time control signal Time Ctr may be a signal for changing the frame frequency of the clock Clk. The clock generator 260 may generate a modified clock Clk' obtained by changing the frame frequency of the clock Clk according to the time control signal Time Ctr.

For example, the fourth logic unit 210_3 may receive a command to change the frame frequency from the processor 100 of FIG. 1 . This may simply come in the form of a frame frequency change signal, or it may come in the form of a command that requests various other operations together, such as a mode signal (Mode).

Accordingly, the fourth logic unit 210_3 may transmit the time control signal Time Ctr to the clock generation unit 260 . Through this, the fourth logic unit 210_3 may receive the changed clock Clk′ having the changed frame frequency from the clock generator 260 .

As described above, the fourth logic unit 210_3 changes the first voltage change signal CV1 and the second voltage through at least one of the frame frequencies of the mode signal Mode, the image data Image, and the clock Clk. A signal CV2 may be generated. Although it is illustrated in FIG. 12 that the fourth logic unit 210_3 generates both the first voltage change signal CV1 and the second voltage change signal CV2, the present exemplary embodiment is not limited thereto. That is, in the display driving circuit according to some embodiments of the present disclosure, the fourth logic unit 210_3 may generate only one of the first voltage change signal CV1 and the second voltage change signal CV2 .

Hereinafter, a display driving circuit of a display device according to some exemplary embodiments will be described with reference to FIGS. 1, 13 and 14 . Descriptions overlapping with the above description will be omitted or simplified.

13 is a block diagram illustrating a display driving circuit according to some embodiments of the present disclosure, and FIG. 14 is a block diagram illustrating the logic unit of FIG. 13 in detail.

1 and 13 , a fifth display driving circuit 200_4 of a display device according to some embodiments of the present disclosure includes a fifth logic unit 210_4.

The fifth logic unit 210_4 may transmit the stored image data Image0 previously received from the processor 100 to the memory 220 , and the memory 220 may store the received stored image data Image0 . After that, the memory 220 may transmit the stored image data Image0 to the fifth logic unit 210_4 again.

The fifth logic unit 210_4 may separately receive the first image data Image1 and the mode signal Mode from the processor 100 .

13 and 14 , the fifth logic unit 210_4 may include an image comparison module 213 .

The image comparison module 213 may receive the stored image data Image0 received from the memory 220 and the first image data Image1 received from the processor 100 . The image comparison module 213 may determine similarity by comparing the stored image data Image0 and the first image data Image1 with each other.

The image comparison module 213 may transmit the time control signal Time Ctr to the clock generator 260 when it is determined that the stored image data Image0 and the first image data Image1 are similar to each other by a predetermined portion or more. When the clock generator 260 receives the time control signal Time Ctr, the clock generator 260 may change the frame frequency of the clock Clk to generate the changed clock Clk'. The clock generator 260 may transmit the changed clock Clk' to the fifth logic unit 210_4.

This is to efficiently use resources because the overall speed does not drop even when the frame frequency is lowered when processing an image having a pattern similar to that of the previous image. That is, the display apparatus can maintain the same level of performance even when the clock Clk according to the lower frame frequency is used because the amount of calculation is small. Accordingly, the display device of the present embodiment can consume lower power with the same level of performance.

As described above, the fifth logic unit 210_4 changes the first voltage change signal CV1 and the second voltage through at least one of the frame frequencies of the mode signal Mode, the image data Image, and the clock Clk. A signal CV2 may be generated. That is, even when the frame frequency is lowered due to the image similarity, the fifth logic unit 210_4 may vary the voltage based on this.

In FIG. 13 , it is illustrated that the fifth logic unit 210_4 generates both the first voltage change signal CV1 and the second voltage change signal CV2 , but the present embodiment is not limited thereto. That is, in the display driving circuit according to some embodiments of the present disclosure, the fifth logic unit 210_4 may generate only one of the first voltage change signal CV1 and the second voltage change signal CV2 .

Hereinafter, a display driving circuit of a display device according to some exemplary embodiments will be described with reference to FIGS. 9 and 15 to 17 . Descriptions overlapping with the above description will be omitted or simplified.

15 is a block diagram illustrating a display driving circuit according to some embodiments of the present disclosure, and FIG. 16 is a block diagram illustrating the logic unit of FIG. 15 in detail. 17 is a block diagram for describing the power supply unit of FIG. 15 in detail.

9 and 15 to 17 , the sixth display driving circuit 200_5 of the display device according to some embodiments of the present invention includes a sixth logic unit 210_5 and a second power supply unit 250_1 . .

The sixth logic unit 210_5 may transmit the stored image data Image0 previously received from the processor 100 to the memory 220 , and the memory 220 may store the received stored image data Image0 . After that, the memory 220 may transmit the stored image data Image0 to the sixth logic unit 210_5 again.

The sixth logic unit 210_5 may separately receive the first image data Image1 and the mode signal Mode from the processor 100 . In addition, the sixth logic unit 210_5 may also receive the clock Clk from the processor 100 , but is not limited thereto. The display driving circuit of the display device according to some embodiments of the present invention may include a clock generator that provides the clock Clk to the sixth logic unit 210_5 . That is, in this case, the sixth logic unit 210_5 may receive the clock Clk through the clock generator.

The sixth logic unit 210_5 may transmit the first voltage change signal CV1 and the third voltage change signal CV3 to the second power supply unit 250_1 . Also, the sixth logic unit 210_5 may transmit the second voltage change signal CV2 to the power module 400 . In FIG. 15 , the sixth logic unit 210_5 is illustrated as generating all of the first voltage change signal CV1 , the second voltage change signal CV2 , and the third voltage change signal CV3 , but is limited thereto. not. In the display driving circuit of the display device according to some embodiments of the present invention, only one or any two of the first voltage change signal CV1, the second voltage change signal CV2, and the third voltage change signal CV3 is generated. It is also possible

The sixth logic unit 210_5 includes a voltage variable determination logic 211 and a fourth voltage adjustment logic 212_3 .

The voltage variable determination logic 211 may receive the mode signal Mode, the first image data Image1 and the clock Clk from the processor 100 , and receive the stored image data Image0 from the memory 220 . have.

The voltage variable determination logic 211 may determine whether it is necessary to vary the supply voltage of the sixth logic unit 210_5 using at least one of the mode signal Mode, the first image data Image1, and the clock Clk. have. The “supply voltage” may include a first internal voltage IV1 and/or an external voltage EV. The voltage variable determination logic 211 may generate the first voltage variable signal S1 when it is determined that the supply voltage needs to be varied.

In addition, the voltage variable determination logic 211 may determine whether it is necessary to vary the supply voltage of the memory 220 using at least one of the first image data Image1 and the stored image data Image0 . The “supply voltage” may include a second internal voltage IV2 and/or an external voltage EV. The voltage variable determination logic 211 may generate a second voltage variable signal S2 when it is determined that the supply voltage needs to be varied.

The fourth voltage adjustment logic 212_3 may receive the first voltage variable signal S1 from the voltage variable determination logic 211 . The fourth voltage control logic 212_3 may generate the first voltage change signal CV1 and the second voltage change signal CV2 according to the first voltage change signal S1 .

Also, the fourth voltage adjustment logic 212_3 may receive the second voltage variable signal S2 from the voltage variable determination logic 211 . The fourth voltage control logic 212_3 may generate the third voltage change signal CV3 according to the second voltage variable signal S2 .

The second power supply unit 250_1 may include a first sub power unit 251 and a second sub power unit 252 . The first internal voltage IV1 of the first sub power unit 251 is supplied to the first logic unit 210 , and the second internal voltage IV2 of the second sub power unit 252 is supplied to the memory 220 . can

The first sub-power unit 251 may receive the first voltage change signal CV1 , and accordingly change the first internal voltage IV1 to the changed first internal voltage IV1 ′. That is, the first sub-power unit 251 supplies the first internal voltage IV1 to the sixth logic unit 210_5 and transmits the first voltage change signal CV1 from the sixth logic unit 210_5. One internal voltage IV1 ′ may be supplied to the sixth logic unit 210_5 .

The second sub power unit 252 may receive the third voltage change signal CV3 , and may change the second internal voltage IV2 to the changed second internal voltage IV2 ′ accordingly. That is, when the second sub power unit 252 supplies the second internal voltage IV2 to the memory 220 and transmits the third voltage change signal CV3 from the sixth logic unit 210_5, the second internal voltage is changed. (IV2') may be supplied to the memory 220 .

The first voltage change signal CV1 and the third voltage change signal CV3 may not be output signals of a digital circuit but may be in the form of mechanical manipulation of an analog circuit. That is, the fourth voltage control logic 212_3 may operate to adjust the contact points of the variable resistance columns of the first sub power supply unit 251 and the second sub power unit 252, respectively, and use the first voltage change signal CV1, respectively. and a third voltage change signal CV3.

In this embodiment, not only the logic part of the display driving circuit but also the supply voltage of the memory can be varied. Accordingly, the efficiency of power consumption of the entire display driving circuit may be maximized.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those of ordinary skill in the art to which the present invention pertains can realize that the present invention can be embodied in other specific forms without changing the technical spirit or essential features. you will be able to understand Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: processor
150: processor interface
200, 200_1, 200_2, 200_3, 200_4, 200_5: display driving circuit
210, 210_1, 210_2, 210_3, 210_4, 210_5: logic unit
220: memory
230: source driver
240: gate driver
250, 250_1: power supply
300: display panel
400: power module
450: power interface

Claims (20)

a source driver for applying source data to the display panel;
a power supply unit receiving an external voltage from the power module and generating a first internal voltage and a second internal voltage; and
a logic unit receiving the first internal voltage and controlling the source driver; and
Including a memory supplied with the second internal voltage,
The logic unit determines whether a supply voltage including the first internal voltage, the second internal voltage, and the external voltage is changed based on at least one of a mode signal, image data, and a clock signal received from a processor to determine a voltage variable signal voltage variable judgment logic to generate
and a voltage control logic configured to receive the voltage variable signal and change the supply voltage. According to claim 1,
The processor generates a mode signal for setting an operation mode,
The voltage variable determination logic is a display driving circuit that determines whether the supply voltage is changed by using the mode signal. According to claim 1,
The logic unit receives the image data, decodes the image data and transmits it to the source driver,
The voltage variable determination logic is a display driving circuit that determines whether the supply voltage is changed by using the image data. 4. The method of claim 3,
The voltage variable determination logic is configured to determine whether the supply voltage is changed in consideration of at least one of a toggle amount of the image data, an on pixel ratio (OPR), and an average of the most significant bit (MSB). drive circuit. According to claim 1,
The logic unit receives the clock signal having a frame frequency,
The voltage variable determination logic is a display driving circuit that determines whether the supply voltage is changed using the frame frequency. 6. The method of claim 5,
The display driving circuit further comprising a clock generator generating the clock signal of which the frame frequency is changed and supplying the clock signal to the logic unit. 7. The method of claim 6,
The logic unit generates a time control signal based on the mode signal and the image data to change the clock signal. 8. The method of claim 7,
Further comprising a memory for receiving and storing the first image data from the logic unit and providing the first image data back to the logic unit,
The logic unit receives and transmits first image data to the memory, receives second image data, receives the first image data from the memory, compares the first image data with the second image data, A display drive circuit that generates a control signal. a display panel for displaying source data;
a display driving circuit for driving the display panel by transmitting the source data and the gate signal; and
A power module for providing an external voltage to the display panel and the display driving circuit,
The display driving circuit,
a first sub power supply unit for receiving an external voltage from the power module and generating a first internal voltage;
a second sub power supply unit receiving the external voltage from the power module and generating a second internal voltage provided to the memory;
It receives the first internal voltage and generates a first voltage change signal provided to the first sub power supply unit, a second voltage change signal provided to the power module, and a third voltage change signal provided to the second sub power supply unit and a logic unit configured to change the first internal voltage, the second internal voltage, and/or the external voltage. 10. The method of claim 9,
The first sub-power supply unit and the second sub-power unit include a voltage control resistance column for regulating the first and second internal voltages,
The logic unit controls the voltage control resistor column to change the first and second internal voltages. delete 10. The method of claim 9,
The display device further comprising a processor for transmitting at least one of a mode signal, image data, and a clock signal to the logic unit. 13. The method of claim 12,
The mode signal sets the operation mode,
wherein the operation mode is set based on a toggle amount of image data, an on pixel ratio (OPR), and a frame frequency. 13. The method of claim 12,
The logic unit receives the first image data from the processor and stores it in the memory, and receives the second image data,
and generating the third voltage change signal based on at least one of the first image data and the second image data stored in the memory. 13. The method of claim 12,
a clock generator for generating a clock signal that is changed according to the time control signal;
The logic unit generates the time control signal based on the mode signal and the image data. 16. The method of claim 15,
wherein the time control signal changes a frame frequency of the clock signal. a source driver for applying source data corresponding to the image data to the display panel;
a power supply unit receiving an external voltage from the power module and generating a first internal voltage and a second internal voltage;
a clock generator generating a clock signal having a frame frequency;
a logic unit receiving the first internal voltage, receiving the clock signal and the image data from a processor, and controlling the source driver; and
Including a memory supplied with the second internal voltage,
The logic unit includes a voltage variable determination logic configured to generate a first variable voltage signal, a second voltage variable signal, and a third voltage variable signal in consideration of at least one of a command, the image data, and a frame frequency of the clock signal;
Voltage control logic for changing the first internal voltage according to the first voltage varying signal, changing the external voltage according to the second voltage varying signal, and changing the second internal voltage according to the third voltage varying signal A display driving circuit comprising a. 18. The method of claim 17,
The power supply unit includes a voltage control resistance column for adjusting the internal voltage,
The logic unit controls the voltage control resistor column to change the internal voltage. 18. The method of claim 17, wherein the voltage variable determination logic considers at least one of a toggle amount of the image data, an on pixel ratio (OPR), and a most significant bit (MSB) average of the first voltage A display driving circuit for generating a variable signal, the second voltage variable signal, and the third voltage variable signal. 18. The method of claim 17,
The logic unit generates a time control signal based on a mode signal and image data,
The clock generator changes the frame frequency according to the time control signal.

Images