KR102416435B1 - Display device - Google Patents

Abstract

A display is provided. The display device includes: an initialization power line extending in a first direction, a scan line extending along the first direction and spaced apart from the initialization power line in a second direction crossing the first direction; a control signal line extending in the first direction and spaced apart from the scan line in the second direction; a data line and a driving voltage line insulated from the initialization power line, the scan line, and the control signal line and extending in the second direction; a first switching element including a first electrode connected to the driving voltage line, a first gate electrode and a second electrode overlapping the initialization power line; a second switching element including a third electrode, a second gate electrode connected to the scan line, and a fourth electrode connected to the first gate electrode; a third switching element including a fifth electrode connected to the third electrode, a third gate electrode connected to the scan line, and a sixth electrode connected to the second electrode; and a light emitting device electrically connected to the second electrode. and a separation distance between the first gate electrode and the scan line measured along the second direction is greater than a separation distance between the first gate electrode and the control signal line measured along the second direction.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device.

The importance of the display device is increasing with the development of multimedia. In response to this, various types of display devices such as a liquid crystal display (LCD) and an organic light emitting display (OLED) are being used. Among them, an organic light emitting display device includes a plurality of pixels including an organic light emitting device that is a self-luminous device, and a plurality of transistors and a storage capacitor for driving the organic light emitting device are formed in each pixel.

The plurality of transistors includes a driving transistor for driving the organic light emitting device. A voltage change at a node connected to the gate electrode of the driving transistor changes a current flowing through the organic light emitting diode, and accordingly, a crosstalk phenomenon that causes a change in luminance may occur.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device capable of improving display quality in a high-resolution structure.

The problems of the present invention are not limited to the problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following window description.

According to an exemplary embodiment, a display device includes: an initialization power line extending in a first direction; a scan line extending along the first direction and spaced apart from the initialization power line in a second direction crossing the first direction; a control signal line extending in the first direction and spaced apart from the scan line in the second direction; a data line and a driving voltage line insulated from the initialization power line, the scan line, and the control signal line and extending in the second direction; a first switching element including a first electrode connected to the driving voltage line, a first gate electrode and a second electrode overlapping the initialization power line; a second switching element including a third electrode, a second gate electrode connected to the scan line, and a fourth electrode connected to the first gate electrode; a third switching element including a fifth electrode connected to the third electrode, a third gate electrode connected to the scan line, and a sixth electrode connected to the second electrode; and a light emitting device electrically connected to the second electrode. and a separation distance between the first gate electrode and the scan line measured along the second direction is greater than a separation distance between the first gate electrode and the control signal line measured along the second direction.

In a display device according to an embodiment of the present invention, a first parasitic capacitance is formed between the scan line and the first gate electrode, and is greater than the first parasitic capacitance between the scan line and the third electrode. A second parasitic capacitance such as .

In an exemplary embodiment, the display device further includes a conductive pattern connected to the third electrode and overlapping the data line, wherein the second parasitic capacitance is further between the scan line and the conductive pattern. can be formed.

In a display device according to an embodiment to solve the above problems, the conductive pattern and the driving voltage line may be positioned on the same layer and made of the same material.

In the display device according to an embodiment to solve the above problems, a first capacitance may be formed between the initialization power line and the first gate electrode, and a second capacitance may be formed between the conductive pattern and the data line. have.

In the display device according to an embodiment to solve the above problem, the second capacitance may be greater than the first capacitance.

The display device according to an embodiment of the present invention may further include a connection pattern connected to the second electrode, and the light emitting device may be electrically connected to the second electrode via the connection pattern.

In a display device according to an embodiment to solve the above problems, the connection pattern and the driving voltage line may be positioned on the same layer and made of the same material.

The display device according to an embodiment of the present invention further includes a bridge pattern connecting the fourth electrode and the first gate electrode, and the bridge pattern, the initialization power line, the scan line, and the control signal line The silver may be located on the same layer and made of the same material.

In one embodiment, the display device further includes an upper initialization signal line insulated from the scan line and the control signal line, extending in the second direction and connected to the initialization power line, and the upper initialization signal line and the driving voltage line may be positioned on the same layer and made of the same material.

According to another exemplary embodiment, a display device includes: a substrate; a semiconductor layer positioned on the substrate and including a first portion, a second portion, and a third portion connecting the first portion and the second portion; a first insulating layer positioned on the semiconductor layer; A first conductive layer disposed on the first insulating layer and including a first gate electrode overlapping the first portion, a second gate electrode overlapping the second portion, and a third gate electrode overlapping the third portion ; a second insulating layer positioned on the first conductive layer; an initialization power line positioned on the second insulating layer, extending in a first direction and overlapping the first gate electrode, a scan line extending in the first direction and connected to the second gate electrode, and the first direction a second conductive layer extending along the line and including a control signal line connected to the third gate electrode; and a distance between the first gate electrode and the scan line measured along a second direction intersecting the first direction is a distance between the first gate electrode and the control signal line measured along the second direction. can be larger

In a display device according to another embodiment to solve the above problem, the second conductive layer may further include a bridge pattern connected to one side of the second portion and the first gate electrode.

According to another exemplary embodiment, a display device includes: a third insulating layer disposed on the second conductive layer; a third conductive layer disposed on the third insulating layer and including a data line extending in the second direction; a fourth insulating layer positioned on the third conductive layer; and a fourth conductive layer disposed on the fourth insulating layer, the fourth conductive layer extending along the second direction and including a driving voltage line connected to one side of the first part; may further include.

In a display device according to another embodiment to solve the above problem, the fourth conductive layer may further include a connection pattern connected to the other side of the first part.

According to another exemplary embodiment, a display device includes: a fifth insulating layer disposed on the fourth conductive layer; and a light emitting device positioned on the fifth insulating layer and connected to the connection pattern.

In a display device according to another embodiment of the present invention, the fourth conductive layer may further include a conductive pattern connected to one side of the second portion and overlapping the data line.

In a display device according to another exemplary embodiment, the conductive pattern may not overlap the first gate electrode.

In a display device according to another embodiment to solve the above problem, the fourth conductive layer may further include an upper initialization power line extending along the second direction and connected to the initialization power line.

A display device according to another embodiment of the present invention provides a first gate electrode connected to a first node, a first electrode connected to a first power line to which a first power is supplied, and a second electrode connected to a third node. A first switching device comprising a; a second switching device including a second gate electrode connected to a scan line, a third electrode connected to the first node, and a fourth electrode connected to the second node; a third switching element including a third gate electrode connected to a control signal line, a fifth electrode connected to the second node, and a sixth electrode connected to the third node; a light emitting device connected to the third node; a first capacitor connected between the first node and an initialization power supply; a second capacitor connected between the second node and a data line; a first parasitic capacitor connected between the scan line and the first node; and a second parasitic capacitor connected between the scan line and the second node and having a capacitance greater than or equal to a capacitance of the first parasitic capacitor.

In a display device according to another embodiment to solve the above problem, a capacitance of the second capacitor may be greater than a capacitance of the first capacitor.

Details of other embodiments are included in the detailed description and drawings.

According to embodiments of the present invention, it is possible to provide a display device capable of realizing high resolution.

Also, according to embodiments of the present invention, it is possible to provide a display device capable of improving display quality by minimizing visibility of crosstalk in a high-resolution structure.

Effects according to the embodiments are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a schematic block diagram of a display device according to an exemplary embodiment.
FIG. 2 is an equivalent circuit diagram of one pixel shown in FIG. 1 .
3 is a diagram illustrating an example in which the pixel of FIG. 2 is driven.
FIG. 4 is a layout diagram of one pixel illustrated in FIG. 1 .
FIG. 5 is a layout view of the semiconductor layer, the first conductive layer, and the second conductive layer of FIG. 4 .
6 is a cross-sectional view taken along the line X1-X1' of FIG.
FIG. 7 is an enlarged view of part Q of FIG. 6 .
8 is a cross-sectional view taken along line X3-X3' of FIG.
9 is a cross-sectional view taken along the line X5-X5' of FIG.
10 is a cross-sectional view taken along the line X7-X7' of FIG.
11 is a cross-sectional view taken along line X9-X9' of FIG.
12 is a cross-sectional view taken along the line X11-X11' of FIG.
13 is a cross-sectional view taken along line X13-X13' of FIG.
14 is a cross-sectional view taken along the line X15-X15' of FIG. 4 .
15 is a diagram illustrating a crosstalk test pattern for checking whether a crosstalk occurs in a display device according to a comparative example.
16 is a diagram illustrating a crosstalk test pattern for checking whether a crosstalk occurs in a display device according to an exemplary embodiment.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

Reference to an element or layer "on" of another element or layer includes any intervening layer or other element directly on or in the middle of the other element or layer. Like reference numerals refer to like elements throughout.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms, of course. These terms are only used to distinguish one component from another. Accordingly, it goes without saying that the first component mentioned below may be the second component within the spirit of the present invention.

Hereinafter, embodiments will be described with reference to the accompanying drawings. Hereinafter, an organic light emitting display device will be described as an example of the display device.

1 is a schematic block diagram of a display device according to an embodiment.

Referring to FIG. 1 , a display device 1 may include a display panel 10 including a plurality of pixels PX and a panel driver driving the display panel 10 .

In an embodiment, the panel driver may drive the display panel 10 in a simultaneous light-emitting method including a non-emission section in which the pixels PX do not emit light and an emission section in which the pixels PX simultaneously emit light. In an embodiment, the panel driver may include a scan driver 20 , a data driver 30 , a power supply unit 40 , and a timing controller 50 .

The display panel 10 may include a plurality of pixels PX to display an image. For example, the display panel 10 may include first to nth (where n is an integer greater than 1) scan lines SL1 to SLn and first to mth (where m is an integer greater than 1) data lines It may include n*m pixels PX positioned at each intersection of (DL1 to DLm). The pixel PX may be connected to the first power source ELVDD and the initialization power source VINT having a voltage level that varies within one frame period to be driven in a simultaneous light emission method. The structure and driving method of the pixel PX will be described later.

The scan driver 20 may provide a scan signal to the pixels PX through the first to nth scan lines SL1 to SLn based on the first control signal CNT1 .

The data driver 30 converts digital image data into an analog data signal based on the second control signal CNT2 , and transmits the data signal to the pixels PX through the first to mth data lines DL1 to DLm. A data signal may be provided.

The power supply unit 40 applies the driving voltage ELVDD, the common voltage ELVSS, and the initialization power VINT having a voltage level that varies within one frame period based on the third control signal CNT3 to the pixel PX. can be provided to For example, the power supply unit 40 is a DC-DC converter that generates output voltages having various voltage levels from an input voltage (eg, a battery voltage) and a driving voltage ELVDD, a common voltage ELVSS, and initialization. Switches that select output voltages as the driving voltage ELVDD, the common voltage ELVSS, and the initialization power VINT based on the third control signal CNT3 to set the voltage level for each of the power sources VINT may include

The timing controller 50 may control the scan driver 20 , the data driver 30 , and the power supply unit 40 . For example, the timing controller 50 may receive the control signal CNT from an external circuit such as a system board. The timing controller 50 may generate first to third control signals CTL1 to CTL3 to control the scan driver 20 , the data driver 30 , and the power supply unit 40 , respectively. The first control signal CTL1 for controlling the scan driver 20 may include a scan start signal, a scan clock signal, and the like. The second control signal CTL2 for controlling the data driver 30 may include a horizontal start signal, a load signal, image data, and the like. The third control signal CTL3 for controlling the power supply unit 40 may include a switch control signal for controlling the voltage level of the driving voltage ELVDD, the common voltage ELVSS, and the initialization power VINT. have. The timing controller 50 may generate digital image data that meets the operating conditions of the display panel 10 based on the input image data and provide it to the data driver 30 .

The display device 1 may improve display quality by compensating for a threshold voltage of a driving transistor and including pixels driven by a simultaneous light emission method. For example, a Head Mounted Display (HMD) is mounted on a user's head, uses a lens to magnify an image (that is, an image output from a display panel), and provides an image directly in front of the user's eyes. can do. Accordingly, when the display panel is driven in the sequential light emission method, screen dragging, color bleeding, etc. may be visually recognized by the user. Since the display device 1 drives pixels having a relatively simple structure in a simultaneous light emission method, a high-resolution display device providing high display quality can be realized.

FIG. 2 is an equivalent circuit diagram of one pixel shown in FIG. 1 .

Referring to FIG. 2 , the pixel PX includes a light emitting device OLED, a first switching device T1 , a second switching device T2 , a third switching device T3 , a first capacitor Cst, and a second It may include a capacitor Cpr, a first parasitic capacitor Ca, and a second parasitic capacitor Cb. The pixel PX may be located in the i-th pixel row and the j-th pixel column.

The first switching element T1 , the second switching element T2 , and the third switching element T3 may be thin film transistors. In some embodiments, each of the first switching device T1 , the second switching device T2 , and the third switching device T3 may be a PMOS transistor, but is not limited thereto. In addition, the first switching element T1 , the second switching element T2 , and the third switching element T3 may be NMOS transistors, and the first switching element T1 , the second switching element T2 , and the third switching element T3 . Some of the elements T3 may be NMOS transistors, and others may be PMOS transistors. Hereinafter, for convenience of description, a case in which each of the first switching element T1 , the second switching element T2 , and the third switching element T3 is a PMOS transistor will be described as an example.

The first switching element T1 may include a gate electrode connected to the first node N1 , a first electrode connected to a driving voltage line to which the driving voltage ELVDD is provided, and a second electrode connected to the third node N3 . have. The second switching element T2 has a gate electrode that receives the i-th scan signal GW[i] from the i-th scan line, a third electrode connected to the first node N1 , and a fourth electrode connected to the second node N2 . It may include an electrode. The third switching element T3 may include a gate electrode receiving the common control signal GC from the control signal line, a fifth electrode connected to the second node N2, and a sixth electrode connected to the third node N3. have.

The first switching element T1 may be a driving transistor. In an embodiment, the first switching element T1 has a first gate electrode connected to the first node N1 , a first electrode connected to a driving voltage line to which the driving voltage ELVDD is provided, and a third node N3 connected to the first switching element T1 . A second electrode may be included.

The second switching element T2 may connect the first node N1 and the second node N2 in response to the i-th scan signal GW[i]. In an embodiment, the second switching element T2 includes a second gate electrode that receives the i-th scan signal GW[i] from the scan line, a third electrode connected to the first node N1, and the second node N2 ) may include a fourth electrode connected to.

The third switching element T3 may connect the second node N2 and the third node N3 in response to the common control signal GC. In an embodiment, the third switching element T3 includes a third gate electrode for receiving the common control signal GC from the control signal line, a fifth electrode connected to the second node N2, and a third node connected to the third node N3. A sixth electrode may be included.

The first capacitor Cst may be located between the initialization power source VINT and the first node N1 . In an embodiment, the first capacitor Cst may include an initial supply of the initialization power VINT, a first capacitor electrode connected to the power line, and a second capacitor electrode connected to the first node N1 . In some embodiments, the first capacitor Cst may be a storage capacitor.

The second capacitor Cpr may be positioned between the data line and the third node N3 . In an embodiment, the second capacitor Cpr may include a third capacitive electrode receiving the data signal D[j] from the data line and a fourth capacitive electrode connected to the third node N3. In some embodiments, the second capacitor Cpr may be a luminance compensation capacitor, and the capacitance of the second capacitor Cpr may be greater than that of the first capacitor Cst.

The light emitting device OLED may emit light based on a driving current flowing from the first switching device T1 . In an embodiment, the light emitting device OLED may include a first device electrode connected to the third node N3 and a second device electrode connected to a common power source to which the common voltage ELVSS is provided.

In the pixel PX illustrated in FIG. 2 , a third switching element T3 is positioned between the fourth electrode of the second switching element T2 and the first element electrode of the organic light emitting diode OLED. Accordingly, since the second node N2 and the third node N3 may be separated by the third switching element T3 , the data signal D[j] is transmitted to the first of the first switching element T1. When a leakage current flowing from the driving voltage line to which the driving voltage ELVDD is provided through the first switching element T1 to the third node N3 occurs while writing to the gate electrode (ie, the first node N1 ) Also, since the data signal D[j] written to the gate electrode of the first switching element T1 is not affected, display quality may be improved.

In addition, since the second capacitor Cpr is positioned between the data line and the third node N3 , it has a different configuration from the first node N1 or the first switching element T1 connected to the first node N1 . A decrease in the luminance of the light emitting device may be compensated for by the parasitic capacitor between them. Accordingly, display quality may be further improved.

The first parasitic capacitor Ca may be positioned between the scan line and the first node N1 , and the second parasitic capacitor Cb may be positioned between the scan line and the second node N2 . In an embodiment, the second parasitic capacitance of the second parasitic capacitor Cb may be greater than the first parasitic capacitance of the first parasitic capacitor Ca.

As mentioned above, the second capacitor Cpr may be larger than the first capacitor Cst, and the second capacitor Cpr may compensate for a decrease in luminance of the light emitting device. However, even in this case, the luminance compensation function of the second capacitor Cpr may be deteriorated by the first parasitic capacitor Ca, and thus display quality may be deteriorated. According to an embodiment, the display quality may be further improved by forming a second parasitic capacitor Cb having a capacitance greater than or equal to that of the first parasitic capacitor Ca between the scan line and the first node N2. can Also, when the scan signal provided to the scan line is changed from an on level to an off level, even if a kickback voltage is generated in the first node N1, the voltage level of the first node N1 is Since the voltage level of the second node N2 or more can be maintained, the visibility of crosstalk failure can be minimized.

3 is a diagram illustrating an example in which the pixel of FIG. 2 is driven. More specifically, it is a diagram illustrating examples in which multiple pixels are driven in a simultaneous light emission method.

1 to 3 , the panel driver drives the display panel 10 in a simultaneous light-emitting method including a non-emission section PA1 to PA4 in which pixels do not emit light and a light emission section PA5 in which pixels emit light at the same time. can do. The non-emission period includes a first initialization period PA1 in which the voltage of the first element electrode of the light emitting element OLED is initialized, and a second initialization period PA2 in which the first gate electrode of the first switching element T1 is initialized. , a threshold voltage compensation period PA3 in which the first switching element T1 is connected to the light emitting element OLED, and a data writing period PA4 in which a data signal is written to the pixels may be sequentially included.

The pixels may be connected to a driving voltage line provided with a driving voltage ELVDD having a voltage level (ie, an AC voltage) that varies within one frame period and an initialization power line provided with an initialization power VINT. For example, the driving power ELVDD includes a first voltage level ELVDD_L, a second voltage level ELVDD_M greater than the first voltage level ELVDD_L, and a third voltage level greater than the second voltage level ELVDD_M. ELVDD_H). The initialization power VINT may have one of a fourth voltage level VINT_L and a fifth voltage level VINT_H greater than the fourth voltage level VINT_L. The voltage level of the common voltage ELVSS may be maintained constant. For example, the common voltage ELVSS may have a ground voltage level GND. In addition, the reference voltage VREF may be applied to the data line other than the data writing period PA4 , and a data signal for expressing a grayscale may be provided to the data line in the data writing period PA4 .

The same common control signal GC may be provided to all pixel rows included in the display panel 10 . The common control signal GC may have an on level in the second initialization period PA2 and the threshold voltage compensation period PA3 , and may have an off level in the first initialization period PA1 and the data writing period PA4 . have.

3 , in the first initialization period PA1 , the driving voltage ELVDD has the second voltage level ELVDD_M, and the initialization power VINT is a fifth voltage greater than the second voltage level ELVDD_M. It may have a voltage level VINT_H, and the scan signal GW[i] and the common control signal GC may have an off level. Accordingly, a current flows from the third node N3 to the driving voltage line to which the driving voltage ELVDD is provided through the first switching element T1, and the voltage of the third node N3 is the second voltage level ELVDD_M. can be set to That is, the voltage of the first device electrode of the light emitting device OLED may be initialized.

In the second initialization period PA2, the driving voltage ELVDD has the second voltage level ELVDD_M, the initialization power VINT has the fifth voltage level VINT_H, and the scan signal GW[i] and The common control signal GC may have an on level. Accordingly, the first gate electrode of the first switching element T1 and the second electrode of the first switching element T1 may be connected by the turned-on second switching element T2 and the third switching element T3. have. Accordingly, the voltage of the first node N1 and the voltage of the third node N3 are the sum of the second voltage level ELVDD_M and the threshold voltage Vth of the first switching element T1 (ie, ELVDD_M + Vth). That is, the voltage of the first element electrode of the light emitting element OLED and the voltage of the first gate electrode of the first switching element T1 may be initialized.

In the threshold voltage compensation section PA3 , the driving voltage ELVDD has a first voltage level ELVDD_L, the initialization power VINT has a fourth voltage level VINT_L, and the scan signal GW[i] and The common control signal GC may have an on level. Accordingly, a voltage obtained by adding the voltage of the first node N1 and the first voltage level ELVDD_L of the third node N3 to the threshold voltage Vth of the first switching element T1 (ie, ELVDD_L + Vth) ) may correspond to

In the data writing period PA4 , the driving voltage ELVDD has a third voltage level ELVDD_H, the initialization power VINT has a fourth voltage level VINT_L, and the common control signal GC has an off level. can have The panel driver may sequentially provide the scan signals GW[1] to GW[n] having an on level to the scan lines so that the data signal D[j] is written to the pixels.

The first capacitor Cst, the second capacitor Cpr, and the light emitting element OLED included in the pixels positioned in the i-th pixel row and the j-th pixel column at the start time (ie, the first time point) of the data writing period PA4 . ), the amount of charge stored in the capacitor (ie, diode capacitor) may be calculated according to the following [Equation 1] to [Equation 3].

[Equation 1]

Qst1 = (ELVDD_L + Vth - VINT_L) x Cst

[Equation 2]

Qpr1 = (ELVDD_L + Vth - Vref) x Cpr

[Equation 3]

Qoled1 = (ELVDD_L + Vth - ELVSS) x Coled

Here, Qst1, Qpr1, and Qoled1 may represent the amounts of charges stored in each of the first capacitor, the second capacitor, and the capacitor of the light emitting device at a first time point. ELVDD_L is the first voltage level of the driving voltage, Vth is the threshold voltage of the first switching element, VINT_L is the fourth voltage level of the initialization power supply, Vref is the reference voltage, ELVSS is the voltage level of the common voltage, Cst, Cpr, and Coled are each Each of the first capacitor, the second capacitor, and the capacitor of the light emitting device represents the capacitance.

In addition, immediately after the i-th scan signal GW[i] having an on level is provided to the i-th pixel row (ie, the second time point) during the data writing period PA4, the The amount of charges stored in the first capacitor Cst, the second capacitor Cpr, and the capacitor of the light emitting device OLED included in the pixel may be calculated according to Equation 4 to Equation 6 below.

[Equation 4]

Qst2 = (Vgate - VINT_L) x Cst

[Equation 5]

Qpr2 = (Vgate - Vdata(i,j)) x Cpr

[Equation 6]

Qoled2 = (Vgate - ELVSS) x Coled

Here, Qst2, Qpr2, and Qoled2 may represent the amount of charges stored in each of the first capacitor, the second capacitor, and the capacitor of the light emitting device at the second time point. Vgate is the voltage of the first gate electrode of the first switching element, VINT_L is the fourth voltage level of the initialization power supply, Vdata(i,j) is the voltage of the data signal, ELVSS is the voltage level of the common voltage, Cst, Cpr, Coled is Each of the first capacitor, the second capacitor, and the capacitor of the light emitting device represents the capacitance.

Since there is no current path between the first gate electrode of the first switching element and the second electrode of the first switching element included in the pixel between the first time point and the second time point, the total amount of charge at the first time point and the second time point is may be equal (ie Qst1 + Qpr1 + Qoled1 = Qst2 + Qpr2 + Qoled2). Based on [Equations 1 to 6], the voltage of the first gate electrode of the first switching element included in the pixel in the data writing period PA4 may be calculated by the following [Equation 7].

[Equation 7]

Accordingly, the voltage of the first gate electrode of the first switching element, which is the driving transistor, may be set independently of voltages of data signals at different timings.

In the emission period PA5, the driving voltage ELVDD has a third voltage level ELVDD_H, the initialization power VINT has a fifth voltage level VINT_H, and the scan signal GW[i] has an off level. can have That is, in the light emission period PA5 , the initialization power VINT rises from the fourth voltage level VINT_L to the fifth voltage level VINT_H, and the voltage of the first node N1 (ie, the voltage of the first gate electrode) ) may increase according to the amount of change (ie, VINT_H - VINT_L) of the initialization power supply VINT. Accordingly, a driving current I_OLED is generated according to a voltage difference between the first gate electrode and the second electrode of the first switching element T1 , and a driving current is generated to the light emitting element OLED through the first switching element T1 . (I_OLED) flows, so that the pixels can emit light at the same time.

Although FIG. 3 illustrates an example in which the pixels are driven using the driving voltage ELVDD and the initialization power VINT having voltage levels that vary within one frame period, the pixels may be driven in various ways. have. For example, as shown in FIG. 4 , in the data writing period PA4 , the driving voltage ELVDD has the second voltage level ELVDD_M, and the initialization power VINT has the fourth voltage level VINT_L. and the panel driver may sequentially provide the scan signals GW[1] to GW[n] having an on level to the scan lines so that the data signal is written to the pixels.

That is, unlike the pixel driving method illustrated in FIG. 3 , in the data writing period PA4 , the driving voltage ELVDD is set to the second voltage level ELVDD_M, so that during the data writing period PA4, the first switching element ( It is possible to prevent a leakage current from flowing from the driving voltage line to which the driving voltage ELVDD is provided through T1) to the third node N3. That is, the voltage of the first electrode of the first switching element T1 is changed to a voltage between the first voltage level ELVDD_L and the third first voltage level ELVDD_H (eg, the second voltage level ELVDD_M). By setting the leakage current path can be eliminated. Accordingly, it is possible to prevent a change in a data signal written to a pixel due to a leakage current, and to prevent display quality deterioration (eg, spot recognition) due to a luminance deviation between pixels.

Meanwhile, when the scan signal GW[i] changes from the on level to the off level after the data writing period PA4, a potential difference may be generated between the first node N1 and the second node N2 due to kickback. . In addition, since the capacitance of the second capacitor Cpr is greater than that of the first capacitor Cst, the voltage level of the first node N1 may be lower than the voltage level of the second node N2. A current may flow in a direction from the second node N2 to the first node N1 or from the second node N2 to the first gate electrode of the first switching element T1 . In this case, the crosstalk, which has not been previously recognized, can be relatively clearly recognized.

On the other hand, according to an exemplary embodiment, the second parasitic capacitor Cb is positioned between the scan line to which the scan signal GW[i] is provided and the second node N2, and the scan line and the first node N! A first parasitic capacitor Ca is positioned between them, but the second parasitic capacitance of the second parasitic capacitor Cb is relatively greater than or equal to the first parasitic capacitance of the first parasitic capacitor Ca. Accordingly, when the scan signal GW[i] changes from the on level to the off level after the data writing period PA4, even if a potential difference occurs between the first node N1 and the second node N2 due to kickback, The voltage level of the first node N1 may be maintained substantially higher than the voltage level of the second node N2 . Accordingly, even if a current flow due to a potential difference occurs, the direction of the current is directed from the first node N2 to the second node N2 or from the first gate electrode of the first switching element T1 to the second node ( N2) can be maintained. Accordingly, it is possible to further reduce the visibility of the crosstalk.

4 is a layout diagram of one pixel shown in FIG. 1 , FIG. 5 is a layout diagram of the semiconductor layer, the first conductive layer, and the second conductive layer of FIG. 4 , and FIG. 6 is a view taken along line X1-X1′ of FIG. 4 . One cross-sectional view, Fig. 7 is an enlarged view of the Q portion of Fig. 6, Fig. 8 is a cross-sectional view taken along the line X3-X3' of Fig. 4, Fig. 9 is a cross-sectional view taken along the line X5-X5' of Fig. 4, 10 is a cross-sectional view taken along line X7-X7' of FIG. 4, FIG. 11 is a cross-sectional view taken along line X9-X9' of FIG. 4, and FIG. 12 is a cross-sectional view taken along line X11-X11' of FIG. , FIG. 13 is a cross-sectional view taken along line X13-X13' of FIG. 4, and FIG. 14 is a cross-sectional view taken along line X15-X15' of FIG. In the following embodiments, new reference numerals have been assigned to some of the components in order to easily explain the arrangement and coupling relationship between the components, even if they are substantially the same as the components mentioned in FIGS. 1 and 2 .

4 to 14 , as described above, the pixel includes the first switching element T1 , the second switching element T2 , the third switching element T3 , the first capacitor Cst, and the second capacitor (Spr), a first parasitic capacitor Ca, and a second parasitic capacitor Cb.

Hereinafter, a stacked structure of each pixel of the display device will be described.

The substrate 100 may be made of an insulating material such as glass, quartz, or polymer resin. Examples of the polymer material include polyethersulphone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), and polyethylene napthalate (PEN). ), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate ( cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. The substrate 100 may include a metal material.

The substrate 100 may be a rigid substrate or a flexible substrate capable of bending, folding, rolling, or the like. Examples of the material constituting the flexible substrate include, but are not limited to, polyimide (PI).

A buffer layer 111 may be positioned on the substrate 100 . The buffer layer 111 may be disposed on the entire surface of the substrate 100 . The buffer layer 111 may prevent diffusion of impurity ions, prevent penetration of moisture or external air, and perform a surface planarization function. The buffer layer 111 may include silicon nitride, silicon oxide, or silicon oxynitride. The buffer layer 111 may be omitted depending on the type of the substrate 100 or process conditions.

The semiconductor layer 150 may be positioned on the buffer layer 111 .

The semiconductor layer 150 includes a first portion 151 , a second portion 153 , and a third portion 155 . The first part 151 includes a channel part 151a, a first electrode 151b, and a second electrode 151c of the first switching element T1, and the second part 153 is a second switching element (T1). T2) includes a channel portion 153a, a third electrode 153b, and a fourth electrode 153c. The third portion 155 includes a channel portion 155a, a fifth electrode 155b, and a sixth electrode 155c of the third switching element T3.

The first part 151 , the second part 153 , and the third part 155 may be positioned on the same layer and may include the same material. Hereinafter, the meaning of being arranged on the same layer includes the meaning of being located on the same level. The meaning that they are disposed on the same layer includes the meaning that the layers located immediately below the configuration are the same as each other, or that they are formed simultaneously in the same process.

The first electrode 151b may be connected to one end of the channel unit 151a, and the second electrode 151c may be connected to the other end of the channel unit 151a. That is, one side of the first part 151 may be the first electrode 151b, and the other side of the first part 151 may be the second electrode 151c. Similarly, the third electrode 153b may be connected to one end of the channel portion 153a and the fourth electrode 153c may be connected to the other end of the channel portion 153a. That is, one side of the second part 153 may be the third electrode 153b, and the other side of the second part 153 may be the fourth electrode 153c. The fifth electrode 155b may be connected to one end of the channel portion 155a and the sixth electrode 155c may be connected to the other end of the channel portion 155a. That is, one side of the third part 155 may be the fifth electrode 155b and the other side of the third part 155 may be the sixth electrode 155c.

Hereinafter, connected means a case in which two components are physically connected to each other. In addition, the meaning of being electrically connected is a concept including a case in which two components are physically connected as well as a case in which two components are electrically connected via another conductor or the like even if they are not physically connected.

The third part 155 may extend from the first part 151 and may be formed integrally with the first part 151 . More specifically, the sixth electrode 155c of the third portion 155 may extend from the second electrode 151c of the first portion 151 to be connected to the second electrode 151c.

The second part 153 may extend from one end of the third part 155 and may be formed integrally with the third part 155 . More specifically, the third electrode 153b of the second portion 153 may extend from the fifth electrode 155b of the third portion 155 to be connected to the fifth electrode 155b.

The semiconductor layer 150 may include polycrystalline silicon. Polycrystalline silicon may be formed by crystallizing amorphous silicon. Examples of the crystallization method include a rapid thermal annealing (RTA) method, a solid phase crystallzation (SPC) method, an excimer laser annealing (ELA) method, a metal induced crystallzation (MIC) method, a metal induced lateral crystallzation (MILC) method, and sequential crystallization (SLS) method. lateral solidification) method, but is not limited thereto. As another example, the semiconductor layer 150 may include single crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, or the like. However, the present invention is not limited thereto, and in another embodiment, the semiconductor layer 150 may include an oxide semiconductor. For example, in another embodiment, the semiconductor layer 150 is a binary compound (ABx) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. , a ternary compound (ABxCy), and a quaternary compound (ABxCyDz) may be included. For example, the semiconductor layer 150 may include ITZO (oxide including indium, tin, and titanium) or IGZO (oxide including indium, gallium, and tin).

In the semiconductor layer 150 , the first electrode 151b, the second electrode 151c, the third electrode 153b, the fourth electrode 153c, the fifth electrode 155b, and the sixth electrode 155c have impurity ions. (P-type impurity ions in the case of PMOS transistors) may be doped. A trivalent dopant such as dPtlwjrdmfh boron (B) may be used as the p-type impurity ion.

A first insulating layer 131 may be positioned on the semiconductor layer 150 . The first insulating layer 131 may be generally disposed over the entire surface of the substrate 100 . The first insulating layer 131 may be a gate insulating layer having a gate insulating function.

The first insulating layer 131 may include a silicon compound, a metal oxide, or the like. For example, the first insulating layer 131 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. These may be used alone or in combination with each other. The first insulating layer 131 may be a single layer or a multi-layered layer including stacked layers of different materials.

The first conductive layer 120 may be positioned on the first insulating layer 131 .

The first conductive layer 120 includes the first gate electrode 121 of the first switching element T1 , the second gate electrode 123 of the second switching element T2 , and the third of the third switching element T3 . A gate electrode 125 may be included.

The first gate electrode 121 , the second gate electrode 123 , and the third gate electrode 125 may be disposed on the same layer and may include the same material.

The first gate electrode 121 , the second gate electrode 123 , and the third gate electrode 125 may be disposed to be spaced apart from each other. The first gate electrode 121 may overlap the channel portion 151a of the first portion 151 of the semiconductor layer 150 and may not overlap the first electrode 151b and the second electrode 151c. can Similarly, the second gate electrode 123 may overlap the channel portion 153a of the second portion 153 of the semiconductor layer 150 and may not overlap the third electrode 153b and the fourth electrode 153c. can Also, the third gate electrode 125 may overlap the channel portion 155a of the third portion 155 of the semiconductor layer 150 and may not overlap the fifth electrode 155b and the sixth electrode 155c. can

The first conductive layer 120 includes molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium ( Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and may include one or more metals selected from copper (Cu). The first conductive layer 200 may be a single layer or a multilayer layer.

The second insulating layer 133 serves to insulate the first conductive layer 120 and the second conductive layer 200 . The second insulating layer 133 is disposed on the first conductive layer 120 , and may be generally disposed over the entire surface of the substrate 100 . The second insulating layer 133 may be an interlayer insulating layer.

The second insulating layer 133 is formed of an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, polyacrylates resin, or epoxy resin. ), phenolic resin, polyamides resin, polyimides rein, unsaturated polyesters resin, polyphenylenethers resin, polyphenyl It may include an organic insulating material such as polyphenylenesulfides resin or benzocyclobutene (BCB). The second insulating layer 133 may be a single layer or a multi-layered layer including stacked layers of different materials.

The second conductive layer 200 is disposed on the second insulating layer 133 . The second conductive layer 200 includes an initialization power line 250 transmitting initialization power (VINT in FIG. 2), a scan line 210 transmitting a scan signal (GW[i] in FIG. 2), and a common control signal (FIG. 2 ), and may include a control signal line 230 for transmitting GC, and may further include a bridge pattern 220 .

The initialization power line 250 , the scan line 210 , the control signal line 230 , and the bridge pattern 220 may be positioned on the same layer and may include the same material.

The initialization power line 250 , the control signal line 230 , and the scan line 210 may extend in a row direction or a first direction DR1 , respectively, and may be a column direction or a second direction intersecting the first direction DR1 . may be spaced apart from each other along (DR2). In some embodiments, the control signal line 250 may be positioned between the initialization power line 250 and the scan line 210 in the second direction DR2 .

The initialization power line 250 is disposed to overlap the first gate electrode 121 of the lower first switching element T1 with the second insulating layer 133 interposed therebetween to form the first capacitor Cst. The first gate electrode 121 of the first switching element T1 becomes the first capacitance electrode of the first capacitor Cst, and the initialization power line 250 superposed thereon has the second capacitance of the first capacitor Cst. The electrode and the second insulating layer 133 interposed therebetween may be a dielectric of the first capacitor Cst.

The control signal line 230 may be disposed to overlap with the third gate electrode 125 of the lower third switching element T3 with the second insulating layer 133 interposed therebetween, and the second insulating layer 133 may be disposed therebetween. Through the penetrating fifth contact hole CNT5 , it may directly contact and be connected to the third gate electrode 125 .

The scan line 210 may be disposed to overlap the second gate electrode 123 of the lower second switching element T2 with the second insulating layer 133 interposed therebetween, and penetrate the second insulating layer 133 . The second gate electrode 123 may be directly contacted and connected to the second gate electrode 123 through the seventh contact hole CNT7 .

The scan line 210 and the first gate electrode 121 may form a first parasitic capacitor Ca. The first gate electrode 121 of the first switching element T1 becomes a first parasitic capacitance electrode of the first parasitic capacitor Ca, and the scan line 210 is a second parasitic capacitance electrode of the first parasitic capacitor Ca , and the second insulating layer 133 interposed therebetween may be a dielectric of the first parasitic capacitor Ca.

The scan line 210 and the third electrode 153b or the scan line 210 and the fifth electrode 155b may form a second parasitic capacitor Cb. The scan line 210 becomes the first parasitic capacitance electrode of the second parasitic capacitor Cb, and the third electrode 153b or the fifth electrode 155b becomes the second parasitic capacitance electrode of the second parasitic capacitor Cb. The first insulating layer 131 and the second insulating layer 133 interposed therebetween may be a dielectric of the second parasitic capacitor Cb.

The separation distance D2 between the first gate electrode 121 and the scan line 210 measured along the second direction DR2 is the first gate electrode 121 and the control signal line measured along the second direction DR2. It may be greater than the separation distance D1 between the 230 . That is, the scan line 210 may be disposed relatively far from the first gate electrode 121 and relatively adjacent to the third electrode 153b or the fifth electrode 155b. Accordingly, the capacitance of the second parasitic capacitor Cb may be formed to be relatively greater than or equal to the capacitance of the first parasitic capacitor Ca.

In some embodiments, in order to further increase the second parasitic capacitance of the second parasitic capacitor Cb, the scan line 210 includes an extension 210a protruding toward the third electrode 153b or the fifth electrode 155b. can be formed.

The bridge pattern 220 may be electrically connected to the fourth electrode 153c of the second switching element T2 and the first gate electrode 121 of the first switching element T1 . In some embodiments, the bridge pattern 220 may be disposed to overlap the fourth electrode 153c of the second switching device T2 and the first gate electrode 121 of the first switching device T1 . An eighth contact hole CNT8 partially exposing the fourth electrode 153c and the first gate electrode 121 may be formed in the first insulating layer 131 and the second insulating layer 133 , and a bridge pattern may be formed. 220 may directly contact and be connected to the fourth electrode 153c and the first gate electrode 121 through the eighth contact hole CNT8 . Accordingly, the fourth electrode 153c and the first gate electrode 121 may be electrically connected through the bridge pattern 220 .

The second conductive layer 200 includes molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium ( Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and may include one or more metals selected from copper (Cu).

A third insulating layer 135 may be positioned on the second conductive layer 200 . The third insulating layer 135 covers the second conductive layer 200 . The third insulating layer 135 may be substantially disposed over the entire surface of the substrate 100 . In some embodiments, the third insulating layer 135 may include the same material as the first insulating layer 131 , or may include one or more materials selected from the exemplified materials of the first insulating layer 131 . .

The third conductive layer 300 may be positioned on the third insulating layer 135 . The third conductive layer may include a data line 310 that transmits a data signal (D[j] of FIG. 2 ).

The data line 310 may extend along a second direction DR2 that is a column direction. The data line 310 may extend to neighboring pixels beyond a pixel boundary in a column direction. In some embodiments, the data line 310 may include a portion having an extended line width.

The third conductive layer 300 includes molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium ( Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and may include one or more metals selected from copper (Cu). The third conductive layer 500 may be a single layer or a multilayer layer. For example, the third conductive layer 300 may be formed in a stacked structure of Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, Ti/Cu, or the like.

A fourth insulating layer 137 may be positioned on the third conductive layer 300 . The fourth insulating layer 137 covers the third conductive layer 300 . The fourth insulating layer 137 may be generally disposed over the entire surface of the substrate 100 . In some embodiments, the fourth insulating layer 137 may be an organic insulating layer including an organic material. The organic material is an imide-based polymer, a general general-purpose polymer such as Polymethylmethacrylate (PMMA) or Polystylene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an arylether-based polymer, an amide-based polymer, a fluorine-based polymer, and a p-xylene-based polymer. Polymers, vinyl alcohol-based polymers, and blends thereof may be included.

A fourth conductive layer 500 may be positioned on the fourth insulating layer 137 . The fourth conductive layer 500 may include a driving voltage line 530 that transmits a driving voltage (ELVDD of FIG. 2 ), and an upper initialization that transmits the initialization power (VINT of FIG. 2 ) to the initialization power line 250 . It may further include a power line 510 , a conductive pattern 533 , and a connection pattern 551 .

The driving voltage line 530 , the upper initialization power line 510 , the conductive pattern 533 , and the connection pattern 551 may be positioned on the same layer and may include the same material.

The driving voltage line 530 may extend along a second direction DR2 that is a column direction. The driving voltage line 530 may extend to neighboring pixels beyond the boundary of the pixels along the column direction. The driving voltage line 530 may be electrically connected to the first electrode 151b of the first portion 151 . In some embodiments, the driving voltage line 530 may overlap the first electrode 151b, and may include a first insulating layer 131 , a second insulating layer 133 , a third insulating layer 135 , and a fourth insulating layer. It may be connected to the first electrode 151b through the first contact hole CNT1 passing through 137 .

The upper initialization power line 510 may extend along the second direction DR2 , which is a column direction, and may be spaced apart from the driving voltage line 530 . The upper initialization power line 510 may extend to neighboring pixels beyond the boundary of the pixels along the column direction. The upper initialization power line 510 may be electrically connected to the initialization power line 250 . In some embodiments, the upper initialization power line 510 may overlap the initialization power line 250 , and may form a fourth contact hole CNT4 penetrating the third insulating layer 135 and the fourth insulating layer 137 . may be connected to the initialization power line 250 through the

The connection pattern 551 may be spaced apart from the upper initialization power line 510 and the driving voltage line 530 . The connection pattern 551 may be electrically connected to the second electrode 151c of the first switching element T1 . In some embodiments, the connection pattern 551 may overlap the second electrode 151c of the first switching element T1 , and the first insulating layer 131 , the second insulating layer 133 , and the third insulating layer It may be connected to the second electrode 151c through the second contact hole CNT2 penetrating the 135 and the fourth insulating layer 137 .

The conductive pattern 553 may be spaced apart from the connection pattern 551 , the upper initialization power line 510 , and the driving voltage line 530 . The conductive pattern 553 may be electrically connected to the fifth electrode 155b of the third switching element T3 or the third electrode 153b of the second switching element T2 . In some embodiments, the connection pattern 551 may overlap the fifth electrode 155b of the third switching element T1 , and the first insulating layer 131 , the second insulating layer 133 , and the third insulating layer It may be connected to the fifth electrode 155b through the sixth contact hole CNT6 penetrating the 135 and the fourth insulating layer 137 .

The conductive pattern 553 is disposed to overlap the lower data line 310 with the third insulating layer 135 and the fourth insulating layer 137 interposed therebetween to form the second capacitor Cpr. The conductive pattern 553 becomes a first capacitive electrode of the second capacitor Cpr, and the data line 310 superimposed thereon becomes a second capacitive electrode of the second capacitor Cpr, and a third capacitor interposed therebetween. The insulating layer 135 and the fourth insulating layer 137 may be a dielectric of the second capacitor Cpr. For luminance compensation, the capacitance of the second capacitor Cpr may be greater than the capacitance of the first capacitor Cst. In some embodiments, when the data line 310 includes a portion having an extended line width, the conductive pattern 553 may further overlap a portion of the data line 310 with an extended line width, and thus the second capacitor ( Cpr) can increase the capacitance.

In some embodiments, the scan line 210 and the conductive pattern 553 may further form a second parasitic capacitor Cb. The scan line 210 becomes a first parasitic capacitance electrode of the second parasitic capacitor Cb, and the conductive pattern 553 becomes a second parasitic capacitance electrode of the second parasitic capacitor Cb, and a third insulation interposed therebetween. The layer 135 and the fourth insulating layer 137 may be a dielectric of the second parasitic capacitor Cb.

In order to reduce a parasitic capacitance that may occur between the conductive pattern 553 and the first gate electrode 121 , the conductive pattern 553 and the first gate electrode 121 may not overlap each other.

The fourth conductive layer 500 includes molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium ( Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and may include one or more metals selected from copper (Cu). The third conductive layer 500 may be a single layer or a multilayer layer. For example, the fourth conductive layer 500 may be formed in a stacked structure of Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, Ti/Cu, or the like.

A fifth insulating layer 139 may be positioned on the fourth conductive layer 500 . The fifth insulating layer 139 covers the fourth conductive layer 500 . The fifth insulating layer 139 may be generally disposed over the entire surface of the substrate 100 . In some embodiments, the fifth insulating layer 139 may include the same material as the fourth insulating layer 137 , or may include one or more materials selected from the exemplified materials of the fourth insulating layer 137 . .

A first device electrode 810 may be positioned on the fifth insulating layer 139 . The first device electrode 810 may be an anode electrode of the light emitting device OLED. The first device electrode 810 may be connected to the connection pattern 551 through the third contact hole CNT3 penetrating the fifth insulating layer 139 . Accordingly, the first element electrode 810 may be electrically connected to the first electrode 151b of the first switching element T1 via the connection pattern 551 .

A pixel defining layer 141 partitioning a light emitting region may be positioned on the fifth insulating layer 139 on which the first device electrode 810 is formed. The pixel defining layer 141 may have an opening exposing a top surface of the first device electrode 810 . The pixel defining layer 141 may include, for example, an organic material such as polyimide or hexamethyldisiloxane (HMDSO).

An emission layer 830 may be positioned on the first device electrode 810 in a region surrounded by the pixel defining layer 141 . In some embodiments, the emission layer 830 may be formed of a low molecular weight organic material or a high molecular weight organic material such as poly 3,4-ethylenedioxythiophene (PEDOT). In addition, the emission layer 830 may include a hole injection layer (HIL), a hole transporting layer (HTL), an electron transporting layer (ETL), and an electron injection layer (EIL). It may be a multi-layer comprising more than one. A second device electrode 850 may be positioned on the emission layer 830 . In some embodiments, the second device electrode 850 may be a cathode electrode.

The first device electrode 810 , the light emitting layer 830 , and the second device electrode 850 form a light emitting device OLED.

15 is a diagram illustrating a crosstalk test pattern for checking whether crosstalk occurs in a display device according to a comparative example, and FIG. 16 is a diagram illustrating a crosstalk test pattern for checking whether or not crosstalk occurs in a display device according to an exemplary embodiment. it is one drawing

In the case of the display device according to the comparative example, unlike the exemplary embodiment, the separation distance between the first gate electrode and the scan line is shorter than the separation distance between the first gate electrode and the control signal line.

15 and 16, when a crosstalk test pattern that induces crosstalk is displayed and driven for a long time, the upper portion (A2) and lower portion (A3) of the central portion (A1) of the square shape displaying black are displayed in gray vertical crosstalk defects may occur. And the color of the upper part A2 may be relatively dark compared to the color of the lower part A3 due to the influence of the parasitic coffee sitter.

In the case of the comparative example, since the separation distance between the first gate electrode and the scan line is shorter than the separation distance between the first gate electrode and the control signal line, the capacitance of the first parasitic capacitor (Ca in FIG. more likely to be greater than Cb). In this case, when the scan signal (GW[i] in FIG. 2) changes from the on level to the off level after the data writing period (PA4 in FIG. 4), the first node (N1 in FIG. 2) and the second node by kickback A potential difference may occur between N2 of FIG. 2 , and the voltage level of the first node ( N1 of FIG. 2 ) may be lower than the voltage level of the second node ( N2 of FIG. 2 ). Accordingly, the first gate electrode of the first switching element (T1 in FIG. 2) in the direction from the second node (N2 in FIG. 2) to the first node (N1 in FIG. 2) or in the second node (N2 in FIG. 2) Current can flow in the direction toward In this case, a vertical crosstalk defect displayed in gray may occur on both sides (A4, A5) of the central portion (A1) where the white color should be displayed. It may be relatively bright compared to the lower part. That is, it may gradually become brighter along the arrow direction of FIG. 15 . Accordingly, the upper part A2, which is relatively dark compared to the lower part A3, is located next to the bright part of both sides A4 and A5, and the lower part A3, which is relatively bright compared to the upper part A2, is the darkest part of the both sides A4 and A5. Since the bar is located next to the part, the crosstalk can be recognized relatively more clearly.

On the other hand, according to an exemplary embodiment, since the separation distance between the first gate electrode and the scan line is longer than the separation distance between the first gate electrode and the control signal line, the capacitance of the second parasitic capacitor (Cb in FIG. 2 ) is the first parasitic It may be larger than the capacitance of the capacitor (Ca in FIG. 2 ). Accordingly, when the scan signal (GW[i] in FIG. 2) changes from the on level to the off level after the data writing period (PA4 in FIG. 4), the first node (N1 in FIG. 2) and the second node (N1 in FIG. 2) by kickback Even when a potential difference occurs between N2 of FIG. 2 , the voltage level of the first node ( N1 of FIG. 2 ) may be maintained substantially higher than the voltage level of the second node ( N2 of FIG. 2 ). Accordingly, even if a current flow due to a potential difference occurs, the direction of the current is directed from the first node N1 to the second node N2 or from the first gate electrode of the first switching element T1 to the second node ( N2) can be maintained. In this case, even if there is a vertical crosstalk defect displayed in gray on both sides A4 and A5 of the central portion A1 where the white color should be displayed, the upper portion of the both sides A4 and A5 is higher than the lower portion based on the drawing. It can be relatively dark. That is, it may be gradually brightened along the arrow direction of FIG. 16 . Accordingly, the upper part A2, which is relatively dark compared to the lower part A3, is located next to the dark part of the both sides A4 and A5, and the lower part A3, which is relatively bright compared to the upper part A2, is the brightest part of the both sides A4 and A5. Since the bar is located next to the part, it is possible to minimize the visible crosstalk.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those of ordinary skill in the art to which the present invention pertains may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. you will be able to understand Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (20)

an initialization power line extending in a first direction;
a scan line extending along the first direction and spaced apart from the initialization power line in a second direction crossing the first direction;
a control signal line extending in the first direction and spaced apart from the scan line in the second direction;
a data line and a driving voltage line insulated from the initialization power line, the scan line, and the control signal line and extending in the second direction;
a first switching element including a first electrode connected to the driving voltage line, a first gate electrode and a second electrode overlapping the initialization power line;
a second switching element including a third electrode, a second gate electrode connected to the scan line, and a fourth electrode connected to the first gate electrode;
a third switching element including a fifth electrode connected to the third electrode, a third gate electrode connected to the control signal line, and a sixth electrode connected to the second electrode; and
a light emitting device electrically connected to the second electrode; including,
A distance between the first gate electrode and the scan line measured along the second direction is greater than a distance between the first gate electrode and the control signal line measured along the second direction. According to claim 1,
A first parasitic capacitance is formed between the scan line and the first gate electrode,
A second parasitic capacitance greater than or equal to the first parasitic capacitance is formed between the scan line and the third electrode. 3. The method of claim 2,
Further comprising a conductive pattern connected to the third electrode and overlapping the data line,
The second parasitic capacitance is further formed between the scan line and the conductive pattern. 4. The method of claim 3,
The conductive pattern and the driving voltage line are positioned on the same layer and made of the same material. 4. The method of claim 3,
A first capacitance is formed between the initialization power line and the first gate electrode,
A second capacitance is formed between the conductive pattern and the data line. 6. The method of claim 5,
The second capacitance is greater than the first capacitance. According to claim 1,
Further comprising a connection pattern connected to the second electrode,
The light emitting device is electrically connected to the second electrode via the connection pattern. 8. The method of claim 7,
The connection pattern and the driving voltage line are positioned on the same layer and made of the same material. According to claim 1,
Further comprising a bridge pattern connecting the fourth electrode and the first gate electrode,
The bridge pattern, the initialization power line, the scan line, and the control signal line are positioned on the same layer and made of the same material. According to claim 1,
an upper initialization signal line insulated from the scan line and the control signal line and extending in the second direction and connected to the initialization power line;
The upper initialization signal line and the driving voltage line are positioned on the same layer and made of the same material. Board;
a semiconductor layer positioned on the substrate and including a first portion, a second portion, and a third portion connecting the first portion and the second portion;
a first insulating layer positioned on the semiconductor layer;
A first conductive layer disposed on the first insulating layer and including a first gate electrode overlapping the first portion, a second gate electrode overlapping the second portion, and a third gate electrode overlapping the third portion ;
a second insulating layer positioned on the first conductive layer;
an initialization power line positioned on the second insulating layer, extending in a first direction and overlapping the first gate electrode, a scan line extending in the first direction and connected to the second gate electrode, and the first direction a second conductive layer extending along the line and including a control signal line connected to the third gate electrode; including,
A distance between the first gate electrode and the scan line measured along a second direction intersecting the first direction is greater than a distance between the first gate electrode and the control signal line measured along the second direction. . 12. The method of claim 11,
The second conductive layer,
The display device further comprising a bridge pattern connected to one side of the second portion and the first gate electrode. 12. The method of claim 11,
a third insulating layer positioned on the second conductive layer;
a third conductive layer disposed on the third insulating layer and including a data line extending in the second direction;
a fourth insulating layer positioned on the third conductive layer; and
a fourth conductive layer disposed on the fourth insulating layer and extending along the second direction and including a driving voltage line connected to one side of the first part; A display device further comprising a. 14. The method of claim 13,
The fourth conductive layer,
The display device further comprising a connection pattern connected to the other side of the first part. 15. The method of claim 14,
a fifth insulating layer positioned on the fourth conductive layer; and
The display device further comprising a light emitting element positioned on the fifth insulating layer and connected to the connection pattern. 14. The method of claim 13,
The fourth conductive layer,
and a conductive pattern connected to one side of the second portion and overlapping the data line. 17. The method of claim 16,
The conductive pattern does not overlap the first gate electrode. 14. The method of claim 13,
The fourth conductive layer,
and an upper initialization power line extending along the second direction and connected to the initialization power line. a first switching element including a first gate electrode connected to a first node, a first electrode connected to a first power line to which a first power is supplied, and a second electrode connected to a third node;
a second switching device including a second gate electrode connected to a scan line, a third electrode connected to the first node, and a fourth electrode connected to the second node;
a third switching element including a third gate electrode connected to a control signal line, a fifth electrode connected to the second node, and a sixth electrode connected to the third node;
a light emitting device connected to the third node;
a first capacitor connected between the first node and an initialization power supply;
a second capacitor connected between the second node and a data line;
a first parasitic capacitor connected between the scan line and the first node; and
a second parasitic capacitor connected between the scan line and the second node and having a capacitance greater than or equal to that of the first parasitic capacitor;
A display device comprising a. 20. The method of claim 19,
A capacitance of the second capacitor is greater than a capacitance of the first capacitor.

Images