KR102414157B1 - 하이브리드 캐시 - Google Patents

하이브리드 캐시 Download PDF

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KR102414157B1
KR102414157B1 KR1020187017114A KR20187017114A KR102414157B1 KR 102414157 B1 KR102414157 B1 KR 102414157B1 KR 1020187017114 A KR1020187017114 A KR 1020187017114A KR 20187017114 A KR20187017114 A KR 20187017114A KR 102414157 B1 KR102414157 B1 KR 102414157B1
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cache
logic
processor
response
memory
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KR20180085752A (ko
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가브리엘 에이치. 로흐
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/502—Control mechanisms for virtual memory, cache or TLB using adaptive policy
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/604—Details relating to cache allocation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020187017114A 2015-12-17 2016-09-20 하이브리드 캐시 Active KR102414157B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/973,448 2015-12-17
US14/973,448 US10255190B2 (en) 2015-12-17 2015-12-17 Hybrid cache
PCT/US2016/052722 WO2017105575A1 (en) 2015-12-17 2016-09-20 Hybrid cache

Publications (2)

Publication Number Publication Date
KR20180085752A KR20180085752A (ko) 2018-07-27
KR102414157B1 true KR102414157B1 (ko) 2022-06-28

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US (1) US10255190B2 (https=)
EP (1) EP3391227B1 (https=)
JP (1) JP6730434B2 (https=)
KR (1) KR102414157B1 (https=)
CN (1) CN108431786B (https=)
WO (1) WO2017105575A1 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103946812B (zh) * 2011-09-30 2017-06-09 英特尔公司 用于实现多级别存储器分级体系的设备和方法
CN106095587B (zh) * 2016-06-24 2019-12-24 北京金山安全软件有限公司 应用程序的缓存扫描方法、装置及电子设备
US11397687B2 (en) * 2017-01-25 2022-07-26 Samsung Electronics Co., Ltd. Flash-integrated high bandwidth memory appliance
US11016665B2 (en) * 2018-01-23 2021-05-25 Seagate Technology Llc Event-based dynamic memory allocation in a data storage device
CN109117291A (zh) * 2018-08-27 2019-01-01 惠州Tcl移动通信有限公司 基于多核处理器的数据调度处理方法、装置和计算机设备
US10740234B2 (en) * 2018-09-04 2020-08-11 International Business Machines Corporation Virtual processor cache reuse
CN112148665B (zh) * 2019-06-28 2024-01-09 深圳市中兴微电子技术有限公司 缓存的分配方法及装置
US11372758B2 (en) * 2020-05-12 2022-06-28 Jackson State University Dynamic reconfigurable multi-level cache for multi-purpose and heterogeneous computing architectures
KR102612947B1 (ko) * 2021-03-31 2023-12-11 광운대학교 산학협력단 통합 l2 캐시-변환 색인 버퍼 메모리의 제어 방법 및 장치
CN113259177B (zh) * 2021-06-17 2021-10-15 国网江苏省电力有限公司信息通信分公司 虚拟网络切片的重构方法和装置
KR102514268B1 (ko) * 2021-07-14 2023-03-24 연세대학교 산학협력단 데이터 마이그레이션 정책 스위칭 방법 및 장치
US11841798B2 (en) * 2021-08-09 2023-12-12 Arm Limited Selective allocation of memory storage elements for operation according to a selected one of multiple cache functions
US11989142B2 (en) 2021-12-10 2024-05-21 Samsung Electronics Co., Ltd. Efficient and concurrent model execution
US12197350B2 (en) 2021-12-10 2025-01-14 Samsung Electronics Co., Ltd. Low-latency input data staging to execute kernels
GB2622841B (en) 2022-09-29 2024-09-25 Imagination Tech Ltd Distributed system level cache
US20250086114A1 (en) * 2023-09-13 2025-03-13 Qualcomm Incorporated Performance-based cache adjustment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070143546A1 (en) 2005-12-21 2007-06-21 Intel Corporation Partitioned shared cache
US20120144092A1 (en) 2010-12-02 2012-06-07 Microsoft Corporation Efficient cache management
US20150205724A1 (en) 2014-01-20 2015-07-23 Honeywell International Inc. System and method of cache partitioning for processors with limited cached memory pools

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6324621B2 (en) * 1998-06-10 2001-11-27 International Business Machines Corporation Data caching with a partially compressed cache
US6792509B2 (en) 2001-04-19 2004-09-14 International Business Machines Corporation Partitioned cache of multiple logical levels with adaptive reconfiguration based on multiple criteria
US20030145170A1 (en) * 2002-01-31 2003-07-31 Kever Wayne D. Dynamically adjusted cache power supply to optimize for cache access or power consumption
US6868485B1 (en) 2002-09-27 2005-03-15 Advanced Micro Devices, Inc. Computer system with integrated directory and processor cache
US20040103251A1 (en) 2002-11-26 2004-05-27 Mitchell Alsup Microprocessor including a first level cache and a second level cache having different cache line sizes
US7643480B2 (en) * 2004-01-22 2010-01-05 Hain-Ching Liu Method and system for reliably and efficiently transporting data over a network
US7257678B2 (en) 2004-10-01 2007-08-14 Advanced Micro Devices, Inc. Dynamic reconfiguration of cache memory
US8037281B2 (en) * 2005-04-07 2011-10-11 Advanced Micro Devices, Inc. Miss-under-miss processing and cache flushing
US20060248287A1 (en) * 2005-04-29 2006-11-02 Ibm Corporation Methods and arrangements for reducing latency and snooping cost in non-uniform cache memory architectures
US7389402B2 (en) 2005-06-07 2008-06-17 Advanced Micro Devices, Inc. Microprocessor including a configurable translation lookaside buffer
US7577793B2 (en) * 2006-01-19 2009-08-18 International Business Machines Corporation Patrol snooping for higher level cache eviction candidate identification
US20080104323A1 (en) 2006-10-26 2008-05-01 Colglazier Daniel J Method for identifying, tracking, and storing hot cache lines in an smp environment
US8433851B2 (en) * 2007-08-16 2013-04-30 International Business Machines Corporation Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing
US8223650B2 (en) * 2008-04-02 2012-07-17 Intel Corporation Express virtual channels in a packet switched on-chip interconnection network
US8019946B2 (en) * 2008-07-31 2011-09-13 Samsung Electronics Co., Ltd. Method and system for securing instruction caches using cache line locking
US8990506B2 (en) * 2009-12-16 2015-03-24 Intel Corporation Replacing cache lines in a cache memory based at least in part on cache coherency state information
US8412971B2 (en) * 2010-05-11 2013-04-02 Advanced Micro Devices, Inc. Method and apparatus for cache control
US8788783B1 (en) * 2010-06-18 2014-07-22 Disney Enterprises, Inc. Dynamically tuning the size of a cache stored in a shared memory
US20120144123A1 (en) * 2010-12-01 2012-06-07 International Business Machines Corporation Read-ahead processing in networked client-server architecture
US20120303897A1 (en) * 2011-05-28 2012-11-29 Sakthivel Komarasamy Pullagoundapatti Configurable set associative cache way architecture
WO2013101092A1 (en) * 2011-12-29 2013-07-04 Intel Corporation Data control using last accessor information
GB2509755B (en) * 2013-01-14 2015-07-08 Imagination Tech Ltd Partitioning a shared cache using masks associated with threads to avoiding thrashing
KR20150115752A (ko) * 2013-01-31 2015-10-14 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. 적응성 입도 로우 버퍼 캐시
US9336144B2 (en) * 2013-07-25 2016-05-10 Globalfoundries Inc. Three-dimensional processing system having multiple caches that can be partitioned, conjoined, and managed according to more than one set of rules and/or configurations
US9251081B2 (en) 2013-08-01 2016-02-02 Advanced Micro Devices, Inc. Management of caches
KR101480143B1 (ko) * 2013-08-02 2015-01-06 전남대학교산학협력단 멀티코어 프로세서의 캐쉬 교체 방법 및 그 방법에 의해 동작하는 멀티코어 프로세서
US9244724B2 (en) * 2013-08-15 2016-01-26 Globalfoundries Inc. Management of transactional memory access requests by a cache memory
US9612961B2 (en) 2013-08-29 2017-04-04 Empire Technology Development Llc Cache partitioning in a multicore processor
US9208103B2 (en) * 2013-09-26 2015-12-08 Cavium, Inc. Translation bypass in multi-stage address translation
CN105579978B (zh) * 2013-10-31 2020-06-09 英特尔公司 用于动态控制高速缓存存储器的寻址模式的方法、设备和系统
US9710383B1 (en) * 2015-09-29 2017-07-18 EMC IP Holding Company LLC Caching techniques

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070143546A1 (en) 2005-12-21 2007-06-21 Intel Corporation Partitioned shared cache
US20120144092A1 (en) 2010-12-02 2012-06-07 Microsoft Corporation Efficient cache management
US20150205724A1 (en) 2014-01-20 2015-07-23 Honeywell International Inc. System and method of cache partitioning for processors with limited cached memory pools

Also Published As

Publication number Publication date
EP3391227A1 (en) 2018-10-24
WO2017105575A1 (en) 2017-06-22
US10255190B2 (en) 2019-04-09
JP6730434B2 (ja) 2020-07-29
KR20180085752A (ko) 2018-07-27
EP3391227B1 (en) 2024-09-11
CN108431786B (zh) 2024-05-03
EP3391227A4 (en) 2019-08-28
JP2019502996A (ja) 2019-01-31
CN108431786A (zh) 2018-08-21
US20170177492A1 (en) 2017-06-22

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