JP6730434B2 - ハイブリッドキャッシュ - Google Patents

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JP6730434B2
JP6730434B2 JP2018531516A JP2018531516A JP6730434B2 JP 6730434 B2 JP6730434 B2 JP 6730434B2 JP 2018531516 A JP2018531516 A JP 2018531516A JP 2018531516 A JP2018531516 A JP 2018531516A JP 6730434 B2 JP6730434 B2 JP 6730434B2
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cache
logical
logical cache
processor
core
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JP2019502996A5 (https=
JP2019502996A (ja
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エイチ． ロー ガブリエル
エイチ． ロー ガブリエル
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/502—Control mechanisms for virtual memory, cache or TLB using adaptive policy
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/604—Details relating to cache allocation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2018531516A 2015-12-17 2016-09-20 ハイブリッドキャッシュ Active JP6730434B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/973,448 2015-12-17
US14/973,448 US10255190B2 (en) 2015-12-17 2015-12-17 Hybrid cache
PCT/US2016/052722 WO2017105575A1 (en) 2015-12-17 2016-09-20 Hybrid cache

Publications (3)

Publication Number Publication Date
JP2019502996A JP2019502996A (ja) 2019-01-31
JP2019502996A5 JP2019502996A5 (https=) 2019-10-31
JP6730434B2 true JP6730434B2 (ja) 2020-07-29

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JP2018531516A Active JP6730434B2 (ja) 2015-12-17 2016-09-20 ハイブリッドキャッシュ

Country Status (6)

Country Link
US (1) US10255190B2 (https=)
EP (1) EP3391227B1 (https=)
JP (1) JP6730434B2 (https=)
KR (1) KR102414157B1 (https=)
CN (1) CN108431786B (https=)
WO (1) WO2017105575A1 (https=)

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US11397687B2 (en) * 2017-01-25 2022-07-26 Samsung Electronics Co., Ltd. Flash-integrated high bandwidth memory appliance
US11016665B2 (en) * 2018-01-23 2021-05-25 Seagate Technology Llc Event-based dynamic memory allocation in a data storage device
CN109117291A (zh) * 2018-08-27 2019-01-01 惠州Tcl移动通信有限公司 基于多核处理器的数据调度处理方法、装置和计算机设备
US10740234B2 (en) * 2018-09-04 2020-08-11 International Business Machines Corporation Virtual processor cache reuse
CN112148665B (zh) * 2019-06-28 2024-01-09 深圳市中兴微电子技术有限公司 缓存的分配方法及装置
US11372758B2 (en) * 2020-05-12 2022-06-28 Jackson State University Dynamic reconfigurable multi-level cache for multi-purpose and heterogeneous computing architectures
KR102612947B1 (ko) * 2021-03-31 2023-12-11 광운대학교 산학협력단 통합 l2 캐시-변환 색인 버퍼 메모리의 제어 방법 및 장치
CN113259177B (zh) * 2021-06-17 2021-10-15 国网江苏省电力有限公司信息通信分公司 虚拟网络切片的重构方法和装置
KR102514268B1 (ko) * 2021-07-14 2023-03-24 연세대학교 산학협력단 데이터 마이그레이션 정책 스위칭 방법 및 장치
US11841798B2 (en) * 2021-08-09 2023-12-12 Arm Limited Selective allocation of memory storage elements for operation according to a selected one of multiple cache functions
US11989142B2 (en) 2021-12-10 2024-05-21 Samsung Electronics Co., Ltd. Efficient and concurrent model execution
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Also Published As

Publication number Publication date
EP3391227A1 (en) 2018-10-24
WO2017105575A1 (en) 2017-06-22
US10255190B2 (en) 2019-04-09
KR102414157B1 (ko) 2022-06-28
KR20180085752A (ko) 2018-07-27
EP3391227B1 (en) 2024-09-11
CN108431786B (zh) 2024-05-03
EP3391227A4 (en) 2019-08-28
JP2019502996A (ja) 2019-01-31
CN108431786A (zh) 2018-08-21
US20170177492A1 (en) 2017-06-22

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