KR102400099B1 - Memory device having detection clock pattern generator for generating detection clock output signal with random data patterns - Google Patents

Abstract

Disclosed is a memory device having a detection clock pattern generator that generates a detection clock output signal of a random data pattern. The memory device includes a detection clock output pin, a mode register controlling a data type output to the detection clock output pin, and a detection clock pattern generator generating a detection clock output signal of a random data pattern. Random data pattern, inverted data pattern, fixed data pattern, error detection code, readout of the first rate or a second rate that is 1/2 ⁿ (n is a natural number) times the first rate, according to the control signal provided from the mode register A data strobe signal or a command address signal is selectively output to the detection clock output pin.

Description

{Memory device having detection clock pattern generator for generating detection clock output signal with random data patterns}

The present invention relates to a memory device, and more particularly, to a detection clock output signal for aligning data of a dynamic random access memory (DRAM) and a clock of a graphics processing unit (GPU) as a random data pattern in a clock data recovery operation. The present invention relates to a memory device including a clock pattern generator.

DRAMs may be used as graphics data memory in electronic devices. The controller (or central processing unit (CPU) or GPU) of the electronic device may transmit a command and an address to the DRAM in synchronization with the command clock, and may transmit data to the DRAM in synchronization with the data clock. The GPU may receive data output from DRAM in synchronization with the clock. In this case, the GPU may align the data of the DRAM with the clock of the GPU through a clock data recovery (hereinafter referred to as “CDR”) operation.

It is an object of the present invention to provide a memory device having a detection clock pattern generator that provides a detection clock output signal used in a clock data recovery operation as a random data pattern.

A memory device according to embodiments of the present invention includes a detection clock output pin, a mode register controlling a data type output to the detection clock output pin, and a detection clock pattern generator generating a detection clock output signal of a random data pattern do. According to the first control signal provided from the mode register, the random data pattern of the detection clock output signal is output to the detection clock output pin at the first rate or at a second rate that is 1/2 ⁿ (n is a natural number) times the first rate .

A memory device according to embodiments of the present invention generates a detection clock pattern for outputting a detection clock output signal of a random data pattern at a first rate or a second rate that is 1/2 ⁿ (n is a natural number) times the first rate includes wealth. The detected clock pattern generator includes a pseudo-random bit sequence generator that generates a plurality of random bit signals in response to the first clock signal, and selectively ORs the random bit signals to generate a plurality of logic output signals, and generates a plurality of random bit signals with some of the random bit signals. first and second logic block receiving the logic output signals and outputting a plurality of first logic switching signals in response to a logic low of the control signal and outputting a plurality of second logic switching signals in response to a logic high of the control signal; A first pattern selector that receives the logic switching signals and outputs a plurality of pattern signals in response to a first clock signal, and a signal that receives the plurality of pattern signals and is selected in response to a second clock signal from among the plurality of pattern signals and a second pattern selector for outputting as a detection clock output signal.

In the memory device according to the exemplary embodiments of the present invention, an error occurs with respect to data transmitted/received through a first error detection code pin used for error detection of data transmitted/received to/from the data input/output pins of a first group and data transmitted/received to/from the data input/output pins of a second group A second error detection code pin outputting a second error detection code used for detection, a mode register controlling data types output to the first and second error detection code pins, and generating a detection clock output signal of a random data pattern and a detection clock pattern generator. In response to the first control signal provided from the mode register, the random data pattern of the detected clock output signal is set at a first rate or at a second rate that is 1/2 ⁿ (n is a natural number) times the first rate and the second error output to the detection code pins.

The memory device of the present invention may reduce a phase offset and reduce a CDR locking time when a clock data recovery (CDR) operation is performed using a clock output signal detected from random data patterns.

1 is a block diagram illustrating a memory system including a memory device according to an embodiment of the present invention.
2A and 2B are timing diagrams illustrating an operation of a memory device according to embodiments of the present invention.
3A and 3B are diagrams illustrating a detection clock pattern generator according to an embodiment of the present invention.
4A and 4B are diagrams for explaining the PRBS generator of FIG. 3A.
5A and 5B are diagrams for explaining the logic block of FIG. 3A.
6A and 6B are views for explaining the first pattern selector of FIG. 3A .
7A and 7B are views for explaining the second pattern selection unit of FIG. 3A .
8A to 8C are diagrams illustrating a detection clock pattern generator according to an embodiment of the present invention.
9A to 9C are diagrams for explaining the logic block of FIG. 8A.
10A to 10C are views for explaining the first pattern selector of FIG. 8A .
11A to 11C are views for explaining the second pattern selection unit of FIG. 8A .
12 and 13 are diagrams illustrating a graphics memory system in which a memory device according to an embodiment of the present invention is mounted.
14 and 15A to 15C are diagrams illustrating a graphic memory system in which a memory device according to an embodiment of the present invention is mounted.
16 and 17A to 17D are diagrams for explaining a graphic memory system in which a memory device according to an embodiment of the present invention is mounted.
18 is a diagram illustrating a data eye pattern when a clock output signal detected of a random data pattern according to the present invention is used for a clock data recovery operation.

1 is a block diagram illustrating a memory system including a memory device according to an embodiment of the present invention.

Referring to FIG. 1 , a memory system 100 includes a controller 110 and a memory device 120 . The controller 110 may be implemented as a CPU or GPU, and may include an arithmetic unit (CPU core) and a cache memory. The memory device 120 may be a clock synchronous DRAM, such as a Synchronous DRAM (SDRAM). For example, the memory device 120 may be a Graphics Double Data Rate (GDDR) SDRAM. According to an embodiment, the memory device 120 may be a memory device such as a double data rate (DDR) SDRAM synchronous dynamic random access memory, a low power double data rate (LPDDR) SDRAM, or a RAMbus dynamic random access memory (RDRAM). .

A clock signal line 11 , a command address bus 12 , and a data bus 13 may be connected between the controller 110 and the memory device 120 . The main clock signal CK generated by the controller 110 may be provided to the memory device 120 through the clock signal line 11 . For example, the main clock signal CK may be provided as a continuous alternating inverted signal together with the inverted main clock signal CKB. Since the rising/falling edges of the main clock signal pair CK and CKB can be detected based on their crossing points, timing accuracy can be improved.

According to an exemplary embodiment, a single main clock signal CK may be provided as a continuous alternating inversion signal to the clock signal line 11 . In this case, in order to identify the rising/falling edges of the main clock signal CK, it is necessary to compare the main clock signal CK with the reference voltage Vref. However, when noise fluctuation or the like occurs in the reference voltage Vref, a shift occurs in the detection of the main clock signal CK, and the timing accuracy is compared to the case of using the main clock signal pair CK and CKB. may fall

Accordingly, it is preferable that the clock signal line 11 transmits complementary continuously alternating inverted signals using the main clock signal pair CK and CKB. In this case, the clock signal line 11 may be composed of two signal lines for transmitting CK and CKB main clock signals. The main clock signal CK described in the embodiments of the present invention may be described as a main clock signal pair CK and CKB. For convenience of description, the main clock signal pair CK and CKB will be collectively referred to as the main clock signal CK.

According to an embodiment, the memory system 100 may support data communication using various clock signals including the data clock signal WCK in addition to the main clock signal CK. For example, the frequency of the data clock signal WCK may be twice or four times the frequency of the main clock signal CK.

The command CMD provided from the controller 110 may be provided to the memory device 120 through the command address bus 12 . Also, the address signal provided from the controller 110 may be provided to the memory device 120 through the command address bus 12 . A command CMD or an address signal may be issued by a combination of command address CA signals that are time-sequentially received through the command address bus 12 .

For a data interface between the controller 110 and the memory device 120 , data DQ may be transmitted through the data bus 13 . For example, write data DQ corresponding to a burst length BL provided from the controller 110 may be transmitted to the memory device 120 through the data bus 13 . The read data DQ corresponding to the burst length BL read from the memory device 120 may be transmitted to the controller 110 through the data bus 13 . The write data DQ or read data DQ may be transmitted/received through a data input/output pin (hereinafter, referred to as a “DQ pin”) of the memory device 120 . Here, the term 'pin' broadly refers to an electrical interconnection to an integrated circuit and includes, for example, a pad or other electrical contact point on the integrated circuit.

The data interface speed between the controller 110 and the memory device 120 is increasing. For example, due to the development of high-speed graphics or games, or the improvement of the operating speed of the controller 110 , the speed of the data interface of the memory device 120 is also required to be increased.

From the viewpoint of a data interface for read data of the memory device 120 , the data DQ output from the memory device 120 is transmitted to the controller 110 , and the controller 110 synchronizes the memory device 120 with a clock signal. ) of the output data DQ can be received. The controller 110 may perform a data synchronization operation of synchronizing the output data DQ of the memory device 120 to a clock signal. The data synchronization operation may include a clock data restoration operation of adjusting a phase so that an edge of the clock signal of the controller 110 comes in the middle of the output data DQ of the memory device 120 . The clock data recovery operation may be performed by the clock data recovery unit 112 (hereinafter referred to as a “CDR unit”) using the detected clock output signal DC provided from the memory device 120 .

The memory device 120 may include a mode register 121 providing a plurality of operation options. The mode register 121 may set various functions, characteristics, and modes of the memory device 120 . The mode register 121 is, for example, CAS Latency, Burst Length, Error Detection Code Scheme, Cyclic Redundancy Check (CRC), CRC Latency, Write Latency Latency), a specific operation mode such as DBI (Data Bus Inversion) can be set.

The mode register 121 may provide a plurality of control signals PRBS_EN, EDC_HOLDP, EDC_HR, EDC_INV, EDC_CRC, EDC_RDQS, and EDC_CA for controlling the operation of the detected clock pattern generator 122 .

The first control signal PRBS_EN is a signal set to enable the detection clock pattern generation unit 122 and the detection clock pattern generation unit 122 to generate a detection clock output signal DC of a random data pattern. For example, when the first control signal PRBS_EN is logic high, the detection clock pattern generator 122 may be enabled to generate the detection clock output signal DC of the random data pattern. When the first control signal PRBS_EN is a logic low, the detection clock pattern generator 122 may be disabled.

The second control signal EDC_HOLDP is a signal set such that a hold data pattern is output to the detection clock output signal DC pin instead of the random data pattern generated by the detection clock pattern generator 122 . The second control signal EDC_HOLDP may be a detection clock output signal DC pin, and may cause a fixed data pattern provided from the mode register 121 to be output. Exemplarily, by the second control signal EDC_HOLDP, the fixed data pattern is 0000, 0001, ... , may be set to any one of 1111 patterns. When the second control signal EDC_HOLDP is set to 0001, the detection clock output signal DC may be repeatedly output in patterns 0001, 0001, and 0001. According to an embodiment, the second control signal EDC_HOLDP of the fixed data pattern may be provided when the detection clock pattern generator 122 is disabled by the logic low of the first control signal PRBS_EN.

The third control signal EDC_HR is a random data pattern of the detection clock output signal DC generated by the detection clock pattern generator 122 at the first rate or 1/2 ⁿ (n is a natural number) times the first rate. It is a signal set to be output at 2 rate. The first rate may be set such that the random data pattern is output in units of 1 bit, and the second rate may be set so that the random data pattern is output in units of 2 ⁿ bits, such as in units of 2 bits, units of 4 bits, units of 8 bits, or the like. For example, when the third control signal EDC_HR is logic low, the random data pattern of the detection clock output signal DC output from the detection clock pattern generator 122 may be output at the first rate. When the third control signal EDC_HR is logic high, the random data pattern of the detection clock output signal DC output from the detection clock pattern generator 122 may be output at a second rate.

According to an embodiment, when the fixed data pattern is output to the detection clock output signal DC pin, if the third control signal EDC_HR is logic low, the fixed data pattern is output at the first rate, and the third control signal EDC_HR ) is logic high, the fixed data pattern may be output at the second rate.

The fourth control signal EDC_INV is a signal set so that the random data pattern of the detection clock output signal DC output from the detection clock pattern generator 122 is inverted and output. For example, when the fourth control signal EDC_INV is logic low, the random data pattern of the detection clock output signal DC output from the detection clock pattern generator 122 may be output without inversion. When the fourth control signal EDC_INV is logic high, the random data pattern of the detection clock output signal DC output from the detection clock pattern generator 122 may be inverted and output.

According to an embodiment, when the fixed data pattern is output to the detection clock output signal DC pin and the fourth control signal EDC_INV is logic low, the fixed data pattern is output to the detection clock output signal DC pin without inversion. and, when the fourth control signal EDC_INV is logic high, the fixed data pattern may be inverted and output to the detection clock output signal DC pin.

The fifth control signal EDC_CRC is a signal set to output a cyclic redundancy check (CRC) code generated by the detection clock pattern generator 122 to the detection clock output signal DC pin. The detected clock pattern generator 122 may detect an error in the data DQ in the data access mode by the controller 110 in order to improve data reliability of the memory device 120 . The detected clock pattern generator 122 may generate a CRC code for the read and/or write data DQ in response to the fifth control signal EDC_CRC and transmit it to the controller 110 through a DC pin. The controller 110 may determine whether there is an error in the data DQ based on the transmitted CRC code and re-issue the read and/or write command.

According to an embodiment, when the CRC code is output to the DC pin, if the third control signal EDC_HR is logic low, the CRC code output to the DC pin is output at the first rate, and the third control signal EDC_HR is When logic high, the CRC code output to the DC pin may be output at a second rate that is 1/2 ⁿ (n is a natural number) times the first rate.

The sixth control signal EDC_RDQS is a signal set to output the read data strobe signal RDQS to the DC pin of the memory device 120 . The read data strobe signal RDQS may be provided to the controller 110 during the read data strobe mode. The controller 110 may receive the read data strobe signal RDQS together with the read data DQ output from the memory device 120 and latch the read data DQ using the read data strobe signal RDQS. there is.

According to an embodiment, when the read data strobe signal RDQS is output to the DC pin and the third control signal EDC_HR is logic low, the read data strobe signal RDQS output to the DC pin is output at the first rate. and, when the third control signal EDC_HR is logic high, the read data strobe signal RDQS output to the DC pin may be output at a second rate that is 1/2 ⁿ (n is a natural number) times the first rate.

The seventh control signal EDC_CA is a signal configured to output the command address CA data to the DC pin of the memory device 120 . The command address CA data is provided to the controller 110 , and the controller 110 may perform a command address CA training operation using the command address CA data. The command address CA training operation refers to a synchronization operation such that the middle of the window of the command address CA transmitted from the controller 110 to the memory device 120 comes to the edge of the main clock signal CK.

According to an embodiment, when the command address CA data is output to the DC pin and the third control signal EDC_HR is logic low, the command address CA data output to the DC pin is output at a first rate, When the third control signal EDC_HR is logic high, the command address CA data output to the DC pin may be output at a second rate that is 1/2 ⁿ (n is a natural number) times the first rate.

The memory device 120 may include a detection clock pattern generator 122 that generates a detection clock output signal DC. The detection clock pattern generator 122 may generate a detection clock output signal DC of a random data pattern. The memory device 120 may transmit the detection clock output signal DC of the random data pattern to the controller 110 through the signal line 14 connected to a dedicated pin for outputting the detection clock output signal DC. The CDR unit 112 of the controller 110 may perform a clock data recovery operation using the detected clock output signal DC of a random data pattern similar to actual data. Accordingly, the CDR unit 112 may reduce the phase offset and reduce the locking time in the clock data restoration operation.

2A and 2B are timing diagrams illustrating an operation of a memory device according to embodiments of the present invention. FIG. 2A shows a type in which the read data strobe signal RDQS is output to the detection clock output signal DC pin of the memory device 120 , and FIG. 2B shows a type in which a random data pattern is output.

Referring to FIG. 2A in conjunction with FIG. 1 , the main clock signal CK is received from a time point Ta0. At a time point Ta0, a mode register setting command MRS synchronized with the rising edge of the main clock signal CK is received by the memory device 120, and the memory device 120 enters a read data strobe (RDQS) mode. there is. Thereafter, at time Ta4 , the mode register setting command MRS synchronized with the rising edge of the main clock signal CK is received from the memory device 120 , and the memory device 120 enters the read data strobe (RDQS) mode. can escape

During the read data strobe RDQS mode, after the read command RD is applied at the time Ta1 , at the time Ta3 when the read latency RL set in the memory device 120 elapses, the memory device 120 transmits the read data DQ ) can be printed. 8-bit data corresponding to BL 8 may be output as the read data DQ. Before the read data DQ is output, a clock-like pattern fixed to the DC pin at the time Ta2 may be output. A pattern such as a fixed clock is output together with the read data DQ and provided to the controller 110 ( FIG. 1 ), and may act as a read data strobe signal RDQS. The controller 110 may use the read data strobe signal RDQS to latch the read data.

Referring to FIG. 2B in conjunction with FIG. 1 , the main clock signal CK may be received by the memory device 120 .

The main clock signal CK is received from the time point Ta. At time Ta, the read command RD synchronized with the rising edge of the main clock signal CK may be received by the memory device 120 .

After application of the read command RD at the time Ta, at a time Tf at which the Cass latency CL set in the memory device 120 elapses, the memory device 120 may output the read data DQ. For the read data DQ, 8-bit data corresponding to BL 8 may be output as, for example, 00110101. If the output period of 1-bit data is defined as "T", the read data DQ of BL 8 may be output for 8T time. The 8T time may be set as a unit interval U.I of the read data DQ. During the data unit interval 8T from the time Tf to the time Tg, the read data DQ of BL 8 may be output. Hereinafter, 8T will be described as a data interval unit and T as a 1-bit data unit.

The detection clock output signal DC output from the detection clock pattern generator 122 may be output as a different data pattern, ie, a random data pattern, for each data unit interval 8T. For example, during the data unit interval 8T from the time Ta to the time Tb, the detection clock output signal DC may be output as a 11000001 data pattern. During the data unit interval 8T from time Tb to time Tc, the detection clock output signal DC is a 01000000 data pattern, and during the data unit interval 8T from time Tc to Td, the detection clock output signal DC is 11100000 As a data pattern, the detection clock output signal DC during the data unit interval 8T from the Td time point to the Te time point is a 10101000 data pattern, and the detection clock output signal during the data unit interval 8T from the Te time point to the Tf time point. (DC) may be output as a 00010000 data pattern. Also, during the data unit interval 8T from the time Tf at which the read data DQ is output to the time Tg, the detection clock output signal DC may be output as a 01010100 data pattern.

The detection clock output signal DC output from the memory device 120 may be output as a random data pattern and transmitted to the controller 110 . The detected clock output signal DC is provided from the detected clock pattern generating unit 122, and the operation of the pseudo random bit sequence generating unit 400 ( FIG. 3 ) in the detected clock pattern generating unit 122 is dependent on the operation of the detected clock output signal DC. It can be generated as a pseudo-random data pattern rather than a completely random data pattern. This is because, when the number of flip-flops constituting the pseudo random bit sequence generator 400 is n (n is a natural number), 2 ⁿ −1 random data patterns are repeatedly generated.

3A and 3B are diagrams illustrating a detection clock pattern generator according to an embodiment of the present invention. FIG. 3A is a block diagram of the detected clock pattern generator of FIG. 1 , and FIG. 3B is a timing diagram illustrating an operation of the detected clock pattern generator.

Referring to FIG. 3A , the detected clock pattern generator 122a may be enabled by the first control signal PRBS_EN provided from the mode register 121 ( FIG. 1 ). The detected clock pattern generation unit 122a includes a pseudo random bit sequence generation unit 400 (hereinafter, referred to as a “PRBS generation unit”), a logic block 500, a first pattern selection unit 600, And it may include a second pattern selector 700 .

The PRBS generator 400 may generate a plurality of random bit signals a _n to a _n+6 in response to the first clock signal CKD8 . The plurality of random bit signals a _n to a _n+6 may be provided to the logic block 500 and the first pattern selector 600 . The PRBS generator 400 may include a plurality of flip-flops and an exclusive OR gate. The first clock signal CKD8 may be an internal clock signal generated in the memory device 120 based on the main clock signal CK. In some embodiments, the first clock signal CKD8 may be an internal clock signal driven based on the data clock signal WCK. The first clock signal CK8D may be generated as a clock signal having a data unit interval of 8T set as 1 clock cycle and having a 50% duty cycle.

The logic block 500 receives the random bit signals a _n to a _{n +6} and selectively performs an exclusive-OR with the random bit signals a _n to a n+6 to generate a plurality of logic output signals ( a _n+16 , a _n+32 , a _n+48 , a _n+64 , a _n+80 , a _n+96 , a _{n+ 112} ) can be created. The logic block 500 may include a plurality of exclusive OR gates. The logic output signals a _n+16 , a _n+32 , a _n+48 , a _n+64 , a _n+80 , a _n+96 , a _n+112 are transmitted to the first pattern selector 600 . can be provided.

The first pattern selection unit 600 is a random bit signal (a _n ) of the PRBS generator 400 and the logic output signals (a _n+16 , a _n+32 , a _n+48 ) of the logic block 500 , a _n+64 , a _n+80 , a _n+96 , a _n+112 ) is received, and a plurality of pattern signals z ₀ , z ₁ , z ₂ , z in response to the first clock signal CKD8 ₃ ) can be created. The first pattern selector 600 may be implemented with a plurality of multiplexers. The pattern signals z ₀ , z ₁ , z ₂ , and z ₃ may be provided to the second pattern selector 700 .

The second pattern selector 700 receives the pattern signals z ₀ , z ₁ , z ₂ , and z ₃ , and a second clock signal among the pattern signals z ₀ , z ₁ , z ₂ , and z ₃ . A pattern signal selected in response to the CKDP[0:3] may be output as the detection clock output signal DC. The second pattern selector 700 may be implemented as one multiplexer. The second clock signals CKDP[0:3] may be generated as clock signals having one clock cycle of 4T, which is half the data unit interval, and having a 25% duty cycle.

Referring to FIG. 3B , first clock signals CKD8 having a period of 8T data unit intervals and second clock signals CKDP[0:3] having a period of 4T which is half the data unit interval are provided. Each of the second clock signals CKDP[0:3] may be provided as a pulse signal having a high level section of time T. The CKDP[1] clock signal is provided by being T time shifted based on the rising edge of the CKDP[0] clock signal, and T time shifted based on the rising edge of the CKDP[1] clock signal to provide the CKDP[2] clock signal The CKDP[2] clock signal may be provided with a T time shift based on the rising edge of the CKDP[2] clock signal.

The detected clock pattern generator 122a may output the detected clock output signal DC in response to the first and second clock signals CKD8 and CKDP[0:3]. The detection clock output signal DC may be output in a different data pattern for each data unit interval 8T. For example, the detection clock output signal DC may be output as a random data pattern in 1-bit data units T, such as 10110111, 10110001, 10100101, and 11011100.

4A and 4B are diagrams for explaining the PRBS generator of FIG. 3A. 4A is a circuit diagram of a PRBS generator, and FIG. 4B is a timing diagram illustrating an operation of the PRBS generator.

Referring to FIG. 4A , the PRBS generator 400 may include a plurality of flip-flops 401 to 407 and an exclusive-OR gate 408 . A plurality of flip-flops 401 to 407 may be connected in series and constitute a linear feedback shift register. The linear feedback shift register can generate 2 ⁿ -1 random patterns. Here, n is the number of flip-flops constituting the linear feedback shift register. In the present embodiment, 2 ⁷ −1, that is, 127 random patterns may be generated using the 7 flip-flops 401 to 407 .

The first flip-flop 401 inputs the output of the exclusive-OR gate 408 and latches the output state of the exclusive-OR gate 408 in response to the rising edge of the first clock signal CKD8, so that a _n+6 random It can be output as a bit signal. The second flip-flop 402 inputs the output of the first flip-flop 401 and latches the output state of the first flip-flop 401 in response to the rising edge of the first clock signal CKD8 to a _n+ It can be output as ₅ random bit signals. In this way, each of the third to seventh flip-flops 403 to 407 latches the output state of the previous flip-flop in response to the rising edge of the first clock signal CKD8 to a _n+4 , a _{n +3} , a _n+2 , a _n+1 , a _n random bit signals may be output.

The exclusive OR gate 408 may input a _n+1 random bit signal that is an output signal of the sixth flip-flop 406 and a _n random bit signal that is an output signal of the seventh flip-flop 407 . The exclusive-OR gate 408 may exclusive-OR a _n+1 and a _n random bit signals to provide an output thereof to the first flip-flop 401 .

Each of the random bit signals a _n to a _n+6 generated by the PRBS generator 400 responds to the first clock signal CKD8 having a data unit interval of 8T, as shown in FIG. 4B . The first clock signal CKD8 may be shifted by one clock cycle 8T. The random bit signals a _n to a _n+6 may be generated as 127 random patterns for each rising edge of the first clock signal CKD8 . The random bit signals a _n to a _n+6 of 127 random patterns may be repeatedly generated in response to the first clock signal CKD8 .

5A and 5B are diagrams for explaining the logic block of FIG. 3A. 5A is a block diagram of a logic block, and FIG. 5B is a timing diagram illustrating an operation of the logic block.

Referring to FIG. 5A , the logic block 500 includes a plurality of exclusive OR gates 501 to 507 for receiving the random bit signals a _n to a _n+6 of the PRBS generator 400 of FIG. 4A . may include Each of the exclusive OR gates 501 to 507 selectively inputs the random bit signals a _n to a _n+6 to provide logic output signals a _n+16 , a _n+32 , a _n+48 , a _n+64 , a _n+80 , a _n+96 , a _n+112 ) can be output.

The first exclusive-OR gate 501 may input a _n+2 and a _n+4 random bit signals to output a _n+16 logic output signal. The second exclusive-OR gate 502 may input a _n+1 , a _n+2 , and a _n+4 random bit signals to output a _n+32 logic output signal. The third exclusive-OR gate 503 may output a _n+48 logic output signal by inputting a _n+1 , a _n+2 , a _n+3 , a _n+4 , a _n+5 random bit signals. there is. The fourth exclusive-OR gate 504 may input a _n+1 and a _n+4 random bit signals to output a _n+64 logic output signal. The fifth exclusive-OR gate 505 may input a _n+1 , a _n+2 , a _n+3 , a _n+5 , a _n+6 random bit signals to output a _n+80 logic output signal. there is. The sixth exclusive-OR gate 506 may input a _n+1 , a _n+3 , and a _n+6 random bit signals to output a _n+96 logic output signal. The seventh exclusive-OR gate 507 may input a _n , a _n+2 , and a _n+4 random bit signals to output a _n+112 logic output signal.

Each of the logic output signals (a _n+16 , a _n+32 , a _n+48 , a _n+64 , a _n+80 , a _n+96 , a _n+112 ) output from the logic block 500 is , shows random data patterns, as shown in FIG. 5B . In FIG. 5B , the logic output signals (a _n+16 , a _{n +32} , a _n+48 , a _n+64 , a _n+80 , a _{n+ 96} , a _n+112 ). a _n , a _n+16 , a _n+32 , a _n+48 , a _n+64 , a _n+80 , a _n+96 , a _n+112 signals are transmitted to the first pattern selector 600 of FIG. 6A . can be provided as

6A and 6B are views for explaining the first pattern selector of FIG. 3A . 6A is a circuit diagram of the first pattern selector, and FIG. 6B is a timing diagram illustrating an operation of the first pattern selector.

Referring to FIG. 6A , the first pattern selector 600 includes a random bit signal a _n output from the PRBS generator 400 and logic output signals a _n+16 output from the logic block 500 , a _n+32 , a _n+48 , a _n+64 , a _n+80 , a _n+96 , a _{n+ 112} ) may be received. The first pattern selector 600 is a _n , a _n+16 , a _n+32 , a _n+48 , a _n+64 , a _n+80 , a _n+96 , a _n+112 Signals selected in response to one clock signal CKD8 may be output as pattern signals z ₀ , z ₁ , z ₂ , and z ₃ . The first pattern selector 600 may be implemented as an 8:4 multiplexer including first to fourth multiplexers 601 to 604 .

The first multiplexer 601 receives a _n random bit signal as a first input I1, a _n+64 logic output signal as a second input I2, and a first clock signal as a select input S By receiving the signal CKD8 , the first pattern signal z ₀ may be output. The first pattern signal z ₀ may be generated depending on a transition between the states of the a _n random bit signal and the a _n+64 logic output signal and the first clock signal CKD8 . When the first clock signal CKD8 of the selection input S is logic high, the state of the a _n random bit signal of the first input I1 may be selected and output as the first pattern signal z ₀ . When the first clock signal CKD8 of the selection input S is a logic low, the state of the a _n+64 logic output signal of the second input I2 may be selected and output as the first pattern signal z ₀ . .

The second multiplexer 602 receives a _n+16 logic output signal as a first input I1, a _n+80 logic output signal as a second input I2, and a second multiplexer 602 as a select input S The first clock signal CKD8 may be received, and the second pattern signal z ₁ may be output. When the first clock signal CKD8 of the selection input S is logic high, the state of the a _n+16 logic output signal of the first input I1 may be selected and output as the second pattern signal z ₁ . . When the first clock signal CKD8 of the selection input S is a logic low, the state of a _n+80 logic output signal of the second input I2 may be selected and output as the second pattern signal z ₁ . .

The third multiplexer 603 receives a _n+32 logic output signal as a first input I1, a _n+96 logic output signal as a second input I2, and a second input signal as a select input S. The first clock signal CKD8 may be received, and the third pattern signal z ₂ may be output. When the first clock signal CKD8 of the selection input S is logic high, the state of the a _n+32 logic output signal of the first input I1 may be selected and output as the third pattern signal z ₂ . . When the first clock signal CKD8 of the selection input S is a logic low, the state of a _n+96 logic output signal of the second input I2 may be selected and output as the third pattern signal z ₂ . .

The fourth multiplexer 604 receives a _n+48 logic output signal as a first input I1, a _n+112 logic output signal as a second input I2, and a second multiplexer 604 as a select input S. The first clock signal CKD8 may be received, and a fourth pattern signal z ₃ may be output. When the first clock signal CKD8 of the selection input S is logic high, the state of the a _n+48 logic output signal of the first input I1 may be selected and output as the fourth pattern signal z ₃ . . When the first clock signal CKD8 of the selection input S is a logic low, the state of a _n+112 logic output signal of the second input I2 may be selected and output as the fourth pattern signal z ₃ . .

Each of the pattern signals z ₀ , z ₁ , z ₂ , and z ₃ output from the first pattern selector 600 shows random data patterns, as shown in FIG. 6B . The pattern signals z ₀ , z ₁ , z ₂ , and z ₃ may be provided to the second pattern selector 700 of FIG. 7A .

7A and 7B are views for explaining the second pattern selection unit of FIG. 3A . 7A is a circuit diagram of the second pattern selector, and FIG. 7B is a timing diagram illustrating an operation of the second pattern selector.

Referring to FIG. 7A , the second pattern selector 700 receives the pattern signals z ₀ , z ₁ , z ₂ , and z ₃ output from the first pattern selector 600 , and a third clock signal A pattern signal selected from among the pattern signals z ₀ , z ₁ , z ₂ , and z ₃ may be generated as the detection clock output signal DC in response to the CKDP[0:3]. The second pattern selector 700 may be implemented as a 4:1 multiplexer.

The second pattern selector 700 receives a z ₀ pattern signal as a first input I1 , a z ₁ pattern signal as a second input I2 , and a z ₂ pattern signal as a third input I3 . , receives the z ₃ pattern signal as the fourth input I4, and receives the third clock signals CKDP[0:3] as the selection input S to generate the detection clock output signal DC can be printed out. The detection clock output signal DC may be generated depending on the states of the pattern signals z ₀ , z ₁ , z ₂ , and z ₃ and the states of the third clock signals CKDP[0:3]. When the third clock signal CKDP[0] of the selection input S is logic high, the state of the z ₀ pattern signal of the first input I1 may be selected and output as the detection clock output signal DC. When the third clock signal CKDP[1] of the selection input S is logic high, the state of the z ₁ pattern signal of the second input I1 may be selected and output as the detection clock output signal DC. When the third clock signal CKDP[2] of the selection input S is logic high, the state of the z ₂ pattern signal of the third input I3 may be selected and output as the detection clock output signal DC. When the third clock signal CKDP[3] of the selection input S is logic high, the state of the z ₃ pattern signal of the fourth input I4 may be selected and output as the detection clock output signal DC.

The detection clock output signal DC output from the second pattern selector 700 shows random data patterns as shown in FIG. 7B . The detection clock output signal DC may be provided as a random data pattern in units of 1-bit data. The detection clock output signal DC is generated based on the random bit signals a _n to a _n+6 of the PRBS generator 400 described with reference to FIG. 4A and has a random data pattern. Since 127 random patterns are repeatedly generated for the random bit signals (a _n to a _n+6 ), the detection clock output signal DC is also random bit signals (a _n to a _n+6 ) of 127 random patterns can be iteratively generated. Accordingly, the detection clock output signal DC may be configured as a pseudo-random data pattern.

8A to 8C are diagrams illustrating a detection clock pattern generator according to an embodiment of the present invention. FIG. 8A is a block diagram of the detection clock pattern generator of FIG. 1 , FIG. 8B is a timing diagram illustrating the operation of the detection clock pattern generator when the third control signal EDC_HR is logic low, and FIG. 8C is the third control signal It is a timing diagram explaining the operation of the detection clock pattern generator when (EDC_HR) is logic high. The third control signal EDC_HR is a signal for controlling the random data pattern of the detection clock output signal DC output from the detection clock pattern generator to be output at a first rate or a second rate that is half of the first rate. The first rate may be set to output the random data pattern in units of 1-bit data, and the second rate may be set to output the random data pattern in units of 2-bit data.

Referring to FIG. 8A , the detected clock pattern generator 122b may be enabled by the first control signal PRBS_EN provided from the mode register 121 ( FIG. 1 ). The detected clock pattern generator 122b may include It may include a PRBS generator 400 , a logic block 900 , a first pattern selector 1000 , and a second pattern selector 1100 .

The PRBS generating unit 400 is the same as the PRBS generating unit 400 described with reference to FIG. 4A . The PRBS generator 400 may be a linear feedback shift register including seven flip-flops 401 to 407 and an exclusive OR gate 408 . The PRBS generator 400 may generate a plurality of random bit signals a _n to a _n+6 in response to the first clock signal CKD8 .

The logic block 900 may receive the random bit signals a _n to a _n+6 and generate a plurality of logic switching signals N1 to N8 in response to the third control signal EDC_HR. The logic block 900 may include a plurality of exclusive-OR gates and a plurality of switching devices. The logic switching signals N1 to N8 may be provided to the first pattern selector 1000 .

The first pattern selector 1000 receives the logic switching signals N1 to N8 of the logic block 500 , and receives a plurality of pattern signals z ₀ , z ₁ , in response to the first clock signal CKD8 , z ₂ , z ₃ ) can be created. The first pattern selector 1000 may be implemented with a plurality of multiplexers. The pattern signals z ₀ , z ₁ , z ₂ , and z ₃ may be provided to the second pattern selector 1100 .

The second pattern selector 1100 receives the pattern signals z ₀ , z ₁ , z ₂ , and z ₃ , and a second clock signal among the pattern signals z ₀ , z ₁ , z ₂ , and z ₃ . A pattern signal selected in response to the CKDP[0:3] may be output as the detection clock output signal DC. The second pattern selector 700 may be implemented as one multiplexer.

Referring to FIG. 8B , a first clock signal CKD8 having a period of a data unit interval of 8T is provided. Each of the second clock signals CKDP[0:3] is provided as a pulse signal having a 4T period, which is half the data unit interval, and a high-level period of T time. When the third control signal EDC_HR is logic low, the detection clock pattern generator 122b receives the detection clock output signal DC in response to the first and second clock signals CKD8 and CKDP[0:3]. can be printed out. The detection clock output signal DC may be output in a 1-bit data unit T, that is, a random data pattern of a first rate.

Referring to FIG. 8C , the second clock signals CKDP[ 0:3]) each is provided. When the third control signal EDC_HR is logic high, the detection clock pattern generator 122b receives the detection clock output signal DC in response to the first and second clock signals CKD8 and CKDP[0:3]. can be printed out. The detection clock output signal DC may be output in a 2-bit data unit T, that is, a random data pattern of a second rate that is half the first rate.

9A to 9C are diagrams for explaining the logic block of FIG. 8A. 9A is a block diagram of a logic block, FIG. 9B is a timing diagram illustrating an operation of a logic block when the third control signal EDC_HR is logic low, and FIG. 9C is a third control signal EDC_HR that is logic high It is a timing diagram that describes the operation of a logic block when.

Referring to FIG. 9A , the logic block 900 may include a plurality of exclusive-OR gates 901 to 907 and a plurality of switching devices 911 to 918 . The plurality of exclusive OR gates 901 to 907 are configured in the same way as the plurality of exclusive OR gates 501 to 507 described with reference to FIG. 5A , and the random bit signals a _n to a of the PRBS generator 400 . _n+6 ) can be received. Each of the exclusive OR gates 901 to 907 selectively inputs the random bit signals a _n to a _n+6 to provide logic output signals a _n+16 , a _n+32 , a _n+48 , a _n+64 , a _n+80 , a _n+96 , a _n+112 ) can be output. The logic output signals a _n+16 , a _n+32 , a _n+48 , a _n+64 , a _n+80 , a _n+96 , a _n+112 have a random data pattern identical to that of FIG. 5B . will be output as

A plurality of switching elements 911 to 918 are logic output signals (a _n+16 , a _n+32 , a _n+48 , a _n+64 , a _n+80 , a _n+96 , a _{n+ 112} ) , and a third control signal (a _n+16 , a _n+32 , a _n+48 , a _n+64 , a _n+80 , a _n+96 , a _n+112 ) Signals selected in response to EDC_HR) may be output as logic switching signals N1 to N8.

The first switching element 911 receives a _n random bit signal as a first input I1, a _n random bit signal as a second input I2, and a third control signal as a selection input S By receiving (EDC_HR), the first logic switching signal N1 may be output. When the third control signal EDC_HR of the selection input S is a logic low, the state of the a _n random bit signal of the first input I1 may be selected and output as the first logic switching signal N1 . When the third control signal EDC_HR of the selection input S is logic high, the state of the a _n random bit signal of the second input I2 may be selected and output as the first logic switching signal N1 . The first switching element 911 may output a _n random bit signal as the first logic switching signal N1 regardless of the logic level of the third control signal EDC_HR.

The second switching element 912 receives a n+64 logic output signal as a first input I1, a _{n+64 logic} output signal as a second input I2, and a select input S A second logic switching signal N2 may be output by receiving the third control signal EDC_HR. When the third control signal EDC_HR of the selection input S is a logic low, the state of the a _n+64 logic output signal of the first input I1 may be selected and output as the second logic switching signal N2 . . When the third control signal EDC_HR of the selection input S is logic high, the state of the a _n+64 logic output signal of the second input I2 may be selected and output as the second logic switching signal N2 . . The second switching element 912 may output a _n+64 logic output signal as the second logic switching signal N2 regardless of the logic level of the third control signal EDC_HR.

The third switching element 913 receives a _n+16 logic output signal as a first input I1, a _n random bit signal as a second input I2, and a third as a selection input S A third logic switching signal N3 may be output by receiving the control signal EDC_HR. When the third control signal EDC_HR of the selection input S is the logic low, the state of the a _n+16 logic output signal of the first input I1 may be selected and output as the second logic switching signal N2 . When the third control signal EDC_HR of the selection input S is logic high, the state of the a _n random bit signal of the second input I2 may be selected and output as the third logic switching signal N3 .

The fourth switching element 914 receives a _n+80 logic output signal as a first input I1, a _n+64 logic output signal as a second input I2, and a select input S A fourth logic switching signal N4 may be output by receiving the third control signal EDC_HR. When the third control signal EDC_HR of the selection input S is a logic low, the state of a _n+80 logic output signal of the first input I1 may be selected and output as the fourth logic switching signal N4 . When the third control signal EDC_HR of the selection input S is logic high, the state of a _n+64 logic output signal of the second input I2 may be selected and output as the fourth logic switching signal N4 . .

The fifth switching element 915 receives a n+32 logic output signal as a first input I1, a _{n+32 logic} output signal as a second input I2, and a selection input S A fifth logic switching signal N5 may be output by receiving the third control signal EDC_HR. When the third control signal EDC_HR of the selection input S is the logic low, the state of the a _n+32 logic output signal of the first input I1 may be selected and output as the fifth logic switching signal N5 . When the third control signal EDC_HR of the selection input S is logic high, the state of a _n+32 logic output signal of the second input I2 may be selected and output as the fifth logic switching signal N5 . The fifth switching element 915 may output a _n+32 logic output signal as the fifth logic switching signal N5 regardless of the logic level of the third control signal EDC_HR.

The sixth switching element 916 receives a n+96 logic output signal as a first input I1, a _{n+96 logic} output signal as a second input I2, and a select input S A sixth logic switching signal N6 may be output by receiving the third control signal EDC_HR. When the third control signal EDC_HR of the selection input S is a logic low, the state of a _n+96 logic output signal of the first input I1 may be selected and output as the sixth logic switching signal N6 . When the third control signal EDC_HR of the selection input S is logic high, the state of a _n+96 logic output signal of the second input I2 may be selected and output as the sixth logic switching signal N6 . . The sixth switching element 916 may output a _n+96 logic output signal as the sixth logic switching signal N6 regardless of the logic level of the third control signal EDC_HR.

The seventh switching element 917 receives a _n+48 logic output signal as a first input I1, a _n+32 logic output signal as a second input I2, and a select input S A seventh logic switching signal N7 may be output by receiving the third control signal EDC_HR. When the third control signal EDC_HR of the selection input S is a logic low, the state of a _n+48 logic output signal of the first input I1 may be selected and output as the seventh logic switching signal N7 . When the third control signal EDC_HR of the selection input S is logic high, the state of the a _n+32 logic output signal of the second input I2 may be selected and output as the seventh logic switching signal N7 .

The eighth switching element 918 receives a _n+112 logic output signal as a first input I1, a _n+96 logic output signal as a second input I2, and a select input S An eighth logic switching signal N8 may be output by receiving the third control signal EDC_HR. When the third control signal EDC_HR of the selection input S is a logic low, the state of a _n+112 logic output signal of the first input I1 may be selected and output as the eighth logic switching signal N8 . When the third control signal EDC_HR of the selection input S is logic high, the state of a _n+96 logic output signal of the second input I2 may be selected and output as the eighth logic switching signal N8. .

Referring to FIG. 9B , when the third control signal EDC_HR is logic low, the first to eighth logic switching signals N1 to N8 output from the logic block 900 show random data patterns. In FIG. 9B, logic output signals (a _n+16 , a _{n +32} , a _n+48 , a _n+64 , a _n+80 , a _{n+ 96} , a _n+112 ) and first to eighth logic switching signals N1 to N8 are shown. Each of the first to eighth logic switching signals N to N8 is a _n , a _n+64 , a _n+16 that is the first input I1 of the first to eighth switching elements 911 to 918 , respectively. , a _n+80 , a _n+32 , a _n+96 , a _n+48 , a _n+112 signals may be generated and provided to the first pattern selector 600 of FIG. 10A .

Referring to FIG. 9C , when the third control signal EDC_HR is logic high, the first to eighth logic switching signals N1 to N8 output from the logic block 900 show random data patterns. In FIG. 9C , logic output signals (a _n+16 , a _{n +32} , a _n+48 , a _n+64 , a _n+80 , a _{n+ 96} , a _n+112 ) and first to eighth logic switching signals N1 to N8 are shown. Each of the first to eighth logic switching signals N to N8 is a _n , a _n+64 , a _n , a which is the second input I2 of the first to eighth switching elements 911 to 918 , respectively. A pattern of _n+64 , a _n+32 , a _n+96 , a _n+32 , a _n+96 signals may be generated and provided to the first pattern selector 600 of FIG. 10A .

10A to 10C are views for explaining the first pattern selector of FIG. 8A . 10A is a circuit diagram of the first pattern selector, FIG. 10B is a timing diagram for explaining the operation of the first pattern selector when the third control signal EDC_HR is logic low, and FIG. 10C is the third control signal EDC_HR This is a timing diagram for explaining the operation of the first pattern selector when is logic high.

Referring to FIG. 10A , the first pattern selector 1000 may receive first to eighth logic switching signals N1 to N8 output from the logic block 900 . The first pattern selector 1000 selects signals selected in response to the first clock signal CKD8 from among the first to eighth logic switching signals N1 to N8 as the pattern signals z ₀ , z ₁ , and z ₂ . , z ₃ ) can be output. The first pattern selector 600 may be implemented as an 8:4 multiplexer including the first to fourth multiplexers 1001 to 1004 .

The first multiplexer 1001 receives a first logic switching signal N1 as a first input I1, a second logic switching signal N2 as a second input I2, and a selection input S may receive the first clock signal CKD8 and output the first pattern signal z ₀ . When the first clock signal CKD8 of the selection input S is logic high, the state of the first logic switching signal N1 of the first input I1 is selected and output as the first pattern signal z ₀ . there is. When the first clock signal CKD8 of the selection input S is logic low, the state of the second logic switching signal N2 of the second input I2 is selected and output as the first pattern signal z ₀ . there is.

The second multiplexer 1002 receives a third logic switching signal N3 as a first input I1, a fourth logic switching signal N4 as a second input I2, and a select input S may receive the first clock signal CKD8 and output the second pattern signal z ₁ . When the first clock signal CKD8 of the selection input S is logic high, the state of the third logic switching signal N3 of the first input I1 is selected and output as the second pattern signal z ₁ . there is. When the first clock signal CKD8 of the selection input S is logic low, the state of the fourth logic switching signal N4 of the second input I2 is selected and output as the second pattern signal z ₁ . there is.

The third multiplexer 1003 receives a fifth logic switching signal N5 as a first input I1, a sixth logic switching signal N6 as a second input I2, and a selection input S may receive the first clock signal CKD8 and output the third pattern signal z ₂ . When the first clock signal CKD8 of the selection input S is logic high, the state of the fifth logic switching signal N5 of the first input I1 is selected and output as the third pattern signal z ₂ . there is. When the first clock signal CKD8 of the selection input S is logic low, the state of the sixth logic switching signal N6 of the second input I2 is selected and output as the third pattern signal z ₂ . there is.

The fourth multiplexer 1004 receives a seventh logic switching signal N7 as a first input I1, an eighth logic switching signal N8 as a second input I2, and a select input S may receive the first clock signal CKD8 and output the fourth pattern signal z ₃ . When the first clock signal CKD8 of the selection input S is logic high, the state of the seventh logic switching signal N7 of the first input I1 is selected and output as the fourth pattern signal z ₃ . there is. When the first clock signal CKD8 of the selection input S is logic low, the state of the eighth logic switching signal N8 of the second input I2 may be selected and output as the fourth pattern signal z ₃ . there is.

Referring to FIG. 10B , when the third control signal EDC_HR is logic low, the first to fourth pattern signals z ₀ , z ₁ , z ₂ , and z ₃ output from the first pattern selector 1000 . ) each shows random data patterns. 10B shows first to fourth pattern signals z ₀ , z ₁ , z ₂ , and z ₃ expressed in the same time domain as the first to eighth logic switching signals N1 to N8 of FIG. 9B .

Referring to FIG. 10C , when the third control signal EDC_HR is logic high, each of the pattern signals z ₀ , z ₁ , z ₂ , and z ₃ output from the first pattern selector 1000 is random. Show data patterns. 10C shows pattern signals z ₀ , z ₁ , z ₂ , and z ₃ in the same time domain as the first to eighth logic switching signals N1 to N8 of FIG. 9C . The pattern signals z ₀ , z ₁ , z ₂ , and z ₃ of FIGS. 10B and 10C may be provided to the second pattern selector 1100 of FIG. 11A .

11A to 11C are views for explaining the second pattern selection unit of FIG. 8A . 11A is a circuit diagram of the second pattern selector, FIG. 11B is a timing diagram illustrating an operation of the second pattern selector when the third control signal EDC_HR is logic low, and FIG. 10C is a third control signal EDC_HR This is a timing diagram illustrating the operation of the second pattern selector when is logic high.

Referring to FIG. 11A , the second pattern selector 1100 receives the pattern signals z ₀ , z ₁ , z ₂ , and z ₃ output from the first pattern selector 1000 , and a third clock signal A pattern signal selected from among the pattern signals z ₀ , z ₁ , z ₂ , and z ₃ may be generated as the detection clock output signal DC in response to the CKDP[0:3]. The second pattern selector 1100 may be implemented as a 4:1 multiplexer.

The second pattern selector 1100 receives a z ₀ pattern signal as a first input I1 , a z ₁ pattern signal as a second input I2 , and a z ₂ pattern signal as a third input I3 . , receives the z ₃ pattern signal as the fourth input I4, and receives the third clock signals CKDP[0:3] as the selection input S to generate the detection clock output signal DC can be printed out. In the second pattern selector 1100 , when the third clock signal CKDP[0] of the selection input S is logic high, the state of the z ₀ pattern signal of the first input I1 is selected to output the detection clock It may be output as a signal DC. When the third clock signal CKDP[1] of the selection input S is logic high, the state of the z ₁ pattern signal of the second input I2 may be selected and output as the detection clock output signal DC. When the third clock signal CKDP[2] of the selection input S is logic high, the state of the z ₂ pattern signal of the third input I3 may be selected and output as the detection clock output signal DC. When the third clock signal CKDP[3] of the selection input S is logic high, the state of the z ₃ pattern signal of the fourth input I4 may be selected and output as the detection clock output signal DC.

Referring to FIG. 11B , when the third control signal EDC_HR is logic low, the detection clock output signal DC output from the second pattern selector 1100 shows random data patterns. 11B shows a detection clock output signal DC represented in the same time domain as the first to fourth pattern signals z ₀ , z ₁ , z ₂ , and z ₃ of FIG. 10B . It can be seen that the random data pattern of the detection clock output signal DC is output at a first rate transitioning in units of 1-bit data.

Referring to FIG. 11C , when the third control signal EDC_HR is logic high, the detection clock output signal DC output from the second pattern selector 1100 shows random data patterns. 11C shows the detection clock output signal DC represented in the same time domain as the first to fourth pattern signals z ₀ , z ₁ , z ₂ , and z ₃ of FIG. 10C . It can be seen that the random data pattern of the detection clock output signal DC is output at a second rate that is half the first rate by shifting in units of 2-bit data.

In the present embodiment, the random data pattern of the detection clock output signal DC generated according to the third control signal EDC_HR by the detection clock pattern generator 122b of FIG. 8A transitions in units of 1-bit data as shown in FIG. 11B . The output is performed at the first rate and is output at a second rate that is 1/2 of the first rate by transitioning in 2-bit data units as shown in FIG. 11C, but the scope of the present invention is not limited thereto, and the second rate is the first rate It can be output variously by 1/2 ⁿ (n is a natural number) times of .

12 and 13 are diagrams illustrating a graphics memory system in which a memory device according to an embodiment of the present invention is mounted.

Referring to FIG. 12 , the graphics memory system 1200 includes a GPU 1210 and a GDDR 1220 . The GPU 1210 includes a CDR unit 112 , and the GDDR 1220 includes a detection clock pattern generation unit 122 . The detected clock pattern generator 122 may include the detected clock pattern generators 122a and 122b described with reference to FIGS. 3A to 11C . The detection clock pattern generator 122 may generate the detection clock output signal DC using a random data pattern. The CDR unit 112 may perform a clock data recovery operation using the detected clock output signal DC transmitted from the GDDR 1220 . The clock data recovery operation may adjust the phase and lock the clock signal so that the edge of the clock signal is in the middle of the received detection clock output signal DC.

The GDDR 1220 may provide error detection of the data DQ in a data access mode by the GPU 1210 in order to improve data reliability of the graphic memory system 1200 . The GDDR 1220 generates a checksum or a cyclic redundancy check (CRC) with respect to the read and write data DQ and transmits it to the GPU 1210. An Error Detection Code Unit 1222: hereinafter “EDC” portion 1222)). Based on the checksum, the GPU 1210 may determine whether there is an error in the transmitted CRC and reissue the read and write commands.

For example, it is assumed that the data access mode of the GDDR 1220 is a read mode as shown in FIG. 13 . 8-bit data corresponding to BL 8 may be output to pins DQ0 to DQ7 when the cast latency CL set in the GDDR 1220 elapses after the read command RD is applied at the time T0. In addition, a data bus inversion signal indicating a data inversion signal of a corresponding burst length may be output to the DBI0# pin. The EDC unit 1222 may calculate 8-bit CRC data (X0 to X7) for 72-bit data including 9 channels including DQ0 to DQ7 pins and DBI0# pins and 8-bit data of each channel. . The EDC unit 1222 may provide the CRC data X0 to X7 to the GPU 1210 through an error detection code pin (EDC: hereinafter referred to as an “EDC pin”) after the read latency CRCRL.

The EDC unit 1222 may include a detected clock pattern generation unit 122 . The EDC unit 1222 outputs the detection clock output signal DC generated by the detection clock pattern generator 122 to the EDC pin EDC in an operation mode other than the data access mode of the GDDR 1220 , for example, in a clocking mode. can do. The detection clock output signal DC may be output as random data patterns through the EDC pin EDC. According to an embodiment, the detection clock pattern generator 122 is not included in the EDC unit 1222 and may exist as a separate circuit block.

14 and 15A to 15C are diagrams illustrating a graphic memory system in which a memory device according to an embodiment of the present invention is mounted.

The graphic memory system 1400 of FIG. 14 is different from the graphic memory system 1200 of FIG. 12 in that the EDC unit 1422 is connected to the first EDC pin EDC0 and the second EDC pin EDC1. , and the rest of the components are almost identical. Hereinafter, differences from FIGS. 12 and 13 will be mainly described.

14 and 15A , the EDC unit 1422 calculates the CRC data X0 to X7 on the data BL0 to BL7 of the first EDC group composed of the DQ0 to DQ7 pins and the DBI0# pin to calculate the second 1 may be provided to the GPU 1410 through the EDC pin EDC0. The EDC unit 1422 calculates the CRC data X0 to X7 with respect to the data BL0 to BL7 of the second EDC group consisting of the DQ8 to DQ15 pins and the DBI1# pin, and the GPU through the second EDC pin EDC1. (1410) can be provided.

The EDC unit 1422 may include a detection clock pattern generation unit 122 . The EDC unit 1422 may output the detection clock output signal DC of the random data patterns generated by the detection clock pattern generation unit 122 to the first and second EDC pins EDC0 and EDC1 in the clocking mode. The detection clock output signal DC output to the first and second EDC pins EDC0 and EDC1 may be the same.

In some embodiments, the detected clock pattern generator 122 may invert the random data pattern of the detected clock output signal DC in response to the fourth control signal EDC_INV provided from the mode register 121 ( FIG. 1 ). there is. As shown in FIG. 15B , the detection clock output signal DC output from the detection clock pattern generator 122 to the first and second EDC pins EDC0 and EDC1 may be inverted random data patterns. . Alternatively, the detection clock output signal DC output from the detection clock pattern generator 122 to the first and second EDC pins EDC0 and EDC1 may be different random data patterns, as shown in FIG. 15C . there is.

16 and 17A to 17D are diagrams for explaining a graphic memory system in which a memory device according to an embodiment of the present invention is mounted.

The graphic memory system 1600 of FIG. 16 is different from the graphic memory system 1400 of FIG. 14 in that the EDC unit 1422 is connected to the first to fourth EDC pins EDC0 to EDC3, The rest of the components are almost identical. Hereinafter, differences from FIGS. 14 and 15A will be mainly described.

Referring to FIGS. 16 and 17A , the EDC unit 1622 calculates the CRC data X0 to X7 on the data BL0 to BL7 of the first EDC group including the DQ0 to DQ7 pins and the DBI0# pin to calculate the second 1 may be provided to the GPU 1610 through the EDC pin EDC0. The EDC unit 1622 calculates the CRC data X0 to X7 with respect to the data BL0 to BL7 of the second EDC group consisting of the DQ8 to DQ15 pins and the DBI1# pin, and the GPU through the second EDC pin EDC1. (1610) can be provided. The EDC unit 1622 calculates the CRC data X0 to X7 with respect to the data BL0 to BL7 of the third EDC group consisting of the DQ16 to DQ23 pins and the DBI2# pin, and the GPU through the third EDC pin EDC2. (1610) can be provided. The EDC unit 1622 calculates the CRC data X0 to X7 with respect to the data BL0 to BL7 of the fourth EDC group consisting of the DQ24 to DQ31 pins and the DBI3# pin, and the GPU through the fourth EDC pin EDC3 (1610) can be provided.

The EDC unit 1622 may include a detected clock pattern generation unit 122 . The EDC unit 1622 may output the detection clock output signal DC of the random data patterns generated by the detection clock pattern generation unit 122 to the first to fourth EDC pins EDC0 to EDC3 in the clocking mode. The detection clock output signal DC output to the first to fourth EDC pins EDC0 to EDC3 may be the same.

In some embodiments, the detected clock pattern generator 122 may invert the random data pattern of the detected clock output signal DC in response to the fourth control signal EDC_INV provided from the mode register 121 ( FIG. 1 ). there is. As shown in FIG. 17B , the detection clock pattern generator 122 generates the detection clock output signal DC output to the first and third EDC pins EDC0 and EDC2 with the same random data pattern, The detection clock output signal DC output to the second EDC pins EDC0 and EDC1 has inverted random data patterns, and the detection clock output signal DC output to the third and fourth EDC pins EDC2 and EDC3 DC) may be output as inverted random data patterns.

According to an embodiment, the detection clock pattern generator 122, as shown in FIG. 17C , outputs the detection clock output signal DC output to the first and third EDC pins EDC0 and EDC2 to different random data. As a pattern, the detection clock output signal DC output to the first and second EDC pins EDC0 and EDC1 is output as inverted random data patterns and to the third and fourth EDC pins EDC2 and EDC3 The detected clock output signal DC may be output as inverted random data patterns.

According to an embodiment, the detection clock pattern generator 122 may convert the detection clock output signal DC output to the first to fourth EDC pins EDC0 to EDC3 to different random data, as shown in FIG. 17D . Patterns can be printed.

18 is a diagram illustrating a data eye pattern when a clock output signal detected of a random data pattern according to the present invention is used for a clock data recovery operation.

Before referring to FIG. 18 , in the data interface between the controller 110 and the memory device 120 described in FIG. 1 , the CDR unit 112 performs a random transmission from the memory device 120 for a clock data recovery operation. The detection clock output signal DC of the data patterns may be used.

Referring to FIG. 18 , a data eye diagram 1820 of a detection clock output signal DC of a random data pattern is shown. The random data eye diagram 1820 is shown as a superposition of a plurality of data transitions representing jitter due to noise, and is provided to the CDR unit 112 (FIG. 1) as a distorted waveform by the environment of the channel through which the data is transmitted. can be

On the other hand, when the detected clock output signal DC is provided as a clock pattern, it can be seen that the eye diagram 1810 of the clock pattern has a symmetrical eye opening area and a maximum eye compared to the random data eye diagram 1820 . The CDR unit 112 may perform a clock data recovery operation by adjusting and locking the phase so that the edge of the clock signal comes to the middle 1811 of the eye diagram 1810 of the clock pattern.

However, in the clock data recovery operation of the CDR unit 112 , the signal for which the phase is actually locked should be data transmitted in real time, not the clock pattern. And, data transmitted in real time will have a random data pattern. When the CDR unit 112 performs a clock data recovery operation using the detected clock output signal DC of the random data pattern, the phase is shifted so that the edge of the clock signal comes to the middle 1821 of the random data eye diagram 1820. can be locked By this phase locking, the CDR unit 112 performs a clock data recovery operation with the CDR locking phase 1821 for actual data. Accordingly, from the standpoint of the CDR unit 112, using the detection clock output signal DC of the random data pattern rather than using the detection clock output signal DC of the clock pattern may be beneficial in reducing the phase offset and reducing the locking time. .

Although the present invention has been described with reference to the embodiment shown in the drawings, which is merely exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

Claims (20)

A memory device comprising:
output pin;
mode register; and
A detection clock output signal including one of a random data pattern and a fixed data pattern is generated in response to a first control signal and a second control signal output from the mode register, and the detection clock output signal is output through the output pin and a detection clock pattern generator, wherein the random data pattern includes pseudo-random data generated by the memory device, the fixed data pattern is a fixed pattern pre-stored in the memory device, and the detection clock output signal is used for the clock data recovery operation,
The detected clock pattern generator outputs the detected clock output signal through the output pin at a first rate or a second rate different from the first rate based on a third control signal output from the mode register. According to claim 1,
The detection clock output signal includes the random data pattern when the first control signal is a first logic level and the second control signal is a second logic level, and the detection clock output signal includes the first control signal The memory device of claim 1, wherein the fixed data pattern is at a second logic level and includes the fixed data pattern when the second control signal is at the first logic level. According to claim 1,
and the second rate is 1/2 ⁿ (n is a natural number greater than or equal to 1) times the first rate. According to claim 1,
The detection clock pattern generator generates an error detection code in response to a fourth control signal output from the mode register, and generates the error detection code at the first rate or the second rate based on the third control signal. and outputted through an output pin, the detection clock output signal is output during a first time period, and the error detection code is output during a second time period after the first time period. 5. The method of claim 4,
and the detected clock pattern generator inverts the detected clock output signal to be output through the output pin in response to a fifth control signal output from the mode register. 6. The method of claim 5,
and the detected clock pattern generator generates a command address signal to be output through the output pin in response to a sixth control signal output from the mode register. 7. The method of claim 6,
The detection clock pattern generator generates a read data strobe signal in response to a seventh control signal output from the mode register, outputs the read data strobe signal through the output pin, and the read data strobe signal is the memory device and used by a device external to the memory device to latch read data output from the memory device. The method of claim 1, wherein the detection clock pattern generator
a pseudo random bit sequence generator for generating a plurality of random bit signals in response to a first clock signal;
a logic block receiving the random bit signals and selectively ORing to generate a plurality of logic output signals;
a first pattern selector receiving one of the random bit signals and the logic output signals as first inputs, and outputting some of the first inputs as a plurality of pattern signals in response to the first clock signal; and
a second pattern selector receiving the plurality of pattern signals as second inputs and outputting one of the second inputs as the detection clock output signal to the output pin in response to a second clock signal;
and a clock cycle of the second clock signal is half a clock cycle of the first clock signal. The method of claim 3, wherein the detection clock pattern generator
a pseudo random bit sequence generator for generating a plurality of random bit signals in response to a first clock signal;
a logic block receiving the random bit signals and generating a plurality of logic switching signals in response to the third control signal;
a first pattern selector that receives one of the logic switching signals as first inputs and outputs some of the first inputs as a plurality of pattern signals in response to the first clock signal; and
a second pattern selector receiving the plurality of pattern signals as second inputs and outputting one of the second inputs as the detection clock output signal to the output pin in response to a second clock signal;
and a clock cycle of the second clock signal is half a clock cycle of the first clock signal. A memory device comprising:
output pin;
mode register; and
During the first mode, training data including a random data pattern is generated in response to a first control signal output from the mode register, and the training data is converted to a first rate or based on a second control signal output from the mode register. and a detection clock pattern generator for outputting through the output pin at a second rate different from the first rate;
the random data pattern includes pseudo-random data generated by the memory device;
The random data pattern is a memory device used for a clock data recovery operation. 11. The method of claim 10,
and the second rate is 1/2 ⁿ (n is a natural number greater than or equal to 1) times the first rate. 11. The method of claim 10,
The detected clock pattern generator generates the training data including a fixed data pattern in response to a second control signal output from the mode register during a second mode, wherein the fixed data pattern is pre-stored in the memory device. A memory device, characterized in that it is a pattern. 12. The method of claim 11,
The detection clock pattern generator generates an error detection code in response to a third control signal output from the mode register, and generates the error detection code at the first rate or the second rate based on the second control signal. The memory device according to claim 1, wherein the output pin is outputted through an output pin, the training data is output during a first time period, and the error detection code is output during a second time period after the first time period. 14. The method of claim 13,
and the detected clock pattern generator inverts the training data to be output through the output pin in response to a fourth control signal output from the mode register. 15. The method of claim 14,
The detection clock pattern generator generates a read data strobe signal in response to a fifth control signal output from the mode register, outputs the read data strobe signal through the output pin, and the read data strobe signal is the memory device and used by a device external to the memory device to latch read data output from the memory device. 11. The method of claim 10, wherein the detection clock pattern generator
a pseudo random bit sequence generator for generating a plurality of random bit signals in response to a first clock signal;
a logic block receiving the random bit signals and selectively ORing to generate a plurality of logic output signals;
a first pattern selector receiving one of the random bit signals and the logic output signals as first inputs, and outputting some of the first inputs as a plurality of pattern signals in response to the first clock signal; and
a second pattern selector receiving the plurality of pattern signals as second inputs and outputting one of the second inputs as the training data to the output pin in response to a second clock signal;
and a clock cycle of the second clock signal is half a clock cycle of the first clock signal. 11. The method of claim 10, wherein the detection clock pattern generator
a pseudo random bit sequence generator for generating a plurality of random bit signals in response to a first clock signal;
a logic block receiving the random bit signals and generating a plurality of logic switching signals in response to the second control signal;
a first pattern selector that receives one of the logic switching signals as first inputs and outputs some of the first inputs as a plurality of pattern signals in response to the first clock signal; and
a second pattern selector receiving the plurality of pattern signals as second inputs and outputting one of the second inputs as the training data to the output pin in response to a second clock signal;
and a clock cycle of the second clock signal is half a clock cycle of the first clock signal. A memory device comprising:
a first error detection code (EDC) pin;
a second EDC pin: and
During the first period, a first detection clock output signal including a first random data pattern is output through the first EDC pin and a second detection clock output signal including a second random data pattern through the second EDC pin output, generate first cyclic redundancy check (CRC) data based on the first data, generate second CRC data based on the second data, and during a second period after the first period, the first EDC and a detection clock pattern generator configured to output the first CRC data through a pin and output the second CRC data through the second EDC pin, wherein the first and second random data patterns are generated by the memory device generated pseudo-random data, wherein the first and second random data patterns are used for a clock data recovery operation;
The detection clock pattern generator generates the first and second detection clock output signals at a first rate or a second rate different from the first rate based on a control signal output from the mode register of the memory device. 2 A memory device that outputs through the EDC pins. 19. The method of claim 18, wherein the memory device,
The memory device further comprising a first group of data input/output pins for transmitting and receiving the first data and a second group of data input/output pins for transmitting and receiving the second data. delete

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