KR20140039948A - Semiconductor memory device and method for generating detecting clock patterns thereof - Google Patents

Abstract

Disclosed is a detection clock pattern generating method of a semiconductor memory device. The detection clock pattern generating method includes the steps of: generating detection clock patterns, which are the same as each other, through a plurality of detection clock output pins when an output selection control signal is in a first state; and generating detection clock patterns, which are different from each other, through the detection clock output pins when the output selection control signal is in a second state which is different from the first state. Thereby, electromagnetic wave noises are minimized or reduced.

Description

Semiconductor memory device and method for generating detecting clock patterns

The present invention relates to the field of semiconductor memory, and more particularly, to a volatile semiconductor memory device and a method for generating a detection clock pattern thereof.

Volatile semiconductor memory devices such as dynamic random access memory (hereinafter referred to as " DRAM ") have been widely adopted as data memory of electronic systems.

For example, a DRAM implemented according to a standard specification of graphics double data rate 5 (hereinafter, referred to as 'GDDR5') may be mounted on a graphics card of an electronic system. Such a GDDR5 DRAM may have EDC pins that output an error detection code (hereinafter 'EDC') to support an error detection and correction function.

In a data access mode in which data is read or data is written, a cyclic redundancy check (CRC) code pattern may be output from the EDC pins to ensure reliability of transmit / receive data.

On the other hand, in an operation mode except the data access mode, for example, a clocking mode, a detection clock pattern such as an EDC hold pattern from the EDC pins provides a clock data recovery (hereinafter, referred to as 'CDR') function to a memory controller or a GPU (or CPU). Can be output for

The present invention has been made in an effort to provide a semiconductor memory device capable of minimizing or reducing electromagnetic noise and a method of generating a detected clock pattern thereof.

According to an aspect of the inventive concept for achieving the above technical problem, a method of generating a detection clock pattern of a semiconductor memory device includes:

Generating the same detection clock patterns through the plurality of detection clock output pins when the output selection control signal is in the first state;

When the output selection control signal is in a second state different from the first state, different detection clock patterns are generated through the plurality of detection clock output pins.

According to an embodiment of the inventive concept, in the second state, a first detection clock pattern is output through the first group detection clock output pins of the plurality of detection clock output pins, and the plurality of detection clock outputs are output. A second detection clock pattern may be output through the second group detection clock output pins of the pins.

According to an embodiment of the inventive concept, the first detection clock pattern may be pseudo random binary pattern signals.

According to an embodiment of the inventive concept, the pseudo random binary pattern signals of the first detection clock pattern may be signals having the same phase with each other or differential signals having the phases opposite to each other.

According to an embodiment of the inventive concept, the second detection clock pattern may be pseudo random binary pattern signals.

According to an embodiment of the inventive concept, the pseudo random binary pattern signals of the second detection clock pattern may be signals having the same phase with each other or differential signals having the phases opposite to each other.

According to an embodiment of the inventive concept, the plurality of detection clock output pins may be error detection code pins.

According to an embodiment of the inventive concept, the different detection clock patterns may be an error detection code hold pattern.

According to an embodiment of the inventive concept, the output selection control signal may be a mode register set signal.

According to an embodiment of the inventive concept, the error detection code hold pattern may be output through the error detection code pins for a clock data recovery function of a graphic processing unit.

According to another aspect of the inventive concept to achieve the above object,

A plurality of detection clock output pins; And

The same detection clock patterns are generated through the plurality of detection clock output pins when the output selection control signal is in a first state, and different detection clocks are generated when the output selection control signal is in a second state different from the first state. And a detection clock pattern generator configured to generate patterns through the plurality of detection clock output pins.

According to an embodiment of the inventive concept, the detection clock pattern generator may include:

In the second state, a first detection clock pattern is output through first group detection clock output pins of the plurality of detection clock output pins, and second group detection clock output pins of the plurality of detection clock output pins are output. May output a second detection clock pattern.

According to an embodiment of the inventive concept, in the case of pseudo random binary pattern signals, the second detection clock pattern may be signals having the same phase or differential signals having opposite phases to each other.

According to an embodiment of the inventive concept, the output selection control signal may be a mode register set signal.

According to an embodiment of the inventive concept, the semiconductor memory device may be disposed as a device unit in a memory module having a plurality of semiconductor memory devices and connected to the graphic processing unit.

According to the exemplary configuration of the present invention, electromagnetic noise is minimized or reduced.

1 is a schematic block diagram of a semiconductor memory device according to the concept of the present invention;
2 is an operation timing diagram of output patterns output from the EDC pin of FIG. 1;
3 is a signal waveform diagram of a general detection clock pattern;
4 is a diagram illustrating that the semiconductor memory device of FIG. 1 is connected to a graphics processing unit in the form of a memory module;
5 is a signal waveform diagram of a detection clock pattern according to an embodiment of the present invention;
6 is a signal waveform diagram of a detection clock pattern according to another embodiment of the present invention;
7 is a block diagram illustrating a specific example of an error detection code output unit shown in FIG. 1;
FIG. 8 is a diagram illustrating a first configuration of a random pattern generator in the EDC pattern generator of FIG. 7;
9 is a diagram illustrating a second configuration of a random pattern generator in the EDC pattern generator of FIG. 7;
FIG. 10 is a table illustrating an output mode setting of a detection clock pattern for each EDC pin group in FIG. 1; FIG.
11 is a block diagram showing an application example of the present invention applied to a graphics card;
12 is a block diagram illustrating an application of the present invention applied to a computing system, and
13 is a diagram showing an example of the present invention mounted on a memory module.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more apparent from the following description of preferred embodiments with reference to the attached drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art, without intention other than to provide an understanding of the present invention.

In this specification, when it is mentioned that some element or lines are connected to a target element block, it also includes a direct connection as well as a meaning indirectly connected to the target element block via some other element.

In addition, the same or similar reference numerals shown in the drawings denote the same or similar components as possible. In some drawings, the connection relationship of elements and lines is shown for an effective explanation of the technical contents, and other elements or circuit blocks may be further provided.

Each embodiment described and illustrated herein may also include complementary embodiments thereof, and details of the basic data access operation for DRAM and the functions of the EDC pins and internal functional circuits are not intended to obscure the subject matter of the present invention. Note that it is not described in detail.

1 is a schematic block diagram of a semiconductor memory device according to the concept of the present invention.

Referring to the drawing, the semiconductor memory device 200 includes an error detection code (EDC) output unit 100 as a detection clock pattern generation unit.

When the semiconductor memory device 200 is a DRAM implemented according to a standard standard of graphics double data rate 5 (hereinafter, referred to as 'GDDR5'), the semiconductor memory device 200 is a graphic of an electronic system. Card or the like. Such a GDDR5 DRAM may have EDC pins that output an error detection code (hereinafter 'EDC') to support an error detection and correction function.

In FIG. 1, the error detection code (EDC) output unit 100 may output an error detection code as a detection clock pattern through the EDC pins EDC0, EDC1, EDC2, and EDC3.

FIG. 2 is an operation timing diagram of output patterns output from the EDC pin of FIG. 1.

In the drawing, the operation timing of the output patterns output from the EDC pin when the read command is applied according to the clock CLK in the semiconductor memory device having the set cascade latency CL is illustrated.

First, in a data access mode in which data is read, a cyclic redundancy check (CRC) code pattern from the EDC pins may be output in an operation period T2 to ensure reliability of transmission / reception data. In the data DQ pin of the semiconductor memory device, the data DATA is output from the time point when the cascade latency CL elapses after the read command RD is applied. In the operation period T2 of FIG. 2, 0,1,2,3,4,5,6,7 are shown to be output through the data DQ pin, which is read from the memory cells by the read command RD. The eight data DATA which have been shown are shown as an example.

On the other hand, in an operation mode except for the data access mode, for example, a clocking mode, a detection clock pattern such as an EDC hold pattern from the EDC pins has a clock data recovery (hereinafter, referred to as 'CDR') function as a memory controller or a GPU (or CPU). ) May be output in the operation periods T1 and T3.

In the clocking mode, a repetitive clocking pattern is continuously output through the EDC pin. In the figure, 0, 1, 2, and 3 are repeatedly outputted, which illustrates the output of a repetitive 4-bit clocking pattern.

As described above, in the clocking mode, the EDC hold pattern is output in the operation sections T1 and T3 through the EDC pin, and in the data access mode, the CRC data CRC DATA is output in the operation section T2 through the EDC pin.

3 is a signal waveform diagram of a general detection clock pattern.

Referring to FIG. 3, EDC hold patterns respectively output through the EDC pins EDC0, EDC1, EDC2, and EDC3 of FIG. 1 are shown in the operation periods T1 and T3 of FIG. 2.

As shown in the figure, it can be seen that the waveform patterns of the EDC hold patterns respectively output through the EDC pins EDC0, EDC1, EDC2, and EDC3 are the same.

The semiconductor memory device of FIG. 1 may be mounted on a memory module and connected to one GPU 300.

In such a case, when the EDC hold patterns are output in the same waveform with each other, electromagnetic noise may increase due to interference between waveform signals. Therefore, a technique for minimizing or reducing electro magnetic interference (EMI) is desired.

In the embodiment of the present invention, a technique for generating a detection clock pattern in which electromagnetic noise may be reduced or minimized even in a connection configuration as shown in FIG. 4 is proposed.

FIG. 4 is a diagram illustrating that the semiconductor memory device of FIG. 1 is connected to a graphics processing unit in the form of a memory module.

Referring to FIG. 4, the GPU 300 is connected to a plurality of semiconductor memory devices 200-1, 200-2, 200-3, and 200-n. The plurality of semiconductor memory devices 200-1, 200-2, 200-3, and 200-n may be mounted on one PCB to form a memory module.

One semiconductor memory device 200-1 may correspond to the semiconductor memory device 200 of FIG. 1. In the case where the semiconductor memory device 200-1 has four EDC pins EDC0, EDC1, EDC2, and EDC3 as in the semiconductor memory device 200 of FIG. 1, k of FIG. 4 may be four. 4 illustrates a configuration in which the plurality of semiconductor memory devices 200-1, 200-2, 200-3, 200-n and the GPU 300 are connected to each other through EDC pins.

In the connection configuration as shown in FIG. 4, the detection clock pattern may be generated as shown in FIG. 5 or 6 to reduce or minimize electromagnetic noise.

5 is a signal waveform diagram of a detection clock pattern according to an exemplary embodiment of the present invention.

Referring to FIG. 5, through the two EDC pins EDC0 and EDC1 corresponding to the first group detection clock output pins among the four EDC pins EDC0, EDC1, EDC2, and EDC3, the same pattern waveform EDC0 and EDC1 may be used. One detection clock pattern is output in the same signal waveform.

In addition, a second detection clock such as pattern waveforms EDC2 and EDC3 is provided through two EDC pins EDC2 and EDC3 corresponding to second group detection clock output pins among the four EDC pins EDC0, EDC1, EDC2 and EDC3. The pattern is output in the same signal waveform.

Here, the first detection clock pattern and the second detection clock pattern are output in different signal waveforms to reduce or minimize electromagnetic noise.

The first detection clock pattern and the second detection clock pattern may be pseudo random binary pattern signals.

As such, when the plurality of detection clock output pins are divided into groups and output different detection clock patterns in the clocking mode as the EDC hold pattern, electromagnetic noise is reduced in response to the divided groups.

6 is a signal waveform diagram of a detection clock pattern according to another exemplary embodiment of the present invention.

Referring to FIG. 6, through the two EDC pins EDC0 and EDC1 corresponding to the first group detection clock output pins among the four EDC pins EDC0, EDC1, EDC2, and EDC3, the same pattern waveform EDC0 and EDC1 may be used. One detection clock pattern is output in the form of a differential signal. That is, the pattern waveforms EDC0, EDC1 are opposite in phase.

In addition, a second detection clock such as pattern waveforms EDC2 and EDC3 is provided through two EDC pins EDC2 and EDC3 corresponding to second group detection clock output pins among the four EDC pins EDC0, EDC1, EDC2 and EDC3. The pattern is output in the form of a differential signal. That is, the pattern waveforms EDC2, EDC3 are opposite in phase.

Here, the first detection clock pattern and the second detection clock pattern are output in different signal waveforms to reduce or minimize electromagnetic noise.

Similarly, the first detection clock pattern and the second detection clock pattern may be pseudo random binary pattern signals.

As such, when the plurality of detection clock output pins are divided into groups and output different detection clock patterns in the form of a differential signal in a clocking mode, a unique detection clock pattern is obtained through each EDC pin, thereby further reducing electromagnetic noise.

Since the detection clock patterns shown in FIGS. 5 and 6 are merely exemplary, the present invention is not limited thereto.

In addition, the output of the detection clock pattern shown in FIGS. 5 and 6 may be controlled by an output selection control signal. For example, when the output selection control signal is in the first state, the same detection clock patterns may be generated or output as shown in FIG. 3. Meanwhile, when the output selection control signal is in a second state different from the first state, different detection clock patterns may be generated or output as shown in FIG. 5 or 6.

Here, the first and second states of the output selection control signal may be determined by a mode register set signal.

Therefore, when the output selection control signal is in the second state, a first detection clock pattern is output through first group detection clock output pins of the plurality of detection clock output pins, and a first one of the plurality of detection clock output pins is output. The second detection clock pattern is output through the two group detection clock output pins, so that electromagnetic noise is reduced or minimized.

In this case, the first detection clock pattern may be signals having the same phase or mutually different signals, and the second detection clock pattern may also be signals having the same phase or opposite to each other. It can be differential signals having a phase of.

Signal waveforms of the detection clock patterns shown in FIGS. 5 and 6 are merely exemplary, and the present invention is not limited thereto.

7 is a block diagram illustrating a specific example of the error detection code output unit of FIG. 1.

Referring to FIG. 7, the error detection code output unit 100 includes a mode register 110 and an EDC pattern generator 120.

The mode register 110 outputs a mode setting control signal according to the logic states of the address signals A0 and A1. The address signals A0 and A1 are set as mode register set signals. For example, when the logic states of the address signals A0 and A1 are given as 1,0, the patterns shown in FIG. 5 are output and given as 1 and 1. 6 may be set to output the patterns shown in FIG. 6.

The EDC pattern generator 120 may output various EDC patterns in response to the mode setting control signal. For example, the simple pattern as shown in FIG. 3, the random pattern as shown in FIG. 5, and the inverted random pattern as shown in FIG. 6 may be selectively output according to the set mode.

FIG. 8 is a diagram illustrating a first configuration of a random pattern generator in the EDC pattern generator of FIG. 7.

Referring to FIG. 8, the plurality of flip-flops D1-D7 and the exclusive OR gate EOR1 may constitute one random pattern generator 122. The plurality of flip-flops D1-D7 form a linear feedback shift register, and the configuration of FIG. 8 generates 2 ⁿ −1 random patterns. Where n is the number of flip-flops used. Therefore, in the case of FIG. 8, 127 pseudo-random binary patterns according to the generated polynomial X ⁷ + X + 1 are generated.

At the output terminal of the flip-flop D7 constituting the random pattern generator 122, a first detection clock pattern such as the pattern waveforms EDC0 and EDC1 in FIG. 5 may be obtained.

FIG. 9 is a diagram illustrating a second configuration of a random pattern generator in the EDC pattern generator of FIG. 7.

Referring to FIG. 9, the plurality of flip-flops D1-D7 and the exclusive OR gate EOR1 may constitute another random pattern generator 124. The plurality of flip-flops D1-D7 form a linear feedback shift register and generate 2 ⁿ −1 random patterns of the configuration of FIG. 9. Where n is the number of flip-flops used. Therefore, in the case of FIG. 9, 127 pseudo random binary patterns are generated according to the generated polynomial X ⁷ + X ⁶ +1. The reason why the generation polynomial is different in comparison with FIG. 8 is that the tap end of the exclusive OR gate EOR1 is connected between the flip-flop D1 and the flip-flop D2.

At the output terminal of the flip-flop D7 constituting the random pattern generator 124, a second detection clock pattern such as the pattern waveforms EDC2 and EDC3 in FIG. 5 may be obtained.

FIG. 10 is a table exemplarily illustrating an output mode setting of a detection clock pattern for each EDC pin group in FIG. 1.

Referring to FIG. 10, four EDC pins EDC0, EDC1, EDC2, and EDC3 are divided into two groups, and an example of a configuration table for outputting an inverted random pattern as shown in FIG. 6 is illustrated.

In FIG. 10, the EDC pin EDC0 of the two EDC pins EDC0 and EDC1 belonging to the first group detection clock output pins is set to the first mode, and the EDC pin EDC1 is set to the inverting first mode. Lose. Accordingly, the first detection clock pattern such as the pattern waveforms EDC0, EDC1 in FIG. 6 is output in the form of a differential signal.

Also, it is shown that the EDC pin EDC2 is set to the second mode and the EDC pin EDC3 is set to the inverting second mode among the two EDC pins EDC2 and EDC3 belonging to the second group detection clock output pins. Accordingly, the second detection clock patterns such as the pattern waveforms EDC2, EDC3 in FIG. 6 are output in the form of differential signals.

11 is a block diagram showing an application example of the present invention applied to a graphics card.

Referring to FIG. 11, the graphics card 500 includes a GDDR5 210 and a GPU 300. Since the GDDR5 210 is configured with the semiconductor memory device as shown in FIG. 1, electromagnetic noise in the graphic card is reduced or minimized.

For reference, the GDDR5 210 refers to graphics double data rate version 5. The GDDR5 210 may have a capacity of 1 GB, a memory interface of 128 bits, a bandwidth of 86.4 GB / s, and a clock of 5400 (1350) MHz. In addition, the GPU 300 may be Nvidia's "Geforce" series and AMD's "Radeon" series. Intel's GPUs can also be used.

Chips constituting the graphics card 500 may be mounted using various types of packages. For example, the chip can be used as a package in package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC), plastic dual in- Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC) ), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) and Wafer-Level Processed Stack Package Can be packaged as a package.

12 is a block diagram illustrating an application of the present invention as applied to a computing system.

Referring to FIG. 12, the computing system 1000 includes the graphics card 500 of FIG. 11. Since the computing system 1000 employs the graphic card 500 of FIG. 11, EMI of the system is reduced.

The computing system 1000 may include a central processing unit (CPU), a user interface (UI), a memory control unit, and a memory module in addition to the graphic card 500.

The computing system 1000 may employ Window 8 (64Bit) as an OS, for example, the CPU uses Core ™ i5-3470T (2.9GHz), the memory module uses 8GB DDR3 (4G X 2), The HDD can mount 1TB (SATA2).

In addition, the computing system 1000 may, for example, mount the graphics card 500 as AMD Radeon ™ HD7690M GDDR5 1GB.

If the configuration of the computing system 1000 is merely exemplary, the present invention is not limited thereto.

The semiconductor memory constituting the memory module may include a memory cell array. The memory cell array may include a normal cell block having normal memory cells connected to normal word lines, and a spare cell block having redundancy memory cells connected to spare word lines. The unit memory cell of the normal memory cell block and the redundancy memory cell block may be a DRAM memory cell including one access transistor and one storage capacitor. The normal cell block and the spare cell block may include a plurality of memory cells in a matrix of rows and columns.

The computing system 1000 may connect a separate interface to an external communication device. The communication device may be a digital versatile disc (DVD) player, a computer, a set top box (STB), a game machine, a digital camcorder, or the like.

Although not shown in the drawings, when the computing system 1000 is configured to be a mobile device, the mobile device further includes an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. It can be provided to those skilled in the art that it can be provided.

The computing system 1000 may include an SSD including nonvolatile storage for storing a large amount of data.

The non-volatile storage may store data information having various data types such as text, graphics, software codes, and the like.

The nonvolatile storage may include, for example, an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic RAM, a spin transfer torque MRAM, a conductive bridging RAM CBRAM), FeRAM (Ferroelectric RAM), PRAM (Phase Change RAM), OBR (Ovonic Unified Memory), Resistive RAM (RRAM or ReRAM), Nanotube RRAM, Polymer RAM ), A nano floating gate memory (NFGM), a holographic memory, a molecular electronic memory device, or an insulator resistance change memory .

13 is a diagram illustrating an example of the present invention mounted in a memory module.

Referring to FIG. 13, the memory module 2000 may include a plurality of memory chips 210 and a plurality of external terminals 230. Each of the plurality of memory chips 210 may be implemented with the semiconductor memory device 200 described above. The external terminal 230 may receive a control signal, an address signal, and data from the computing system and transmit the received control signal, address signal, and data to the memory module 2000. In addition, the external terminal 230 may transfer data stored in memory cells of each memory chip 210 to a display element of the computing system.

In the case of FIG. 13, since the memory module 2000 includes the memory chip 210 as shown in FIG. 1, EMI generated in the memory module is reduced or minimized.

As described above, an optimal embodiment has been disclosed in the drawings and specification. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. For example, in other cases, it may be possible to variously change the shape of the detection clock patterns of FIG. 5 or 6 without departing from the technical spirit of the present invention.

Description of the Related Art [0002]
100: error detection code output unit
110: mode register
120: EDC pattern generator
200: semiconductor memory device

Claims (10)

Generating the same detection clock patterns through the plurality of detection clock output pins when the output selection control signal is in the first state;
And generating different detection clock patterns through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.
The method of claim 1, wherein in the second state, a first detection clock pattern is output through a first group detection clock output pins of the plurality of detection clock output pins, and a second group of the plurality of detection clock output pins is provided. A detection clock pattern generation method of a semiconductor memory device outputting a second detection clock pattern through the detection clock output pins.
The method of claim 2, wherein the first detection clock patterns are pseudo random binary pattern signals.
The method of claim 3, wherein the pseudo random binary pattern signals of the first detection clock pattern are signals having the same phase or are differential signals having opposite phases to each other.
The method of claim 2, wherein the second detection clock pattern comprises pseudo random binary pattern signals.
The method of claim 5, wherein the pseudo random binary pattern signals of the second detection clock pattern are signals having the same phase or are differential signals having opposite phases to each other.
A plurality of detection clock output pins; And
The same detection clock patterns are generated through the plurality of detection clock output pins when the output selection control signal is in a first state, and different detection clocks are generated when the output selection control signal is in a second state different from the first state. And a detection clock pattern generator configured to generate patterns through the plurality of detection clock output pins.
The method of claim 7, wherein the detection clock pattern generation unit,
In the second state, a first detection clock pattern is output through first group detection clock output pins of the plurality of detection clock output pins, and second group detection clock output pins of the plurality of detection clock output pins are output. The semiconductor memory device outputs a second detection clock pattern.
8. The semiconductor memory device of claim 7, wherein the second detection clock pattern is a signal having the same phase as each other or differential signals having a phase opposite to each other when the pseudo random binary pattern signals are generated.
8. The semiconductor memory device of claim 7, wherein the output selection control signal is a mode register set signal.

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