KR102383040B1 - 홈 에이전트 기반 캐시 전송 가속 기법 - Google Patents

홈 에이전트 기반 캐시 전송 가속 기법 Download PDF

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KR102383040B1
KR102383040B1 KR1020207020385A KR20207020385A KR102383040B1 KR 102383040 B1 KR102383040 B1 KR 102383040B1 KR 1020207020385 A KR1020207020385 A KR 1020207020385A KR 20207020385 A KR20207020385 A KR 20207020385A KR 102383040 B1 KR102383040 B1 KR 102383040B1
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probe
cache
early
entry
processing node
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KR20200096975A (ko
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아밋 피. 압테
가네쉬 발라크리쉬난
비드햐나단 칼야나순드하람
케빈 엠. 리팍
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/082—Associative directories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0824—Distributed directories, e.g. linked lists of caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0826—Limited pointers directories; State-only directories without pointers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/507—Control mechanisms for virtual memory, cache or TLB using speculative control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020207020385A 2017-12-15 2018-09-19 홈 에이전트 기반 캐시 전송 가속 기법 Active KR102383040B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/844,215 2017-12-15
US15/844,215 US10776282B2 (en) 2017-12-15 2017-12-15 Home agent based cache transfer acceleration scheme
PCT/US2018/051756 WO2019118037A1 (en) 2017-12-15 2018-09-19 Home agent based cache transfer acceleration scheme

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KR20200096975A KR20200096975A (ko) 2020-08-14
KR102383040B1 true KR102383040B1 (ko) 2022-04-08

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US (2) US10776282B2 (enExample)
EP (2) EP3724772B1 (enExample)
JP (1) JP6975335B2 (enExample)
KR (1) KR102383040B1 (enExample)
CN (1) CN111656332B (enExample)
WO (1) WO2019118037A1 (enExample)

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Publication number Priority date Publication date Assignee Title
US10776282B2 (en) 2017-12-15 2020-09-15 Advanced Micro Devices, Inc. Home agent based cache transfer acceleration scheme
US11210248B2 (en) * 2019-12-20 2021-12-28 Advanced Micro Devices, Inc. System direct memory access engine offload
US11874783B2 (en) * 2021-12-21 2024-01-16 Advanced Micro Devices, Inc. Coherent block read fulfillment
US20250240156A1 (en) * 2022-12-23 2025-07-24 Advanced Micro Devices, Inc. Systems and methods relating to confidential computing key mixing hazard management
CN117651021B (zh) * 2024-01-25 2024-04-30 苏州萨沙迈半导体有限公司 过滤器及其控制方法和装置、电气设备

Citations (3)

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US20020087811A1 (en) 2000-12-28 2002-07-04 Manoj Khare Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
US20090327616A1 (en) 2008-06-30 2009-12-31 Patrick Conway Snoop filtering mechanism
US20170177484A1 (en) 2015-12-22 2017-06-22 Advanced Micro Devices, Inc. Region probe filter for distributed memory system

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US6055610A (en) * 1997-08-25 2000-04-25 Hewlett-Packard Company Distributed memory multiprocessor computer system with directory based cache coherency with ambiguous mapping of cached data to main-memory locations
US6631401B1 (en) 1998-12-21 2003-10-07 Advanced Micro Devices, Inc. Flexible probe/probe response routing for maintaining coherency
US7395375B2 (en) * 2004-11-08 2008-07-01 International Business Machines Corporation Prefetch miss indicator for cache coherence directory misses on external caches
JP5103396B2 (ja) 2005-08-23 2012-12-19 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド コンピュータシステムにおいて能動的に同期をとる方法
JP5136652B2 (ja) * 2008-11-10 2013-02-06 富士通株式会社 情報処理装置及びメモリ制御装置
US9081706B2 (en) * 2012-05-10 2015-07-14 Oracle International Corporation Using a shared last-level TLB to reduce address-translation latency
US9405687B2 (en) * 2013-11-04 2016-08-02 Intel Corporation Method, apparatus and system for handling cache misses in a processor
US9639470B2 (en) * 2014-08-26 2017-05-02 Arm Limited Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuit
DE102015115582A1 (de) 2014-10-22 2016-04-28 Imagination Technologies Limited Vorrichtung und Verfahren zum Drosseln des Hardwarevorauslesens
CN104331377B (zh) 2014-11-12 2018-06-26 浪潮(北京)电子信息产业有限公司 一种多核处理器系统的目录缓存管理方法
US11237965B2 (en) * 2014-12-31 2022-02-01 Arteris, Inc. Configurable snoop filters for cache coherent systems
US9817760B2 (en) * 2016-03-07 2017-11-14 Qualcomm Incorporated Self-healing coarse-grained snoop filter
US11061572B2 (en) * 2016-04-22 2021-07-13 Advanced Micro Devices, Inc. Memory object tagged memory monitoring method and system
US10776282B2 (en) 2017-12-15 2020-09-15 Advanced Micro Devices, Inc. Home agent based cache transfer acceleration scheme

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
US20020087811A1 (en) 2000-12-28 2002-07-04 Manoj Khare Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
US20090327616A1 (en) 2008-06-30 2009-12-31 Patrick Conway Snoop filtering mechanism
US20170177484A1 (en) 2015-12-22 2017-06-22 Advanced Micro Devices, Inc. Region probe filter for distributed memory system

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Publication number Publication date
US10776282B2 (en) 2020-09-15
US20190188155A1 (en) 2019-06-20
JP2021507371A (ja) 2021-02-22
CN111656332A (zh) 2020-09-11
CN111656332B (zh) 2024-08-27
JP6975335B2 (ja) 2021-12-01
WO2019118037A1 (en) 2019-06-20
EP3724772B1 (en) 2021-10-27
US20210064545A1 (en) 2021-03-04
EP3724772A1 (en) 2020-10-21
US11782848B2 (en) 2023-10-10
KR20200096975A (ko) 2020-08-14
EP3961409A1 (en) 2022-03-02
EP3961409B1 (en) 2024-04-10

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