KR102378251B1 - Pwm control method for improving dynamic false contour of display - Google Patents

Abstract

In accordance with the present invention, disclosed are a display device capable of improving a dynamic false contour and a control method thereof. In accordance with the present invention, the display device includes: a display panel including M x N pixel driving circuits; a data driving circuit outputting signals related with the driving of a plurality of light emitting elements included in each of the pixel driving circuits through a plurality of data lines connected with each of the pixel driving circuits; a gray clock driving circuit outputting a plurality of width-modulated pulses for a light emission time set in one frame to the pixel driving circuits through a plurality of gray clock lines connected with each of the pixel driving circuits; and a control part outputting a control signal so as to execute the operation of the data driving circuit and the gray clock driving circuit. The control part can include: a data output part changing a sequence of image data outputted from the data driving circuit; and a scheduler changing a sequence of pulses outputted from the gray clock driving circuit.

Description

PWM CONTROL METHOD FOR IMPROVING DYNAMIC FALSE CONTOUR OF DISPLAY

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to displays, and more particularly, to control of pulse width modulation.

The content described in this section merely provides background information for the embodiments described herein and does not necessarily constitute prior art.

An active matrix liquid crystal display maintains a state of emitting light while information of all other pixels is updated. In the case of a digital method including a memory in a pixel, data related to the light to be output by the pixel is stored for one row horizontal frequency (Horizontal time), and the brightness is controlled by PWM (Pulse Width Modulation) method. In general, when three or four light emitting devices (eg, LEDs) are included in one pixel, each light emitting device is called a sub-pixel.

1 is a digital PWM driving circuit diagram of a typical sub-pixel.

Referring to FIG. 1 , a driving circuit diagram of a sub-pixel may be identified. In the case of a digital PWM driving type pixel, image data is stored in the pixel memory for a predetermined time (pixel data programming). And, according to the image data stored in the pixel memory, the sub-pixels emit light for an on duty set by the user within one frame. At this time, the brightness of the sub-pixel is controlled by the PWM method. A gray clock signal, which is a light emission gradation signal for PWM control, is input to a driving circuit of a sub-pixel as illustrated in FIG. 1 . The number of gray clock signals (MSB, MSB-1, MSB-2, ......, LSB) is determined according to the number of bits of image data.

2 is a reference diagram for output timing of a gray clock signal during one frame.

Referring to FIG. 2 , a gray clock signal is sequentially output to sub-pixels arranged in a row direction of a display panel. Each gray clock signal is a combination of a plurality of pulse width modulated signals, and the pulse widths of each signal differ by a multiple of 2. In general, the gray clock signal is output from the signal corresponding to the MSB of the image data and sequentially input to the sub-pixels so that the signal corresponding to the LSB of the image data is output last.

3 is an exemplary diagram in which pseudo-contour image quality distortion occurs.

Referring to FIG. 3 , when the image data is 6 bits, it can be confirmed that the gradation is 31 and 32. In general, the gray clock signal may be output from a signal corresponding to the MSB of the image data, and a signal corresponding to the LSB of the image data may be output last. Accordingly, in case of gray level 32, the LED emits light while the pulse width corresponding to the MSB is input (PWM 5), and the LED does not emit light during the remaining time (PWM4 to PWM0). On the other hand, in case of gray level 31, the LED does not emit light while the pulse width corresponding to the MSB is input (PWM 5), and the LED emits light during the remaining time period (PWM4 to PWM0).

The problem is that when pixels corresponding to grayscale 32 and grayscale 31 are adjacent to each other, the difference in time difference between the two pixels when the LED is emitted is large, which causes display distortion that viewers perceive as 0 or 64 instead of halftone. That is, DYNAMIC FALSE CONTOUR may occur.

Republic of Korea Patent Publication No. 10-2017-0111788

An object of the present specification is to provide a display apparatus capable of improving distortion of pseudo-contour image quality and a method for controlling the same.

The present specification is not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to the present specification for solving the above problems includes: a display panel including M x N pixel driving circuits; a data driving circuit for outputting signals related to driving of a plurality of light emitting devices included in each pixel driving circuit through a plurality of data lines connected to each pixel driving circuit; and a gray clock driving circuit for outputting, to the pixel driving circuits, a plurality of width-modulated pulses at a light emission time set within one frame through a plurality of gray clock lines connected to each pixel driving circuit; a control unit for outputting a control signal to execute the operations of the data driving circuit and the gray clock driving circuit, wherein the control unit includes: a data output unit for changing the order of image data output from the data driving circuit; and a scheduler for changing the order of pulses output from the gray clock driving circuit.

According to an embodiment of the present specification, the data output unit controls the data driving circuit to output the most significant bit of the image data in the first frame group and output the image data from the least significant bit in the second frame group, The scheduler may control the gray clock driving circuit to output a pulse having a longest width in a first frame group and output a pulse having a smallest width in a second frame group.

According to another embodiment of the present specification, the data output unit causes the data driving circuit to output the most significant bit of the image data to the pixel driving circuit included in the first group row in the first frame group, and the image data in the second frame group. Control to output the data from the least significant bit, control the pixel driving circuit included in the second group row to output the image data from the least significant bit in the first frame group, and output the image data from the most significant bit in the second frame group and the scheduler causes the gray clock driving circuit to output the longest pulse in the first frame group to the pixel driving circuit included in the row of the first group and output the pulse with the smallest width in the second frame group. control, and to output the pulse with the smallest width in the first frame group to the pixel driving circuit included in the row of the second group, and output the pulse with the longest width in the second frame group.

A method for controlling a display device according to the present specification for solving the above-described problems includes a data driving circuit for outputting a signal related to driving of light emitting devices to a pixel driving circuit, and outputting a width-modulated pulse to the pixel driving circuits. A control method for a display device comprising: a gray clock driving circuit; and a control unit outputting a control signal to execute the operations of the data driving circuit and the gray clock driving circuit, wherein the control unit includes (a) a first frame group, controlling the data driving circuit to output the most significant bit of the image data and outputting the gray clock driving circuit from the longest pulse; and (b) controlling the data driving circuit to output the image data from the least significant bit in the second frame group, and controlling the gray clock driving circuit to output the pulse with the smallest width. can

A method for controlling a display device according to the present specification for solving the above-described problems includes a data driving circuit for outputting a signal related to driving of light emitting devices to a pixel driving circuit, and outputting a width-modulated pulse to the pixel driving circuits. A control method for a display device comprising: a gray clock driving circuit; and a control unit outputting a control signal to execute the operations of the data driving circuit and the gray clock driving circuit, wherein the control unit includes (a) a first frame group, the data driving circuit causes the pixel driving circuit included in the first group row to output from the most significant bit of the image data and the pixel driving circuit included in the second group row to output from the least significant bit of the image data, and the gray clock driving circuit controlling the row to output the longest pulse to the pixel driving circuit included in the first group row and outputting the smallest pulse to the pixel driving circuit included in the second group row; and (b) in the second frame group, the data driving circuit causes the pixel driving circuit included in the first group row to output the least significant bit of the image data, and transmits the image data to the pixel driving circuit included in the second group row. output from the most significant bit, the gray clock driving circuit outputs the smallest pulse to the pixel driving circuit included in the first group row, and starting from the largest pulse to the pixel driving circuit included in the second group row The step of controlling to output; can be repeated.

The method for controlling a display device according to the present specification may be implemented in the form of a computer program written to perform each step in a computer and recorded in a computer-readable recording medium.

Other specific details of the invention are included in the detailed description and drawings.

According to the present specification, it is possible to improve the pseudo contour image quality distortion.

Effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a driving circuit diagram of a typical sub-pixel.
2 is a reference diagram for output timing of a gray clock signal during one frame.
3 is an exemplary diagram in which pseudo-contour image quality distortion occurs.
4 is a display device including a plurality of pixel circuits according to the present specification.
5 is an exemplary embodiment in which an output order is changed between frames.
6 is an exemplary embodiment in which an output order is changed between rows within a frame.

Advantages and features of the invention disclosed herein, and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but may be implemented in various different forms, and only the present embodiments allow the disclosure of the present specification to be complete, and those of ordinary skill in the art to which this specification belongs. It is provided to fully inform those skilled in the art (hereinafter, 'those skilled in the art') the scope of the present specification, and the scope of the present specification is only defined by the scope of the claims.

The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the scope of the present specification. In this specification, the singular also includes the plural unless otherwise specified in the phrase. As used herein, “comprises” and/or “comprising” does not exclude the presence or addition of one or more other components in addition to the stated components. Like reference numerals refer to like elements throughout, and "and/or" includes each and every combination of one or more of the recited elements. Although "first", "second", etc. are used to describe various elements, these elements are not limited by these terms, of course. These terms are only used to distinguish one component from another. Accordingly, it goes without saying that the first component mentioned below may be the second component within the spirit of the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein will have the meaning commonly understood by those of ordinary skill in the art to which this specification belongs. In addition, terms defined in a commonly used dictionary are not to be interpreted ideally or excessively unless specifically defined explicitly. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a display device including a plurality of pixel circuits according to the present specification.

Referring to FIG. 4 , the display device 100 according to the present specification includes a display panel 110 , a scan driving circuit 120 , a data driving circuit 130 , a gray clock driving circuit 150 , and a control unit 150 . can do.

The display panel 110 may include a plurality of pixels (PX) according to the present specification. M x N (M and N are natural numbers) of the plurality of pixels PX may be arranged in a matrix form. However, the pattern in which the plurality of pixels are arranged may be arranged in various patterns according to embodiments, such as a zigzag type.

The display panel 110 is a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, an active-matrix OLED (AMOLED) display, an electrochromic display (ECD), a digital mirror device (DMD), It can be implemented as one of AMD (Actuated Mirror Device), GLV (Grating Light Valve), PDP (Plasma Display Panel), ELD (Electro Luminescent Display), VFD (Vacuum Fluorescent Display), and other types of flat panel display or flexible display It may be implemented as a display. In this specification, the LED display panel will be described as an example.

Each pixel PX may include a plurality of light emitting devices. The light emitting device may be a light emitting diode (LED). The light emitting diode may be a micro LED having a size of 80 μm or less. One pixel PX may output various colors through a plurality of light emitting devices having different colors. For example, one pixel PX may include a light emitting device composed of red, green, and blue colors. As another example, if a white light emitting device may be further included, the white light emitting device may replace any one of the red, green, and blue light emitting devices. Each light emitting element included in one pixel PX is called a 'sub pixel'.

Each pixel PX may include a pixel driving circuit for driving a plurality of sub-pixels. In the pixel driving circuit, a sub-pixel may be turned on or off by a signal output from the scan driving circuit 120 and/or the data driving circuit 130 . The pixel driving circuit may include at least one thin film transistor and at least one capacitor. The pixel driving circuit may be implemented by a stacked structure on a semiconductor wafer.

The display panel 110 includes scan lines SL ₁ to SL _M arranged in a row direction, gray clock lines GC ₁ to GC _M arranged in a row direction, and a column direction. It may include data lines DL ₁ to DL _N arranged as . Pixels PX may be positioned at intersections of the scan lines SL ₁ to SL _m and the data lines DL ₁ to DL _n . Each pixel PX may be connected to any one scan line SL _k and any one data line DL _k . The scan lines SL ₁ to SL _m are connected to the scan driving circuit 120 , the data lines DL ₁ to DL _n are connected to the data driving circuit 130 , and the gray clock line (GC ₁ to GC _M ) may be connected to the gray clock driving circuit 150 .

The scan driving circuit 120 may drive pixels connected to any one of the scan lines SL ₁ to SL _m . Preferably, in the scan driving circuit 120 , the scan lines SL ₁ to SL _m may be sequentially selected. For example, pixels connected to the first scan line SL ₁ may be driven during the first scan driving period, and pixels connected to the second scan line SL ₂ may be driven during the second scan driving period. The operation of the scan driving circuit 120 according to the present specification will be described in more detail later.

The data driving circuit 130 may output image data to each pixel through the data lines DL ₁ to DL _n . The image data may be output in the form of a signal related to a gradation to be expressed by pixels during one frame. Although one data line is connected to a plurality of pixels in the longitudinal direction, a signal related to image data may be input only to pixels connected to the scan line selected by the scan driving circuit 120 . The operation of the data driving circuit 130 according to the present specification will be described in more detail later.

The gray clock driving circuit 150 may output a gray clock signal to the pixels through the gray clock lines GC ₁ to GC _M . The gray clock signal can be composed of a plurality of pulse width modulated signals (Pulse Width Modulator, PWM), and the number of PWM signals (MSB, MSB-1, MSB-2, ......, LSB) is an image It may be determined according to the number of bits of data. The gray clock driving circuit 150 may output a gray clock signal for a set emission time within one frame.

The control unit 150 may output a control signal to execute the operations of the scan driving circuit 120 , the data driving circuit 130 and the gray clock driving circuit 150 . The control unit 150 may output a control signal corresponding to image data corresponding to one image frame to the scan driving circuit 120 , the data driving circuit 130 , and the gray clock driving circuit 150 , respectively.

The control unit 150 according to the present specification may include a data output unit 151 and a scheduler 152 .

The data output unit 151 may change the order of image data output from the data driving circuit 130 . Changing the order of image data means whether image data consisting of n bits are output in the order of [MSB, MSB-1, MSB-2, ..., LSB+1, LSB], [LSB, LSB+ 1, LSB+2, ..., MSB-1, MSB] means to change whether to output in the order.

The scheduler 152 may change the order of the pulses output from the gray clock driving circuit 140 . Changing the order of the pulses means whether the width of the pulses corresponding to n bits in the image data is output in the order [2 ⁿ , 2 ^n-1 , 2 ^n-2 , ..., 2 ¹ , 2 ⁰ ], [2 ⁰ , 2 ¹ , 2 ² , ... 2 ^n-1 , 2 ⁿ ] means to change whether to output in the order.

According to an embodiment of the present specification, the output order may be changed from frame to frame.

In this case, the data output unit 151 may control the data driving circuit 130 to output the most significant bit of the image data in the first frame group and output the image data from the least significant bit in the second frame group. there is.

In addition, the scheduler 152 may control the gray clock driving circuit 140 to output a pulse having the longest width in the first frame group and output a pulse having the smallest width in the second frame group.

5 is an exemplary embodiment in which an output order is changed between frames.

Referring to FIG. 5 , when the image data is 6 bits, the PWM signal output order can be checked. In the embodiment shown in FIG. 5 , the first frame group is an odd numbered frame, and the second frame group is an even numbered frame. In an odd frame, the signal corresponding to the MSB is output first, and the signal corresponding to the LSB is output last. In an even frame, the signal corresponding to the LSB is output first, and the signal corresponding to the MSB is output last.

According to another embodiment of the present specification, the output order is changed between frames, but the output order may also be changed between rows and rows within a frame.

In this case, the data output unit 151 causes the data driving circuit 130 to output the most significant bit of the image data in the first frame group to the pixel driving circuit included in the first group row, and in the second frame group control to output the image data from the least significant bit, to the pixel driving circuit included in the second group row to output the image data from the least significant bit in the first frame group, and to output the image data from the most significant bit to the second frame group can be controlled

In addition, the scheduler 152 causes the gray clock driving circuit 140 to output the longest pulse in the first frame group to the pixel driving circuit included in the first group row, and in the second frame group, the width increases. Control to output the smallest pulse first, and control the pixel driving circuit included in the row of the second group to output the pulse with the smallest width in the first frame group, and to output the pulse with the longest width in the second frame group. can

6 is an exemplary embodiment in which an output order is changed between rows within a frame.

Referring to FIG. 6 , it can be seen that, in an odd-numbered frame, a signal corresponding to the MSB is output first in an odd-numbered row, and a signal corresponding to an LSB is output in an even-numbered row first. In addition, it can be seen that in an even frame, a signal corresponding to the LSB is output first in an odd row, and a signal corresponding to the MSB is output in an even row first.

Meanwhile, although an example in which the relationship between the first frame group and the second frame group is set to an even frame and an odd frame is presented in FIGS. 5 and 6 , the present specification is not limited thereto. Each of the first frame group and the second frame group may be a group in which two, three, four, or the like, frames are bundled together. In addition, although an example in which the relationship between the first group row and the second group row is set to an odd row and an even row is similarly provided, the present specification is not limited to the above example. The first group row and the second group row may be a group in which two, three, four, or the like, rows are grouped together.

As described above, through the control of changing the output sequence of the image data and the output sequence of the PWM signal corresponding thereto, the average value of the difference in the light emission time of the LEDs at grayscales 32 and 31 becomes the same. Through this, it is possible to improve the pseudo-contour image quality distortion (DFC) caused by the disparity in the LED emission time between adjacent grayscales. Meanwhile, although an embodiment in which the size of the image data is 6 bits has been presented for convenience of description, it is obvious that the size of the image data may vary.

The above-described computer program is C/C++, C#, JAVA that can be read by a processor (CPU) of the computer through a device interface of the computer in order for the computer to read the program and execute the methods implemented as a program , Python, may include code coded in a computer language such as machine language. Such code may include functional code related to a function defining functions necessary for executing the methods, etc., and includes an execution procedure related control code necessary for the processor of the computer to execute the functions according to a predetermined procedure. can do. In addition, the code may further include additional information necessary for the processor of the computer to execute the functions or code related to memory reference for which location (address address) in the internal or external memory of the computer to be referenced. there is. In addition, when the processor of the computer needs to communicate with any other computer or server located remotely in order to execute the above functions, the code uses the communication module of the computer to determine how to communicate with any other computer or server remotely. It may further include a communication-related code for whether to communicate and what information or media to transmit and receive during communication.

The storage medium is not a medium that stores data for a short moment, such as a register, a cache, a memory, etc., but a medium that stores data semi-permanently and can be read by a device. Specifically, examples of the storage medium include, but are not limited to, ROM, RAM, CD-ROM, magnetic tape, floppy disk, and optical data storage device. That is, the program may be stored in various recording media on various servers accessible by the computer or in various recording media on the computer of the user. In addition, the medium may be distributed in a computer system connected to a network, and a computer-readable code may be stored in a distributed manner.

As mentioned above, although the embodiments of the present specification have been described with reference to the accompanying drawings, those skilled in the art to which this specification belongs can realize that the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. you will be able to understand Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: display device
110: display panel 120: scan driving circuit
130: data driving circuit 140: gray clock driving circuit
150: control unit

Claims (6)

a display panel including M x N pixel driving circuits;
a data driving circuit for outputting signals related to driving of a plurality of light emitting devices included in each pixel driving circuit through a plurality of data lines connected to each pixel driving circuit; and
a gray clock driving circuit for outputting a plurality of width-modulated pulses to the pixel driving circuits through a plurality of gray clock lines connected to each pixel driving circuit for a light emission time set within one frame;
A display device comprising: a control unit outputting a control signal to execute the operation of the data driving circuit and the gray clock driving circuit;
The control unit is
a data output unit for changing the order of image data output from the data driving circuit; and
and a scheduler for changing the order of pulses output from the gray clock driving circuit. The method according to claim 1,
The data output unit,
controlling the data driving circuit to output the most significant bit of the image data in the first frame group and output the image data from the least significant bit in the second frame group;
The scheduler is
A display device for controlling the gray clock driving circuit to output a pulse having the longest width in a first frame group and output a pulse having the smallest width in a second frame group. The method according to claim 1,
The data output unit includes the data driving circuit
controlling the pixel driving circuit included in the first group row to output the most significant bit of the image data in the first frame group and output the image data from the least significant bit in the second frame group;
controlling the pixel driving circuit included in the second group row to output the least significant bit of the image data in the first frame group and output the image data from the most significant bit in the second frame group;
The scheduler is the gray clock driving circuit
Controlling the pixel driving circuit included in the row of the first group to output the pulse with the longest width in the first frame group and output the pulse with the smallest width in the second frame group;
A display device that controls the pixel driving circuit included in the row of the second group to output a pulse having the smallest width in a first frame group and output a pulse having the longest width in a second frame group. A data driving circuit for outputting a signal related to driving of light emitting devices to the pixel driving circuit, a gray clock driving circuit for outputting a width-modulated pulse to the pixel driving circuits, and the operation of the data driving circuit and the gray clock driving circuit A control method for controlling a display device comprising a; a control unit for outputting a control signal to be executed,
the control unit
(a) controlling the data driving circuit to output the most significant bit of the image data from the most significant bit of the image data and outputting the gray clock driving circuit from the longest pulse in the case of the first frame group; and
(b) controlling the data driving circuit to output the image data from the least significant bit in the second frame group, and controlling the gray clock driving circuit to output the pulse with the smallest width; How to control the device. A data driving circuit for outputting a signal related to driving of light emitting devices to the pixel driving circuit, a gray clock driving circuit for outputting a width-modulated pulse to the pixel driving circuits, and the operation of the data driving circuit and the gray clock driving circuit A control method for controlling a display device comprising a; a control unit for outputting a control signal to be executed,
the control unit
(a) In the case of the first frame group, the data driving circuit causes the pixel driving circuit included in the first group row to output the most significant bit of the image data, and the pixel driving circuit included in the second group row to the pixel driving circuit included in the second group row. bit first, the gray clock driving circuit outputs the longest pulse to the pixel driving circuit included in the first group row, and outputting the smallest pulse to the pixel driving circuit included in the second group row to control it; and
(b) in the second frame group, the data driving circuit causes the pixel driving circuit included in the first group row to output the least significant bit of the image data, and sends the pixel driving circuit included in the second group row the most significant bit of the image data bit first, the gray clock driving circuit outputs the smallest pulse to the pixel driving circuit included in the first group row, and outputting the largest pulse to the pixel driving circuit included in the second group row A control method of a display device that repeatedly performs; A computer program recorded in a computer-readable recording medium written to perform each step of the method according to claim 4 or 5 in a computer.

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