KR102375585B1 - PMOS-diode type eFuse One-Time programmable cell - Google Patents

Abstract

The present invention relates to a PMOS-diode type eFuse one-time programmable (OTP) cell. The eFuse OTP cell comprises a PMOS transistor formed in an N-well and an eFuse link, and the e-fuse link is blown with a junction diode parasitic in the PMOS transistor. The present invention consists of the PMOS transistor (MP1) formed in the N-well (12) formed on a substrate (11) and the eFuse link connected to a source node (ps) of the PMOS transistor (MP1), and the e-fuse link of the eFuse OTP cell is blown in a program mode with the junction diode parasitic between the N-well as a body of the PMOS transistor and a p+diffusion layer, thereby reducing process unit costs in a CMOS process and implementing the small size of a cell to be the same as an NMOS transistor.

Description

PMOS-diode type eFuse One-Time programmable cell

The present invention relates to a PMOS-diode type eFuse One-Time Programmable (OTP) cell, and more particularly, to a PMOS transistor and a memory device formed in an N-WELL. By composing an eFuse OTP cell with an in eFuse link and making the pn junction diode parasitic in the PMOS transistor available for eFuse link blowing, there is no need for an additional deep-n-well mask process in the CMOS process. It relates to a PMOS-diode type eFuse OTP cell that can achieve the same cell size as that of an NMOS transistor.

In general, Si MOSFETs, Si IGBTs and SiC devices are used as power semiconductor devices due to their high voltage rating, high current rating, low ON resistance and low switching loss.

On the other hand, in order to drive power semiconductor devices such as Si IGBT and SiC with one gate driving chip for various applications such as DC-DC converters for EV/HEV (Electric Vehicle/Hybrid Electric Vehicle), the blocking voltage and the gate to completely block the switch Various options related to negative voltage and the like may occur.

When it is necessary to trim the analog circuit used to control this with an option code suitable for power semiconductor devices such as Si IGBT and SiC, the small-capacity non-volatile memory eFuse OTP (electrical Fuse One) -Time programmable memory is used a lot, and these eFuse OTP memory cells cause thermal blowing of the eFuse link by flowing an overcurrent of more than tens of [mA] to the eFuse link, which is a polysilicon gate in the selected cell. It is programmed in such a way that it breaks by blowing).

In this regard, Republic of Korea Patent No. 10-1762918 (registered on July 24, 2017; hereinafter abbreviated as 'Patent Document 1') discloses a technology related to an eFuse OTP memory circuit using a junction diode proposed by the present applicant. is known.

1 and 2 illustrate an equivalent circuit diagram of an NMOS-Diode type eFuse OTP cell proposed in Patent Document 1 and a cross-sectional view of a process of an NMOS transistor in the eFuse OTP cell.

According to Patent Document 1, a low-area 5V NMOS diode eFuse OTP cell is a P-WELL formed in a Deep N-WELL (DNW) formed on a p-snbstrate as illustrated in FIG. 1 . ) is composed of an isolated 5V NMOS transistor (MN1) and an eFuse link using the same layer as the gate polysilicon as a memory device. A pn junction diode is parasitic between the P-WELL to which the (Source Line) is connected and the NS (NMOS Source), which is the source node of the NMOS transistor connected to the anode of the eFuse link. is made In program mode, the eFuse link is programmed by thermally blowing the junction diode formed at the source junction of the isolated 5V NMOS transistor and the overcurrent flowing through the eFuse link.

However, the 5V NMOS-diode type eFuse OTP cell size can be implemented with a small area, but as illustrated in FIG. 2 , a deep-n-well mask must be added, so the semiconductor process cost increases.

KR 10-1762918 B1 2017.07.24. registration

Therefore, the present invention has been devised to solve the above problems, and the technical problem to be solved by the present invention is to provide an eFuse OTP cell with a PMOS transistor formed in an N-WELL and an eFuse link, which is a memory element. By using a pn junction diode parasitic between the p+ diffusion layer connected to the PS node in the PMOS transistor and the N-well to which the Write WL bar signal is connected, for blowing the eFuse link of the cell, CMOS An object of the present invention is to provide a PMOS-diode type eFuse OTP cell that can be implemented in the same size as that of an NMOS transistor without the need for an additional deep-n-well mask process in the (CMOS) process.

One embodiment of the present invention for achieving the above object is a PMOS transistor formed in an N-well formed on a substrate, and an eFuse link connected to a source node of the PMOS transistor. It is a tipi cell.

According to the present invention, an eFuse OTP cell is constituted by a PMOS transistor formed in the N-WELL of the substrate and an eFuse link, which is a memory element, and a p+ diffusion region and a write word line bar connected to the PS node of the PMOS transistor. By making the pn junction diode parasitic between the N-well to which the (WWLb) signal is connected can be used for e-fuse link blowing, there is no need for an additional process for the deep-n-well mask when using the existing NMOS transistor in the CMOS process Therefore, it is possible to reduce the process cost and provide the advantage that the cell size can be implemented as small as that of the NMOS transistor.

1 is an equivalent circuit diagram of a conventional NMOS-diode type eFuse OTP cell.
2 is a cross-sectional view of an NMOS transistor in a conventional eFuse OTP cell.
3 is a block diagram illustrating the overall configuration of an eFuse OTP memory circuit that can be implemented as a PMOS-diode type eFuse OTP cell according to the present invention.
4 is an equivalent circuit diagram of a PMOS-diode type eFuse OTP cell according to the present invention.
5 is a cross-sectional view of a PMOS transistor of an eFuse OTP cell according to the present invention.
6 is a detailed circuit diagram of a word line driver for driving an eFuse OTP cell according to the present invention.
7 is a detailed circuit diagram of a source line driver for driving an eFuse OTP cell according to the present invention.
8 is a detailed circuit diagram of a sense amplifier for driving an eFuse OTP cell according to the present invention.
9 is a reference photograph illustrating a layout image of a PMOS-diode type eFuse OTP cell according to the present invention, which is composed of a 5V PMOS transistor and an eFuse link using gate polysilicon.
10 is a reference photograph illustrating a layout image of a 512b eFuse OTP memory IP according to the present invention designed using DB HiTek 130nm BCD process.
11 is a reference photograph illustrating the read mode measurement waveforms before (a) and after (b) programming in the 512-bit eFuse OTP IP wafer according to the present invention, in which the process of FIG. 10 has been performed.

Hereinafter, the configuration and operation of the PMOS-diode type eFuse OTP cell according to a preferred embodiment of the present invention and the effect thereof will be described in detail with reference to the accompanying drawings.

The terms or words used in the present specification and claims are not to be construed as limited in their ordinary or dictionary meanings, and on the principle that the inventor can appropriately define the concept of the term in order to best describe his invention. It should be interpreted as meaning and concept consistent with the technical idea of the present invention. Therefore, since the embodiments described in this specification and the configurations shown in the drawings are only the most preferred embodiment of the present invention, it is understood that there may be various equivalents and modifications that can be substituted for them at the time of the present application. shall.

3 is a block diagram illustrating the overall configuration of an eFuse OTP memory circuit that can be implemented as a PMOS-diode type eFuse OTP cell according to the present invention. As illustrated in FIG. 3 , the eFuse OTP memory circuit implemented as an OTP cell includes an eFuse OTP cell array unit 10 , a control logic unit 20 , a word line driver 30 , a column decoder 40 , and a source line driver and a sense amplifier 50 .

The eFuse OTP cell array unit 10 includes a matrix of eFuse OTP cells including a junction diode parasitic between an N-WELL, which is a body of a PMOS transistor formed on a p-substrate, and a p+ diffusion layer. An array of eFuse OTP cells is provided, wherein the eFuse link of the corresponding eFuse OTP cell is blown by the junction diode in the program mode, and the eFuse OTP cell is blown by the PMOS transistor in the read mode. The data programmed in the eFuse link is read. Here, the cell arrangement shape or capacity of the eFuse OTP cell array unit 10 is not particularly limited, but in this embodiment, the eFuse OTP cells are arranged in 64 rows x 8 columns as an example.

4 is an equivalent circuit diagram of a PMOS-diode type eFuse OTP cell according to the present invention. As illustrated in FIG. 4, the PMOS-diode type eFuse OTP cell according to the present invention has a PMOS device It is configured to include a stirrer (MP1), and an eFuse link (eFuse link). In the PMOS transistor MP1, a read word line bar (RWLb) signal is supplied to the gate, a bit line (BL) signal is supplied to one terminal (drain), and a write word line bar (WWLb) signal is supplied to N-Well. is supplied The eFuse link is configured such that one terminal (cathode) is connected to the other terminal (PMOS Source) of the PMOS transistor MP1, and the source line SL signal is supplied to the other terminal (positive).

5 is a cross-sectional view of a PMOS transistor of an eFuse OTP cell according to the present invention. The PMOS transistor MP1 of the eFuse OTP cell is a Nwell 12 that is a body of a PMOS transistor formed on a substrate 11 . , and a p+ diffusion layer 13 and an n+ diffusion layer 14 formed in the nwell 12, wherein a junction diode parasitic between the nwell 12 and the p+ diffusion layer 13 is used to blow the eFuse link of the cell do. The eFuse OTP cell array may be an eFuse OTP cell array arranged in 64 rows x 8 columns as a matrix structure, and the PMOS transistor MP1 is formed in the Nwell 12 formed in the substrate 11 , , the eFuse link uses gate polysilicon as a memory device.

The control logic unit 20 provides a program mode, a normal read mode, and a program for the eFuse OTP cell array unit 10 according to various control signals (PGM, READ, A[11:0], TM_EN). Outputs an internal control signal suitable for the Program-Verify-Read mode.

The word line driver 30 receives a row address under the control of the control logic unit 20 and outputs a read word line (RWL) signal and a write word line bar (WWLb) signal to the eFuse OTP cell array unit 10 . do.

The column decoder 40 decodes the column address under the control of the control logic unit 20 and transmits the decoded column address to the source line driver and the sense amplifier 50 to drive the source line of the eFuse OTP cell array unit 10 . ) is printed in

The source line driver and sense amplifier 50 supplies program data corresponding to input data to the eFuse OTP cell array unit 10 in the program mode under the control of the control logic unit 20, and in the read mode, the eFuse OTP cell array unit 10 Detects and amplifies the bit line BL signal supplied from the TP cell array unit 10 to generate output data accordingly.

6 to 8 are detailed circuit diagrams of a word line driver, a source line driver, and a sense amplifier for driving an eFuse OTP cell according to the present invention, respectively.

As illustrated in FIG. 6 , the word line driver 30 includes a first NAND gate ND01 for performing a NAND operation on a control signal, a first inverter I01 for inverting an output signal of the first NAND gate ND01, and a first The second NAND gate ND02 performs a NAND operation on the output signal of the inverter I01 and the word line enable (WLEN_PGM) signal in the program mode, and the second inverter I02 inverts the output signal of the second NAND gate ND02. , a PMOS transistor MP01 and an NMOS transistor MN01 connected in parallel to output a VDD_PGM switching voltage or 0V voltage as a write word line bar WWLb signal by the output signal of the second inverter I02, the first The first NOR gate (NOR01) that performs NOR operation on the output signal of the inverter (I01) and the word line enable bar (WLENb_RD) signal in the read mode, and the read word line bar by inverting the output signal of the first NOR gate (NOR01) and a third inverter I03 for outputting a (RWLb) signal.

As illustrated in FIG. 7 , the source line driver and the source line driver of the sum amplifier 50 receive the output signal and input data DIN of the fourth inverter I04 and the fourth inverter I04 for inverting the control signal. The second NOR gate (NOR02), the fifth inverter (I05) that inverts the output signal of the second NOR gate (NOR02), and the output signal of the fifth inverter (I05) and the internal program (IPGM) signal for NAND operation The third NAND gate ND03, the sixth inverter I06 for inverting the output signal of the third NAND gate ND03, and the VDD_PGM switching voltage or 0V voltage connected in parallel to the output signal of the sixth inverter I06 and a PMOS transistor MP02 and an NMOS transistor MN02 for outputting as a source line SL signal.

As illustrated in FIG. 8, the source line driver and the sense amplifier of the sense amplifier 50 include the bit line pre-charge bar (BL_PCGb) signal and bit line load (BL_LOAD) signal in the normal read mode, and the bit in the test read mode. The bit line control unit 51 that controls the bit line BL signal according to the line load (TM_BL_LOAD) signal, and the output signals of the bit line control unit 51 are applied to the sense amplifier enable bar (SAENb) signal and the sense amplifier enable signal (SAEN). Switching according to the output signal of the clock inverter unit 52 and the clock inverter unit 52, the sense amplifier enable bar (SAENb) signal, and the sense amplifier enable signal (SAEN) signal to be inverted in synchronization with the signal and a switching voltage level converting unit 53 that converts the voltage and outputs the level.

The PMOS-diode type eFuse OTP cell of the present invention configured as described above constitutes the eFuse OTP cell array unit 10, and each eFuse OTP cell has a channel width as illustrated in FIG. It consists of this small 5V PMOS transistor (MP1) and an eFuse link using gate polysilicon as a memory element. At this time, the PMOS transistor MP1 connects the write word line bar WWLb signal to the n+ diffusion layer 14 of the body formed in the nwell 12 as illustrated in the process cross-sectional view of FIG. 5 , and a read word line to the gate The bar signal RWLb is connected, and the bit line BL signal is connected to the p+ diffusion layer 13 (drain). In addition, the eFuse link connects one terminal (cathode) to the other terminal (PS) of the PMOS transistor MP1 and connects the source line (SL) signal to the other terminal (positive electrode). In this case, in the PMOS transistor MP1, the pn junction diode is parasitic between the p+ diffusion layer connected to the PS node of FIG. 5 and the N-WELL connected to the write word line bar WWLb signal.

At this time, in order to program the selected eFuse link, the source line (SL) signal connected to the anode of the eFuse link, the read word line bar (RWLb) signal connected to the gate of the PMOS transistor, and the N-Well gate of the PMOS transistor When VDD (=5.5V), VDD and 0V voltages are respectively applied to the write word line bar (WWLb) signal connected to An overcurrent of several tens of [mA] or more flows from the source line (SL) signal to the current path of the write word line bar (WWLb) signal through the pn junction diode, and thermally blows the selected eFuse link to break it, resulting in a high level of more than several [㏁]. make it resistant. On the other hand, the resistance of the unprogrammed eFuse link is about 100[Ω].

9 exemplifies a layout image of a PMOS-diode type eFuse OTP cell composed of a 5V PMOS transistor and an eFuse link using gate polysilicon, and the size of the eFuse OTP cell is 3.475㎛ x 4.21 μm (=14.62975 μm ² ). The figure illustrates that the p+ diffusion layer of the source line SL signal is arranged as close as possible to the n+ diffusion layer 14, which is the pick-up of the N-well, which is the body node of the 5V PMOS transistor, as close as possible to reduce parasitic N-well resistance.

On the other hand, the size of the PMOS-diode type eFuse OTP cell of the present invention is a dual-port eFuse OTP cell based on a 0.18 µm BCD process having a cell size of 89.96 µm ² , which is a conventional eFuse OTP cell, and 97 µm ² It is much smaller than the 0.18㎛ generic process-based dual-port eFuse OTP cell with a cell size of ^13.745㎛2 , similar to the 5V NMOS-diode type eFuse OTP cell size. Therefore, the PMOS-diode type eFuse OTP cell according to the present invention has a similar cell size as compared to the 5V NMOS-diode type eFuse OTP cell, while one deep-n-well mask can be reduced.

Table 1 below shows the main characteristics of a 512b eFuse OTP memory circuit designed using the PMOS-diode type eFuse OTP cell of the present invention.

[Table 1]

In Table 1, the process technology is DB Hitech 0.13 μm BCD process, and the format or size of the eFuse OTP cell array unit is not particularly limited, but in this embodiment, 64 rows x 8 columns are described as an example. In addition, the eFuse link is made of cobalt silicide n+ polysilicon, and as an operation mode, there are a program, a normal read, and a program-verify-read mode. In addition, 1 bit may be allocated as a program bit for the eFuse OTP memory circuit and 8 bits may be allocated as a read bit. The reason for setting the program bit to 1 bit is that when programming in byte units, a large program current of several hundred mA causes a resistive voltage drop on the VDD power line, VSS line, etc. This is because the program characteristics of the eFuse OTP cell are deteriorated.

10%)를 사용하며, V2V는 반도체 칩에서 제공되는 내부공급 전압원이고, 프로그램 모드 시 VDD 전압은 이퓨즈 링크를 서멀 블로잉시키기 위해 충분한 파워를 공급하는 전압인 5.5V가 사용된다.Meanwhile, the voltage used is VDD and V2V (=2.0V

10%), V2V is the internal supply voltage source provided by the semiconductor chip, and the VDD voltage in the program mode is 5.5V, which is a voltage that provides sufficient power to thermally blow the eFuse link.

Table 2 below illustrates bias conditions for each operation mode for the 5V PMOS-diode type eFuse OTP cell according to the present invention.

[Table 2]

In the program mode, in order to program to a logic '0' state where the eFuse link resistance is high resistance, as shown in Table 2, the source line (SL) signal, the read word line bar (RWLb) signal, and the bit line ( BL) signal and write word line bar (WWLb) signal are driven to VDD (=5.5V), VDD, floating and 0V, respectively. In this way, when the source line SL signal and the write word line bar WWLb signal are driven at VDD and 0V, the current formed from the source line SL signal to the e-fuse link, pn junction diode and the write word line bar WWLb signal. An overcurrent of several tens of [mA] flows through the path and the eFuse link to be programmed has a high resistance of several [㏁] or more as it is blown off due to thermal breakdown. On the other hand, when the program data is logic '1', the eFuse link resistance must be maintained at 100[Ω], so the source line (SL) signals in all rows are driven to 0V, so no current flows through the eFuse link. In the unblown state, the e-fuse link maintains a resistance of about 100 [Ω].

When the source line (SL) signal, the read word line bar (RWLb) signal, and the write word line bar (WWLb) signal of the cell selected in the read mode are driven at VLV, 0V and VLV, respectively, the eFuse programmed to a logic '0' In the OTP cell, the eFuse link is in a high resistance state, and a logic '0' is output to the output data (DOUT) port. On the other hand, in the eFuse OTP cell programmed with logic '1', the eFuse link has a resistance of about 100 [Ω], so the bit line (BL) signal is pulled up to the VLV voltage and a logic '' at the output data (DOUT) port. 1' will be output.

On the other hand, looking at the operation of each driving circuit illustrated in FIGS. 6 to 8 ,

First, in the word line driving circuit of FIG. 6, when entering the program mode, the write word line bar (WWLb) signal and the read word line of the row selected by decoding of A876 and A543 decoded by row address A[8:3] The bar (RWLb) signal drives 0V and VDD voltages. And when the read mode is entered, the write word line bar (WWLb) signal and the read word line bar (RWLb) signal of the row selected by decoding of A876 and A543 drive VDD_PGM (=VLV) and 0V voltage.

Next, in the source line driver circuit of the source line driver and the sum amplifier 50 of FIG. 7 , when the program mode is entered, the input data DIN is set to logic '0' by A210 that has decoded the column address A[2:0]. In the case of , the selected source line SL signal VDD_PGM switching voltage is driven, and if it is not selected by A210 or the input data DIN is logic '1', the source line SL signal drives 0V. The VDD_PGM switching voltage drives the VDD voltage only in the program mode, and drives the VLV voltage in the other modes.

Finally, in the bit line sense amplifier circuit of FIG. 8, clocked inverters (MP13, MP14, MN13 and MN14) instead of using the BL sensing circuit using the conventional S/A (Sense Amplifier)-based DF/F A type of BL S/A circuit is used. When the read mode is entered, a low pulse is applied to the bit line precharge bar (BL_PCGb) signal, and the bit line (BL) signal is precharged to a voltage of V2V by the PMOS transistor MP11. After the bit line (BL) signal voltage is sufficiently precharged to 2V, when the NMOS transistor (MN11) is turned on to pull down the bit line (BL) signal, the eFuse link of the selected cell has a resistance of about 100 [Ω] , the bit line (BL) signal voltage maintains a logic '1' state voltage, whereas when the eFuse link has resistances of several [㏁] or more, the bit line (BL) signal voltage maintains a logic '0' state voltage will be maintained. As such, when the voltage for the program resistance of the eFuse OTP cell is transferred to the bit line BL signal, the sensed data of the bit line BL signal is output data DOUT by the clock inverters MP13, MP14, MN13 and MN14. ) is output.

10 illustrates a layout image of a 512b eFuse OTP memory IP designed using DB HiTek 130nm BCD process, and the layout area is 119.315㎛ x 41.95㎛ (=0.0408㎟).

Tables 3 and 4 below exemplify the SPICE simulation results for the sensing resistance of the programmed eFuse link according to the operation mode in the designed 512-bit eFuse OTP memory IP, and Table 3 is the result of the normal read mode. , Table 4 shows the results of the program-check-read mode.

[Table 3]

[Table 4]

As can be seen from Tables 3 and 4, the sensing resistance of the eFuse link programmed in the normal read mode (refer to Table 3) and the program-check-read mode (refer to Table 4) of the eFuse OTP IP by model parameter and temperature. were simulated as 30kΩ and 61kΩ, respectively. On the other hand, in the normal read mode, since a voltage is transferred to the bit line (BL) signal using a PMOS transistor with a small channel width, the maximum read current flowing through the non-blowing eFuse link of the eFuse OTP cell is set to 97.7 µA and 100 µA suppressed within.

11 exemplifies the read mode measurement waveforms before (a) and after (b) programming on a 512-bit eFuse OTP IP wafer that has been processed, and it can be seen that the program is normally programmed.

According to the present invention, an eFuse OTP cell is constituted by a PMOS transistor formed in the N-WELL of the substrate and an eFuse link, which is a memory element, and a p+ diffusion region and a write word connected to the PS node of the PMOS transistor. By making it possible to use the pn junction diode created parasitic between the N-well to which the write WL bar signal is connected for e-fuse link blowing, the process cost is reduced by eliminating the need for an additional deep-n-well mask in the CMOS process. There is an advantage that can be achieved, and it also provides an advantage of enabling the cell size to be implemented as small as that of an NMOS transistor.

10: eFuse OTP cell array unit 11: substrate
12: N-Well 13: p+ diffusion layer
14: n+ diffusion layer 20: control logic unit
30: word line driver 40: column decoder
50: source line driver and sense amplifier SL: source line
BL: bit line

Claims (7)

In the PMOS-diode type eFuse OTP cell,
The PMOS-diode type eFuse OTP cell is driven by a word line driver,
The word line driver is
a first NAND gate ND01 for performing a NAND operation on a control signal;
a first inverter I01 for inverting the output signal of the first NAND gate ND01;
a second NAND gate (ND02) for performing a NAND operation on the output signal of the first inverter (I01) and the word line enable (WLEN_PGM) signal of the program mode;
a second inverter I02 for inverting the output signal of the second NAND gate ND02;
a PMOS transistor MP01 and an NMOS transistor MN01 connected in parallel to output a VDD_PGM switching voltage or 0V voltage as a write word line bar WWLb signal according to the output signal of the second inverter I02;
a first NOR gate (NOR01) for performing a NOR operation on the output signal of the first inverter (I01) and the word line enable bar (WLENb_RD) signal in the read mode; and
A PMOS-diode type eFuse OTP cell comprising a; . In the PMOS-diode type eFuse OTP cell,
The PMOS-diode type eFuse OTP cell is driven by a source line driver and a sense amplifier,
The source line driver
a fourth inverter (I04) for inverting the control signal;
a second NOR gate (NOR02) for performing a NOR operation on the output signal of the fourth inverter (I04) and the input data (DIN);
a fifth inverter (I05) for inverting the output signal of the second NOR gate (NOR02);
a third NAND gate (ND03) for performing a NAND operation on the output signal of the fifth inverter (I05) and the internal program (IPGM) signal;
a sixth inverter I06 for inverting the output signal of the third NAND gate ND03; and
A PMOS transistor (MP02) and an NMOS transistor (MN02) connected in parallel to output a VDD_PGM switching voltage or 0V voltage as a source line (SL) signal according to the output signal of the sixth inverter (I06); A PMOS-diode type eFuse OTP cell. In the PMOS-diode type eFuse OTP cell,
The PMOS-diode type eFuse OTP cell is driven by a source line driver and a sense amplifier,
The sense amplifier,
A bit line controller that controls the bit line (BL) signal according to the bit line pre-charge bar (BL_PCGb) signal and the bit line load (BL_LOAD) signal in the normal read mode, and the bit line load (TM_BL_LOAD) signal in the test read mode (51);
a clocked inverter unit 52 that synchronizes the output signal of the bit line control unit 51 with a sense amplifier enable bar (SAENb) signal and a sense amplifier enable signal (SAEN) signal and inverts the output signal; and
a switching voltage level converting unit 53 for level-converting and outputting a switching voltage according to an output signal of the clock inverter unit 52, a sense amplifier enable bar (SAENb) signal, and a sense amplifier enable (SAEN) signal; A PMOS-diode type eFuse OTP cell. 4. The method according to any one of claims 1 to 3,
The PMOS-diode type E-Fuse OTP cell is
a semiconductor substrate containing impurities of a first type;
a well formed inside the semiconductor substrate and containing a second type of impurity;
a PMOS transistor MP1 formed inside the well, a gate node connected to a word line RWLb for a read operation, and a drain node connected to a bit line BL; and
and an e-fuse link having one terminal connected to the source node of the PMOS transistor MP1 and the other terminal connected to the source line. 5. The method of claim 4,
The PMOS-diode type eFuse OTP cell, characterized in that the second type of impurity in the well is an N-type. 5. The method of claim 4,
The eFuse link is a PMOS-diode type eFuse OTP cell, characterized in that a gate polysilicon is used as a memory device. 5. The method of claim 4,
a well 12 serving as a body of the PMOS transistor MP1; and
a p+ diffusion layer 13 and an n+ diffusion layer 14 formed in the well 12;
A PMOS-diode type eFuse OTP cell, characterized in that a junction diode parasitic between the well (12) and the p+ diffusion layer (13) is used to blow the eFuse link of the cell.

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