KR102374588B1 - Three dimensional semiconductor memory device and method for manufacturing the same - Google Patents

Abstract

The present disclosure relates to a three-dimensional semiconductor device and a method for manufacturing the same. According to an embodiment, a method of manufacturing a 3D semiconductor device includes: forming a vertical stack including a plurality of insulating layers and a plurality of sacrificial layers that are alternately stacked on a substrate; etching the formed vertical stack to create a first opening in the vertical stack and a recessed region in the substrate; forming a first gate electrode on a portion of a sidewall of the first opening; forming a second opening exposing the substrate in the vertical stack by etching the vertical stack; and forming a word line by forming a second gate electrode in a region corresponding to the first gate electrode on a sidewall of the formed second opening. may include

Description

3D semiconductor device and manufacturing method thereof

The present disclosure relates to a semiconductor device and a method for manufacturing the same. More particularly, it relates to a three-dimensional semiconductor memory device and a method of manufacturing the same.

Due to characteristics such as miniaturization, multifunctionality, and/or low manufacturing cost, a semiconductor device is in the spotlight as an important element in the electronic industry. However, as the electronics industry is highly developed, the trend toward high integration of semiconductor devices is deepening. For the high integration of the semiconductor device, the line width of the patterns of the semiconductor device is gradually decreasing, thereby making precise patterning difficult.

Conventionally, the degree of integration of a general two-dimensional semiconductor memory device is gradually reduced because the planar area occupied by a unit memory cell is a major determining factor, and thus, the degree of integration of a two-dimensional semiconductor memory device is greatly affected by the level of technology for forming a fine pattern. The line width to be used has a limit that leads to an increase in the process difficulty of semiconductor manufacturing.

Accordingly, a semiconductor memory device including three-dimensionally arranged memory cells has been developed in order to overcome the above-mentioned limitations for improving the degree of integration. However, due to the structural shape of the 3D semiconductor memory device, various problems of deterioration of characteristics according to manufacturing difficulty occur.

Accordingly, there is a demand for the development of a new three-dimensional vertical structure semiconductor device manufacturing technology exhibiting uniform device characteristics.

Korea Patent Publication No. 2020-0024630-0020133

According to an embodiment, a 3D semiconductor device having uniform device characteristics may be provided.

Also, according to an embodiment, a method of manufacturing a 3D semiconductor device using an area selective deposition method may be provided.

According to an exemplary embodiment of the present disclosure for achieving the above-described technical problem, a method of manufacturing a 3D semiconductor device includes forming a vertical stack including a plurality of insulating layers and a plurality of sacrificial layers that are alternately stacked on a substrate. step; etching the formed vertical stack to create a first opening in the vertical stack and a recessed region in the substrate; forming a first gate electrode on a portion of a sidewall of the first opening; forming a second opening exposing the substrate in the vertical stack by etching the vertical stack; and forming a word line by forming a second gate electrode in a region corresponding to the first gate electrode on a sidewall of the formed second opening. may include

In an embodiment, the method includes: forming a gate dielectric film on a sidewall of the first opening in which the first gate electrode is formed, in regions corresponding to the insulating film and the first gate electrode; lining a vertical active layer along the gate dielectric layer; and filling the recess region including sidewalls of the first opening lined with the vertical active layer with an insulating pattern; may further include.

In an embodiment, the forming of the first gate electrode may include forming the first gate electrode on the insulating layer and the sacrificial layer based on a difference in deposition rates of the insulating layer and the sacrificial layer exposed on the sidewall of the first opening. depositing a metal film; etching at least a portion of the first metal layer deposited on the insulating layer and the sacrificial layer; and forming the first gate electrode using a first metal layer on the sacrificial layer remaining after the etching. may include

In an embodiment, the forming of the word line may include removing the plurality of sacrificial layers between the plurality of insulating layers in the vertical stack through the second opening; and forming a word line by forming the second gate electrode in a partial region on a sidewall of the second opening from which the plurality of sacrificial layers are removed. may include

In an embodiment, the forming of the word line may include: exposing a portion of the first gate electrode on a sidewall of the second opening by removing the plurality of sacrificial layers; forming the second gate electrode by depositing a second metal film on the exposed first gate electrode and the insulating film in sidewalls of the second opening; and forming the word line by etching at least a portion of the deposited second metal layer constituting the second gate electrode. may include

In an embodiment, the forming of the gate dielectric layer may include: forming a blocking layer on a sidewall of the first opening in regions corresponding to the insulating layer and the deposited first gate electrode; forming a charge storage film along the formed blocking film; and forming the gate dielectric layer by forming a tunnel dielectric layer along the formed charge storage layer. may include

In an embodiment, the depositing of the first metal layer may include depositing the first metal layer on the insulating layer and the sacrificial layer at different rates based on a difference in deposition rates for the insulating layer and the sacrificial layer. ; It further includes, wherein the first metal layer may be deposited on the sacrificial layer at a higher rate.

In an embodiment, the first metal layer and the second metal layer are at least one of tungsten, a tungsten nitride layer (WN), a tungsten carbide layer, titanium, tantalum, aluminum, or hafnium, and the first metal layer and the second metal layer The films may be made of different metals.

In an embodiment, the substrate may include a well region of a first conductivity type and a common source region of a second conductivity type, and the recess region may extend into the well region through the common source region.

According to an embodiment, the vertical stacked body extends in a first direction with respect to the substrate, is spaced apart from each other in a second direction perpendicular to the first direction, and the first direction and the second direction are of the substrate. It may be parallel to the upper surface.

In an embodiment, the vertical active layer is in contact with a sidewall of the recess region, extends from an upper portion of the vertical active layer in the second direction, is connected to a bit line intersecting the vertical stack, and the vertical active layer may be connected to the well region by extending into the recess region formed in the common source region from a lower portion of the .

In addition, according to another embodiment of the present disclosure for solving the above technical problem, a three-dimensional semiconductor device includes a substrate; a vertical stack including a plurality of insulating layers and a plurality of removable sacrificial layer regions that are alternately stacked on the substrate; a first gate electrode formed on a portion of a sidewall of a recess region extending onto the substrate in the vertical stack; a gate dielectric layer formed along the first gate electrode and the plurality of insulating layers exposed on sidewalls of the recess region; a vertical active layer lined along the gate dielectric layer; an insulating pattern filling the recess region lined with the vertical active layer; and a word line generated by forming a second gate electrode in a region corresponding to the first gate electrode in a slit region spaced apart from the recess region by a predetermined distance to expose the substrate; may include

According to an embodiment, a three-dimensional semiconductor device having a vertical structure having uniform device characteristics may be effectively manufactured.

According to an embodiment, a 3D semiconductor device capable of using various materials as a stacked structure may be provided.

1 is a diagram for describing a structure of a 3D semiconductor device generated according to a method of manufacturing a 3D semiconductor device according to an exemplary embodiment.
2 is a view for explaining a manufacturing process of a general 3D semiconductor device according to an exemplary embodiment.
3 is a view for explaining a manufacturing process of a 3D semiconductor device according to an embodiment of the present disclosure.
4 is a flowchart of a method of manufacturing a 3D semiconductor device according to an exemplary embodiment.
5 is a flowchart of a method of manufacturing a 3D semiconductor device according to another exemplary embodiment.
FIG. 6 is a view for explaining a process of forming a first gate electrode according to an area selective deposition method, according to an exemplary embodiment.
7 is a view for explaining a process of forming a first gate electrode by a region selective deposition method according to an exemplary embodiment.
8 is a diagram illustrating an example of an electronic system including a 3D semiconductor device according to an exemplary embodiment.
9 is a diagram illustrating an example of a memory including a 3D semiconductor device according to an exemplary embodiment.

Terms used in this specification will be briefly described, and the present disclosure will be described in detail.

The terms used in the present disclosure have been selected as currently widely used general terms as possible while considering the functions in the present disclosure, but these may vary depending on the intention or precedent of a person skilled in the art, the emergence of new technology, and the like. In addition, in a specific case, there is a term arbitrarily selected by the applicant, and in this case, the meaning will be described in detail in the description of the corresponding invention. Therefore, the terms used in the present disclosure should be defined based on the meaning of the term and the contents of the present disclosure, rather than the simple name of the term.

Further, in the present specification, when a certain film (or layer) is referred to as being on another film (or layer) or substrate, it may be formed directly on the other film (or layer) or substrate or a third layer between them. In addition, in the drawings, the size and thickness of the components are exaggerated for clarity. In various embodiments of the present specification, the terms first, second, third, etc. are used to describe various regions, films (or layers), etc., but these regions and films should not be limited by these terms. Can not be done. These terms are only used to distinguish one region or film (or layer) from another region or film (or layer). Accordingly, a film quality referred to as the first film quality in one embodiment may be referred to as the second film quality in another embodiment. Each embodiment described and illustrated herein also includes a complementary embodiment thereof. In this specification, the expression 'and/or' is used in a sense including at least one of the elements listed before and after. Parts indicated with like reference numerals throughout the specification indicate like elements.

In the entire specification, when a part "includes" a certain element, this means that other elements may be further included, rather than excluding other elements, unless otherwise stated. In addition, terms such as "...unit" and "module" described in the specification mean a unit that processes at least one function or operation, which may be implemented as hardware or software, or a combination of hardware and software. .

Hereinafter, with reference to the accompanying drawings, the embodiments of the present disclosure will be described in detail so that those of ordinary skill in the art to which the present disclosure pertains can easily implement them. However, the present disclosure may be implemented in several different forms and is not limited to the embodiments described herein. And in order to clearly explain the present disclosure in the drawings, parts irrelevant to the description are omitted, and similar reference numerals are attached to similar parts throughout the specification.

1 is a diagram for describing a structure of a 3D semiconductor device generated according to a method of manufacturing a 3D semiconductor device according to an exemplary embodiment.

Referring to FIG. 1 , a cross-sectional view of a 3D semiconductor device that may be generated by processing a vertical stack on the substrate according to a method of manufacturing a 3D semiconductor device according to an exemplary embodiment is shown. According to an embodiment, insulating layers 102 , 104 , 106 , and 108 and sacrificial layers 103 , 105 , 107 , and 109 may be alternately stacked on the substrate 110 . For example, the substrate 110 may include a well region doped with a dopant of the first conductivity type. The substrate 110 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. A common source region doped with a dopant of the second conductivity type may be formed in the well region in the substrate. One of the dopant of the first conductivity type and the dopant of the second conductivity type may be an n-type dopant, and the other may be a p-type dopant.

For example, vertical stacks that are alternately and repeatedly stacked may be positioned on the substrate 110 . For example, after the insulating layer 102 is stacked on the substrate 110 , the sacrificial layer 103 may be stacked, and after the sacrificial layer 103 is stacked, the insulating layer 104 may be stacked again. According to an embodiment, the stacked structures may extend by being stacked in a first direction perpendicular to the upper surface of the substrate, and may be spaced apart from each other in a second direction perpendicular to the first direction. According to an embodiment, the first direction and the second direction may be parallel to the upper surface of the substrate 110 .

According to an embodiment, the insulating layers 102 , 104 , 106 , and 108 may include oxide, nitride, and/or oxynitride. According to another embodiment, the insulating layers may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. According to an embodiment, the insulating layers may be SiO ₂ , but is not limited thereto.

In addition, according to an embodiment, the sacrificial layers 103 , 105 , 107 , and 109 may include oxide or nitride and/or oxynitride. According to another embodiment, the sacrificial layers may include silicon nitride, silicon oxynitride, or polycrystalline silicon. According to an embodiment, the sacrificial layers may be SiN, but is not limited thereto. In an embodiment, the insulating layers and the sacrificial layers may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (Atom Layer). Deposition (ALD) may be deposited on the substrate based on at least one process.

The 3D semiconductor device 1000 according to the present disclosure may be included in a memory device for storing data. For example, the 3D semiconductor device according to the present disclosure may be included in a memory device such as a NAND flash memory or a DRAM. Also, according to an embodiment, the 3D semiconductor device according to the present disclosure may be used in a memory device having a 2-terminal structure. Since the three-dimensional semiconductor device 1000 according to the present disclosure is generated by depositing electrodes in only a predetermined selective area vertically on a substrate using Area Selective Deposition (ASD), a smaller number than the existing manufacturing process It can be manufactured by the process step of , and can exhibit more uniform device characteristics compared to a semiconductor device having a general vertical structure.

The 3D semiconductor device 1000 according to the present disclosure includes a substrate 140 , a vertical stack, a first gate electrode 156 , a gate dielectric layer 142 , a vertical active layer 178 , an insulating pattern 147 , and the first The word lines 158 , 181 , 182 , 183 , 184 , etc. generated by forming the second gate electrode 158 in a region corresponding to the gate electrode may be included. According to an embodiment, the three-dimensional semiconductor device 1000 is formed on the upper portion of the substrate to be perpendicular to a word line (Word Line, W/L, 158, 181, 182, 183, 184, etc.) including a gate electrode. , may further include a bit line (B/L) connected to the vertical active layer 178 .

A three-dimensional semiconductor device according to the present disclosure forms at least one opening in a vertical stack and a recess region formed between the opening and the substrate according to a predetermined etching selectivity, followed by a predetermined film By performing a deposition process, the recess region is filled, and after the recess region is filled, a portion in a predetermined vertical stack is again etched, thereby depositing a metal film in a preset gate electrode region. there is. According to an embodiment, the etching selectivity may include an etching selectivity of SiO2 and SiN.

The three-dimensional semiconductor device 1000 according to the present disclosure includes a first opening 152 and the first opening formed by etching a part of a vertical stack in which an insulating layer and a sacrificial layer are alternately stacked, and at least in the substrate. It may include a recessed area 154 extending to a partial area. The recess region 154 may represent a space that is opened upwardly of the substrate through the first opening on one side and extends to at least a partial region of the substrate on the other side. According to an embodiment, the recess region 154 vertically penetrates the common source region in the substrate, so that the bottom surface of the recess region may be located at a lower level than the lower surface of the common source region in the substrate.

A first gate electrode 156 may be deposited in a predetermined region on a sidewall of the first opening 152 in the recess region 154 . According to an embodiment, the first gate electrode 156 is formed on a sidewall of the first opening by a selective area deposition method (ASD), as will be described later with reference to FIG. 3 , in a region corresponding to a region to which predetermined sacrificial layers are exposed. can be deposited on The first gate electrode forms a predetermined gate voltage together with the second gate electrode deposited on one side of the first gate electrode, and according to the formed voltage, electrons in the vertical active layer move to the charge storage layer through tunneling or , electrons in the charge storage layer can be tunneled back to the source region.

According to an embodiment, the entire lower surface of the first gate electrode formed at the bottom of the first gate electrodes may overlap the common source region. Also, the first gate electrode may include a conductive material. For example, the first gate electrode may include at least one of a doped semiconductor, a metal, a transition metal, or a conductive metal nitride.

The insulating layer and predetermined gate dielectric layers may be formed on a sidewall of the first opening in which the first gate electrode is formed along the first gate electrode. According to an embodiment, the gate dielectric layer may include a blocking layer, a charge trap layer, and a tunnel dielectric layer. The gate dielectric layer 142 may be formed along a pattern formed by the deposited first gate electrode 156 and one sidewall of the insulating layer, between the vertical active layer and one sidewall formed by the first gate electrode and the insulating layer.

According to an embodiment, the blocking film 172 may include a high-k film (eg, a metal oxide such as aluminum oxide or hafnium oxide) having a higher dielectric constant than that of the tunnel dielectric film. In addition, the blocking layer may further include a barrier dielectric layer. The barrier dielectric layer may include a dielectric material having a larger band gap than the high-k layer in the blocking dielectric layer. The barrier dielectric layer may further include an oxide, and may be formed between the high-k layer and the charge storage layer.

The charge storage layer 174 may include a dielectric material having traps capable of storing charges, for example, nitride and/or metal oxide. The tunnel dielectric layer 176 may include oxide and/or oxynitride. The tunnel dielectric layer 176 may be formed as a single layer or multiple layers. The tunnel dielectric layer may provide a tunneling path so that electrons of the vertical active layer can tunnel into the charge storage layer by a voltage formed on the gate electrode.

The vertical active layer 178 is lined between a common source region and a drain region doped with a dopant of a second conductivity type formed on the upper surface of the vertical stack, and charges tunneling into the charge storage layer. may include The insulating pattern 147 may gap-fill a recess region including a sidewall of the first opening lined with the vertical active layer. According to an embodiment, the active insulating pattern 147 may include an insulating material for insulating purposes. For example, the insulating pattern 147 may include SiO ₂ for insulating purposes.

The 3D semiconductor device may include second openings 162 and 164 formed at positions spaced apart from the first opening formed in the vertical stack by a predetermined distance. The second opening may include a slit region exposing the substrate into the vertical stack. A second gate electrode 158 formed in regions corresponding to the first gate electrode may be formed in the slit region opened in the upper direction of the substrate through the second openings 162 and 164 .

In addition, insulating layers and sacrificial layers constituting the vertical stack in addition to the second gate electrode 158 may be alternately exposed on a sidewall of the second opening formed through the second opening. In addition, the second gate electrode in the slit region may form a gate of the memory cell in the 3D semiconductor device together with the first gate electrode, and a word line may be formed by etching at least a portion of the formed second gate electrode. .

2 is a view for explaining a manufacturing process of a general 3D semiconductor device according to an exemplary embodiment.

In S202 , an insulating film 202 and a sacrificial film 204 may be alternately laminated on the substrate 202 . According to an embodiment, the insulating layer and the sacrificial layer may be stacked on the substrate 202 to a preset thickness (eg, 100 nm or less). In S204 , a hole may be formed by etching a partial region in the vertical stack on the substrate 202 . For example, the hole may include a first opening that opens in an upper direction of the substrate and a recess region including the first opening.

In S206 , vertical active layers 208 and 210 may be lined on sidewalls of the first openings formed in the vertical stack. For example, the sidewall of the first opening may correspond to the sidewall of the hole in the vertical stack. According to an embodiment, the vertical active layer is a channel including charges tunneled into the charge storage layer, and may be deposited with poly-Si (Poly-Si). In S208 , a hole in the vertical stack including the first opening may be gap-filled with an insulating pattern. According to an embodiment, the insulating pattern may include an insulating SiO2 thin film.

In S210 , a slit region may be formed by etching at least a partial region in the vertical stack at a distance spaced apart from the first opening by a predetermined distance. The slit region may include a second opening formed in an upper portion of the substrate. For example, in S212 , the sacrificial layers (eg, SiN) in the slit region may be removed through the formed second opening.

In S214 , after the sacrificial layers are removed, a tunnel dielectric layer may be formed by oxidizing the vertical active layer (eg, Poly-Si) exposed between the insulating layers. According to an embodiment, the tunnel dielectric layer may include a tunnel oxide layer generated by oxidizing the poly-Si. In S216 , when the tunnel oxide layer 218 is generated by oxidizing the vertical active layer, a charge trap layer 220 may be deposited in the region corresponding to the insulating layer and the tunnel oxide layer on the sidewall of the slit region.

In S218 , after the charge storage layer is deposited, the blocking layer 222 may be deposited. According to an embodiment, the blocking layer may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. In S220 , when the blocking layer is deposited, a gate electrode may be formed by depositing a metal layer 224 along the deposited blocking layer. In S222 , the word line W/L may be formed by etching the over-deposited metal layer among the formed gate electrodes.

The general method of manufacturing a 3D semiconductor device described above with reference to FIG. 2 has a problem in that the number of stacking stages in the vertical stack increases, and the aspect ratio of the depth to the opening size of the second opening is low. A problem in that the difficulty of the process increases by increasing the size, a problem in that the etching is not uniform from the entrance of the second opening to the upper portion of the substrate exposed in the slit region, and the etching is uniform from the entrance of the second opening in the slit region to the upper part of the substrate in the slit region In this case, there is a problem in that the device characteristic uniformity is deteriorated due to the height difference of the memory cells in the slit region.

In addition, in the above-described general method of manufacturing a three-dimensional semiconductor device, in partially etching the metal film deposited in the slit region, the previously deposited blocking film is damaged, and by depositing the metal film in the slit region to form a gate electrode. Due to the problem in that the blocking film is damaged due to the compound, there is a limit in that device characteristics of the memory device are deteriorated.

Accordingly, there is a demand for development of a new 3D semiconductor manufacturing technology to overcome the above-mentioned problems and limitations that occur in manufacturing a semiconductor device having a general 3D vertical structure. Hereinafter, a method of manufacturing a 3D semiconductor device having uniform device characteristics using a selective region deposition method according to the present disclosure will be described in detail with reference to FIG. 3 .

3 is a view for explaining a manufacturing process of a 3D semiconductor device according to an embodiment of the present disclosure.

In S302 , an insulating film 302 and a sacrificial film 304 may be alternately laminated on the substrate 302 . According to an embodiment, the alternately stacked insulating and sacrificial layers may extend in a first direction perpendicular to the upper surface of the substrate to a thickness of 100 nm or less, but is not limited thereto. In addition, according to an embodiment, the vertical laminate according to the present disclosure may extend in a first direction perpendicular to the upper surface of the substrate with respect to the substrate and may be spaced apart from each other in a second direction perpendicular to the first direction. there is.

In S304 , a hole may be formed by etching a partial region in the vertical stack on the substrate. For example, the hole may include a first opening and a recess region extending onto the substrate including the first opening. According to an embodiment, the recess region may extend to at least a partial region of the substrate. Also, according to an embodiment, the substrate may include a well region of a first conductivity type and a common source region of a second conductivity type, and the recess region may extend through the common source region to the well region.

In S306 , a first gate electrode 308 may be formed on a portion of a sidewall of the first opening in the vertical stack. According to an embodiment, the sidewall of the first opening may correspond to the sidewall in a space defined by the recess region. In more detail, an insulating layer and a sacrificial layer that are alternately stacked may be exposed on the sidewall of the first opening formed by etching the vertical stack, and a first gate electrode is selectively disposed in regions corresponding to the exposed sacrificial layer. can be formed. According to an embodiment, when the sacrificial layer is made of SiN, the first gate electrode may be formed by depositing a first metal layer in a region corresponding to SiN exposed on the sidewall of the hole.

In more detail, an insulating layer and a sacrificial layer are exposed on a sidewall of the first opening, and a deposition rate of the first metal layer with respect to the insulating layer and the sacrificial layer may vary. For example, the first metal layer may be deposited on the sacrificial layer at a higher rate based on a difference in deposition rates for the insulating layer and the sacrificial layer on the sidewall of the first opening. After the first metal layer is deposited, a portion of the first metal layer deposited on the insulating layer and the sacrificial layer may be etched. In an embodiment, the insulating layer on the sidewall of the first opening and the first metal layer deposited on the sacrificial layer may be etched to the same degree. Since the first metal layer may be deposited on the sacrificial layer at a higher rate, when the first metal layer deposited on the sacrificial layer and the insulating layer is etched to the same extent, more first metal layers may remain on the sacrificial layer. .

In addition, according to an embodiment, after depositing the first metal layer on the sacrificial layer and the insulating layer at different rates, the etching process may be repeated, and by repeating the process, the first metal layer is deposited only on the sacrificial layer, which is a selective region. 1 A metal film may be deposited. Accordingly, according to the above-described process, a first metal layer may be selectively deposited on the sacrificial layer region on the sidewall of the first opening in the vertical stack.

According to another embodiment of the present disclosure, after an active deposition film is formed on the sidewall of the first opening, the first metal is formed in a selective region on the sidewall of the first opening by using a guide pattern for exposing only the deposition active film region. Films may be selectively deposited.

An area selective deposition (ASD) method for selectively depositing a first gate electrode on a partial region on a sidewall of the first opening will be described in more detail with reference to FIGS. 6 to 7 .

In S308 , a blocking layer 310 may be formed in a region corresponding to the first gate electrode formed on the sidewall of the first opening and the insulating layer exposed on the sidewall of the first opening. In S310 , after the blocking layer is formed, a charge storage layer 312 may be formed along the blocking layer. In S312 , a tunnel dielectric layer 314 providing a path for charges to tunnel from the vertical active layer to the charge storage layer may be formed along the charge storage layer. According to an embodiment, the formed blocking layer, the charge storage layer, and the tunnel dielectric layer may be included in the gate dielectric layer.

In S314 , the vertical active layer 316 may be lined along the outermost thin film of the tunnel dielectric layer or the gate dielectric layer. The vertical active layer may correspond to a channel including charges tunneling into the charge storage layer. According to an embodiment, the vertical active layer may be lined along the pattern of the formed tunnel dielectric layer, and as a result, the pattern of the tunnel dielectric layer and the pattern of the vertical active layer may correspond. In S316 , a recess region including a sidewall of the first opening lined with the vertical active layer may be filled with an insulating pattern 318 . According to an embodiment, the insulating pattern may be provided as a SiO ₂ thin film for insulating purposes.

According to an embodiment, the vertical active layer may be in contact with a sidewall of a recess region formed in the vertical stack, extend from an upper portion of the vertical active layer in the second direction, and may be connected to a bit line crossing the vertical stack. there is. In addition, the vertical active layer may be connected to the well region in the substrate by extending into the recess region formed in the common source region under the vertical active layer.

In S318 , after the insulating pattern in the recess region is filled, a slit region may be formed by etching at least a partial region in the vertical stack at a distance spaced apart from the first opening by a predetermined distance. For example, the slit region may include a second opening formed over the substrate. According to an embodiment, the second opening may be formed in a slit shape and may extend in a direction toward the substrate in the vertical stack.

In S320 , the sacrificial layers 324 exposed in the slit region may be removed through the formed second opening. For example, when the sacrificial layers exposed in the slit region are removed, the other side of the first gate electrode deposited by the selective region deposition method in the recess region may be exposed. In S322 , after the sacrificial layers in the slit region are removed, the second gate electrode 326 may be formed in the exposed region corresponding to the other side region of the first gate electrode and the insulating layer exposed on the sidewall of the second opening. there is. In more detail, by depositing a second metal layer in the region corresponding to the insulating layer exposed on the sidewall of the second opening and the other side of the first gate electrode exposed after the sacrificial layers in the slit region are removed, the second gate An electrode may be formed. In S324 , a portion of the second gate electrode that is excessively deposited among the formed second gate electrodes is etched to form a word line W/L including the gate electrode.

According to an embodiment, the first metal layer and the second metal layer may include at least one of tungsten, a tungsten nitride layer (WN), a tungsten carbide layer, titanium, tantalum, aluminum, or hafnium. Also, according to an embodiment, the first metal layer and the second metal layer may be made of the same metal, but according to another embodiment, the first metal layer and the second metal layer may be made of different metals.

The method for manufacturing a 3D semiconductor device according to the present disclosure is different from the general method of manufacturing a 3D semiconductor device of a vertical tank shown in S212 to S214, in which the sidewalls formed in the hole are all formed of the same material after SiN is removed, As shown in S304 , since the sacrificial layer and the insulating layer in the sidewall of the first opening are made of different materials, it is possible to deposit the gate electrode layer using the region selective deposition method.

That is, in the method of manufacturing a three-dimensional semiconductor device according to the present disclosure, a blocking film, a charge storage film, a tunnel dielectric film and a vertical active layer deposited first in depositing or etching a gate electrode in a general method of manufacturing a three-dimensional semiconductor device In contrast to exhibiting device degradation characteristics due to damage to a portion of may have fewer advantages.

In addition, in the method of manufacturing a 3D semiconductor device according to the present disclosure, since the aspect ratio, which is the ratio of the depth of the slit region to the entrance size of the slit region, increases, even if the etching is not uniformly performed to the upper part of the substrate in the slit region, it is Since it only brings about a height difference between the gate electrode layer itself, it may have an advantage that it does not significantly affect the characteristics of the semiconductor device due to damage to other layers or a height difference.

In addition, the method of manufacturing a three-dimensional semiconductor device according to the present disclosure does not form a tunnel dielectric film by oxidizing the vertical active layer in step S214, but forms a tunnel dielectric film by deposition as in step S312, There is an advantage that is not limited to SiO2 or nitridation-SiO2. In addition, in the case of the method of manufacturing a three-dimensional semiconductor device according to the present disclosure, since the vertical active layer (eg, a channel) may be formed after the first gate electrode, the blocking film, the charge storage film, and the tunnel dielectric film are formed, the subsequent process There is an advantage in that it can utilize oxide semiconductors that are easily degraded by heat, transition metal dichalcogenides (TMDCs) series.

In addition, according to an embodiment, in the method of manufacturing a 3D semiconductor device according to the present disclosure, a word line is formed by forming a gate electrode using a single type of metal film in the conventional method of manufacturing a 3D semiconductor device. Unlike the above, after forming the first gate electrode, the word line may be formed by forming the second gate electrode through the slit region. Accordingly, the method of manufacturing a 3D semiconductor device according to the present disclosure has an advantage in that a word line can be formed by using a multi-material stacked structure.

The method of manufacturing a 3D semiconductor device according to the present disclosure may be used in a vertical structure manufacturing process of a two-terminal structure semiconductor device, such as a conventional vertical NAND flash memory device. However, according to another embodiment, the method of manufacturing a 3D semiconductor device according to the present disclosure may be used in a vertical structure manufacturing process of a 3-terminal structure semiconductor device such as DRAM, but is not limited thereto. Of course, it can also be used in a vertical structure manufacturing process.

4 is a flowchart of a method of manufacturing a 3D semiconductor device according to an exemplary embodiment.

According to an embodiment, although not shown in the drawings, the 3D semiconductor device according to the present disclosure may be generated by a system for manufacturing a semiconductor device. According to an embodiment, a system for manufacturing a semiconductor device may include a memory storing at least one instruction and at least one processor executing a method of manufacturing a 3D semiconductor device by executing the instructions stored in the memory. . According to an embodiment, a system for manufacturing a semiconductor device forms a slit region or a recess region by etching a part of a stacked part in which an insulating layer and a sacrificial layer are alternately stacked on a substrate, and a part of a vertical stack generated by the stacked part. etching part. A deposition portion for selectively depositing a metal film in the recess region or depositing a gate dielectric film along the deposited metal film, a lining portion for lining a predetermined vertical active layer along a line on which the gate dielectric film is deposited, the vertical active layer A filling part for filling the lined recess region with an insulating pattern may be further included.

In S410 , the system for manufacturing a semiconductor device may form a vertical stack including a plurality of insulating layers and a plurality of sacrificial layers that are alternately stacked on a substrate. According to an embodiment, a system for manufacturing a semiconductor device may stack an insulating layer and a sacrificial layer on a substrate to a thickness of 100 nm or less in a first direction perpendicular to the upper surface of the substrate, but is not limited thereto.

In S420 , the system for manufacturing a semiconductor device may create a first opening in the vertical stack and a recess region in the substrate by etching the vertical stack. In S430 , the system for manufacturing the semiconductor device may form a first gate electrode on a portion of a sidewall of the first opening. For example, in a system for manufacturing a semiconductor device, the first gate electrode may be formed by depositing a first metal layer in a region corresponding to the sacrificial layer exposed on the sidewall of the first opening using an area selective deposition method (ASD). there is.

In S470 , the system for manufacturing a semiconductor device may form a second opening exposing the substrate in the vertical stack by etching the vertical stack. For example, in a system for manufacturing a semiconductor device, the second opening through which the upper surface of the substrate is exposed may be formed by etching at least a portion of the vertical stack at a distance spaced apart from the first opening by a predetermined distance.

In S480 , the system for manufacturing a semiconductor device may form a word line by forming a second gate electrode in a region corresponding to the first gate electrode on a sidewall of the second opening. For example, in a system for manufacturing a semiconductor device, the second gate electrode may be formed by depositing a second metal layer in a region corresponding to the first gate electrode exposed on the sidewall of the second opening. In a system for manufacturing a semiconductor device, the word line W/L may be formed by etching a portion of the deposited second metal layer from among the formed second gate electrodes.

5 is a flowchart of a method of manufacturing a 3D semiconductor device according to another exemplary embodiment.

Referring to FIG. 5 , a process in which a system for manufacturing a semiconductor device fills a recess region formed in a vertical stack will be described in more detail.

In S440 , the system for manufacturing the semiconductor device may form an insulating layer on a sidewall of the first opening in which the first gate electrode is formed and a gate dielectric layer in regions corresponding to the first gate electrode. More specifically, in a system for manufacturing a semiconductor device, a blocking film is formed in regions corresponding to the deposited first gate electrode and an insulating film on a sidewall of a first opening, and charges are stored along the formed blocking film. The gate dielectric layer may be formed by forming a charge trap layer and forming a tunnel oxide layer along the formed charge storage layer. According to an embodiment, the gate dielectric layer according to the present disclosure may include a blocking layer, a charge storage layer, and a tunnel dielectric layer.

In S450 , the system for manufacturing the semiconductor device may line the vertical active layer along the gate dielectric layer after the gate dielectric layer is formed. For example, in a system for manufacturing a semiconductor device, after forming the blocking layer, the charge storage layer, and the tunnel dielectric layer, a vertical active layer including charges to be tunneled through the tunnel dielectric layer may be deposited on the sidewall of the tunnel dielectric layer. In S460 , the system for manufacturing the semiconductor device may fill the recess region including the sidewall of the first opening lined with the vertical active layer with an insulating pattern.

FIG. 6 is a view for explaining a process of forming a first gate electrode according to an area selective deposition method, according to an exemplary embodiment.

A process of selectively depositing the first gate electrode on the sidewall of the first opening in the 3D semiconductor device of the present application will be described in detail with reference to FIG. 6 . In a system for manufacturing a semiconductor device according to the present disclosure, a first gate electrode is formed by selectively depositing a first metal film in a region corresponding to a sacrificial film exposed on a sidewall of a first opening using an area selective deposition method (ASD). can

For example, in S620 , the system for manufacturing the semiconductor device may deposit the first metal layer based on a difference in deposition rates for the insulating layer and the sacrificial layer exposed on the sidewall of the first opening. According to an embodiment, a system for manufacturing a semiconductor device may deposit the first metal layer at different rates on the insulating layer and the sacrificial layer exposed on the sidewall of the first opening. According to an embodiment, the first metal layer may be deposited on the sacrificial layer at a relatively faster rate than the insulating layer.

According to another embodiment, the system for manufacturing the semiconductor device may deposit the first metal layer only on the sacrificial layer exposed on the sidewall of the first opening.

In S630 , the system for manufacturing the semiconductor device may etch at least a portion of the first metal layer deposited on the insulating layer and the sacrificial layer. According to an embodiment, a system for manufacturing a semiconductor device may etch the first metal layer deposited on the sacrificial layer and the insulating layer to the same extent.

According to an embodiment, when the first metal layer is deposited on the sacrificial layer at a higher rate, the first metal layer may be deposited thicker on the sacrificial layer region. Accordingly, when the system for manufacturing the semiconductor device etches the first metal layer to the same degree in S630 , the first metal layer may remain only in a region corresponding to the sacrificial layer.

According to another embodiment, when the difference between the deposition rate of the first metal layer on the sacrificial layer and the deposition rate on the insulating layer is very large, the system for manufacturing a semiconductor device can perform a process of etching the first metal layer without performing a process of etching the first metal layer. , the first metal layer may be deposited only on the sacrificial layer.

In S640 , the system for manufacturing the semiconductor device may form a first gate electrode by using the first metal layer on the sacrificial layer remaining after the etching in S630 . That is, in a system for manufacturing a semiconductor device, the first gate electrode may be formed by selectively depositing the first metal layer only in a region corresponding to the sacrificial layer. Also, according to an embodiment, although not shown in FIG. 6 , the system for manufacturing a semiconductor device may repeat steps S620 to S630 a predetermined number of times. In the system for manufacturing a semiconductor device according to the present disclosure, by repeating S620 to S630 a predetermined number of times, the first metal layer may be selectively deposited only in the region corresponding to the sacrificial layer.

According to another embodiment, in a system for manufacturing a semiconductor device, a deposition active film is formed on a sidewall of a first opening, and a guide pattern defining an exposed surface of the deposition active film is formed to deposit the first metal film only in a selected area. You may.

7 is a view for explaining a process of forming a first gate electrode according to an area selective deposition method according to an exemplary embodiment.

Referring to FIG. 7 , according to the number of repetitions 704 of a series of cycles of depositing a first metal film on blocks A and B, and etching the deposited first metal film, the first deposited on block A and block B A change in the thickness 702 of the metal film is shown. For example, block A shown in FIG. 7 may correspond to the sacrificial layer 734 exposed on the sidewall of the first opening, and block B may correspond to the insulating layer 732 exposed on the sidewall of the first opening. there is. According to an embodiment, a system for manufacturing a semiconductor device may deposit the first metal layer with respect to the block A and the block B at different rates.

Specifically, in FIG. 7 , thickness curve 706 and thickness curve 708 represent the change in thickness 702 of the first metal film deposited on block A and block B in the first cycle. For example, in a first cycle, referring to thickness curve 706 and thickness curve 708, a first metal film begins to deposit at a faster rate on block A, and on block B the first metal film on block A After a predetermined delay time elapses from the time when the deposition of the metal layer is started, the deposition may be started. Accordingly, at the first time point, the thickness of the first metal film deposited on the blocks A and B may be different.

A system for manufacturing a semiconductor device may etch the first metal film deposited on block A and block B to the same extent at a first time point. For example, referring to the thickness curve 710 and the thickness curve 712 , the first metal layer is deposited thicker on the block A, but may be etched to the same degree. According to an embodiment, the system for manufacturing a semiconductor device may etch the first metal layer deposited on the block A by an amount corresponding to the amount by which the first metal layer deposited on the block B is etched.

A system for manufacturing a semiconductor device may deposit a first metal layer on the blocks A and B again after the etching process. In the second cycle, referring to thickness curve 714 and thickness curve 716, the first metal film begins to deposit at a faster rate on block A, and the deposition of the first metal film on block A again on block B. It can be seen that deposition is started after a predetermined delay time has elapsed from the start time. Accordingly, a difference in the thickness of the first metal layer deposited on the block A and the block B at the second time point may be greater.

Referring to the thickness curve 718 and the thickness curve 719 , the system for manufacturing a semiconductor device may etch the deposited first metal layer according to a second cycle. According to an embodiment, the system for manufacturing a semiconductor device may etch the first metal layer deposited on the block A by an amount corresponding to the amount by which the first metal layer deposited on the block B is etched. Accordingly, in the system for manufacturing a semiconductor device according to the present disclosure, the first metal layer 736 may be selectively deposited only on the sacrificial layer exposed on the sidewall of the first opening by repeating the above-described cycle.

In the system for manufacturing a semiconductor device according to the present disclosure, the sacrificial film region in the recess region is different from the existing process, where the region selective deposition method cannot be used because the wall surfaces are all made of the same material after SiN is removed using the channel first scheme. By selectively depositing the first metal film corresponding to , there is an advantage in that damage to other layers due to the formation of the gate electrode can be minimized.

8 is a diagram illustrating an example of an electronic system including a 3D semiconductor device according to an exemplary embodiment.

Referring to FIG. 8 , an example of an electronic system including a 3D semiconductor device generated according to a method of manufacturing a 3D semiconductor device according to an exemplary embodiment will be described in detail. The controller 1110 , the input/output unit 1120 , the memory 1130 , and the interface 1140 of the electronic system 1100 according to an embodiment may be connected to each other through the bus 1150 . The bus 1150 may correspond to a data path through which data moves.

The controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic devices capable of performing functions similar thereto. The input/output unit 1110 may include a keypad, a keyboard, and a display device. The memory 1130 may store data and/or instructions. The memory 1130 may include at least one of the 3D semiconductor devices described in the above-described embodiments. Also, the memory 1130 may further include other types of semiconductor memory devices (eg, a magnetic memory device, a phase change memory device, a DRAM device, and/or an SRAM device).

The interface 1140 may perform a function of transmitting data to or receiving data from a communication network. The interface 1140 may be in a wired or wireless form. For example, the interface 1140 may include an antenna or a wired/wireless transceiver. According to an embodiment, although not shown in FIG. 8 , the electronic system 1100 may further include a high-speed DRAM device and/or an SRAM device as a motion memory device for improving the operation of the controller 1110 .

According to an embodiment, the electronic system 1100 may transmit and/or receive information from a portable information terminal (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or information in a wireless environment. It can be applied to all electronic products.

9 is a diagram illustrating an example of a memory including a 3D semiconductor device according to an exemplary embodiment.

Referring to FIG. 9 , a memory 1210 according to an exemplary embodiment may include a 3D semiconductor device according to the present disclosure. The 3D semiconductor device may further include a semiconductor memory element (eg, a magnetic memory element, a phase change memory element, a DRAM element, and/or an SRAM element) that can be formed in another type of vertical structure. According to an embodiment, the memory 1210 may further include a memory controller 1220 that controls data exchange between the host and the memory 1210 .

The memory controller 1220 may include a processor 1222 that controls the overall operation of the memory. Also, the memory controller 1220 may include an SRAM 1221 used as an operating memory of the processor 1222 . In addition, the memory controller 12220 may further include a host interface 1223 and a memory interface 1225 . The host interface 1223 may include a data exchange protocol between the memory 1200 and the host. The memory interface 1225 may connect the memory controller 1220 and the memory 1210 . Furthermore, the memory controller 1220 may further include an error correction block 1224 (Ecc). The error correction block 1224 may detect and correct an error in data read from the memory 1210 . Although not shown, the memory 1210 may further include a ROM device for storing code data for interfacing with the host. The memory 1210 may be used as a portable data storage card. Alternatively, the memory 1210 may be implemented as a solid state disk (SSD) that can replace the hard disk of the computer system.

In the above, embodiments of the present invention have been described with reference to the accompanying drawings, but the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. Therefore, the scope of the present disclosure is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present disclosure defined in the following claims also fall within the scope of the present disclosure.

Claims (20)

A method for manufacturing a three-dimensional semiconductor device, comprising:
forming a vertical stack including a plurality of insulating layers and a plurality of sacrificial layers alternately stacked on a substrate;
etching the formed vertical stack to create a first opening in the vertical stack and a recessed region in the substrate;
forming a first gate electrode using a first metal layer deposited on the plurality of sacrificial layers according to a difference in deposition rates of the insulating layer exposed on the sidewall of the first opening and the sacrificial layer;
forming a second opening exposing the substrate in the vertical stack by etching the vertical stack; and
forming a word line by forming a second gate electrode in a region corresponding to the first gate electrode on a sidewall of the formed second opening; A method comprising The method of claim 1, wherein the method
forming a gate dielectric layer on a sidewall of the first opening in which the first gate electrode is formed, in regions corresponding to the insulating layer and the first gate electrode;
lining a vertical active layer along the gate dielectric layer; and
filling the recess region including the sidewall of the first opening lined with the vertical active layer with an insulating pattern; A method further comprising: The method of claim 1 , wherein forming the first gate electrode comprises:
depositing the first metal layer on the insulating layer and the sacrificial layer based on a difference in deposition rates of the insulating layer and the sacrificial layer exposed on a sidewall of the first opening;
etching at least a portion of the first metal layer deposited on the insulating layer and the sacrificial layer; and
forming the first gate electrode by using a first metal layer on the sacrificial layer remaining after the etching; A method comprising The method of claim 1, wherein forming the word line comprises:
removing the plurality of sacrificial layers between the plurality of insulating layers in the vertical stack through the second opening; and
forming a word line by forming the second gate electrode in a partial region on a sidewall of the second opening from which the plurality of sacrificial layers are removed; A method comprising 5. The method of claim 4, wherein forming the word line comprises:
exposing a portion of the first gate electrode on a sidewall of the second opening by removing the plurality of sacrificial layers;
forming the second gate electrode by depositing a second metal film on the exposed first gate electrode and the insulating film in sidewalls of the second opening; and
forming the word line by etching at least a portion of the deposited second metal layer constituting the second gate electrode; A method comprising The method of claim 2 , wherein forming the gate dielectric layer comprises:
forming a blocking film on a sidewall of the first opening in regions corresponding to the insulating film and the deposited first gate electrode;
forming a charge storage film along the formed blocking film; and
forming the gate dielectric film by forming a tunnel dielectric film along the formed charge storage film; A method comprising The method of claim 3 , wherein the depositing of the first metal layer comprises:
depositing the first metal layer on the insulating layer and the sacrificial layer at different rates based on a difference in deposition rates for the insulating layer and the sacrificial layer; further comprising,
and the first metal film is deposited at a higher rate on the sacrificial film. 6. The method of claim 5,
The first metal layer and the second metal layer are at least one of tungsten, a tungsten nitride layer (WN), a tungsten carbide layer, titanium, tantalum, aluminum, or hafnium, and the first metal layer and the second metal layer are made of different metals. A method characterized in that it becomes. 3. The method of claim 2,
wherein the substrate comprises a well region of a first conductivity type and a common source region of a second conductivity type, the recess region extending through the common source region into the well region. 10. The method of claim 9,
The vertical stacked body extends in a first direction with respect to the substrate, is spaced apart from each other in a second direction perpendicular to the first direction, and the first direction and the second direction are parallel to the upper surface of the substrate. Characterized by a method. 11. The method of claim 10,
the vertical active layer is in contact with a sidewall of the recess region;
extending in the second direction from an upper portion of the vertical active layer and connected to a bit line crossing the vertical stack;
and connecting to the well region by extending under the vertical active layer into the recess region formed in the common source region. The method of claim 1 , wherein forming the first gate electrode comprises:
depositing a first metal layer on the sacrificial layer exposed on a sidewall of the first opening; and
forming the first gate electrode by using a first metal layer on the sacrificial layer; A method comprising Board;
a vertical stack including a plurality of insulating layers and a plurality of removable sacrificial layer regions that are alternately stacked on the substrate;
By etching the vertical stack, the plurality of sacrificial layers are formed on the plurality of sacrificial layers according to a difference in deposition rates of the insulating layer and the sacrificial layer exposed on sidewalls of a recess region extending onto the substrate in the vertical stack. a first gate electrode formed using the deposited first metal film;
a gate dielectric layer formed along the first gate electrode and the plurality of insulating layers exposed on sidewalls of the recess region;
a vertical active layer lined along the gate dielectric layer;
an insulating pattern filling the recess region lined with the vertical active layer; and
a word line generated by forming a second gate electrode in a region corresponding to the first gate electrode in a slit region spaced apart from the recess region by a predetermined distance to expose the substrate; A three-dimensional semiconductor device comprising a. 14. The method of claim 13, wherein the first gate electrode
The first metal layer is deposited on the insulating layer and the sacrificial layer based on a difference in deposition rates of the insulating layer and the sacrificial layer exposed on the sidewalls of the recess region, and the first metal layer is deposited on the insulating layer and the sacrificial layer. A three-dimensional semiconductor device, characterized in that formed by etching at least a portion of the first metal film. 15. The method of claim 14, wherein the word line is
By removing the plurality of sacrificial layers in the vertical stack through the slit region, one surface of the first gate electrode exposed on the sidewall of the slit region and the second gate formed on the insulating layer on the sidewall of the slit region A three-dimensional semiconductor device comprising an electrode. 16. The method of claim 15,
The second gate electrode is formed by depositing a second metal film on one surface of the first gate electrode exposed on the sidewall of the slit region and on the insulating film formed on the sidewall of the slit region,
The word line is a three-dimensional semiconductor device, characterized in that formed by etching at least a portion of the deposited second metal layer. 14. The method of claim 13, wherein the gate dielectric layer
A blocking film formed in regions corresponding to the insulating film and the formed first gate electrode on a sidewall of the recess region, a charge storage film formed along the blocking film, and a tunnel dielectric film formed along the charge storage film Characterized in, a three-dimensional semiconductor device. 15. The method of claim 14, wherein the first metal layer
The 3D semiconductor device is characterized in that the deposition is performed at a higher rate on the sacrificial layer exposed on the sidewall of the recess region based on the difference in the deposition rate. 17. The method of claim 16,
The first metal layer and the second metal layer are at least one of tungsten, a tungsten nitride layer (WN), a tungsten carbide layer, titanium, tantalum, aluminum, or hafnium, and the first metal layer and the second metal layer are made of different metals. A three-dimensional semiconductor device, characterized in that it becomes. 20. The method of claim 19,
The vertical stacked body extends in a first direction with respect to the substrate, is spaced apart from each other in a second direction perpendicular to the first direction, and the second direction is parallel to the upper surface of the substrate,
the vertical active layer is in contact with a sidewall of the recess region, extends from an upper portion of the vertical active layer in the second direction, and is connected to a bit line crossing the vertical stack;
The substrate includes a well region of a first conductivity type and a common source region of a second conductivity type;
The vertical active layer is connected to the well region by extending into the recess region formed in the common source region under the vertical active layer.

Images