KR102355989B1 - 다중 노드 시스템 저전력 관리 - Google Patents

다중 노드 시스템 저전력 관리 Download PDF

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Publication number
KR102355989B1
KR102355989B1 KR1020207021188A KR20207021188A KR102355989B1 KR 102355989 B1 KR102355989 B1 KR 102355989B1 KR 1020207021188 A KR1020207021188 A KR 1020207021188A KR 20207021188 A KR20207021188 A KR 20207021188A KR 102355989 B1 KR102355989 B1 KR 102355989B1
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node
nodes
response
interrupt
clients
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KR20200100152A (ko
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벤자민 첸
브라이언 피. 브루사드
비디아나탄 칼랴나순다람
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
KR1020207021188A 2017-12-21 2018-09-19 다중 노드 시스템 저전력 관리 Active KR102355989B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/850,261 US10671148B2 (en) 2017-12-21 2017-12-21 Multi-node system low power management
US15/850,261 2017-12-21
PCT/US2018/051789 WO2019125562A1 (en) 2017-12-21 2018-09-19 Multi-node system low power management

Publications (2)

Publication Number Publication Date
KR20200100152A KR20200100152A (ko) 2020-08-25
KR102355989B1 true KR102355989B1 (ko) 2022-02-08

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KR1020207021188A Active KR102355989B1 (ko) 2017-12-21 2018-09-19 다중 노드 시스템 저전력 관리

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Country Link
US (1) US10671148B2 (https=)
EP (1) EP3729233B1 (https=)
JP (1) JP6984022B2 (https=)
KR (1) KR102355989B1 (https=)
CN (1) CN111684426B (https=)
WO (1) WO2019125562A1 (https=)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10725946B1 (en) 2019-02-08 2020-07-28 Dell Products L.P. System and method of rerouting an inter-processor communication link based on a link utilization value
US12416962B2 (en) * 2020-09-24 2025-09-16 Advanced Micro Devices, Inc. Mechanism for performing distributed power management of a multi-GPU system by powering down links based on previously detected idle conditions
US12093689B2 (en) * 2020-09-25 2024-09-17 Advanced Micro Devices, Inc. Shared data fabric processing client reset system and method
US11341069B2 (en) * 2020-10-12 2022-05-24 Advanced Micro Devices, Inc. Distributed interrupt priority and resolution of race conditions
KR102754182B1 (ko) * 2020-11-20 2025-01-15 엘지전자 주식회사 무선랜 시스템에서 송신 mld 내 ap들에 대한 부분 정보를 요청하는 방법 및 장치
CN112612726B (zh) * 2020-12-08 2022-09-27 海光信息技术股份有限公司 基于缓存一致性的数据存储方法、装置、处理芯片及服务器
US11620248B2 (en) * 2021-03-31 2023-04-04 Advanced Micro Devices, Inc. Optical bridge interconnect unit for adjacent processors
US11703932B2 (en) 2021-06-24 2023-07-18 Advanced Micro Devices, Inc. Demand based probe filter initialization after low power state
US11487340B1 (en) * 2021-06-24 2022-11-01 Advanced Micro Devices, Inc. Probe filter retention based low power state
US11989144B2 (en) * 2021-07-30 2024-05-21 Advanced Micro Devices, Inc. Centralized interrupt handling for chiplet processing units
CN114490194B (zh) * 2022-04-19 2022-07-01 海光信息技术股份有限公司 掉电处理方法、功能节点、处理系统、设备和存储介质
CN115269466A (zh) * 2022-07-29 2022-11-01 联想(北京)有限公司 一种电子设备及控制方法
US12566211B2 (en) 2022-10-28 2026-03-03 Advanced Micro Devices, Inc. Peak power package tracking
US12050535B2 (en) * 2022-10-31 2024-07-30 Google Llc Dynamic migration of point-of-coherency and point-of-serialization in NUMA coherent interconnects
CN119292749B (zh) * 2024-10-29 2025-08-22 北京奕斯伟计算技术股份有限公司 集成电路、处理中断请求的方法及系统

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140122833A1 (en) 2009-09-24 2014-05-01 Mark Bradley Davis Server on a chip and node cards comprising one or more of same

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980836A (en) 1988-10-14 1990-12-25 Compaq Computer Corporation Apparatus for reducing computer system power consumption
US5396635A (en) 1990-06-01 1995-03-07 Vadem Corporation Power conservation apparatus having multiple power reduction levels dependent upon the activity of the computer system
US5617572A (en) 1995-01-31 1997-04-01 Dell Usa, L.P. System for reducing power consumption in computers
US5692202A (en) 1995-12-29 1997-11-25 Intel Corporation System, apparatus, and method for managing power in a computer system
US6334167B1 (en) 1998-08-31 2001-12-25 International Business Machines Corporation System and method for memory self-timed refresh for reduced power consumption
US6295573B1 (en) * 1999-02-16 2001-09-25 Advanced Micro Devices, Inc. Point-to-point interrupt messaging within a multiprocessing computer system
US6657634B1 (en) 1999-02-25 2003-12-02 Ati International Srl Dynamic graphics and/or video memory power reducing circuit and method
JP2003308246A (ja) 2002-04-17 2003-10-31 Fujitsu Ltd メモリコントローラのクロック制御装置及び方法
US7028200B2 (en) 2002-05-15 2006-04-11 Broadcom Corporation Method and apparatus for adaptive power management of memory subsystem
US7039740B2 (en) 2002-07-19 2006-05-02 Newisys, Inc. Interrupt handling in systems having multiple multi-processor clusters
US7428644B2 (en) 2003-06-20 2008-09-23 Micron Technology, Inc. System and method for selective memory module power management
US7673164B1 (en) * 2004-12-13 2010-03-02 Massachusetts Institute Of Technology Managing power in a parallel processing environment
US7800621B2 (en) 2005-05-16 2010-09-21 Ati Technologies Inc. Apparatus and methods for control of a memory controller
DE102005037635B4 (de) 2005-08-09 2007-07-12 Infineon Technologies Ag Hardwaresteuerung für den Wechsel des Betriebsmodus eines Speichers
US7496777B2 (en) 2005-10-12 2009-02-24 Sun Microsystems, Inc. Power throttling in a memory system
EP1785982A1 (en) 2005-11-14 2007-05-16 Texas Instruments Incorporated Display power management
US7899990B2 (en) 2005-11-15 2011-03-01 Oracle America, Inc. Power conservation via DRAM access
US7613941B2 (en) 2005-12-29 2009-11-03 Intel Corporation Mechanism for self refresh during advanced configuration and power interface (ACPI) standard C0 power state
US7873850B2 (en) 2006-10-11 2011-01-18 Hewlett-Packard Development Company, L.P. System and method of controlling power consumption and associated heat generated by a computing device
US7743267B2 (en) 2006-11-08 2010-06-22 Xerox Corporation System and method for reducing power consumption in a device
US7868479B2 (en) 2007-06-27 2011-01-11 Qualcomm Incorporated Power gating for multimedia processing power management
JP5169731B2 (ja) 2008-10-24 2013-03-27 富士通セミコンダクター株式会社 マルチプロセッサシステムｌｓｉ
US8181046B2 (en) 2008-10-29 2012-05-15 Sandisk Il Ltd. Transparent self-hibernation of non-volatile memory system
US8195887B2 (en) * 2009-01-21 2012-06-05 Globalfoundries Inc. Processor power management and method
US8359436B2 (en) 2009-12-18 2013-01-22 Intel Corporation Core snoop handling during performance state and power state transitions in a distributed caching agent
US8402232B2 (en) 2009-12-23 2013-03-19 Oracle America, Inc. Memory utilization tracking
JP2011150653A (ja) * 2010-01-25 2011-08-04 Renesas Electronics Corp マルチプロセッサシステム
US8656198B2 (en) 2010-04-26 2014-02-18 Advanced Micro Devices Method and apparatus for memory power management
US8438416B2 (en) 2010-10-21 2013-05-07 Advanced Micro Devices, Inc. Function based dynamic power control
US20120254526A1 (en) 2011-03-28 2012-10-04 Advanced Micro Devices, Inc. Routing, security and storage of sensitive data in random access memory (ram)
US8924758B2 (en) 2011-12-13 2014-12-30 Advanced Micro Devices, Inc. Method for SOC performance and power optimization
WO2013165357A1 (en) 2012-04-30 2013-11-07 Intel Corporation Master slave qpi protocol for coordinated idle power management in glueless and clustered systems
US20140095801A1 (en) 2012-09-28 2014-04-03 Devadatta V. Bodas System and method for retaining coherent cache contents during deep power-down operations
US9213643B2 (en) 2013-03-13 2015-12-15 Applied Micro Circuits Corporation Broadcast messaging and acknowledgment messaging for power management in a multiprocessor system
US9983652B2 (en) 2015-12-04 2018-05-29 Advanced Micro Devices, Inc. Balancing computation and communication power in power constrained clusters
US11054887B2 (en) 2017-12-28 2021-07-06 Advanced Micro Devices, Inc. System-wide low power management

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140122833A1 (en) 2009-09-24 2014-05-01 Mark Bradley Davis Server on a chip and node cards comprising one or more of same

Also Published As

Publication number Publication date
EP3729233B1 (en) 2025-08-06
JP2021507412A (ja) 2021-02-22
EP3729233A1 (en) 2020-10-28
US10671148B2 (en) 2020-06-02
WO2019125562A1 (en) 2019-06-27
CN111684426A (zh) 2020-09-18
US20190196574A1 (en) 2019-06-27
KR20200100152A (ko) 2020-08-25
JP6984022B2 (ja) 2021-12-17
CN111684426B (zh) 2024-11-05

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