KR102344709B1 - Two-dimensional via pillar structures - Google Patents

Abstract

Exemplary embodiments for various via filler structures include one or more second conductors in a second interconnect layer of the semiconductor stack and one or more first conductors in a first interconnect layer of the semiconductor stack interconnected. The one or more first conductors and/or the one or more second conductors in the first interconnect layer and the second interconnect layer may each transverse a plurality of directions. In some circumstances, this may allow multiple interconnects to be utilized to interconnect one or more first conductors and one or more second conductors. These multiple interconnects may reduce resistance between the one or more first conductors and the one or more second conductors to improve performance of signals flowing between the one or more first conductors and the one or more second conductors.

Description

Two-dimensional via pillar structures {TWO-DIMENSIONAL VIA PILLAR STRUCTURES}

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Patent Application No. 62/586,475, filed on November 15, 2017, which is incorporated herein by reference in its entirety.

Continuous improvement of semiconductor manufacturing processes is enabling manufacturers and designers to manufacture smaller and more powerful electronic devices. The semiconductor manufacturing process has evolved from a 10 μm semiconductor manufacturing process reached around 1971 to a 22 nm semiconductor manufacturing process reached around 2012. The semiconductor manufacturing process is expected to accelerate development to 5 nm semiconductor manufacturing process around 2019. However, with each development stage of such a semiconductor manufacturing process, a new problem has been discovered in the formation of an integrated circuit. Often, semiconductor manufacturing processes define one or more electronic design constraints imposed on the manufacture of electronic devices. One such electronic design constraint relates to the spacing between conductors in the conductive layers of the semiconductor stack. To ensure that this electronic design constraint is met, one of the conductive layers of the semiconductor stack is designated to contain conductors in the horizontal direction, and the other of the conductive layers of the semiconductor stack is designated to contain conductors only in the vertical direction. By interconnecting the conductors in the horizontal direction and the conductors in the vertical direction, various components of the electronic device may be interconnected to form the electronic device. However, in some circumstances, this interconnection between the conductors in the horizontal direction and the conductors in the vertical direction undesirably degrades the signal flowing through these conductors, which degrades the performance of the electronic device. For example, the resistance of a conductor and associated interconnect may be characterized as inversely proportional to its physical size. As semiconductor manufacturing processes continue to advance, the physical size of the conductors and associated interconnects becomes smaller, resulting in increased resistance. Also, the resistance of the interconnects undesirably increases the degradation of the electronic device.

Aspects of the present disclosure are best understood from the following detailed description when taken in conjunction with the accompanying drawings. Standard industry practice has shown that various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily increased or decreased for clarity of description.
1 is a block diagram of an exemplary semiconductor stack in accordance with an exemplary embodiment of the present disclosure;
2A-2P are top views of various exemplary two-dimensional via filler structures in accordance with exemplary embodiments of the present disclosure;
3 is a block diagram of an electronic design platform in accordance with an embodiment of the present disclosure;
4 is a block diagram of an exemplary computer system for implementing an exemplary design platform in accordance with a DMKL exemplary embodiment of the present disclosure;
5 is a flow diagram of an exemplary operation for fabricating an exemplary via filler structure in accordance with an exemplary embodiment of the present disclosure.

The following disclosure provides many other embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over a second feature may include an embodiment in which the first and second features are formed to be in direct contact, and the first and second features may not be in direct contact. It may include embodiments in which additional features may be formed between the first and second features. In addition, this disclosure may repeat reference numbers and/or letters in the various examples. This repetition in itself does not indicate a relationship between the various embodiments and/or configurations discussed.

outline

Exemplary embodiments for various via filler structures include one or more second conductors of a second interconnect layer of the semiconductor stack and one or more first conductors of a first interconnect layer of the semiconductor stack interconnected. The one or more first conductors and/or the one or more second conductors in the first interconnect layer and the second interconnect layer may each traverse a plurality of directions. In some circumstances, this allows the use of multiple interconnects, such as vias, to interconnect one or more first conductors and one or more second conductors. These multiple interconnects may improve performance of signals passed between the one or more first conductors and the one or more second conductors by reducing the resistance between the one or more first conductors and the one or more second conductors.

Exemplary semiconductor stack

1 illustrates a block diagram of an exemplary semiconductor stack in accordance with an embodiment of the present disclosure. As illustrated in FIG. 1 , an exemplary semiconductor stack 100 includes one or more interconnect layers 102.1 - 102.m. One or more interconnect layers 102.1 - 102.m may include one or more conductive layers, such as one or more metal routing layers, to provide examples. One or more metal routing layers may be formed of tungsten (W), aluminum (Al), copper (Cu), gold (Au), silver (Ag), platinum (Pt) and/or related art without departing from the spirit and scope of the present disclosure. any other known metal would be apparent to one of ordinary skill in the art. The one or more interconnect layers 102.1 - 102.m may additionally or alternatively include one or more non-conductive layers, such as one or more dielectric layers providing examples. The one or more dielectric layers may include silicon oxide, spin-on glass, silicon nitride, silicon carbide, silicon carbon nitride, silicon oxynitride, silicon oxycarbide, silicon carbon nitride fluorine-doped silicate glass (FSG), a low-k dielectric material and/or the present invention. one or more dielectric materials, such as any other known dielectric, would be apparent to one of ordinary skill in the art without departing from the spirit and scope of the disclosure. In addition, one or more of the interconnect layers 102.1 - 102.m may include one or more of the interconnection layers 102.1 - 102.m, such as one or more via structures illustrated for electrically and/or mechanically interconnecting the various interconnection layers 102.1 - 102.m. It may include more than one interconnection part. The one or more via structures may be implemented as one or more through-hole vias, one or more blind vias, one or more buried vias, or any other suitable via structures apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. . Moreover, those skilled in the relevant art will recognize that the configuration and arrangement of the exemplary semiconductor stack 100 as illustrated in FIG. 1 is provided for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements for one or more interconnect layers 102.1 to 102.m are possible without departing from the spirit and scope of the present disclosure.

In the exemplary embodiment shown in FIG. 1 , one or more interconnect layers 102.1 - 102.m are located on the semiconductor substrate 106 , for example, over the semiconductor substrate 106 . The semiconductor substrate 106 may be a thin piece of semiconductor material, such as a silicon crystal, but other materials, such as sapphire, or any other suitable material apparent to one of ordinary skill in the art without departing from the scope and scope of the present disclosure. may include a combination of In an exemplary embodiment, the exemplary semiconductor stack 100 may further include one or more diffusion layers and/or one or more polysilicon layers. In this exemplary embodiment, one or more active components, such as one or more transistors, such as one or more passive components, such as one or more resistors, and/or one or more capacitors, and/or one or more inductors, and/or one skilled in the art One or more semiconductor components may be formed using one or more diffusion layers and/or one or more polysilicon layers, such as one or more other suitable components apparent to. In some circumstances, one or more semiconductor components may be interconnected to each other and/or to other semiconductor components using one or more interconnection layers 102.1 - 102.m to form one or more integrated circuits.

Exemplary two-dimensional via filler structures

2A-2P illustrate top views of various two-dimensional via filler structures in accordance with example embodiments of the present disclosure. As illustrated in FIGS. 2A-2P , two-dimensional via filler structures 200 - 230 are first conductors of one or more conductive materials formed in a first interconnect layer of a semiconductor stack, such as the illustrated semiconductor stack 100 . 240 and a second conductor 242 of one or more conductive materials formed in the second interconnect layer of the semiconductor stack. Here, the terms "first interconnect layer" and "second interconnect layer" are only used to distinguish an interconnect layer of a semiconductor layer stack. The terms “first interconnect layer” and “second interconnect layer” need not be the first interconnect layer and the second interconnect layer of the semiconductor layer stack, respectively. Rather, one of ordinary skill in the art will recognize that the “first interconnect layer” and the “second interconnect layer” may be any two interconnect layers of the semiconductor layer stack. In an exemplary embodiment, the first interconnect layer and the second interconnect layer represent two conductive layers, for example the illustrated two metal routing layers provided in a semiconductor stack. For convenience, the first conductor is illustrated using black shading and the second conductor is illustrated using white shading in FIGS. 2A-2P . Additionally, the widths of the first conductor 240 and the second conductor 242 are not illustrated to scale in FIGS. 2A-2P . For example, the width of the first conductor 240 is exaggerated in FIGS. 2A-2P for illustrative purposes as those skilled in the art will appreciate without departing from the spirit and scope of the present disclosure. 2A-2P , a first interconnect layer having a first conductor 240 is positioned under a second interconnect layer having a second conductor 242 in the semiconductor layer stack. This exaggeration of the width of the first conductor 240 causes the first conductor 240 to be visible in FIGS. 2A-2P . However, one of ordinary skill in the relevant art will allow the width of the first conductor 240 to be approximately equal to the width of the second conductor 242 and/or the width of the first conductor 240 without departing from the spirit and scope of the present disclosure. ) may be less than the width of the second conductor 242 .

As further illustrated in FIGS. 2A-2P , first conductors 240 traverse multiple directions within the first interconnect layer, and second conductors 242 are similarly multiple within the second interconnect layer. cross the direction of For example, first conductor 240 traverses first direction 250 and second direction 252 within the first interconnect layer as illustrated in FIGS. 2A-2P . In this example, the second conductor 242 similarly transverses the first direction 250 and the second direction 252 within the second interconnect layer. In some of the exemplary embodiments shown in FIGS. 2A-2P , the first conductor 240 may be considered asymmetric with respect to an axis of symmetry traversing the two-dimensional via filler structures 200 - 230 , and the second Conductor 242 may be considered asymmetric about this axis of symmetry. For example, the axis of symmetry may be transverse to the second direction 252 to divide the second conductor 242 into two approximately equal portions of one or more conductive material of the two-dimensional via filler structure 204 as illustrated in FIG. 2C . can be separated. In this example, as illustrated in FIG. 2C , the first conductor 240 can be considered asymmetric to the axis of symmetry 240 perpendicularly transverse to the second conductor 242 in the second direction 252 , Second conductor 242 may be considered symmetrical about axis of symmetry 240 perpendicular to second conductor 242 in second direction 252 . As another example, the axis of symmetry is traversed in the first direction 250 to divide the second conductor 242 into two approximately equal portions of one or more conductive material of the two-dimensional via pillar structure 206 as illustrated in FIG. 2D . can be separated. In this example, as illustrated in FIG. 2D , first conductor 240 may be considered asymmetric with respect to an axis of symmetry that horizontally traverses second conductor 242 in first direction 250 , and Conductor 242 may be considered symmetrical about an axis of symmetry that horizontally traverses second conductor 242 in first direction 250 .

Also, the first conductor 240 and the second conductor 242 are interconnected using multiple interconnects, such as the multi-via structure described above in FIG. 1 , illustrated using a square “x” in FIGS. 2A-2P. The two-dimensional via filler structures 200 to 230 are formed. The multi-via structure may include one or more through-hole vias interconnecting the first conductor 240 and the second conductor 242, one or more blind vias, one or more buried vias, or related art without departing from the spirit and scope of the present disclosure. Multiple electrical connections, such as any other suitable via structures apparent to those skilled in the art, are shown.

In general, the first conductor 240 will be characterized as a first sequence of interconnected sculptural segments of one or more conductive material traversing between a first direction 250 and a second direction 252 within a first interconnection layer. wherein the second conductor 242 may be characterized as a second sequence of interconnected sculptural segments of one or more conductive material traversing between the first direction 250 and the second direction 252 in the second interconnection layer. can For example, as illustrated in FIG. 2A , first conductor 240 may have a first segment transverse to first direction 250 and a second segment transverse to second direction 252 within the first interconnect layer. and may be characterized as a first sequence of sculptural segments of one or more conductive material having segments. In this example, second conductor 242 is formed of one or more conductive materials having a first segment transverse to first direction 250 and a second segment transverse to second direction 252 within a second interconnect layer. can be characterized as a second sequence of sculptural segments.

In some situations, referring to FIGS. 2A-2P , a multi-via structure is a sculpted segment of the first conductor 240 to electrically and/or mechanically interconnect the first conductor 240 and the second conductor 242 . positioned overlapping between the first sequence of and the second sequence of sculptural segments of the second conductor 242 . The multi-via structure as illustrated in FIGS. 2A-2P is for illustrative purposes only. Those skilled in the relevant art will recognize that more or fewer via structures may be applied without departing from the spirit and scope of the present disclosure. For example, as illustrated in FIG. 2A , this overlap between a first sequence of sculptural segments of first conductor 240 and a second sequence of sculptural segments of second conductor 242 is The first sequence of sculptural segments of 240 and the second sequence of sculptural segments of second conductor 242 may occur approximately midway of the segments. In this example, a multi-via structure is positioned between approximately midpoints of the segments to electrically and/or mechanically interconnect the first conductor 240 and the second conductor 242 . As another example, as illustrated in FIG. 2D , this overlap between the first sequence of sculptural segments of first conductor 240 and the second sequence of sculptural segments of second conductor 242 is The first sequence of sculptural segments of 240 and the second sequence of sculptural segments of second conductor 242 may occur at approximately the end points of the segments. In this example, a multi-via structure is positioned between approximately the end points of the segments to electrically and/or mechanically interconnect the first conductor 240 and the second conductor 242 .

In the embodiment illustrated in FIGS. 2A-2P , the multi-via structure uses a single via structure that interconnects the first conductor 240 and the second conductor 242 , compared to using a single via structure 200-230 . ) may reduce the resistance between the first conductor 240 and the second conductor 242 by a factor proportional to the number of via structures. In general, this reduction in resistance can be expressed as:

Here, R _NEW represents the reduced resistance between the first conductor 240 and the second conductor 242 , and R _OLD is a single via structure between the first conductor 240 and the second conductor 242 . is the resistance between the first conductor 240 and the second conductor 242 when having, ψ represents the number of via structures between the first conductor 240 and the second conductor 242 . As an example, two via structures of the two-dimensional via filler structure 200 may reduce the resistance between the first conductor 240 and the second conductor 242 by a factor of two; 2D via filler structure 202 , 2D pillar structure 204 , 2D pillar structure 216 , 2D pillar structure 222 , 2D filler structure 224 , 2D pillar structure 226 , 2 The 3D pillar structure 228 and the three via structures of the 2D pillar structure 230 may reduce the resistance between the first conductor 240 and the second conductor 242 by three factors; The four via structures of the 2D via filler structure 212 , the 2D via filler structure 218 , and the 2D via filler structure 220 are the first conductor 240 and the second conductor 242 by four factors. can reduce the resistance between; The two-dimensional pillar structure 206 and the five via structures of the two-dimensional pillar structure 214 can reduce the resistance between the first conductor 240 and the second conductor 242 by a factor of five; The eight via structures of the two-dimensional pillar structure 208 may reduce the resistance between the first conductor 240 and the second conductor 242 by a factor of eight; The ten via structures of the 2D pillar structure 210 may reduce the resistance between the first conductor 240 and the second conductor 242 by a factor of ten. This reduction in resistance between first and second conductors 240 and 242 improves the performance of the signal flowing between first and second conductors 240 and 242 .

Electronic Design Platform for Implementing Exemplary Via Filler Structures

3 illustrates a block diagram of an electronic design platform in accordance with an exemplary embodiment of the present disclosure. As illustrated in FIG. 3 , the electronic design platform 300 represents a design flow comprising one or more electronic design software applications, the design flow comprising one or more computing devices, processors, controllers, or the spirit and spirit of the present disclosure; One or more high level software level descriptions of analog and/or digital circuits for electronic devices may be designed, simulated, analyzed, and/or verified when executed by other devices apparent to those skilled in the art without departing from their scope. In an exemplary embodiment, the one or more high-level software level descriptions may include, for example, C, System C, C++, a graphical design application such as LabVIEW and/or MATLAB, a general-purpose system design language such as SysML, SMDL and/or SSDL; or a common power format (CPF), combined power format (UPF), or any other suitable high level software language, such as a general purpose system design language, or any other suitable high level software or general purpose system design language apparent to those skilled in the relevant art without departing from the spirit and scope of the present disclosure. , or any other suitable high level software format apparent to those skilled in the relevant art without departing from the spirit and scope of the present disclosure. In the exemplary embodiment shown in FIG. 3 , the electronic design platform 30 includes a synthesis application 302 , a placement and routing application 304 , a simulation application 306 , and a validation application 308 .

In addition, embodiments of the present disclosure may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the present disclosure may be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a device (eg, a computing device). For example, machine-readable media may include non-transitory machine-readable media such as read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; It may include a flash memory device and the like. As another example, machine-readable media may include transitory machine-readable media such as electrical, optical, acoustical, or other forms of propagated signals (eg, carrier waves, infrared signals, digital signals, etc.). Also, firmware, software, routines, and instructions may be described herein as performing specific operations. It should be understood, however, that this description is for convenience only, and that such operations are derived from computing devices, processors, controllers, or other devices executing firmware, software, routines, instructions, or the like in fact. In an exemplary embodiment, the synthesis application 302 , the placement and routing application 30 , the simulation application 306 , and the verification application 308 may include one or more computing devices, processors, controllers, or other devices that do not depart from the spirit and scope of the present disclosure. configuration of one or more computing devices, processors, controllers, or other devices from general-purpose electronic devices to special-purpose electronic devices when executed by other devices apparent to those skilled in the relevant art(s) for one of these applications, as described in more detail below. Represents one or more electronic design software applications executing the above.

The synthesizing application 302 may define one or more characteristics, parameters, or properties of an electronic device as one or more logical operations, one or more arithmetic operations, one or more control operations, and/or apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. into one or more high level software level descriptions of analog and/or digital circuitry of the electronic device, in any other suitable operation or operations. The synthesis application 302 may be configured to validate one or more logical operations, one or more arithmetic operations, one or more control operations, and/or other suitable operations according to one or more characteristics, parameters, or properties of an electronic device as outlined in an electronic design specification. A simulation algorithm may be utilized to simulate a logical operation, one or more arithmetic operations, one or more control operations, and/or other suitable operation or operations.

The placement and routing application 304 transforms one or more high level software level descriptions to form electronic architectural designs for analog and/or digital circuits of an electronic device. The placement and routing application 304 optionally configures one or more logical operations, one or more arithmetic operations, one or more control operations, and/or other suitable operations or operations of one or more high-level software level descriptions to the geometry and/or the geometry. A selection of one or more standard cells within a library of standard cells to transform into interconnections between them forms an electronic architectural design for analog and/or digital circuits of an electronic device. In general, one or more standard cell variants have a function similar to the corresponding standard cell, but differ from the corresponding standard cell in terms of geometry, the location of those geometric shapes, and/or the interconnections between the geometric shapes.

After selecting one or more standard cells from the library of standard cells, the placement and routing application 304 places the one or more selected standard cells in the electronic device design real estate. In an exemplary embodiment, the placement and routing application 304 interconnects one or more selected standard cells by placing one or more conductors of one or more conductive materials traversing the various interconnection layers, thereby enabling analog circuitry and/or digital processing of electronic devices. Forms the electronic architecture design for the circuit. In this exemplary embodiment, the placement and routing application 304 deploys a two-dimensional via filler structure, such as one or more of the two-dimensional via filler structures 200-230 illustrated hereinafter, to the other of the multiple interconnect layers. One or more conductive routings within the connection layer may be interconnected.

The simulation application 306 simulates an electronic architectural design for an analog and/or digital circuit of an electronic device to replicate one or more features, parameters, or attributes of the electronic architectural design for an analog and/or digital circuit of the electronic device. In an exemplary embodiment, the simulation application 306 includes static timing analysis (STA), voltage drop analysis, also referred to as IREM analysis, clock domain cross-validation (CDC check), regularity verification, also referred to as model check, equivalence check, or any other suitable analysis apparent to one of ordinary skill in the relevant art without departing from the spirit and scope of the present disclosure. In a further exemplary embodiment, the simulation application 306 performs alternating current (AC) analysis, such as linear small-signal frequency domain analysis, and/or non-linear breakpoint calculations or sweeping voltages, currents and/or parameters. Direct current (DC) analysis, such as a sequence of computed non-linear operating points, may be performed to perform STA, IREM analysis, or other suitable analysis.

The verification application 306 verifies one or more features, parameters, or attributes of the electronic architectural design for analog circuits and/or digital circuits of the electronic device replicated by the simulation application 306 to meet electronic design specifications. The verification application 308 refers to one or more recommended design rules for electronic architectural designs for analog and/or digital circuits of an electronic device as defined by a semiconductor foundry and/or semiconductor technology node for manufacturing the electronic device. Physical verification, also referred to as design rule check (DRC), may be performed to confirm whether the specified parameters are satisfied.

Example computer system for implementing the example design platform

4 illustrates a block diagram of an exemplary computer system for implementing a design platform in accordance with an exemplary embodiment of the present disclosure. Computer system 400 may be used to implement electronic design platform 100 . However, in some situations, more than one computer system 400 may be used to implement the electronic design platform 100 . After reading this description, it will be apparent to those skilled in the art how to implement the embodiments using other computer systems and/or computer architectures.

The computer system 400 is also referred to as a central processing device or CPU to execute the synthesis application 302 , the batch and routing application 30 , the simulation application 306 and/or the verification application 308 as illustrated in FIG. 3 . one or more processors 404 being One or more processors 404 may be coupled to a communication infrastructure or bus 406 . In an example embodiment, one or more of the one or more processors 404 may be implemented as a graphics processing unit (GPU). GPUs represent specialized electronic circuits designed to expedite mathematically intensive applications on electronic devices. GPUs can have highly parallel structures that are efficient for parallel processing of large blocks of data, such as mathematically intensive data commonly used in computer graphics applications, images, and video.

Computer system 400 also includes user input/output device(s) 403 , such as monitors, keyboards, pointing devices, etc., that communicate with communication infrastructure 406 via user input/output interface(s) 402 . do.

Computer system 400 includes main or primary memory 408, such as random access memory (RAM) as illustrated. Main memory 408 may include one or more levels of cache. Main memory 408 includes control logic (ie, computer software) such as synthesis application 302 , placement and routing application 304 , simulation application 306 and/or verification application 308 as described above in FIG. 3 . and/or storing data. The computer system 400 may include one or more secondary storage devices or to store the synthesis application 302 , the placement and routing application 304 , the simulation application 306 and/or the validation application 308 as described above in FIG. 3 . It may include a memory 410 . The one or more secondary storage devices or memories 410 may include, for example, a hard disk drive 412 and/or a removable storage device or drive 414 . Removable storage device 414 may be a floppy disk drive, magnetic tape drive, compact disk drive, optical storage device, tape backup device, and/or any other storage device/drive. Removable storage drive 414 may interact with removable storage unit 418 . Removable storage unit 418 includes a computer usable or readable storage device that stores computer software (control logic) and/or data. Removable storage unit 418 may be a floppy disk, magnetic tape, compact disk, DVD, optical storage disk, and/or any other computer data storage device. Removable storage drive 414 reads and/or writes to and/or writes to removable storage unit 418 in a well known manner.

According to an exemplary embodiment, the one or more secondary storage devices or memories 410 may include other means, schemes or other approaches to make computer system 400 accessible to computer programs and/or other instructions and/or data. can Such means, schemes or other approaches may include, for example, a removable storage unit 422 and an interface 420 . Examples of removable storage units 422 and interfaces 420 include program cartridges and cartridge interfaces (eg, those found in video game devices), removable memory chips (eg, EPROM or PROM) and associated sockets, memory sticks. and a USB port, a memory card and associated memory card slot and/or any other removable storage unit and associated interface.

Computer system 400 may further include a communication or network interface 424 . The communication or network interface 424 may enable the computer system 400 to communicate and interact with any combination of remote devices, remote networks, remote entities, etc. (individually and collectively indicated at 428 ). For example, the communication or network interface 424 enables the computer system 400 to communicate with the remote device 428 via a communication path 426, which may be wired and/or wireless, the communication path being a LAN; It may include any combination of WAN, Internet, and the like. Control logic and/or data may be transmitted to computer system 400 via communication path 426 .

In one embodiment, a tangible apparatus or article comprising a tangible computer readable or readable medium having control logic (software) stored therein is also referred to herein as a computer program product or program storage device. An immersive manufacturing device or article comprising any combination of the above, of course, includes, but is not limited to, computer system 400 , main memory 408 , secondary memory 410 and removable storage units 418 and 422 . do. Such control logic, when executed by one or more data processing devices (eg, computer system 400 ), causes the data processing devices to operate as described herein.

Based on the teachings contained in this disclosure, it will be apparent to those skilled in the art how to configure and use a data processing device, computer system, and/or computer architecture not illustrated in FIG. 4 .

Exemplary Fabrication of Exemplary Via Filler Structures

5 is a flow diagram of an exemplary operation for fabricating an exemplary via filler structure in accordance with an exemplary embodiment of the present disclosure. The present disclosure is not limited to these operational descriptions. Rather, it will be apparent to those skilled in the art that other operational control flows are within the scope and spirit of the present disclosure. The exemplary operation control flow 500 represents a multi-step sequence of photolithographic and chemical processing steps to form an exemplary two-dimensional via filler structure, such as one or more of the two-dimensional via filler structures 200 - 230 presented by way of example. A multi-step sequence of photolithographic and chemical processing steps may include deposition, removal, and/or patterning operations presented in some examples. A deposition operation refers to a processing operation in which a material is grown coating or transferred. Removal refers to another action in which material is removed. A patterning operation represents a further processing operation in which the material is formed or altered.

In operation 502 , operational control flow 500 forms one or more first conductors, such as first conductor 240 , in the first interconnect layer of the semiconductor stack as illustrated in the illustrated FIGS. 2A-2P . In the exemplary embodiment presented in FIG. 5 , the operational control flow 500 transfers a geometric pattern corresponding to the one or more first conductors to the first interconnect layer. The operational control flow 500 then performs a patterning process that removes a portion of the conductive material from the first interconnect layer according to a geometric pattern to form one or more first conductors. In an exemplary embodiment, the operational control flow 500 utilizes a more advanced semiconductor technology node, such as a 12nm semiconductor technology node, to form one or more primary conductors. In this exemplary embodiment, operation control flow 500 is a patterning process for forming one or more first conductors, including Extreme UltraViolet Lithography (EUV) technology, X-ray lithography technology, electron beam lithography technology, focused ion beam lithography technology, and /or using next-generation lithography (NGL) technology, such as nanoimprint lithography technology. In this exemplary embodiment, use of NGL technology allows one or more first conductors to traverse multiple directions, such as, for example, first direction 250 and second direction 252 illustrated in the first interconnect layer of the semiconductor stack. make it possible For example, the achievable resolution for NGL technology may be such that one or more first conductors within a first interconnect layer of a semiconductor stack only in a single direction, such as the illustrated first direction 250 or second direction 252 , for example. It is lower than the achievable resolution of other conventional lithographic techniques, such as photolithography, which allows traversal.

At operation 504 , operational control flow 500 forms one or more interconnections between the first conductor of operation 502 and the second conductor of operation 506 , described in greater detail below in operation 506 . 5 , the operational control flow 500 forms a plurality of via structures interconnecting the first conductor of operation 502 and the second conductor of operation 506 . The multiple via structures represent multiple electrical connections between the first and second interconnect layers for electrically and/or mechanically and mechanically interconnecting the first conductors 308 and the second conductors 310 . . The multiple via structures may be implemented as one or more through hole vias, one or more blind vias, one or more buried vias, or any other suitable via structures apparent to those skilled in the art without departing from the spirit and scope of the present disclosure.

In operation 506 , the operational control flow 500 forms one or more second conductors in the second interconnect layer of the semiconductor stack, such as the second conductor 242 as described above in the illustrated FIGS. 2A-2P . An exemplary via filler structure is formed. In an exemplary embodiment, the first interconnect layer represents a lower interconnect layer of the interconnect layers of the semiconductor stack, and the second interconnect layer represents an upper interconnect layer of the interconnect layers of the semiconductor stack. In this exemplary embodiment, the lower interconnect layer is positioned over the semiconductor substrate of the semiconductor stack, and the upper interconnect layer is positioned over the lower semiconductor layer. 5, the operational control flow 500 transfers a geometric pattern corresponding to one or more second conductors to the second interconnect layer. The operational control flow 500 then performs a patterning process that removes a portion of the conductive material from the second interconnect layer according to a geometric pattern to form one or more second conductors. In another exemplary embodiment, operational control flow 500 utilizes more advanced semiconductor technology nodes to form one or more secondary conductors in a manner substantially similar to one or more primary conductors as described above. In this other exemplary embodiment, the use of NGL technology allows one or more second conductors within the second interconnect layer of the semiconductor stack to traverse multiple directions, such as first direction 250 and second direction 252 , for example. allow to do For example, the resolution achievable for NGL technology may be such that one or more secondary conductors within a second interconnect layer of a semiconductor stack only in a single direction, such as the illustrated first direction 250 or second direction 252 , for example. It is lower than the achievable resolution of other conventional lithographic techniques, such as photolithography, which allows traversal.

conclusion

The foregoing detailed description discloses a via filler structure. The via filler structure includes a first conductor in a first interconnect layer of the semiconductor stack, a second conductor in a second interconnect layer of the semiconductor stack, and multiple vias electrically and/or mechanically connecting the first conductor and the second conductor. include structures. The first conductor traverses first and second directions in the first interconnect layer of the semiconductor stack, and the second conductor traverses the first direction and the second direction in the second interconnect layer of the semiconductor stack.

The foregoing detailed description discloses other via filler structures. This further via filler structure comprises a first interconnected sculptural segment of a conductive material in a first interconnect layer of the semiconductor stack, a second interconnected sculptural segment of a conductive material in a second interconnect layer of the semiconductor stack, and the and a plurality of via structures electrically connecting a first segment of at least one of the first interconnected sculptural segments and a second segment of at least one of the second interconnected sculptural segments. The first interconnecting sculptural segments traverse multiple directions within a first interconnect layer of the semiconductor stack, and the second interconnected sculptural segments of conductive material traverse multiple directions within a second interconnect layer of the semiconductor stack. traverse

The foregoing detailed description further discloses a method of making a via filler structure. The method includes forming a first conductor traversing a first direction and a second direction in a first interconnect layer of a semiconductor stack, traversing the first direction and a second direction in a second interconnect layer of the semiconductor stack and forming a second conductor, and forming a plurality of via structures connecting the first conductor and the second conductor.

Examples

Example 1. A via filler structure comprising:

a first conductor in a first interconnect layer of the semiconductor stack, the first conductor traversing a first direction and a second direction in the first interconnect layer of the semiconductor stack ;

a second conductor in a second interconnect layer of the semiconductor stack, the second conductor transverse to the first direction and the second direction in the second interconnect layer of the semiconductor stack ; and

a plurality of via structures connecting the first conductor and the second conductor

A via filler structure comprising a.

Embodiment 2. The via pillar structure of Embodiment 1, wherein the first direction is perpendicular to the second direction.

Example 3. The method of Example 2,

The first direction includes the x-axis of the Cartesian coordinate system,

The second direction is a via pillar structure including the y-axis of the Cartesian coordinate system.

Embodiment 4. The embodiment of Embodiment 1, wherein the first conductor comprises a first plurality of interconnected piecewise segments;

and the second conductor comprises a second plurality of interconnected sculptural segments.

Embodiment 5 The first segment of embodiment 1, wherein a first segment of the first plurality of interconnected sculptural segments comprises: a second segment of the second plurality of interconnected sculptural segments; and at midpoints of the second segment,

at least one via structure of the plurality of via structures is positioned between the intermediate points to connect the first segment and the second segment.

Embodiment 6. The second segment of Embodiment 1, wherein a first segment of the first plurality of interconnected sculptural segments comprises a second segment of the second plurality of interconnected sculptural segments; overlap at the terminal points of

and at least one via structure of the plurality of via structures is positioned between the end points to connect the first segment and the second segment.

Embodiment 7. The embodiment of Embodiment 1, wherein the first conductor is asymmetrical to an axis of symmetry traversing through the via pillar structure;

and the second conductor is symmetrical to the axis of symmetry traversing through the via pillar structure.

Embodiment 8 The via pillar structure of embodiment 7, wherein the axis of symmetry traverses through the second conductor in either the first direction or the second direction to separate the second conductor into equal parts.

Example 9. A via filler structure comprising:

a first plurality of interconnected sculptural segments of a conductive material in a first interconnection layer of a semiconductor stack, the first plurality of interconnected sculptural segments in a plurality of directions in the first interconnection layer of the semiconductor stack the first plurality of interconnected sculptural segments traversing

a second plurality of interconnected sculptural segments of a conductive material in a second interconnect layer of the semiconductor stack, the second plurality of interconnected sculptural segments of a conductive material comprising the second interconnect layer of the semiconductor stack the second plurality of interconnected sculptural segments transverse to the plurality of directions within; and

a plurality of via structures connecting a first segment of at least one of the first plurality of interconnected sculptural segments and a second segment of at least one of the second plurality of interconnected sculptural segments

A via filler structure comprising a.

Embodiment 10. The method of embodiment 9, wherein the plurality of directions are

first direction; and

a second direction perpendicular to the first direction

A via filler structure comprising a.

Embodiment 11 The plurality of via structures of Embodiment 9 connecting the one or more first segments and the one or more second segments to a resistance between the one or more first segments and the one or more second segments wherein the via filler structure is proportional to the number of via structures among them.

Embodiment 12. The method of embodiment 9, wherein a first segment of the one or more first segments overlaps a second segment of the one or more second segments at midpoints of the first segment and the second segment; ,

and at least one via structure of the plurality of via structures is positioned between the intermediate points to connect the first segment and the second segment.

Embodiment 13. The method of embodiment 9, wherein a first segment of the one or more first segments overlaps a second segment of the one or more second segments at end points of the second segment;

and at least one via structure of the plurality of via structures is positioned between the end points to connect the first segment and the second segment.

Embodiment 14. The method of embodiment 9, wherein the first conductor is asymmetric to an axis of symmetry traversing through the via pillar structure;

and the second conductor is symmetrical to the axis of symmetry traversing through the via pillar structure.

Embodiment 15. The method of embodiment 14, wherein the axis of symmetry traverses through the second plurality of interconnected sculptural segments in one of the plurality of directions to separate the second conductor into equal parts. via filler structures.

Example 16. A method for manufacturing a via filler structure, comprising:

forming a first conductor transverse to a first direction and a second direction within a first interconnect layer of the semiconductor stack;

forming a second conductor transverse to the first direction and the second direction within a second interconnect layer of the semiconductor stack; and

forming a plurality of via structures to connect the first conductor and the second conductor;

How to include.

Embodiment 17. The method of embodiment 16, wherein the first direction is perpendicular to the second direction.

Embodiment 18. The method of embodiment 16, wherein a resistance between the first conductor and the second conductor is proportional to the number of via structures among the plurality of via structures connecting the first conductor and the second conductor how to be.

Embodiment 19. The method of embodiment 16, wherein forming the first conductor comprises:

forming a first plurality of interconnected sculptural segments within the first interconnect layer of the semiconductor stack;

Forming the second conductor comprises:

forming a second plurality of interconnected sculptural segments within the second interconnect layer of the semiconductor stack;

A first segment of the first plurality of interconnected sculptural segments comprises a second segment of the second plurality of interconnected sculptural segments at midpoints between the first and second segments. overlapped,

The forming of the plurality of via structures includes:

and forming at least one via structure of the plurality of via structures between the intermediate points to connect the first segment and the second segment.

Embodiment 20. The method of embodiment 16, wherein forming the first conductor comprises:

forming a first plurality of interconnected sculptural segments;

Forming the second conductor comprises:

forming a second plurality of interconnected sculptural segments;

a first one of the first plurality of interconnected sculptural segments overlaps a second one of the second plurality of interconnected sculptural segments at distal points of the second segment;

The forming of the plurality of via structures includes:

and forming at least one via structure of the plurality of via structures between the end points to connect the first segment and the second segment.

Claims (7)

In the via pillar structure,
a first conductor in a first interconnect layer of the semiconductor stack, the first conductor traversing a first direction and a second direction in the first interconnect layer of the semiconductor stack ;
a second conductor in a second interconnect layer of the semiconductor stack, the second conductor transverse to the first direction and the second direction in the second interconnect layer of the semiconductor stack ; and
a plurality of via structures connecting the first conductor and the second conductor
including,
wherein the first conductor comprises a first plurality of interconnected piecewise segments and the second conductor comprises a second plurality of interconnected piecewise segments;
the first plurality of interconnected sculptural segments comprising:
a first segment extending in the first direction;
a second segment extending from one end to the other end in the second direction, wherein one end of the second segment is connected to the first segment;
a third segment extending from one end to the other end in the first direction, wherein one end of the third segment is connected to the second segment;
a fourth segment connected to the third segment, the fourth segment including a plurality of first portions extending in the first direction and a plurality of second portions extending in the second direction, wherein the first each of the portions is connected to at least one of the plurality of second portions, each of the second portions is connected to at least one of the plurality of first portions, the fourth segment
including,
wherein the plurality of via structures include first through fourth vias respectively disposed on the first through fourth segments of the first plurality of interconnected sculptural segments;
wherein the second plurality of interconnected sculptural segments are configured to electrically couple the first to fourth vias to each other and to connect adjacent vias a straight distance along the first direction or the second direction. , via filler structures. The via pillar structure of claim 1 , wherein the first direction is perpendicular to the second direction. 3. The method of claim 2,
The first direction includes the x-axis of the Cartesian coordinate system,
The second direction is a via pillar structure including the y-axis of the Cartesian coordinate system. 2. The method of claim 1, wherein the first conductor is asymmetrical to an axis of symmetry traversing through the via pillar structure;
and the second conductor has a symmetrical shape. 5. The via pillar structure of claim 4, wherein the axis of symmetry traverses through the second conductor in the first direction or the second direction to separate the second conductor into equal parts. In the via pillar structure,
a first plurality of interconnected sculptural segments of a conductive material in a first interconnection layer of a semiconductor stack, the first plurality of interconnected sculptural segments in a plurality of directions in the first interconnection layer of the semiconductor stack the first plurality of interconnected sculptural segments traversing
a second plurality of interconnected sculptural segments of a conductive material in a second interconnect layer of the semiconductor stack, the second plurality of interconnected sculptural segments of a conductive material comprising the second interconnect layer of the semiconductor stack the second plurality of interconnected sculptural segments transverse to the plurality of directions within; and
a plurality of via structures connecting at least one of the first plurality of interconnected sculptural segments and at least one of the second plurality of interconnected sculptural segments
including,
the first plurality of interconnected sculptural segments comprising:
a first segment extending in a first direction;
a second segment extending from one end to the other end in a second direction, wherein one end of the second segment is connected to the first segment;
a third segment extending from one end to the other end in the first direction, wherein one end of the third segment is connected to the second segment;
a fourth segment connected to the third segment, the fourth segment including a plurality of first portions extending in the first direction and a plurality of second portions extending in the second direction, wherein the first each of the portions is connected to at least one of the plurality of second portions, each of the second portions is connected to at least one of the plurality of first portions, the fourth segment
including,
the plurality of via structures comprising first through fourth vias respectively disposed on the first through fourth segments of the first plurality of interconnected sculptural segments;
wherein the second plurality of interconnected sculptural segments are configured to electrically couple the first to fourth vias to each other and to connect adjacent vias a straight distance along the first direction or the second direction. , via filler structures. A method for manufacturing a via filler structure comprising:
forming a first conductor transverse to a first direction and a second direction within a first interconnect layer of the semiconductor stack;
forming a second conductor transverse to the first direction and the second direction within a second interconnect layer of the semiconductor stack; and
forming a plurality of via structures to connect the first conductor and the second conductor;
including,
Forming the first conductor comprises:
forming a first segment extending in the first direction;
forming a second segment extending from one end to the other end in the second direction, wherein one end of the second segment is connected to the first segment;
forming a third segment extending from one end to the other end in the first direction, wherein one end of the third segment is connected to the second segment;
forming a fourth segment connected to the third segment, the fourth segment comprising a plurality of first portions extending in the first direction and a plurality of second portions extending in the second direction; , each of the first portions is connected with at least one of the plurality of second portions, and each of the second portions is connected with at least one of the plurality of first portions, forming the fourth segment step
including,
The plurality of via structures may include first to fourth vias respectively disposed on the first to fourth segments,
Forming the second conductor comprises:
forming segments connecting adjacent vias at a linear distance along the first direction or the second direction to electrically couple the first to fourth vias to each other;
A method comprising:

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