KR102342315B1 - Semiconductor apparatus and semiconductor system - Google Patents

Abstract

A semiconductor device includes one or more main memory cells and one or more spare memory cells; and generating shift values respectively corresponding to the main memory cells based on defect information of one or more defective memory cells, and shifting one or more first bits from the main memory cells in the direction of the spare memory cell by the shift values. and a control unit configured to write to the cells.

Description

Semiconductor device and semiconductor system

The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device capable of storing data.

A semiconductor device, particularly a semiconductor memory device, may be used to store data. A semiconductor memory device may be largely divided into a nonvolatile memory device and a volatile memory device.

The nonvolatile memory device may retain stored data even when power is not applied. Nonvolatile memory devices include flash memory devices such as NAND Flash or NOR Flash, Ferroelectrics Random Access Memory (FeRAM), Phase-Change Random Access Memory (PCRAM), Magnetic Random Access Memory (MRAM), or It may include resistive random access memory (ReRAM) and the like.

The volatile memory device may not retain stored data and may lose it when power is not applied. The volatile memory device may include static random access memory (SRAM) or dynamic random access memory (DRAM).

SUMMARY OF THE INVENTION An aspect of the present invention is to provide a semiconductor device and a semiconductor system that provide a maximized memory capacity and an improved yield rate by efficiently utilizing a spare cell in preparation for a defective cell.

A semiconductor device according to an embodiment of the present invention includes one or more main memory cells and one or more spare memory cells; and generating shift values respectively corresponding to the main memory cells based on defect information of one or more defective memory cells, and shifting one or more first bits from the main memory cells in the direction of the spare memory cell by the shift values. It may include a control unit configured to write to the cells.

A semiconductor system according to an embodiment of the present invention includes one or more main signal lines and one or more spare signal lines; Shift values corresponding to each of the main signal lines are generated based on defect information of one or more defective signal lines, and one or more first signals are respectively shifted from the main signal lines in the direction of the spare signal line by the shift values. a first semiconductor device configured to transmit to the signal lines; and a second semiconductor device configured to equally generate the shift values and receive the first signals from the shifted signal lines based on the shift values.

A semiconductor device and a semiconductor system according to an embodiment of the present invention may provide a maximized memory capacity and an improved yield rate by efficiently utilizing a spare cell in preparation for a defective cell.

1 is a block diagram schematically illustrating a semiconductor device according to an embodiment of the present invention;
2 is a diagram exemplarily showing shift values generated for main memory cells;
3 is a diagram specifically illustrating an operation method of the shift value generator of FIG. 1;
4 is a block diagram schematically illustrating a semiconductor device according to an embodiment of the present invention;
FIG. 5 is a diagram for exemplarily explaining a method of the vector generator of FIG. 4 generating encoding vectors; FIG.
FIG. 6 is a diagram for exemplarily explaining a method in which the encoder of FIG. 4 generates second data based on the first data;
7 is a diagram for illustratively explaining a method for the vector generator of FIG. 4 to generate decoded vectors;
FIG. 8 is a diagram for exemplarily explaining a method in which the decoder of FIG. 4 recovers first data based on second data;
9 is a block diagram illustrating a shift value generator according to an embodiment of the present invention;
10 is a block diagram illustrating a vector generator according to an embodiment of the present invention;
11 is a block diagram exemplarily illustrating a semiconductor system according to an embodiment of the present invention.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

1 is a block diagram schematically illustrating a semiconductor device 100 according to an embodiment of the present invention.

Referring to FIG. 1 , a semiconductor device 100 may include a memory area 110 and a controller 120 .

The memory area 110 may store data DATA transmitted from an external device under the control of the controller 120 . The memory area 110 may include a plurality of main memory cells MC0 to MCm and spare memory cells SC0 to SCs for storing data DATA. The main memory cells MC0 to MCm and the spare memory cells SC0 to SCs may correspond to a single row address and may respectively correspond to a plurality of consecutive column addresses. Column addresses may be sequentially allocated, for example, in a direction of a spare memory cell. That is, among the main memory cells MC0 to MCm, the column address of the first main memory cell MC0 may be the first, and the column address of the last spare memory cell SCs may be the last. However, the order of these column addresses is assumed to facilitate the description of the invention below by allocating relative positions to the memory cells. According to an embodiment, column addresses may be allocated to the main memory cells MC0 to MCm and the spare memory cells SC0 to SCs in a different order.

The main memory cells MC0 to MCm may be regions accessible to an external device. That is, the external device may instruct the semiconductor device 100 to perform a write operation and a read operation by designating a row address and a column address of the main memory cells MC0 to MCm.

The spare memory cells SC0 to SCs may be used to compensate for memory capacity insufficient due to one or more defective memory cells included in the main memory cells MC0 to MCm. That is, when the main memory cells MC0 to MCm include defective memory cells, the semiconductor device 100 may store data using the spare memory cells SC0 to SCs. The spare memory cells SC0 to SCs may be aligned to one side of the main memory cells MC0 to MCm, that is, in the direction of the spare memory cell. Meanwhile, hereinafter, the direction opposite to the spare memory cell direction may be referred to as a main memory cell direction.

1 exemplarily illustrates main memory cells MC0 to MCm and spare memory cells SC0 to SCs corresponding to one row address, the memory area 110 is a main memory corresponding to a plurality of row addresses. It may further include cells and spare memory cells.

The controller 120 may receive a write request for data DATA with respect to the row address RA and the column address CA of the main memory cells MC0 to MCm from an external device, and may perform a write operation. In this case, the controller 120 is configured to control the row address RA based on the defect information FINF, that is, the location information of the defective memory cells included in the main memory cells MC0 to MCm and the spare memory cells SC0 to SCs. , one or more bits included in the data DATA may be stored only in normal memory cells excluding defective memory cells among the main memory cells MC0 to MCm and the spare memory cells SC0 to SCs.

Specifically, the controller 120 may generate shift values corresponding to the main memory cells MC0 to MCm, respectively, based on the defect information FINF. In addition, the controller 120 shifts the bits of the data DATA instructed to be written by the external device to the predetermined main memory cell from the predetermined main memory cell toward the spare memory cell by a shift value corresponding to the predetermined main memory cell. can be stored in As will be described in detail with reference to FIG. 2 , shift values corresponding to the main memory cells MC0 to MCm are normal memory cells among the main memory cells MC0 to MCm and the spare memory cells SC0 to SCs. ) can be created to store bits of

Meanwhile, the external device may recognize that the data DATA is stored in the main memory cells MC0 to MCm and instruct the controller 120 to read the data DATA from the main memory cells MC0 to MCm. The controller 120 may receive a read request for data DATA with respect to the row addresses RA and column addresses CA of the main memory cells MC0 to MCm from an external device, and may perform a read operation. In this case, the controller 120 controls the data DATA stored in normal memory cells among the main memory cells MC0 to MCm and the spare memory cells SC0 to SCs based on the defect information FINF of the row address RA. bits can be read. That is, since the controller 120 stores the data DATA in the normal memory cells by avoiding the defective memory cells through the defect information FINF when performing a write operation, the controller 120 stores the defect information FINF even when performing a read operation. The data DATA may be read from the normal memory cells by avoiding the defective memory cells. To this end, the controller 120 equally generates shift values corresponding to the main memory cells MC0 to MCm generated for the write operation based on the defect information FINF, and generates data DATA based on the shift values. can lead

The controller 120 may include a defect information manager 121 and a shift value generator 122 .

The defect information manager 121 may store the defect information FINF of the memory area 110 . The defect information manager 121 may store the defect information FINF corresponding to each of a plurality of row addresses of the memory area 110 . When a write operation or a read operation is performed, the defect information manager 121 generates the defect information FINF corresponding to the row address RA in response to the row address RA provided from the external device, and generates the shift value generator 122 . ) can be provided. The defect information FINF corresponding to the row address RA includes location information of defective memory cells among the main memory cells MC0 to MCm and the spare memory cells SC0 to SCs of the row address RA, for example, a defect. It may include column addresses of memory cells.

The shift value generating unit 122 is configured to perform a write operation on the main memory cells MC0 to MCm to be performed based on the defect information FINF transmitted from the defect information management unit 121 and the column address CA transmitted from the external device. It is possible to generate shift values respectively corresponding to . The shift value generator 122 compares the column address CA instructed to write the data DATA by the external device with the column addresses of the defective memory cells included in the defect information FINF to obtain the data DATA. Shift values may be generated such that bits are stored in normal memory cells by skipping defective memory cells. A specific operation method of the shift value generator 122 will be described in detail with reference to FIGS. 2 and 3 .

Meanwhile, the controller 220 may further receive a read/write signal RW indicating whether a read operation or a write operation is performed from an external device.

Meanwhile, the semiconductor device 100 may include a nonvolatile memory device or a volatile memory device. Nonvolatile memory devices include flash memory devices such as NAND Flash or NOR Flash, Ferroelectrics Random Access Memory (FeRAM), Phase-Change Random Access Memory (PCRAM), Magnetic Random Access Memory (MRAM), or It may include resistive random access memory (ReRAM) and the like. The volatile memory device may include static random access memory (SRAM) and dynamic random access memory (DRAM). However, the semiconductor device 100 of the present invention is not limited thereto, and may include other types of semiconductor memory devices.

2 is a diagram exemplarily illustrating shift values generated with respect to the main memory cells C0 to C5. FIG. 2 further shows memory cells C6 to C7 positioned in the spare memory cell direction after the main memory cells C0 to C5. The memory cells C6 to C7 may be spare memory cells or main memory cells. The memory cells C0 to C7 may correspond to the same row address RA, and may be sequentially assigned column addresses CA0 to CA7 in the direction of the spare memory cell. In this case, the memory cells C0 to C7 may include defective memory cells C1 and C4 and normal memory cells C0 , C2 , C3 , C5 to C7 .

Referring now to FIG. 2 , since the normal memory cell C0 is writeable, a shift value SHV corresponding to the normal memory cell C0 may be generated as “0”. Accordingly, data instructed by the external device to be stored in the normal memory cell C0 may be directly stored in the normal memory cell C0 based on the shift value SHV of “0”.

The shift value SHV corresponding to the defective memory cell C1 may be “1” because the normal memory cell C2 that follows the defective memory cell C1 by “1” is writeable. Accordingly, data instructed by the external device to be stored in the defective memory cell C1 may be stored in the normal memory cell C2 based on the shift value SHV of “1”.

The shift value SHV corresponding to the normal memory cell C2 may be generated as “1” because the normal memory cell C3 that follows the normal memory cell C2 by “1” is writeable. That is, once the preceding data is shifted, subsequent data must also be shifted continuously, so the data instructed by the external device to be stored in the normal memory cell C2 is transmitted to the normal memory cell C3 based on the shift value SHV “1”. can be stored in

The shift value SHV corresponding to the normal memory cell C3 may be generated as “2” because the normal memory cell C5 that follows the normal memory cell C3 by “2” is writeable. That is, data instructed by the external device to be stored in the normal memory cell C3 may be stored in the normal memory cell C5 by skipping the defective memory cell C4 based on the shift value SHV of “2”.

The shift value SHV corresponding to the defective memory cell C4 may be “2” because the normal memory cell C6 that follows the defective memory cell C4 by “2” is writeable. Accordingly, data instructed by the external device to be stored in the defective memory cell C4 may be stored in the normal memory cell C6 based on the shift value SHV of “2”.

The shift value SHV corresponding to the normal memory cell C5 may be generated as “2” because the normal memory cell C7 that follows the normal memory cell C5 by “2” is writeable. Accordingly, data instructed by the external device to be stored in the normal memory cell C5 may be stored in the normal memory cell C7 based on the shift value SHV of “2”.

In summary, the shift value SHV corresponding to the predetermined main memory cell may be a value in which data instructed by an external device to be stored in the predetermined main memory cell is shifted from the predetermined main memory cell to a normal memory cell where it is actually stored. Accordingly, data instructed by the external device to be stored in the predetermined main memory cell may be stored in the normal memory cell shifted by the shift value SHV from the predetermined main memory cell toward the spare memory cell.

FIG. 3 is a diagram specifically illustrating an operation method of the shift value generator 122 of FIG. 1 .

Referring to FIG. 3 , the shift value generator 122 receives defect information FINF corresponding to the row address RA from the defect information manager 121 of FIG. 1 , that is, column addresses FA0 to FA0 of defective memory cells. FA(n-1)) may be received. Also, the shift value generator 122 may receive a column address CA of a predetermined main memory cell instructing an external device to perform a write operation.

In steps S10 to S14 , the shift value generator 122 converts the column address CA of the predetermined main memory cell to the reference column address based on the column addresses FA0 to FA(n-1) of the defective memory cells. A shift value SHV corresponding to a predetermined main memory cell may be generated by comparing the values. When a write operation is instructed to be performed on two or more main memory cells, the shift value generator 122 repeatedly performs the procedure shown in FIG. 3 to generate a shift value SHV for each of the corresponding main memory cells. can do. In steps S10 to S14 , the column addresses FA0 to FA(n-1) of the defective memory cells are determined from the column address FA0 of the first defective memory cell to the column address FA(n-1) of the last defective memory cell. )) may be sequentially applied according to the direction of the spare memory cell.

First, in step S10 , the shift value generator 122 determines whether the column address CA of the main memory cell precedes the first reference column address, ie, the column address FA0 of the first defective memory cell, and determines A shift value SHV may be generated according to the result. Specifically, when the column address CA of the main memory cell precedes the column address FA0 of the first defective memory cell, the shift value generator 122 may generate the shift value SHV as “0”. However, when the column address CA of the main memory cell does not precede the column address FA0 of the first defective memory cell, that is, the column address CA of the main memory cell is equal to the column address FA0 of the first defective memory cell. When equal or behind, the procedure may move to step S11.

In step S11 , the shift value generator 122 determines whether the column address CA of the main memory cell precedes the second reference column address FA1-1, and generates a shift value SHV according to the determined result. can do. The second reference column address FA1-1 may be a column address preceding the column address FA1 of the second defective memory cell by “1”. Specifically, when the column address CA of the main memory cell precedes the second reference column address FA1-1, the shift value generator 122 may generate the shift value SHV as “1”. However, when the column address CA of the main memory cell does not precede the second reference column address FA1-1, that is, the column address CA of the main memory cell is equal to the second reference column address FA1-1, or In case of a turn, the procedure may move to the next step.

This procedure may be repeated until the column address FA(n-1) of the last defective memory cell. Specifically, in a certain intermediate step ( S12 ), the shift value generator 122 determines that the column address CA of the main memory cell is the “i”-th reference column address FA(i-1)-(i-1). ), and may generate a shift value SHV according to the determined result. The "i"-th reference column address FA(i-1)-(i-1)) is a column address preceding the column address FA(i-1) of the "i"-th defective memory cell by "i-1" can be Specifically, when the column address CA of the main memory cell precedes the "i"-th reference column address FA(i-1)-(i-1), the shift value generator 122 generates the shift value SHV ) can be created as "i-1". However, when the column address CA of the main memory cell does not precede the "i"-th reference column addresses FA(i-1)-(i-1), that is, the column address CA of the main memory cell When the "i"-th reference column address is equal to or behind the FA(i-1)-(i-1)), the procedure may move to the next step S13.

In step S13 , the shift value generator 122 determines whether the column address CA of the main memory cell precedes the “i+1”-th reference column address FAi-i, and the shift value according to the determined result (SHV) can be created. The "i+1"th reference column address FAi-i may be a column address preceding the column address FAi of the "i+1"th defective memory cell by "i". Specifically, when the column address CA of the main memory cell precedes the “i+1”-th reference column address FAi-i, the shift value generator 122 generates the shift value SHV as “i”. can do. However, when the column address CA of the main memory cell does not precede the "i+1"-th reference column address FAi-i, that is, the column address CA of the main memory cell is the "i+1"-th reference column address. When it is equal to or after the column address FAi-i, the procedure can move to the next step.

When the procedure continues and the final step S14 is reached, the shift value generator 122 determines that the column address CA of the main memory cell is the "n"th reference column address FA(n-1)-(n-1). )), and may generate a shift value (SHV) according to the determined result. The "n"th reference column address FA(n-1)-(n-1)) is a column preceding the column address FA(n-1) of the last "n"th defective memory cell by "n-1" It can be an address. Specifically, when the column address CA of the main memory cell precedes the "n"-th reference column address FA(n-1)-(n-1), the shift value generator 122 generates the shift value SHV ) can be created as "n-1". However, when the column address CA of the main memory cell does not precede the "n"-th reference column addresses FA(n-1)-(n-1), that is, the column address CA of the main memory cell When it is equal to or behind the "n"th reference column address FA(n-1)-(n-1), the shift value generator 122 may generate the shift value SHV as "n".

In summary, if the shift value SHV corresponding to a predetermined main memory cell maintains the shift value SHV corresponding to the previous main memory cell, but is shifted to the defective memory cell by the maintained shift value SHV, can be created by incrementing further by 1". Also, according to the procedure illustrated in FIG. 3 , the shift value generator 122 may generate a shift value SHV corresponding to a corresponding main memory cell even if any main memory cell is randomly accessed. As a result, data instructed by an external device to be written to a certain main memory cell can be written to a normal memory cell while avoiding defective memory cells.

4 is a block diagram schematically illustrating a semiconductor device 200 according to an embodiment of the present invention.

Referring to FIG. 4 , the semiconductor device 200 may include a memory area 210 and a controller 220 . The memory area 210 may have the same configuration as the memory area 110 of FIG. 1 .

When the controller 220 receives a write request for the first data DATA1 with respect to the row address RA and the column address CA of the main memory cells MC0 to MCm from the external device, the control unit 220 receives a write request for the main memory cells MC0 to MCm. ), the second data DATA2 is generated from the first data DATA1 based on shift values SHV corresponding to the main memory cells MC0 to MCm, and the second data DATA2 is DATA2) may be stored in the main memory cells MC0 to MCm and the spare memory cells SC0 to SCs. Also, when receiving a read request of the first data DATA1 for the row address RA and the column addresses CA of the main memory cells MC0 to MCm from the external device, the controller 220 receives a read request from the main memory cells MC0 to MCm. The second data DATA2 is read from the MC0 to MCm and the spare memory cells SC0 to SCs, and the second data DATA2 is read from the second data DATA2 based on the shift values SHV corresponding to the main memory cells MC0 to MCm. The first data DATA1 may be recovered.

In summary, the controller 220 stores the first data DATA1 transmitted from the external device in the normal memory cells by avoiding defective memory cells included in the main memory cells MC0 to MCm to store the second data DATA2 . By relocating to , the second data DATA2 may be substantially written to the main memory cells MC0 to MCm and the spare memory cells SC0 to SCs. That is, the second data DATA2 may be generated by rearranging bits of the first data DATA1 to positions of normal memory cells. In addition, the second data DATA2 may include dummy bits inserted at positions of defective memory cells.

The controller 220 may include a defect information manager 221 , a shift value generator 222 , a vector generator 223 , an encoder 224 , and a decoder 225 . The defect information manager 221 and the shift value generator 222 may be configured and operated in the same manner as the defect information manager 121 and the shift value generator 122 shown in FIG. 1 , and thus detailed descriptions thereof will be omitted.

The vector generator 223 may select one or more encoding vectors based on shift values SHV corresponding to the main memory cells MC0 to MCm generated by the shift value generator 222 when a write operation is performed. (EV) can be created. The encoding vectors EV may respectively correspond to the main memory cells MC0 to MCm and the spare memory cells SC0 to SCs in which the second data DATA2 is to be stored. Each of the encoding vectors EV may be used by the encoder 224 to generate a bit of the second data DATA2 to be stored in a corresponding memory cell. A method of generating the encoding vector EV by the vector generator 223 will be described in detail with reference to FIG. 5 .

The encoder 224 may generate the second data DATA2 from the first data DATA1 based on the encoding vectors EV. In particular, the encoder 224 may generate one or more bits of the second data DATA2 in parallel. An operation method of the encoder 224 will be described in detail with reference to FIG.

Also, when a read operation is performed, the vector generator 223 may be configured to perform one or more decoding vectors based on shift values SHV corresponding to the main memory cells MC0 to MCm generated by the shift value generator 222 . DVs can be created. The decoding vectors DV may respectively correspond to the main memory cells MC0 to MCm instructed by the external device to read the first data DATA1 . Each of the decoding vectors DV may be used by the decoder 225 to recover a bit of the first data DATA1 that has been instructed to be stored in a corresponding main memory cell. A method of generating the decoded vector DV by the vector generator 223 will be described in detail with reference to FIG. 7 .

The decoder 225 may recover the first data DATA1 from the second data DATA2 based on the decoding vectors DV. In particular, the decoder 225 may recover bits of the first data DATA1 in parallel. An operation method of the decoder 225 will be described in detail with reference to FIG. 8 .

FIG. 5 is a diagram for exemplarily explaining a method of generating the encoding vectors EV0 to EV7 by the vector generator 223 of FIG. 4 . FIG. 5 shows, for example, the memory cells C0 to C5 generated with reference to FIG. 2 when the external device instructs the write operation of the first data DATA1 to the main memory cells C0 to C5. A process in which encoding vectors EV0 to EV7 respectively corresponding to the memory cells C0 to C7 are generated based on the respective shift values SHV is illustrated.

5. First, if there are "s" spare memory cells for a single row address RA, "s" defective memory cells will be allowed. And, if there are “s” number of spare memory cells for a single row address RA, that is, if there are a maximum of “s” number of defective memory cells, the shift value SHV may be generated with a maximum of “s”. .

In this case, when “s” number of spare memory cells exist for a single row address RA, a single encoding vector may include “s+1” number of vector elements. Hereinafter, it will be assumed that there are “2” spare memory cells for the row address RA, and therefore, each of the encoding vectors EV0 to EV7 may include “3” vector elements. In addition, the predetermined shift value SHV may correspond to a predetermined value of the encoding vector. For example, a shift value (SHV) “0” corresponds to the encoding vector “001”, a shift value (SHV) “1” corresponds to the encoding vector “010”, and a shift value (SHV) “2” corresponds to the encoding vector “001”. It can correspond to "100".

Meanwhile, among the shift values SHV corresponding to the memory cells C0 to C5 , the shift value SHV corresponding to the first main memory cell C0 is the start bit of the first data DATA1 , that is, the least significant bit. As a start bit of the second data DATA2 , it may indicate a rearranged position. Currently, since the shift value SHV corresponding to the memory cell C0 is “0”, the start bit of the first data DATA1 is not shifted and may be stored in the memory cell C0 as it is, and the memory cell C0 ) may be a start memory cell of a write operation of the second data DATA2 .

In this situation, the encoding vectors EV0, EV2, EV3, EV5 to EV7 corresponding to the respective shift values SHV skip the defective memory cells C1 and C4, and start the normal memory cells from the start memory cell C0. (C0, C2, C3, C5 to C7) may be sequentially corresponding. In addition, the defective memory cells C1 and C4 may correspond to arbitrary dummy encoding vectors EV1 and EV4. A position at which the dummy encoding vectors EV1 and EV4 are inserted is between consecutive encoding vectors having different values among the encoding vectors EV0, EV2, EV3, and EV5 to EV7, for example, "001" and " between the consecutive encoding vectors EV0, EV2 with 010" and the continuous encoding vectors EV3, EV5 with "010" and "100". As illustrated in each of the dummy encoding vectors EV1 and EV4, for example, an encoding vector disposed immediately before may be overlapped. However, since the dummy encoding vectors EV1 and EV4 are used to select dummy bits to be stored in the defective memory cells C1 and C4, as will be described later, they may be generated with different values.

As a result, the encoding vectors EV0 to EV7 may be generated by the sum of the number of the memory cells C0 to C5 and the number of defective memory cells C1 and C4 included in the memory cells C0 to C5 . That is, the encoding vectors EV0 to EV7 are generated not only for the memory cells C0 to C5 to which the external device has instructed the write operation, but also for the memory cells C6 and C7 to supplement the defective memory cells C1 and C4. can be As will be described in detail with reference to FIG. 6 , each of the encoding vectors EV0 to EV7 may be used to select a bit of the second data DATA2 to be stored in a corresponding memory cell from the first data DATA1 .

FIG. 6 is a diagram for exemplarily explaining a method in which the encoder 224 of FIG. 4 generates the second data DATA2 based on the first data DATA1 . 6 shows the first data DATA1 and the encoding vectors EV0 to EV7 generated in FIG. 5 when the external device instructs the write operation of the first data DATA1 to the memory cells C0 to C5. A process in which the second data DATA2 is generated based on , and the second data DATA2 is actually written to the memory cells C0 to C7 is illustrated. As a result of writing the second data DATA2 to the memory cells C0 to C7 , the bits b0 to b5 of the first data DATA1 may avoid defective memory cells and be stored in normal memory cells.

Referring to FIG. 6 , the encoder 224 may generate bits of the second data DATA2 in parallel based on the first data DATA1 and the encoding vectors EV0 to EV7 .

First, the encoder 224 may generate the encoding bit groups EG0 to EG7 based on the first data DATA1 . The encoding bit groups EG0 to EG7 may respectively correspond to the memory cells C0 to C7 to which the second data DATA2 is to be written. As a result, the encoding bit groups EG0 to EG7 may be generated by the same number as the encoding vectors EV0 to EV7 and may respectively correspond to the encoding vectors EV0 to EV7.

The encoding bit groups EG0 to EG7 may be generated according to a predetermined rule when only the first data DATA1 is received regardless of the presence or location of defective memory cells. First, when there are “s” spare memory cells for a single row address RA, any single encoding bit group may include “s+1” bit components. As it is assumed in FIG. 5 that "2" spare memory cells exist for the row address RA, each of the encoding bit groups EG0 to EG7 may include "3" bit components. .

Bit components included in each of the encoding bit groups EG0 to EG7 may include one or more candidate bit components selected from bits b0 to b5 of the first data DATA1 . Specifically, the candidate bit components included in each of the encoding bit groups EG0 to EG7 are stored in the corresponding memory cell among the bits b0 to b5 of the first data DATA1 if the corresponding memory cell is a normal memory cell. It may be bits that are likely to be stored. Some encoding bit groups EG0, EG1, EG6, EG7 may include fewer than “3” candidate bit components, and in this case may include a dummy bit component, for example, “0”.

For example, among the bits b0 to b5 of the first data DATA1 , only the bit b0 is likely to be stored in the memory cell C0 . That is, when the memory cell C0 is a normal memory cell, the bit b0 may be stored in the memory cell C0. Accordingly, the encoding bit group EG0 corresponding to the memory cell C0 may include two “0s” as candidate bit components b0 and dummy bit components.

Also, among the bits b0 to b5 of the first data DATA1 , bits that are likely to be stored in the memory cell C1 may be bits b0 and b1 . That is, when the memory cell C0 is a defective memory cell, the bit b0 may be stored in the memory cell C1 , and when the memory cells C0 and C1 are all normal memory cells, the bit b1 is stored in the memory cell C1 . ) can be stored in Accordingly, the encoding bit group EG1 corresponding to the memory cell C1 may include the candidate bit components b0 and b1 and one “0” as the dummy bit component.

And, among the bits b0 to b5 of the first data DATA1 , only the bit b5 is likely to be stored in the memory cell C7 . That is, in a state where up to two defective memory cells are allowed as assumed, when the memory cells C0 to C5 include two defective memory cells, the bit b5 may be stored in the memory cell C7 . Accordingly, the encoding bit group EG7 corresponding to the memory cell C7 may include two “0s” as a candidate bit component b5 and a dummy bit component.

That is, the present invention collectively generates the candidate bit components of the encoding bit groups EG0 to EG7 in consideration of this possibility, and then the encoding vectors EV0 to EV0 to which the actual positions of the defective memory cells C1 and C4 are reflected. EV7), any one of the candidate bit components may be selected. A method of generating the encoding bit groups EG2 to EG6 corresponding to the remaining memory cells C2 to C6 can be easily applied to a person skilled in the art according to the above-described rule, and thus a detailed description thereof will be omitted.

Also, candidate bit components in each of the encoding bit groups EG0 to EG7 may be arranged according to a predetermined method. For example, candidate bit components included in a single encoding bit group are arranged as lower candidate bit components in the encoding bit group as higher bits in the first data DATA1 are higher, and “0s”, which are dummy bit components, are encoded in the encoding bit group. can be aligned to the remaining positions of . For example, in the encoding bit group EG0, the candidate bit component b0 becomes the least significant bit component, and “0s” may be aligned at the remaining positions. For example, in the encoding bit group G1, the candidate bit component b1 becomes the least significant bit component, the candidate bit component b0 becomes the next least significant bit component, and "0s" are to be aligned in the remaining positions. can

Also, the encoder 224 may include operation units OP0 to OP7 that generate the second data DATA2 in parallel. Each of the operation units OP0 to OP7 may receive an encoding vector and an encoding bit group corresponding to each other and perform a bitwise operation to output bits to be included in the second data DATA2 . Each of the operation units OP0 to OP7 may output any one of the candidate bit components of the received encoding bit group based on the received encoding vector. Specifically, each of the operation units OP0 to OP7 may output a candidate bit component corresponding to the vector component “1” of the received encoding vector, that is, arranged at the same position as the vector component “1”.

As a result, the encoder 224 uses the bits b0 to b5 of the first data DATA1 to avoid the defective memory cells C1 and C4 to position the normal memory cells C0, C2, C3, C5 to C7. By rearranging , the second data DATA2 may be generated. A dummy bit, for example, a bit b1 that would have been stored if the defective memory cell C1 was a normal memory cell, may be stored in the defective memory cell C1 . A dummy bit, for example, a bit b3 that would have been stored if the defective memory cell C4 was a normal memory cell, may be stored in the defective memory cells C4 .

FIG. 7 is a diagram for exemplarily explaining a method in which the vector generator 223 of FIG. 4 generates decoding vectors DV0 to DV5. 7 illustrates, for example, shift values SHV corresponding to each of the memory cells C0 to C5 when the external device instructs a read operation of the first data DATA1 with respect to the main memory cells C0 to C5. ), a process in which decoding vectors DV0 to DV5 corresponding to the memory cells C0 to C5 are generated, respectively.

Before describing FIG. 7, when there are “s” spare memory cells for a single row address RA, any single decoding vector may include “s+1” vector elements. As previously assumed, there will be “2” spare memory cells for the row address RA. Accordingly, each of the decoding vectors DV0 to DV5 may include “3” vector components.

And, similarly to generating the encoding vector in FIG. 5 , the predetermined shift value SHV may correspond to the predetermined value of the decoding vector. For example, a shift value (SHV) "0" corresponds to a decoding vector "001", a shift value (SHV) "1" corresponds to a decoding vector "010", and a shift value (SHV) "2" corresponds to a decoding vector It can correspond to "100".

In this situation, decoding vectors DV0 to DV5 may be generated according to the shift values SHV for each of the memory cells C0 to C5 for which the external device has instructed the read operation. As will be described in detail with reference to FIG. 8 , each of the decoding vectors DV0 to DV5 corresponds to the bit of the first data DATA1 that was instructed to be stored in the corresponding memory cell, and the second bit of the first data DATA1 actually read from the memory cells C0 to C7. It can be used to recover from data DATA2.

FIG. 8 is a diagram for exemplarily explaining a method in which the decoder 225 of FIG. 4 recovers the first data DATA1 based on the second data DATA2 . 8 shows the second data DATA2 actually read from the memory cells C0 to C7 when the external device instructs the read operation of the first data DATA1 to the memory cells C0 to C5 and FIG. 7 . A process of recovering the first data DATA1 based on the decoding vectors DV0 to DV5 generated in .

First, when the external device instructs to read the memory cells C0 to C5, the range actually read is, considering the possibility that additional memory cells are used due to defective memory cells, not only the memory cells C0 to C5 but also the spare memory. It may be up to the memory cells C6 and C7 that follow in the cell direction. That is, the number of additionally read memory cells may be equal to the number of spare memory cells.

The decoder 225 may recover bits of the first data DATA1 in parallel based on the second data DATA2 read from the memory cells C0 to C7 and the decoding vectors DV0 to DV5 .

First, the decoder 225 may generate decoding bit groups DG0 to DG5 based on the second data DATA2 . The decoding bit groups DG0 to DG5 may respectively correspond to the memory cells C0 to C5 to which an external device has instructed a read operation. As a result, the decoding bit groups DG0 to DG5 are generated by the same number as the decoding vectors DV0 to DV5 and may correspond to the decoding vectors DV0 to DV5, respectively.

The decoding bit groups DG0 to DG5 may be generated according to a predetermined rule when only the second data DATA2 is read regardless of the presence or location of defective memory cells. First, when there are “s” spare memory cells for a single row address RA, any single decoding bit group may include “s+1” bit components. As it is assumed in FIG. 5 , it is assumed that “2” spare memory cells exist for the row address RA, so each of the decoding bit groups DG0 to DG5 may include “3” bit components. .

Bit components included in each of the decoding bit groups DG0 to DG5 may include one or more candidate bit components selected from bits b10 to b17 of the second data DATA2 . Specifically, the candidate bit components included in each of the decoding bit groups DG0 to DG5 may be bits that an external device has likely instructed to store in a corresponding memory cell. As a result, the candidate bit components included in each of the decoding bit groups DG0 to DG5 are the bit read from the corresponding memory cell among the bits b10 to b17 of the second data DATA2 and the "2" of the corresponding bit. "It can be the upper bits of

For example, the decoding bit group DG0 corresponding to the memory cell C0 may contain the candidate bit components b10, b11, b12 that the external device has likely instructed to store in the memory cell C0. can That is, when the memory cell C0 is a normal memory cell, the bit b10 may be stored in the memory cell C0 as it is according to an instruction from an external device. The bit b11 is instructed to be stored in the memory cell C0 by an external device, but may be shifted and stored in the memory cell C1 when the memory cell C0 is a defective memory cell. Also, although the bit b12 is instructed to be stored in the memory cell C0 by an external device, when the memory cells C0 and C1 are defective memory cells, the bit b12 may be shifted and stored in the memory cell C2.

That is, the present invention collectively generates the candidate bit components of the decoding bit groups DG0 to DG5 in consideration of this possibility, and then the decoding vectors DV0 to which the actual positions of the defective memory cells C1 and C4 are reflected. DV5), any one of the candidate bit components may be selected. A method of generating the decoding bit groups DG2 to DG5 corresponding to the remaining memory cells C2 to C5 can be easily applied from a point of view of a person skilled in the art according to the above-described rule, and thus a detailed description thereof will be omitted.

In addition, candidate bit components in each of the decoding bit groups DG0 to DG5 may be arranged according to a predetermined method. For example, candidate bit components included in a single decoding bit group may be arranged as high-order bit components in the decoding bit group as the higher bits in the second data DATA2 are.

In addition, the decoder 225 may include operation units OP10 to OP15 that generate the first data DATA1 in parallel. Each of the operation units OP10 to OP15 may receive a decoding vector and a decoding bit group corresponding to each other and perform a bitwise operation to output a bit to be restored as the first data DATA1 . Each of the operation units OP10 to OP15 may output any one of the candidate bit components of the received decoding bit group based on the received decoding vector. Specifically, each of the operation units OP10 to OP15 may output a candidate bit component corresponding to the vector component “1” of the received decoding vector, that is, arranged at the same position as the vector component “1”.

As a result, the decoder 225 removes the bits b11 and b14 read from the defective memory cells C1 and C4 from the second data DATA2 and the normal memory cells C0, C2, C3, C5 to C7. ), the first data DATA1 may be recovered by leaving only the bits b10, b12, b13, and b15 to b17.

9 is a block diagram illustrating a shift value generator 322 according to an embodiment of the present invention. The shift value generator 322 may be an embodiment of the shift value generators 122 and 222 of FIG. 1 or FIG. 4 .

The shift value generated through the procedure shown in FIG. 3 will not change unless a new defective memory cell is subsequently generated. That is, the shift value generated for a predetermined main memory cell based on the positions of the current defective memory cells will always be the same unless a new defective memory cell is generated at the row address of the corresponding main memory cell.

Accordingly, referring to FIG. 9 , the shift value generating unit 322 may further include a shift value storing unit 422 . The shift value storage unit 422 may store shift values generated by the shift value generation unit 322 . The shift value storage unit 422 may output a shift value corresponding to a main memory cell on which a write operation is to be performed, based on a row address and a column address provided from an external device. If a new defective memory cell is generated at a predetermined row address, new shift values corresponding to the main memory cells of the corresponding row address may be generated through the shift value generator 322 and stored in the shift value storage 422 .

10 is a block diagram illustrating a vector generator 323 according to an embodiment of the present invention. The vector generator 323 may be an embodiment of the vector generator 223 of FIG. 4 .

The encoding vectors and decoding vectors generated through the process described with reference to FIGS. 5 and 7 will not change unless a new defective memory cell is generated thereafter. That is, the encoding vector and decoding vector generated for a given memory cell based on the positions of the current defective memory cells will always be the same unless a new defective memory cell occurs at the row address of the corresponding memory cell.

Accordingly, referring to FIG. 10 , the vector generator 323 may further include a vector storage 423 . The vector storage 423 may store the encoding vectors and the decoding vectors generated by the vector generator 323 . The vector storage unit 423 may output an encoding vector or a decoding vector corresponding to a memory cell on which a write operation or a read operation is to be performed, based on a row address and a column address provided from an external device. If a new defective memory cell is generated at a predetermined row address, new encoding vectors and decoding vectors corresponding to the memory cells of the corresponding row address may be generated through the vector generator 323 and stored in the vector storage unit 423 . .

11 is a block diagram exemplarily showing a semiconductor system 1 according to an embodiment of the present invention.

The semiconductor system 1 may include a first semiconductor device 1100 and a second semiconductor device 1200 .

The first and second semiconductor devices 1100 and 1200 may be connected through main signal lines ML0 to MLm and spare signal lines SL0 to SLs. Prior to description, a predetermined order may be given to the main signal lines ML0 to MLm and the spare signal lines SL0 to SLs in the direction of the spare signal line. That is, the main signal line ML0 may be the first among the main signal lines ML0 to MLm, and the last spare memory cell SLs may be the last. This order is assumed to facilitate the description of the invention below by assigning relative positions to the signal lines.

The communication method of the first and second semiconductor devices 1100 and 1200 through the main signal lines ML0 to MLm and the spare signal lines SL0 to SLs is the semiconductor device 100 of FIGS. 1 and 4 . 200 may be substantially similar to a method in which only normal memory cells are used by avoiding defective memory cells among the main memory cells MC0 to MCm and the spare memory cells SC0 to SCs.

Specifically, the first semiconductor device 1100 transmits the first signals SGN1 to be transmitted to the second semiconductor device 1200 through the main signal lines ML0 to MLm as second signals to avoid defective signal lines. (SGN2) may be converted and transmitted through the main signal lines ML0 to MLm and the spare signal lines SL0 to SLs. The second signals SGN2 include first signals SGN1 to be transmitted to normal signal lines among the main signal lines ML0 to MLm and the spare signal lines SL0 to SLs, and are formed as defective signal lines. It may include dummy signals to be transmitted.

The second semiconductor device 1200 may recover the first signals SGN1 from the second signals SGN2 received from the main signal lines ML0 to MLm and the spare signal lines SL0 to SLs. .

Accordingly, even if defective signal lines exist in the main signal lines ML0 to MLm, the first and second semiconductor devices 1100 and 1200 may communicate normally.

The first semiconductor device 1100 may include a defect information manager 1110 , a shift value generator 1120 , an encoding vector generator 1130 , and an encoder 1140 . The second semiconductor device 1200 may include a defect information manager 1210 , a shift value generator 1220 , a decoding vector generator 1230 , and a decoder 1240 . The defect information managers 1110 and 1210, the shift value generators 1120 and 1220, the encoding vector generator 1130, and the decoding vector generator 1230 included in the first and second semiconductor devices 1100 and 1200. ), the encoder 1140 and the decoder 1240 are the defect information management units 121 and 221, the shift value generation units 122 and 222, the vector generation unit 223 and the encoder 224 shown in FIG. 1 or 4 . and decoder 225 may be configured and operated substantially similarly.

Specifically, in the first and second semiconductor devices 1100 and 1200 , the defect information management units 1110 and 1210 are configured to have one or more defects in the main signal lines ML0 to MLm and the spare signal lines SL0 to SLs. Defect information FINF_L including position information of signal lines may be stored, respectively. The defect information managers 1110 and 1210 are configured to allow the first and second semiconductor devices 1100 and 1200 to communicate with each other through the main signal lines ML0 to MLm and the spare signal lines SL0 to SLs. At this time, the defect information FINF_L may be provided to the shift value generators 1120 and 1220 , respectively.

The shift value generators 1120 and 1220 may generate shift values SHV_L respectively corresponding to the main signal lines ML0 to MLm based on the defect information FINF_L. Similar to the process shown in FIG. 3 , the shift value generators 1120 and 1220 compare the positions of the predetermined main signal lines with reference positions based on the positions of the defective signal lines, thereby shifting corresponding to the predetermined main signal lines. A value (SHV_L) can be created. The i-th reference position among the reference positions may be a position preceding the position of the i-th defect signal line among the defect signal lines by (i-1). The shift value generators 1120 and 1220 may generate the shift value of the predetermined main signal line as “0” when the position of the predetermined main signal line is ahead of the position of the first defective signal line among the defective signal lines. The shift value generators 1120 and 1220 set the shift value of the predetermined main signal line to “i” when the position of the predetermined main signal line is equal to or behind the i-th reference position and ahead of the (i+1)-th reference position. can create The shift value generators 1120 and 1220 generate the shift value of the predetermined main signal line as “n” when the position of the predetermined main signal line is equal to or behind the n-th reference position, but in this case, the n-th reference position is defective. The position may be advanced by the position “n-1” of the n-th defect signal line, which is the last defect signal line among the signal lines. The shift value generators 1120 and 1220 may provide the shift values SHV_L to the encoding vector generator 1130 and the decoding vector generator 1230 , respectively.

The encoding vector generator 1130 and the decoding vector generator 1230 may generate one or more encoding vectors EV_L and one or more decoding vectors DV_L, respectively, based on the shift values SHV_L. The encoding vector generator 1130 may generate the encoding vectors EV_L similar to that described with reference to FIG. 5 and provide them to the encoder 1140 . The decoding vector generator 1230 may generate the decoding vectors DV_L similar to that described with reference to FIG. 7 and provide them to the decoder 1240 .

The encoder 1140 may generate the second signals SGN2 based on the first signals SGN1 and the encoding vectors EV_L provided from the encoding vector generator 1130 . The encoder 1140 rearranges the first signals SGN1 to positions of normal signal lines among the main signal lines ML0 to MLm and the spare signal lines SL0 to SLs, and transfers the dummy signals to the defective signal lines. By disposing, the second signals SGN2 may be generated.

In addition, the decoder 1240 may recover the first signals SGN1 based on the second signals SGN2 and the decoding vectors DV_L provided from the decoding vector generator 1230 . The decoder 1240 may recover the first signals SGN1 by removing the dummy signals transmitted through the defective signal lines from the second signals SGN2 .

According to an embodiment, the first and second semiconductor devices 1100 and 1200 may be vertically stacked semiconductor memory devices. In this case, each of the main signal lines ML0 to MLm and the spare signal lines SL0 to SLs may be formed of a through silicon via. The main signal lines ML0 to MLm and the spare signal lines SL0 to SLs may transmit control signals and data for controlling the semiconductor memory device.

Meanwhile, although FIG. 11 illustrates the first and second semiconductor devices 1100 and 1200 performing unidirectional communication, the first and second semiconductor devices 1100 and 1200 may be configured to perform bidirectional communication according to an embodiment. . In this case, each of the first and second semiconductor devices 1100 and 1200 may include an encoding vector generator, a decoding vector generator, an encoder, and a decoder. Since the configuration and operation method of such a semiconductor system can be easily derived by a person skilled in the art through the above description, a detailed description thereof will be omitted.

According to an embodiment, the shift value generators 1120 and 1220 of FIG. 11 may be configured and operated similarly to the shift value generator 322 of FIG. 9 . That is, the shift value generators 1120 and 1220 may include shift value storage units, respectively.

According to an embodiment, the encoding vector generator 1130 and the decoding vector generator 1230 of FIG. 11 may be configured and operated similarly to the vector generator 323 of FIG. 10 . That is, the encoding vector generation unit 1130 and the decoding vector generation unit 1230 may include an encoding vector storage unit and a decoding vector storage unit, respectively.

Those of ordinary skill in the art to which the present invention pertains, since the present invention can be embodied in other specific forms without changing the technical spirit or essential features thereof, the embodiments described above are illustrative in all respects and not restrictive must be understood as The scope of the present invention is indicated by the following claims rather than the above detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. do.

100: semiconductor device
110: memory area
MC0~MCm: main memory cells
SC0~SCs: spare memory cells
120: control unit
121: defect information management unit
122: shift value generator

Claims (21)

one or more main memory cells and one or more spare memory cells; and
Memory cells in which shift values corresponding to each of the main memory cells are generated based on defect information of one or more defective memory cells, and one or more first bits are respectively shifted from the main memory cells in the direction of the spare memory cell by the shift values A control unit configured to write to
The control unit generates a shift value corresponding to the main memory cell by sequentially comparing a column address of the main memory cell with one or more reference column addresses based on the defect information;
The i-th reference column address among the reference column addresses is a column address preceding the column address of the i-th defective memory cell among the defective memory cells by (i-1). delete delete ◈Claim 4 was abandoned when paying the registration fee.◈ According to claim 1,
The control unit is configured to generate a shift value of the main memory cell as “0” when the column address of the main memory cell precedes the column address of a first defective memory cell among the defective memory cells. ◈Claim 5 was abandoned when paying the registration fee.◈ According to claim 1,
The control unit generates the shift value of the main memory cell as “i” when the column address of the main memory cell is equal to or after the i-th reference column address and precedes the (i+1)-th reference column address. semiconductor device. ◈Claim 6 was abandoned when paying the registration fee.◈ According to claim 1,
The control unit generates a shift value of the main memory cell as “n” when the column address of the main memory cell is equal to or behind an n-th reference column address;
The n-th reference column address is a column address that precedes a column address of an n-th defective memory cell that is a last defective memory cell among the defective memory cells by “n-1”. ◈Claim 7 was abandoned at the time of payment of the registration fee.◈ According to claim 1,
The controller generates second bits in parallel by arranging the first bits at positions of the shifted memory cells and dummy bits at positions of the defective memory cells, and generates the second bits in the shifted positions. A semiconductor device for writing to the old memory cells and the defective memory cells. ◈Claim 8 was abandoned when paying the registration fee.◈ 8. The method of claim 7,
The controller generates one or more encoding vectors respectively corresponding to the shift values, inserts dummy encoding vectors between consecutive encoding vectors having different values among the encoding vectors, and based on the encoding vectors and disposing the first bits and disposing the dummy bits based on the dummy encoding vectors. ◈Claim 9 was abandoned at the time of payment of the registration fee.◈ 8. The method of claim 7,
The controller reads the second bits from the shifted memory cells and the defective memory cells, and restores the first bits in parallel by removing the dummy bits from the second bits based on the shift values. semiconductor device. ◈Claim 10 was abandoned when paying the registration fee.◈ 10. The method of claim 9,
The control unit generates one or more decoding vectors corresponding to the shift values, respectively, and recovers the first bits based on the decoding vectors. ◈Claim 11 was abandoned when paying the registration fee.◈ According to claim 1,
The main memory cells and the spare memory cells correspond to a single row address. one or more main signal lines and one or more spare signal lines;
Shift values corresponding to each of the main signal lines are generated based on defect information of one or more defective signal lines, and one or more first signals are respectively shifted from the main signal lines in the direction of the spare signal line by the shift values. a first semiconductor device configured to transmit to the signal lines; and
a second semiconductor device configured to equally generate the shift values and to receive the first signals from the shifted signal lines based on the shift values,
the first semiconductor device generates a shift value corresponding to the main signal line by sequentially comparing the position of the main signal line with one or more reference positions based on the defect information;
The i-th reference position among the reference positions is a position preceding the position of the i-th defect signal line among the defect signal lines by (i-1). delete delete ◈Claim 15 was abandoned when paying the registration fee.◈ 13. The method of claim 12,
The first semiconductor device generates a shift value of the main signal line as “0” when the position of the main signal line precedes the position of a first defect signal line among the defect signal lines. ◈Claim 16 was abandoned when paying the registration fee.◈ 13. The method of claim 12,
The first semiconductor device generates a shift value of the main signal line as “i” when the position of the main signal line is equal to or behind the i-th reference position and precedes the (i+1)-th reference position. semiconductor system. ◈Claim 17 was abandoned when paying the registration fee.◈ 13. The method of claim 12,
the first semiconductor device generates a shift value of the main signal line as “n” when the position of the main signal line is equal to or behind an n-th reference position;
The n-th reference position is a position preceding a position of an n-th defect signal line which is a last defect signal line among the defect signal lines by “n-1”. ◈Claim 18 was abandoned when paying the registration fee.◈ 13. The method of claim 12,
The first semiconductor device generates second signals in parallel by arranging the first signals at positions of the shifted signal lines and dummy signals at positions of the defect signal lines, and the second signal are transmitted to the shifted signal lines and the defect signal lines. ◈Claim 19 was abandoned at the time of payment of the registration fee.◈ 19. The method of claim 18,
The first semiconductor device generates one or more encoding vectors respectively corresponding to the shift values, inserts dummy encoding vectors between consecutive encoding vectors having different values among the encoding vectors, and selects the encoding vectors. and disposing the first signals and the dummy signals based on dummy encoding vectors. ◈Claim 20 was abandoned when paying the registration fee.◈ 19. The method of claim 18,
The second semiconductor device receives the second signals from the shifted signal lines and the defective signal lines, and parallelizes the first signals by removing dummy bits from the second signals based on the shift values. A semiconductor system that recovers from the enemy. ◈Claim 21 has been abandoned at the time of payment of the registration fee.◈ 21. The method of claim 20,
The second semiconductor device generates one or more decoding vectors respectively corresponding to the shift values, and recovers the first signals based on the decoding vectors.

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