KR102341263B1 - Low defective semiconductor device and method of manufacturing the same - Google Patents

Abstract

Disclosed are a low-defect semiconductor device and a method for manufacturing the same.
In the disclosed semiconductor device manufacturing method, a buffer layer is formed on a silicon substrate, an interface control layer is formed on the buffer layer under a first growth condition, and a second growth condition different from the first growth condition is formed on the interface control layer. A nitride laminate is formed under the conditions.

Description

Low defective semiconductor device and method of manufacturing the same

To a low-defect semiconductor device and a method for manufacturing the same, and to a semiconductor device having a reduced twist grain boundary while being small and to a method for manufacturing the same.

A sapphire substrate or a silicon carbide (SiC) substrate is often used as a substrate for forming a nitride-based semiconductor device. However, the sapphire substrate is expensive, it is hard to manufacture a chip, and the electrical conductivity is low. In addition, when epitaxially growing a sapphire substrate to a large diameter, it is difficult to fabricate a large area due to the low thermal conductivity causing the substrate itself to warp at a high temperature. In order to overcome this limitation, a nitride-based semiconductor device using a silicon substrate instead of a sapphire substrate is being developed.

Since the silicon substrate has higher thermal conductivity than the sapphire substrate, the degree of warpage of the substrate is not large even at the growth temperature of the nitride thin film grown at high temperature, enabling the growth of a large-diameter thin film. However, when a nitride thin film is grown on a silicon substrate, a dislocation density increases due to a mismatch of a lattice constant between the substrate and the thin film, and cracks occur due to a mismatch in thermal expansion coefficient. Therefore, methods for reducing the defect density and methods for preventing cracks have been studied a lot. However, when the defect density is decreased, a tensile stress is generated incidentally, so that the defect density is decreased while the occurrence of cracks is increased, or conversely, cracks are decreased but the defect density is increased. As described above, it is difficult to satisfy both the defect density reduction and the crack reduction when the nitride thin film is grown on a silicon substrate.

SUMMARY Embodiments of the present invention provide a method of manufacturing a small-sized semiconductor device with few defects.

SUMMARY Embodiments of the present invention provide a small semiconductor device with few defects.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a buffer layer on a silicon substrate; forming an interface control layer on the buffer layer under first growth conditions; and forming a nitride laminate on the interface control layer under a second growth condition different from the first growth condition;

The first growth condition and the second growth condition may be adjusted so that a ratio of the minimum value of the reflectance vibration center of the interface control layer to the maximum value of the reflectance vibration center value of the nitride laminate has a range of 0.8 or more.

A ratio of a minimum value of a reflectance oscillation center of the interface control layer to a maximum value of a reflectance oscillation center value of the nitride laminate may have a range of 0.9 or more.

At least one of temperature, pressure, and thickness of the interface control layer may be formed under a condition different from that of the nitride laminate.

The interface control layer may be formed at a first temperature in a range greater than 900°C and less than 1050°C, and the nitride laminate may be formed at a second temperature higher than the first temperature.

The interface control layer may be formed at a first pressure in the range of 20 to 500 torr, and the nitride laminate may be formed at a second pressure equal to or higher than the first pressure.

The interface control layer may be formed to have a thickness in a range of 2 to 1000 nm.

The interface control layer and the nitride laminate may be formed of a group V/III compound, and when the interface control layer is grown, a molar composition ratio of the group V material to the group III material may be in the range of 20 to 2000.

The interface control layer may be continuously stacked on the buffer layer without intervening other layers.

The nitride laminate may be continuously laminated on the interface control layer without intervening other layers.

The nitride laminate may include at least one nitride semiconductor layer formed of a nitride containing gallium.

In the nitride laminate, a plurality of nitride semiconductor layers formed of the same kind of nitride compound may be sequentially stacked.

The nitride laminate may be formed of Al _x1 In _y2 Ga _{1 -x1- y1} N (0≤x1, y1≤1, x1+y1≤1).

The buffer layer may include one layer or a plurality of layers, and _{may be formed of Al x2} In _y2 Ga _{1 -x2- y2} N (0≤x2, y2≤1, x2+y2≤1).

A nucleation layer may be formed between the silicon substrate and the buffer layer.

The nucleation layer may be formed of AlN.

The method may further include removing the substrate and the buffer layer.

A semiconductor device according to an embodiment of the present invention,

silicon substrate;

a buffer layer on the silicon substrate;

an interface control layer provided on the buffer layer; and

Including; a nitride laminate on the interface control layer;

A ratio of a minimum value of a reflectance oscillation center value of the interface control layer to a maximum value of a reflectance oscillation center value of the nitride laminate may have a range of 0.8 or more.

A semiconductor device and a method for manufacturing the same according to an embodiment of the present invention can provide a small-sized and low-defect semiconductor device due to the thin and low surface roughness interface control layer.

1 schematically illustrates a low-defect semiconductor device according to an embodiment of the present invention.
FIG. 2 illustrates an example in which a nucleation layer is further provided in the low-defect semiconductor device shown in FIG. 1 .
FIG. 3 illustrates an example in which an active layer is further provided in the low-defect semiconductor device shown in FIG. 1 .
FIG. 4 illustrates a state in which a substrate and a buffer layer are removed from the low-defect semiconductor device shown in FIG. 3 .
5A to 5D illustrate changes in reflectivity as the growth temperature of an interface control layer of a semiconductor device is changed.
6A and 6B show the grain size of the surface of the nitride semiconductor layer according to the growth temperature of the interface control layer of the semiconductor device.
7A and 7B show threading dislocations according to a growth temperature of an interface control layer of a semiconductor device in a transverse cross-section.
8A and 8B are longitudinal cross-sectional views illustrating threading dislocations according to a growth temperature of an interface control layer of a semiconductor device.
9A and 9B show AFM images of the surface of the interface control layer according to the growth temperature of the interface control layer of the semiconductor device.
10 to 15 are cross-sectional views illustrating examples of silicon substrates employed in semiconductor devices according to embodiments.
16 illustrates an example of a buffer layer employed in a semiconductor device according to embodiments of the present invention.
17A-17D show examples of individual layers employed in the buffer layer of FIG. 16 .
18 is a cross-sectional view illustrating another example of a buffer layer employed in a semiconductor device according to embodiments of the present invention.
19 is a cross-sectional view illustrating a buffer layer of another example employed in a semiconductor device according to another embodiment.
20 is a graph showing the relationship between the lattice constants of each layer constituting the buffer layers of FIGS. 16, 18 and 19 .
21 shows an exemplary combination of thicknesses and lattice constants of each layer constituting the buffer layers of FIGS. 16, 18, and 19 .
22 shows another example of a combination of thicknesses and lattice constants of each layer constituting the buffer layers of FIGS. 16, 18, and 19 .
23 is a cross-sectional view showing a schematic structure of a semiconductor device according to another embodiment.
24 to 27 are cross-sectional views illustrating examples of a semiconductor device applied to a light emitting device according to another embodiment. FIG. 28 is a cross-sectional view showing an example of a light emitting device package as a semiconductor device according to another embodiment.
29 is an exploded perspective view illustrating an example of a lighting device employing a light emitting device package according to an embodiment.

Hereinafter, a low-defect semiconductor device and a method for manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numbers refer to the same components, and the size or thickness of each component may be exaggerated for convenience of description. Meanwhile, the embodiments described below are merely exemplary, and various modifications are possible from these embodiments. Hereinafter, reference to "above" or "above" of a layer may include not only those directly on the other layer in contact with it, but also those directly on the other layer in a non-contact manner.

1 schematically illustrates a low-defect semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a substrate 110 , a buffer layer 115 on the substrate, an interface control layer 120 on the buffer layer 115 , and a nitride stack 125 on the interface control layer 120 . do. The substrate 110 may be a silicon-based substrate. For example, the substrate 110 may be a silicon substrate.

The silicon substrate may use, for example, a (111) plane, and may be cleaned with sulfuric acid, hydrofluoric acid, or deionized water. The cleaned substrate may be in a state suitable for epitaxial growth by removing impurities such as metals and organic materials and natural oxide films, and terminating the surface with hydrogen. The buffer layer 115 is, for example, AlN, AlGaN, step grade Al _x In _y Ga _{1 -x- y} N (0≤x,y≤1, x+y≤1), Al _x1 In _y1 Ga _{1 - x1- y1} N/ Al _x2 In _y2 Ga _{1 -x2-y2} N (0≤x1,x2,y1,y2≤1, x1≠x2 or y1≠y2, x1+y1≤1,x2+y2≤1) seconds It may be formed of a material including any one selected from the group consisting of lattice.

The buffer layer 115 is, for example, to reduce dislocation due to mismatch of lattice constants between the substrate 110 and the interface control layer 120, and to suppress cracks generated due to mismatch of thermal expansion coefficients. can be provided. 1 illustrates an example in which the buffer layer is one layer, it is also possible that a plurality of buffer layers are provided. Also, one of the plurality of buffer layers may serve as a nucleation layer. Hereinafter, the buffer layer and the nuclear growth layer will be separately described. The buffer layer 115 may be formed of, for example, a plurality of AlGaN/AlN/AlGaN layers. However, the present invention is not limited thereto, and other examples will be described later.

The interface control layer 120 may be formed of Al _x3 In _y3 Ga _{1 -x3- y3} N (0≤x3, y3≤1, x3+y3≤1). For example, the interface control layer 120 may be formed of a nitride containing gallium. The buffer layer 115 and the interface control layer 120 may be distinguished by being formed of different materials. For example, the buffer layer 115 may be formed of a nitride containing Al, and the interface control layer 120 may be formed of a nitride not containing Al. For example, the buffer layer 115 may be formed of AlGaN, and the interface control layer may be formed of GaN. However, the present invention is not limited thereto.

A dislocation loop may be formed at the interface between the buffer layer 115 and the interface control layer 120 to decrease dislocation density. When the buffer layer 115 is formed of, for example, Al _x Ga _{1 -x} N (0<x≤1), the Al composition may have a single composition or may have a sequentially decreasing composition. For example, an Al composition _{Al 0 .7 Ga 0 .3 N -} > Al 0 .5 Ga 0 .5 N -> Al 0 .3 Ga _{0 .7} to N may be reduced in order to step-grade. In this case, the lattice mismatch and the thermal expansion coefficient mismatch between the buffer layer 115 and the interface control layer 120 are reduced in stages, thereby effectively generating compressive stress during epitaxial growth. Due to this compressive stress, the tensile stress generated during epi cooling is reduced, thereby reducing the occurrence of cracks. In addition, the buffer layer 115 may cause bending of the penetration dislocation, thereby reducing defects. As the thickness of the buffer layer increases, compressive stress relaxation of the nitride stack grown thereon may be reduced, and defects may also be reduced. However, as the thickness of the buffer layer increases, there is a disadvantage in that the processing time increases. Therefore, it is necessary to limit the thickness of the buffer layer for appropriate defect reduction. For example, the thickness of the buffer layer may have a thickness of several hundred nanometers to several micrometers.

Meanwhile, the substrate 110 may be removed during or after the fabrication of the semiconductor device. Alternatively, when the substrate 110 is removed, the buffer layer 115 may also be removed. Since the silicon substrate does not transmit light, the substrate may be selectively removed to transmit light emitted from the semiconductor device.

The interface control layer 120 may reduce the occurrence of twist grain boundaries at the interface with the nitride stack 125 . The interface control layer 120 may have a thickness in a range of 2 to 1000 nm, and a roughness ratio of the interface control layer 120 to the roughness of the buffer layer 115 may be in a range of 3 or less.

As the thickness of the interface control layer 120 increases, the occurrence of twist grain boundaries at the interface between the interface control layer 120 and the nitride stack 125 may be reduced. However, if the thickness of the interface control layer 120 is increased, the crystallinity of the entire thin film may be deteriorated. This is because the interface control layer is grown at a relatively low temperature compared to the nitride semiconductor layer, so that defects may increase. Therefore, it is preferable to reduce the occurrence of twist grain boundaries while reducing the thickness of the interface control layer 120 .

When the twist grain boundary is reduced, defects in the nitride laminate stacked on the interface control layer 120 may be reduced. That is, the interface control layer 120 has a thickness in the range of 2 to 1000 nm, and the roughness ratio of the interface control layer to the roughness of the buffer layer has a range of 3 or less, thereby reducing defects in the nitride laminate stacked thereon. Accordingly, the same degree of crystallinity can be obtained at a lower thickness compared to a thick layer that does not use an interface control layer, so that the entire structure can be thinned. In addition, it is possible to reduce the process time and cost of the epitaxial growth step for the semiconductor device according to the embodiment of the present invention.

The nitride stack 125 may include one nitride semiconductor layer or a plurality of nitride semiconductor layers. The nitride laminate 125 may represent a target layer to be grown on the buffer layer. The nitride semiconductor layer may be formed of Al _x4 In _y4 Ga _{1 -x4-y4} N (0≤x4, y4≤1, x4+y4<1). When the nitride layered body 125 includes a plurality of nitride semiconductor layers, the nitride semiconductor layers may be classified functionally or according to composition quality. For example, the plurality of nitride semiconductor layers may be distinguished by having different composition ratios, by doping and undoping, or by having different doping concentrations. The nitride laminate 125 may include, for example, an undoped GaN layer and an n-type GaN layer.

FIG. 2 illustrates an example in which a nuclear growth layer is further provided in the semiconductor device shown in FIG. 1 . The semiconductor device 100A illustrated in FIG. 2 may further include a nuclear growth layer 113 between the substrate 110 and the buffer layer 115 . The nucleation layer 113 may be formed of Al _x4 In _y4 Ga _{1 -x4- y4} N (0≤x4, y4≤1, x4+y4≤1). The nucleation layer may have a thickness of tens to hundreds of nanometers. In addition, the nucleation layer 113 and the buffer layer 115 may be distinguished by their respective composition materials.

The nucleation layer 113 may be formed of, for example, AlN. The nucleation layer prevents the melt-back phenomenon caused by the reaction of the substrate and the nitride stack, and may serve to allow the buffer layer 115 or the interface control layer 120 to wet well. In the growth stage of the nucleation layer, an Al source rather than an N source is injected into the deposition apparatus first. This is to prevent the substrate from being first exposed to ammonia and nitridation when ammonia, which is an N source, is first injected.

The semiconductor device 200 illustrated in FIG. 3 includes a substrate 210 , a buffer layer 215 on the substrate, an interface control layer 220 on the buffer layer 215 , and a first nitride stack 225 on the interface control layer 220 . ) is included. In addition, an active layer 230 may be provided on the first nitride stack 225 , and a second nitride stack 325 may be provided on the active layer 230 . The substrate 210 may be a silicon-based substrate, for example, a silicon substrate. Since the buffer layer 215 and the interface control layer 220 have substantially the same configuration and operation as the buffer layer and the interface control layer described with reference to FIG. 1 , a detailed description thereof will be omitted.

The first nitride semiconductor layer 225 may include one nitride semiconductor layer or a plurality of nitride semiconductor layers. The nitride semiconductor layer constituting the first nitride stack 225 may be doped with type 1 or undoped. Type 1 may be, for example, n-type. For example, a nitride semiconductor layer in direct contact with the active layer 230 among nitride semiconductor layers constituting the first nitride stack may be doped with a first type, for example, an n-type. However, it is also possible that the first type is p-type.

The second nitride stacked body 235 may include one nitride semiconductor layer or a plurality of nitride semiconductor layers. The nitride semiconductor layer constituting the second nitride stack 235 may be type 2 doped or undoped. The type 2 may be, for example, the p-type. However, when the nitride semiconductor layer of the first nitride stack 235 is p-type doped, the nitride semiconductor layer of the second nitride stack body 235 may be doped in the n-type. For example, a nitride semiconductor layer in direct contact with the active layer 230 among the nitride semiconductor layers constituting the second nitride stack may be doped with a second type, for example, a p type.

The active layer 230 may have a multi-quantum well structure. For example, the active layer 230 may be formed of a GaN/InGaN multi-quantum well structure. In the active layer 230 , light may be emitted while electrons (or holes) from the first nitride stack and holes (or electrons) from the second nitride stack are combined.

In the semiconductor device according to the embodiment of the present invention, it is possible to manufacture a large-diameter wafer using a silicon substrate. The semiconductor device according to the embodiment of the present invention may be applied to a light emitting diode, a Schottky diode, a laser diode, a field effect transistor, or a power device.

Meanwhile, as shown in FIG. 4 , the substrate 210 and the buffer layer 215 may be removed from the semiconductor device 200 . For example, the substrate and buffer layer may be removed to allow light from the active layer 230 to be emitted downwards. Although not shown, when the substrate 210 and the buffer layer 215 are removed, a support substrate may be further provided on the second nitride stack 235 to support a semiconductor device.

Next, the interface control layer 120 and the nitride laminate 125 will be described in detail with reference to FIG. 1 .

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, growth conditions may be adjusted to reduce the roughness of the interface control layer 120 . An interface control layer is formed on the buffer layer under the first growth conditions to control a ratio of the roughness of the interface control layer to the roughness of the buffer layer. Then, a nitride laminate is formed on the interface control layer under a second growth condition different from the first growth condition. For example, the interface control layer 120 may be grown by controlling at least one of temperature, pressure, and thickness. Alternatively, the interface control layer may be formed of a group V/III compound, and may be grown by adjusting the molar composition ratio of the group V material and the group III material of the interface control layer. In addition, the growth conditions of the interface control layer 120 may be adjusted differently for the growth conditions of the nitride stack 125 .

For example, the interface control layer 120 may be grown in a range greater than 900°C and less than 1050°C. The interface control layer 120 may be grown at a pressure in the range of 20 to 500 torr.

5A shows the curvature and reflectance (%) in the thickness direction of the semiconductor device when the interface control layer 120 is grown at 900°C. A portion indicated by A1 (sections 20 to 21) indicates a portion corresponding to the interface control layer 120 . The reflectance may be an index capable of determining the roughness of the surface. For example, if the surface roughness is high, light may be scattered from the surface and the reflectance may be low. For reference, in the following experiment, a relatively high temperature of 1050° C. was used for the growth of the nitride semiconductor layer after the growth of the interface control layer. In the example shown in A1 of FIG. 5A , the ratio of the minimum value of the reflectance vibration center of the interface control layer to the maximum value of the reflectance vibration center value of the nitride laminate may have about 0.48. The reflectance oscillation center value may represent central values of amplitude in each period of the reflectance oscillation. As a method for monitoring the state of a thin film when growing a thin film, a laser is irradiated to the thin film and the intensity of light reflected from the thin film is measured. At this time, since the sum of the light reflected from the outside of the thin film and the light reflected from the inside of the thin film is measured, when the thickness of the thin film is changed, the measured light intensity vibrates according to the interference effect. Here, a center value of reflectivity oscillation, which is a central value of an oscillation amplitude, may be used as a value representing the film quality. For example, the maximum value of the reflectance oscillation center value of the nitride laminate may represent a maximum value among reflectance oscillation center values in the section of the nitride laminate. The minimum value of the reflectance vibration center value of the interface adjustment layer may represent a minimum value among reflectance vibration center values in the section of the interface adjustment layer.

For example, in FIG. 5A , a maximum value among reflectance oscillation center values of the nitride laminate may be obtained in a section 22-25, and a minimum value among reflectance oscillation center values of the interface control layer may be obtained in a section 20-21.

FIG. 5B shows the curvature and reflectance (%) in the thickness direction of the semiconductor device when the interface control layer 120 is grown at 950°C. A portion marked with A2 (sections 20 to 21) indicates a portion corresponding to the interface control layer. The roughness in the interface control layer shown in FIG. 5B may have approximately r.m.s 7.1 nm. In FIG. 5B , the maximum value among the reflectance oscillation center values of the nitride laminate can be obtained in the section 22-25, and the minimum value among the reflectance oscillation center values of the interface control layer can be obtained in the section 20-21. In the example shown in A1 of FIG. 5B , the ratio of the minimum value of the reflectance vibration center of the interface control layer to the maximum value of the reflectance vibration center value of the nitride laminate may have about 0.99.

FIG. 5C shows the curvature and reflectance (%) in the thickness direction of the semiconductor device when the interface control layer 120 is grown at 1000°C. A portion marked with A3 (sections 20 to 21) indicates a portion corresponding to the interface control layer. In the example shown in A1 of FIG. 5C , the ratio of the minimum value of the reflectance vibration center of the interface control layer to the maximum value of the reflectance vibration center value of the nitride laminate may have about 0.93. 5D shows the curvature and reflectance (%) of the semiconductor device in the thickness direction when the interface control layer 120 is grown at 1050°C. A portion marked with A4 (sections 20 to 21) indicates a portion corresponding to the interface control layer. The roughness of the interface control layer shown in FIG. 5D may have approximately r.m.s 28.6. In the example illustrated in A1 of FIG. 5D , the ratio of the minimum value of the reflectance vibration center of the interface control layer to the maximum value of the reflectance vibration center value of the nitride laminate may have about 0.71.

The following shows the ratio of the minimum value (RImin) of the reflectance vibration center of the interface control layer to the maximum value (RNmax) of the reflectance vibration center value of the nitride laminate with respect to the growth temperature of the interface control layer.

Interface control layer growth temperature (℃) 900 950 1000 1050 (RImin/RNmax) 0.48 0.99 0.93 0.71

As will be described later, the crystallinity of the semiconductor device shown in FIGS. 5B and 5C is relatively good. Accordingly, for example, in the semiconductor device according to an embodiment of the present invention, a ratio of a minimum value of a reflectance oscillation center value of the interface control layer to a maximum value of a reflectance oscillation center value of the nitride laminate may be greater than 0.71. For example, in the semiconductor device according to an embodiment of the present invention, a ratio of a minimum value of a reflectance oscillation center value of an interface control layer to a maximum value of a reflectance oscillation center value of the nitride laminate may have a range of 0.8 or more. Here, in most cases, it can be expected that the roughness of the interface control layer is greater than that of the nitride laminate, and the reflectance oscillation center value of the nitride laminate is larger than the reflectance oscillation center value of the interface control layer. In this case, the ratio of the minimum value of the reflectance oscillation center value of the interface control layer to the maximum value of the reflectance oscillation center value of the nitride laminate may be less than 1. However, the present invention is not limited thereto, and it is also possible that the reflectance oscillation center value of the nitride laminate and the reflectance oscillation center value of the interface control layer are approximately the same, and in this case, the maximum value of the reflectance oscillation center value of the nitride laminate The ratio of the minimum value of the reflectance oscillation center value of the interface control layer to that of the interface control layer may be approximately 1. In addition, depending on the growth conditions of the nitride laminate and/or the growth conditions of the interface control layer, the maximum value of the reflectance oscillation center value of the nitride laminate may be smaller than the minimum value of the reflectance oscillation center value of the interface control layer. have. In this case, the ratio of the minimum value of the reflectance oscillation center of the interface control layer to the maximum value of the reflectance oscillation center value of the nitride laminate may be greater than 1. For example, a ratio of a minimum value of a reflectance oscillation center value of the interface control layer to a maximum value of a reflectance oscillation center value of the nitride laminate may have a range of 0.8 to 1.1.

For example, in the semiconductor device according to an embodiment of the present invention, a ratio of a minimum value of a reflectance oscillation center value of an interface control layer to a maximum value of a reflectance oscillation center value of the nitride laminate may have a range of 0.9-1.1. In A1 and A4, the reflective properties were irregular, which is relatively higher than the growth conditions of the interface control layer in FIGS. 5B and 5C in the case of the interface control layer in FIG. It indicates that the illuminance increases. The full widths at half maximum (FWHM) of the GaN(002) and GaN(102) X-ray rocking curve (XRC) of the entire thin film according to each growth temperature is shown as follows.

Interfacial control layer growth temperature XRC FWHM (arcsec) (002) (102) 900℃ N/A N/A 950℃ 275 323 1000℃ 287 357 1050℃ 316 375

Here, the full width at half maximum (FWHM) of X-Ray rocking curves (XRC) represents the full width at half maximum in the light intensity change graph according to the angle of incidence of X-Ray. The smaller the FWHM value, the smaller the defect. Crystallinity and compressive stress were improved as the temperature decreased to 1050° C. or less, and when the temperature was decreased to 900° C. or less, a rough interface with poor reflectivity was formed during film growth, as in the case of 1050° C., and crystallinity was deteriorated. In the case of 900 ℃, the compressive stress relaxation due to the high defect density increased, so cracks occurred, and XRC FWHM could not be obtained, which is shown as N/A (Not available) in Table 2.

6a shows a scanning transmission emission microscope (STEM) image when the interface control layer is grown at 950°C, and FIG. 6b shows a STEM image when the interface control layer is grown at 1050°C. The grain size in the interface control layer of FIG. 6A is relatively larger than the grain size in the interface control layer of FIG. 6B . When the grain size is large, a twist grain boundary generated at a boundary between grains may be reduced.

7A and 7B show the threading dislocations reaching the surface of the interface control layer when the interface control layer is grown at 950° C. and 1050° C., respectively, in the transverse section (in the flat-zone direction of the Si(111) substrate). parallel cross-section). 8A and 8B show the penetration dislocations reaching the surface of the interface control layer in the longitudinal section (the section perpendicular to the flat-zone direction of the Si(111) substrate) when the interface control layer is grown at 950°C and 1050°C, respectively. will be. In FIGS. 7A, 7B, 8A, and 8B, arrows indicate penetration dislocations. The arrows in FIGS. 7A and 8A were relatively small compared to the arrows in FIGS. 7B and 8B. This indicates that the penetration dislocation of the interfacial control layer grown at 950°C was smaller than that of the interface control layer grown at 1050°C.

9A and 9B show AFM images of the surface of the interface control layer when the interface control layer is grown at 950°C and 1050°C, respectively. In FIG. 9B , it is shown that edge-type dislocations generated when twisted grain boundaries meet at a portion indicated by an arrow are arranged in a line form.

Therefore, by growing the interface control layer 120 at, for example, a temperature in a range greater than 900° C. and less than 1050° C., it is possible to increase crystallinity and reduce the occurrence of twist grain boundaries.

Next, by adjusting the thickness of the interface control layer, crystallinity may be increased and the occurrence of twist grain boundaries may be reduced. As the thickness of the interface control layer increases, crystallinity may decrease and compressive stress may be reduced. The following shows the FWHM of XRC when the thickness of the interface control layer is grown to 160 nm, 320 nm, and 640 nm, respectively, at 950 °C.

thickness XRC FWHM (002) (102) 160nm 282 311 320nm 275 323 640nm 310 382

According to Table 3, the higher the thickness, the lower the crystallinity and the compressive stress was reduced. Since the growth temperature of the interfacial control layer is relatively low, although roughness is improved as the thickness is increased, crystallinity and compressive stress may deteriorate. Accordingly, the roughness can be improved by making the growth temperature greater than 900°C and smaller than 1050°C while improving the crystallinity and compressive stress by appropriately reducing the thickness according to the temperature. Thereby, it is possible to reduce the twist grain boundary. The interface control layer may have a roughness ratio of 3 or less compared to the roughness of the buffer layer 115 . As described above, by controlling the growth conditions of the interface control layer, the thickness of the interface control layer can be reduced while reducing the roughness ratio of the interface control layer to the buffer layer.

Next, the crystallinity and compressive stress were investigated while controlling the growth pressure of the interface control layer and the growth molar composition ratio of the interface control layer. Here, the interface control layer was formed of GaN, and simulation was performed while changing the molar composition ratio (V/III) of Ga and N. Here, V/III represents the molar composition ratio of the group V material and the group III material used for growing the interface control layer.

growing conditions XRC FWHM (arcsec) pressure Temperature matter composition ratio (002) (102) 75 torr 950℃ GaN V/III=837 273 294 200 torr 950℃ GaN V/III=812 282 304 500 torr 950℃ GaN V/III=812 330 530 75 torr 950℃ GaN V/III=1674 280 300

According to Table 4, the lower the pressure, the better the crystallinity and the compressive stress, the higher the V/III composition ratio, the higher the crystallinity and the compressive stress.

For example, the interface control layer may be grown at a pressure in the range of 20 to 500 torr. In addition, the interface control layer may have a V/III molar composition ratio in the range of 10 to 2000.

Next, a nitride laminate 125 is formed on the interface control layer 120 . The nitride stack 125 may be formed under different growth conditions from those of the interface control layer 120 . Accordingly, the interface control layer 120 and the nitride stack 125 may be distinguished by, for example, growth characteristics. For example, the nitride laminate 125 may be grown in a temperature range of 950 to 1100°C. The nitride stack 125 may be grown in a pressure range of 50 to 300 torr.

The nitride stack 125 may be formed of Al _x4 In _y4 Ga _{1 -x4-y4} N (0≤x4, y4≤1, x4+y4<1). The nitride stack 125 may include one nitride semiconductor layer or a plurality of nitride semiconductor layers. When the nitride stack 125 includes a plurality of nitride semiconductor layers, the nitride semiconductor layers may be functionally or materially divided. For example, the plurality of nitride semiconductor layers may be distinguished by having different compositions, doping or not, and different doping concentrations. The nitride laminate 125 may include, for example, an undoped GaN layer and an n-type GaN layer.

The interface control layer 120 is formed to have a thin thickness depending on growth conditions, and the surface roughness of the interface control layer has a range of 3 or less compared to the buffer layer, so that the nitride laminate on the interface control layer 120 is formed. (125) can be grown with low defects. Since a low penetration dislocation can be obtained by the interface control layer 120 and thus the phenomenon of relaxation of the compressive stress caused by the penetration dislocation is reduced, the nitride stack 125 has crystallinity or compression between the nitride semiconductor layers. It can be grown without inserting other layers to secure stress. That is, the nitride semiconductor layers constituting the nitride stack may be sequentially stacked without intervening other layers. Here, the nitride semiconductor layers may be formed of the same material. Materials of the same type may indicate that the nitride semiconductor layer has the same composition. However, the intervening of a heterogeneous nitride semiconductor layer between the nitride semiconductor layers is not limited to ensure other characteristics.

Also, the interface control layer may be continuously stacked on the buffer layer without intervening other layers. That is, since crystallinity and compressive stress characteristics are secured by the interface control layer, the interface control layer may be stacked directly on the buffer layer without intervening other layers for securing crystallinity and compressive stress between the buffer layer and the interface control layer.

The semiconductor device and the manufacturing method according to the embodiment of the present invention can provide a semiconductor device having low defects in a thin film structure having a relatively low thickness due to the thin interfacial control layer having a low surface roughness. In the case of reducing the defect density using the SiNx mask layer, the semiconductor device manufactured using this method can be manufactured thickly because it must be grown to a thickness of several μm or more for coalescence during growth of the nitride layer on the mask layer. have. In addition, a relative tensile stress may be induced during the coalescence process, thereby increasing the possibility of cracking of the thin film. However, in the embodiment of the present invention, even if such a mask layer is not used, the total thickness of the buffer layer, the interface control layer, and the nitride laminate may be, for example, 6 μm or less. And, the surface pit density observed by AFM (Atomic Force Microscope) may have a low defect density of ^{5E8/cm 2 or less.} And, the ratio of the FWHM to the (002) direction and the (102) direction may have a crystallinity of 280″/300″ or less. In addition, for example, an ^{n-type GaN layer having a Si doping concentration of 4E18/cm 3} or more may be grown without cracks of 3 μm or more. This is merely exemplary, and the present invention is not limited thereto. As described above, the semiconductor device and the manufacturing method according to the embodiment of the present invention can secure performance with a low defect while being thin.

The semiconductor device according to the embodiment of the present invention may have good crystallinity with a small thickness, and may be manufactured with a large diameter of 8 inches or more, for example.

Meanwhile, FIGS. 10 to 15 are cross-sectional views illustrating examples of a substrate S that may be employed in a semiconductor device according to embodiments of the present invention.

The substrate S may be used in a form in which a crack prevention part is provided on the edge part S1 that is vulnerable to cracks that may occur during the semiconductor thin film growth process.

Referring to FIG. 10 , the substrate S may include a main portion S2 and an edge portion S1 on the periphery of the main portion S2 . The substrate S may have, for example, a circular shape, and the main portion S2 may represent a portion inside the edge of the substrate. Also, the main part S2 may indicate a region in which a single crystal nitride semiconductor thin film is to be grown. The silicon substrate S may include, for example, a crack prevention part CP1 in which the direction of the crystal plane is randomly formed on the upper surface of the edge part S1 .

The main part S2 may have, for example, a (111) crystal plane, and the crack prevention part CP1 may have an irregular crystal plane. In the case of growing the nitride semiconductor thin film thereon because the direction of the crystal plane is irregularly formed in the crack preventing part CP1 , the nitride semiconductor thin film cannot be grown as a single crystal, but may be formed in an amorphous or polycrystalline form. On the other hand, on the main part S2, the nitride semiconductor thin film may be grown as a single crystal.

When the crack prevention part CP1 has a crystal plane in a random direction or a rough surface, in the main part S2 in the process of growing the nitride semiconductor thin film on the silicon substrate, for example, the crystal is oriented in the (111) direction. On the other hand, in the crack prevention part CP1, the crystal direction of the surface may be randomly oriented due to the rough surface. Therefore, since the nitride semiconductor thin film grown on the surface of the crack prevention part CP1 is grown in a polycrystalline or amorphous state, the growth of a heterogeneous material is different from the single crystal part of the nitride semiconductor thin film grown on the (111) plane of the silicon substrate. stress at the interface between the substrate and the thin film by Accordingly, when the nitride semiconductor thin film is grown on the edge portion S1 , stress due to the thin film is reduced, thereby reducing the denaturation of the silicon substrate.

Referring to FIG. 11 , the silicon substrate S includes a main portion S2 and an edge portion S1 on the periphery of the main portion S2 , and a crack preventing portion having a concave-convex pattern shape on the edge portion S1 . (CP2) may be included. The concave-convex pattern may be formed according to a general photolithography process, and the crack preventing part CP2 may have a rough surface or the crystal direction of the surface may be random due to the concave-convex pattern.

Referring to FIG. 12 , the silicon substrate S includes a silicon main part S2 , a silicon rim part S1 around the silicon main part S2 , and a crack preventing part formed on the silicon rim part S1 . (CP3) may be included. The crack prevention part CP3 may be formed of, for example, a thermal oxide formed by thermal oxidation of the edge part S1 . Alternatively, a dielectric material such as oxide or nitride is deposited on a silicon substrate S using chemical vapor deposition (CVD) or sputtering, and a photolithography process is performed on the edge portion S1. The crack preventing portion CP2 made of a dielectric layer may be formed by patterning and etching so that only the dielectric material remains. Here, the crack preventing portion CP2 may be formed to extend to the side surface of the silicon substrate S in addition to the upper portion of the silicon edge portion S1 , or may be formed to extend to the bottom surface of the silicon substrate S.

Referring to FIG. 13 , in the silicon substrate S, the upper portion of the edge portion S1 is etched to form a step, and on the upper portion of the edge portion S1 stepped lower than the main portion S2 of the silicon substrate S. A crack prevention part CP4 may be included.

Referring to FIG. 14 , the silicon substrate S includes a main portion S2 , an edge portion S1 on the periphery of the main portion S2 , and a crack prevention portion CP5 formed on the silicon edge portion S1 . may include The crack prevention part CP5 may be formed on the edge part S1 through ion implantation. The surface of the edge portion S1 may be transformed into polycrystalline or amorphous form by the ion implant. On the other hand, in the drawing, it is illustrated that the ion implant is only on the upper surface of the silicon rim part S1, but it is not limited thereto, and the side and lower surfaces including the upper surface of the rim part S1, and the silicon main part S2. It is also possible to perform ion implantation by extending it to the lower surface. For example, when the crack prevention part is formed even on the side surface of the edge part S1, when the silicon substrate is rotated at a high speed in the deposition apparatus, the effect of reducing cracks may be further enhanced by alleviating the impact caused by the high speed rotation.

Referring to FIG. 15 , in the silicon substrate S, the upper portion of the edge portion S1 is etched to form a step, and on the upper portion of the edge portion S1 stepped lower than the main portion S2 of the silicon substrate S. The crack prevention part CP5 by ion implantation may be formed.

The silicon substrate S shown in FIGS. 10 to 15 may be used in a form doped with impurities at a predetermined concentration so as to reduce a bow generated during a semiconductor thin film manufacturing process.

Next, a buffer layer employed in a semiconductor device according to an embodiment of the present invention will be described.

The buffer layer may include a single layer or a composite layer. The layers constituting the single layer or the composite layer may have a uniform composition, or may have a structure in which the composition is changed within the layer. When the composition is changed, for example, the Al composition may be reduced toward the nitride laminate.

When a composite layer is used as the buffer layer, a superlattice layer may be used, and it is also possible to use a superlattice layer in part. For example, as shown in FIG. 16 , the buffer layer 315 may include a first layer 315a, a second layer 315b, and a third layer 315c.

The first layer 315A includes Al _x In _y Ga _{1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and the lattice constant LP1 is the substrate (Fig. 1 to 3 may have a value smaller than the lattice constant LP0 of 110 and 210). The second layer 315B is formed on the first layer 315A, and Al _x In _y Ga _{1 -x- y} N (0≤x<1, 0≤y<1, 0≤x+y<1) Including, the lattice constant LP2 may have a value greater than LP1 and smaller than LP0. The third layer 315C is formed on the second layer 315B, and Al _x In _y Ga _{1 -x- y} N (0≤x<1, 0≤y<1, 0≤x+y<1) , and the lattice constant LP3 may have a smaller value than LP2. LP3 may have a value greater than or equal to LP1.

The first layer 315A has a lattice constant value smaller than the lattice constant of the substrate, and thus may be subjected to tensile stress. Since the second layer 315B has a larger lattice constant than the lattice constant of the first layer 315A, it may be subjected to compressive stress by the first layer 315A, and the third layer 315C may be subjected to a compressive stress by the second layer 315B. ), since it has a smaller value than the lattice constant of ), it is possible to receive a tensile stress by the second layer 315B. However, the type and magnitude of the stress received by each layer may vary depending on a thickness relationship and lattice relaxation in addition to a difference in lattice constant with a lower layer. For example, since the thickness of the second layer 315B, which is subjected to compressive stress by the first layer 315A in which lattice relaxation has occurred on the silicon substrate, is very thin, lattice relaxation does not occur and the first The type of stress applied to the third layer 315C when it is grown coherently with the lattice of the layer 315A, that is, when the lattice size of the second layer 315B grows to be substantially similar to the lattice size of the first layer 315A. and the size will depend on the lattice size of the first layer 315A. According to this relationship, for example, when the first layer 315A and the third layer 315C are layers subjected to tensile stress by the substrate and the second layer 315B, cracks may occur if the tensile stress is excessive. Therefore, it may be configured to have a thickness equal to or less than the critical thickness at which cracks occur during growth or cooling.

In addition, the first layer 315A may be configured as a layer in direct contact with the substrate, and may be made of AlN.

Also, the first layer 315A receives a tensile stress by the substrate, and lattice relaxation may occur.

In addition, the thickness and lattice constant of each layer may be determined so that the sum of the stresses of each layer constituting the buffer layer 315 becomes a compressive stress, that is, to apply a compressive stress to the target layer to be formed on the buffer layer 315. .

17A to 17D show examples of individual layers included in the buffer layer.

17A and 17B show examples of a superlattice layer (SLS) (SLS′) as a structure applicable to at least one of a plurality of layers included in the buffer layer.

The superlattice layer SLS of FIG. 17A is a structure that implements a corresponding lattice constant, that is, a lattice constant condition for at least one of a plurality of layers constituting the buffer layer. Two layers L1 and L2 having different lattice constants It has an alternating stacked structure. The thicknesses of the two layers L1 and L2 having different lattice constants may be the same. The two layers L1 (L2) may include Al _x In _y Ga _{1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and in each layer The x and y composition may be determined according to a lattice constant to be implemented.

The superlattice layer SLS′ of FIG. 17b is a structure that implements a corresponding lattice constant, that is, a lattice constant condition for at least one of a plurality of layers constituting the buffer layer, and two layers L3 and L4 having different lattice constants. ) has an alternately stacked structure, and the two layers L3 and L4 having different lattice constants may have different thicknesses. The two layers L3 and L4 may include Al _x In _y Ga _{1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and in each layer The x and y composition may be determined according to a lattice constant to be implemented.

17C and 17D show an example in which a corresponding lattice constant, ie, a lattice constant condition for at least one of a plurality of layers constituting the buffer layer, is implemented as a single layer. Here, the meaning of a single layer means that it consists of one layer without a physical boundary therein, and does not mean that the material composition in the layer is constant.

The single layer SL of FIG. 17C may have a constant lattice constant according to the thickness direction, and the single layer SL' of FIG. 17D may have a lattice constant that varies according to the thickness direction.

Here, the buffer layer may include at least one layer configured as described above.

18 is a cross-sectional view illustrating a structure of a buffer layer according to another example.

The buffer layer 330 of FIG. 18 has a first layer 330A, a second layer 330B, and a second layer that are substantially the same as the first layer 315A, the second layer 315B, and the third layer 315C of FIG. 16 . Including a third layer 330C, and also on the third layer 330C Al _x In _y Ga _{1 -x- y} N (0≤x<1, 0≤y<1, 0≤x+y<1) and may further include a fourth layer 330D having a lattice constant LP4 greater than LP2.

19 is a cross-sectional view showing a schematic structure of a buffer layer according to another example.

The buffer layer 340 of FIG. 19 has a first layer 340A, a second layer 340B, and a second layer that are substantially the same as the first layer 315A, the second layer 315B, and the third layer 315C of FIG. 16 . Including the third layer 340C, and also on the third layer 340C Al _x In _y Ga _{1 -x- y} N (0≤x<1, 0≤y<1, 0≤x+y<1) Al _x In _y Ga _{1 -x- y} N (0≤x<1, 0≤y< 1, 0≤x+y<1), and may further include a fifth layer 340E having a lattice constant LP5 greater than LP3 and smaller than LP4.

20 is a graph showing the relationship between the lattice constants of the respective layers constituting the buffer layers 315, 330, and 340 of FIGS. 16, 18, and 19. Referring to FIG.

The buffer layers 315, 330, and 340 may be composed of a plurality of layers satisfying the lattice constant relationship shown in the graph of FIG. The lattice constant may have a value smaller than the lattice constant of the target layer to be formed, for example, a nitride semiconductor layer.

21 and 22 show exemplary combinations of thicknesses and lattice constants of respective layers constituting the buffer layers 315, 330, and 340 of FIGS. 16, 18, and 19 .

Referring to FIG. 21 , the second layer and the fourth layer may have the same thickness, the third layer and the fifth layer may have the same thickness, and the third layer may have a greater thickness than the second layer. . Such thickness arrangement may be an example in which tensile stress is not applied to the third and fifth layers having a lattice constant smaller than the lattice constant of the lower layer. When the lower layers with high lattice constants, i.e., the second and fourth layers, are sufficiently small to have conditions in which lattice relaxation hardly occurs, tensile stress is applied to the upper layers with small lattice constants, i.e., the third and fifth layers. may not approve. In this case, since the upper layer having a small lattice constant is less likely to crack due to tensile stress, the thickness of the upper layer may be greater than that of the lower layer.

22 , the second layer and the fourth layer may have the same thickness, the third layer and the fifth layer may have the same thickness, and the third layer may have a smaller thickness than the second layer. . Such thickness arrangement may be an example in which the lower layer having a large lattice constant is formed to a thickness sufficient to apply a tensile stress to the upper layer having a small lattice constant. In the case of the third and fifth layers subjected to tensile stress, they may be formed to a small thickness so that cracks do not occur during the manufacturing process, growth or cooling.

Through the examples of FIGS. 21 and 22, it can be seen that the type and size of the stress applied to each layer may vary depending on the thickness and lattice relaxation as well as the difference in the lattice constant determined by the composition. .

On the other hand, the semiconductor device according to the embodiment of the present invention is a light emitting device (Light emitting diode, LED), a Schottky diode (Schottky diode), a laser diode (LD), a field effect transistor (Field Effect Transistor, FET) or It can be applied as a template for a High Electron Mobility Transistor (HEMT).

23 is a cross-sectional view showing a schematic structure of a semiconductor device 2000 according to another embodiment of the present invention.

The semiconductor device 2000 according to the present embodiment includes a silicon substrate S, a buffer layer 1200 formed on the silicon substrate S, an interface control layer ICL on the buffer layer 1200, and an interface control layer ICL on the interface control layer ICL. The formed nitride semiconductor layer 1300 includes a device layer formed on the nitride semiconductor layer 1300 . Since the silicon substrate S, the buffer layer 1200, the interface control layer ICL, and the nitride semiconductor layer 1300 are substantially the same as those described above, a detailed description thereof will be omitted.

The device layer may include a type 1 semiconductor layer 1500 , an active layer 1600 , and a type 2 semiconductor layer 1700 .

The type 1 semiconductor layer 1500 is a type 1 doped semiconductor layer, and may be formed of a group III-V nitride semiconductor material, for example, AlxGayInzN doped with an n-type impurity (0≤x≤1, It may be formed of a semiconductor material having 0≤y≤1, 0≤z≤1, and x+y+z=1). Si, Ge, Se, Te, etc. may be used as the n-type impurity.

The first-type semiconductor layer 1700 is a second-type doped semiconductor layer, and may be formed of a III-V nitride semiconductor material, for example, AlxGayInzN doped with p-type impurities (0≤x≤1, It may be formed of a semiconductor material having 0≤y≤1, 0≤z≤1, and x+y+z=1). As the p-type impurity, Mg, Zn, Be, or the like may be used.

The active layer 1600 is a layer that emits light by electron-hole bonding, and energy corresponding to an energy band gap of the active layer 1600 may be emitted in the form of light. The active layer 1600 may have a single quantum well or multi quantum well structure made by periodically changing the x, y, and z values in AlxGayInzN to control the band interval. For example, the quantum well layer and the barrier layer may be paired in the form of InGaN/GaN, InGaN/InGaN, InGaN/AlGaN, or InGaN/InAlGaN to form a quantum well structure. Gap energy is controlled so that the emission wavelength band can be adjusted. Typically, when the mole fraction of In changes by 1%, the emission wavelength is shifted by about 5 nm.

Although the first-type semiconductor layer 1500 and the second-type semiconductor layer 1700 are illustrated as a single-layer structure, they may be formed of a plurality of layers.

In addition, although it is shown that the first type semiconductor layer 1500 is formed on the nitride semiconductor layer 1300, when the nitride semiconductor layer 1300 is formed, the type 1 semiconductor layer 1500 may be formed by doping the first type impurity. may be

In the above description, the device layer has been described by exemplifying the LED structure, but in addition, it may be formed of a Laser Diode (LD), Field Effect Transistor (FET), High Electron Mobility Transistor (HEMT), or Schottky Diode structure. .

The semiconductor device 2001 of FIG. 24 may include various types of electrode structures in which currents are injected so that electrons and holes are recombined in the active layer 1600 , and FIGS. 25 to 27 show such examples.

24 to 27 are cross-sectional views illustrating various examples in which a semiconductor device according to an embodiment of the present invention is applied as a light emitting device.

Referring to FIG. 24 , the light emitting device 2001 is formed on the type 1 semiconductor layer 1500 exposed by etching predetermined regions of the type 2 semiconductor layer 1700 , the active layer 1600 , and the type 1 semiconductor layer 1500 . A first electrode 191 is formed on the first electrode 191 , and a second electrode 192 is formed on the second type semiconductor layer 1700 . A transparent electrode layer 1800 may be further formed between the type 2 semiconductor layer 1700 and the second electrode 1920 .

This type of chip structure is called an epi-up structure.

The first electrode 1910 and the second electrode 1920 are formed of a single material of a metal such as Ag, Al, Ni, Cr, Pd, Cu, Pt, Sn, W, Au, Rh, Ir, Ru, Mg, Zn, or It may be made of an alloy. or Ni/Ag, Zn/Ag, Ni/Al, Zn/Al, Pd/Ag, Pd/Al, Ir/Ag. It may have a structure of two or more layers, such as Ir/Au, Pt/Ag, Pt/Al, Ni/Ag/Pt, or the like.

The transparent electrode layer 1800 may be made of a transparent conductive oxide (TCO), for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), AZO (Aluminum Zinc Oxide), ZnO, It may be made of GZO (ZnO:Ga), In2O3, SnO2, CdO, CdSnO4, Ga2O3, or the like.

25 is a cross-sectional view schematically illustrating a vertical structure of a light emitting device 2002 as a semiconductor device according to another embodiment.

The light emitting device 2002 is a form in which the silicon substrate S, the buffer layer 1200, and the interface control layer (ICL) used for the epitaxial growth are removed, and the support substrate 2070 is provided on the side of the type 2 semiconductor layer 1700 . can be

The silicon substrate S, the nucleation layer 120, the buffer layer 1200, and the interface control layer (ICL) are removed, and the exposed upper surface of the type 1 semiconductor layer 1500 is textured to increase light extraction efficiency. It may include a concave-convex surface 1500a having a concave-convex pattern. The concave-convex pattern is not limited to the illustrated shape, and may have various periods, heights, and shapes, and may also be formed in an irregular pattern.

In the drawing, the silicon substrate S, the buffer layer 1200, and the interface control layer (ICL) are all removed, but at least a portion of the interface control layer (ICL) and the buffer layer 1200 is a type 1 semiconductor layer ( 1500), and may be textured together with the type 1 semiconductor layer 1500 to form the concave-convex surface 1500a.

The first electrode 2010 is formed on the type 1 semiconductor layer 1500 , the second electrode 2030 is formed on the lower surface of the type 2 semiconductor layer 1700 , and the second electrode 2030 and the supporting substrate ( A bonding metal layer 2050 may be provided between 2070 . The bonding metal layer 2050 may include, for example, Au/Sn. The support substrate 2070 is a Si substrate, or a SiAl substrate may be used. A back metal layer 2090 may be formed on a lower surface of the support substrate 2070 .

26 is a cross-sectional view showing a schematic structure of a light emitting device 2003 having a vertical-horizontal structure as a semiconductor device according to another embodiment.

The light emitting device 2003 has a form in which the silicon substrate S used for epitaxial growth, the buffer layer 1200, and the interface control layer are removed, and the support substrate 2250 may be provided on the side of the type 2 semiconductor layer 1700 . have.

The silicon substrate S, the buffer layer 1200, and the interface control layer (ICL) are removed, and the exposed upper surface of the type 1 semiconductor layer 1500 is textured to increase light extraction efficiency, and includes an uneven surface 1500a. can do. Also, in the drawings, the silicon substrate S, the buffer layer 1200 , and the interface control layer ICL are all removed, but at least a portion of the interface control layer ICL and the buffer layer 1200 is a type 1 semiconductor. It may remain on the layer 1500 and may be textured together with the type 1 semiconductor layer 1500 .

A plurality of via holes VH passing through the first-type semiconductor layer 1500 and the active layer 1600 are formed to form the first electrode 2150 in contact with the first-type semiconductor layer 1500 . A second electrode 2130 is formed on the semiconductor layer 1700 . A metal layer 2170 for connection to the electrode pad 2290 is formed on the second electrode 2130 . The first passivation layer 2100 is formed to cover the side surfaces of the plurality of via holes and a portion of the upper surface of the second type semiconductor layer 1700, and the second passivation layer 2190 is formed to cover the metal layer 2170. have. The barrier metal layer 2210 is connected to the first electrode 2150 and is formed to fill a plurality of via holes.

A bonding metal layer 2230 may be formed on an upper surface of the support substrate 2250 , and a back metal layer 2270 may be formed on a lower surface of the support substrate 2250 .

27 is a cross-sectional view showing a schematic structure of a flip-chip type light emitting device 2004 as a semiconductor device according to another embodiment.

The light emitting device 2004 according to the embodiment is different from the light emitting device 2003 of FIG. 25 in that the first electrode 2150 and the second electrode 2130 are both electrically exposed downward.

That is, the second passivation layer 2190 is patterned to expose a portion of the metal layer 2170 in contact with the first electrode 2130 . In addition, the barrier metal layer 2211 is patterned to be electrically separated into two parts, so that one part contacts the first electrode 2150 and the other part contacts the second electrode 2130 .

The support substrate 2250 may be a non-conductive substrate on which the first conductive vias CV1 and the second conductive vias CV2 are formed. The upper and lower bonding metal layers 2231 and 2271 of the support substrate 2250 are patterned to have two electrically separated regions, respectively. One region of the bonding metal layer 2231 and one region of the back metal layer 2271 are electrically connected to each other through the first conductive via CV1 , and the other region of the metal layer 2231 and the back metal layer 2271 are electrically connected to each other. The other regions of the are electrically connected to each other through the second conductive via CV2 , thereby exposing the first electrode 2150 and the second electrode 2130 to the outside.

As the support substrate 2250 , a non-conductive substrate on which conductive vias are formed has been exemplarily described, but the present invention is not limited thereto, and a conductive substrate on which insulating vias are formed may be used.

28 is a cross-sectional view illustrating an example of a light emitting device 2005 that emits white light as a semiconductor device according to another embodiment.

The light emitting device 2005 may be formed by further coating the wavelength conversion layer 2300 on the semiconductor device 2004 of FIG. 27 .

The wavelength conversion layer 2300 functions to convert the wavelength of light emitted from the active layer 1600 , and may include a wavelength conversion material such as a phosphor or quantum dots. When the wavelength conversion material is a phosphor and blue light is emitted from the active layer 1600, as the red phosphor, a nitride-based phosphor of MAlSiNx:Re (1≤x≤5) and a sulfide-based phosphor of MD:Re are the wavelength conversion layer ( 2300) can be used. Here, M is at least one selected from Ba, Sr, Ca, and Mg, D is at least one selected from S, Se, and Te, and Re is Eu, Y, La, Ce, Nd, Pm, Sm, Gd, Tb, At least one selected from Dy, Ho, Er, Tm, Yb, Lu, F, Cl, Br, and I. In addition, the green phosphor includes a silicate-based phosphor of M2SiO4:Re, a sulfide-based phosphor of MA2D4:Re, a β-SiAlON:Re phosphor, and an oxide-based phosphor of MA'2O4:Re', where M is Ba, Sr, Ca , at least one element selected from Mg, A is at least one selected from Ga, Al, and In, D is at least one selected from S, Se, and Te, and A' is Sc, Y, Gd, La, Lu, Al And at least one selected from In, Re is at least one selected from Eu, Y, La, Ce, Nd, Pm, Sm, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, F, Cl, Br, and I and Re' may be at least one selected from Ce, Nd, Pm, Sm, Tb, Dy, Ho, Er, Tm, Yb, F, Cl, Br, and I.

In addition, the wavelength conversion material may be a quantum dot. Quantum dots are nanocrystal particles composed of a core and a shell, and the size of the core is in the range of about 2 to 100 nm. In addition, quantum dots can be used as fluorescent materials emitting various colors such as blue (B), yellow (Y), green (G), and red (R) by controlling the size of the core, and group II-VI compound semiconductors (ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, HgSe, HgTe, MgTe, etc.), III-V compound semiconductors (GaN, GaP, GaAs, GaSb, InN, InP, InAs, InSb, AlAs, AlP , AlSb, AlS, etc.) or group IV semiconductors (Ge, Si, Pb, etc.) may be heterojunctioned to form a core and shell structure constituting quantum dots. In this case, oleic acid (Oleic acid) is used to terminate the molecular bonding of the shell surface to the outer shell of the quantum dot, suppress aggregation of quantum dots, improve dispersibility in a resin such as silicone resin or epoxy resin, or improve the phosphor function. acid) may be used to form an organic ligand.

The wavelength conversion layer 2300 is shown to be formed to cover the entire light emitting structure consisting of the first type semiconductor layer 1500, the active layer 1600, and the second type semiconductor layer 1700, that is, the upper part and the side part, This is exemplary, and may be formed only on the first type semiconductor layer 1500 .

29 is a cross-sectional view illustrating an example of a light emitting device package 2006 as a semiconductor device according to another embodiment.

The light emitting device package 2006 may further include a lens 2400 formed on the light emitting device 2005 of FIG. 28 . The lens 2400 may function as a protective layer for the light emitting structure, and may also serve to adjust the beam angle of light emitted from the light emitting structure. The lens 2400 may be formed in a state separated into individual chips, or formed at a wafer level and diced together with the support substrate 2250 . Although the lens 2400 is shown to cover both the upper part and the side part of the light emitting device, this is exemplary and may be disposed only on the upper part.

In the light emitting device and light emitting device package described above, a light emitting structure may be grown using a silicon substrate, and the growth substrate may be removed using a silicon-based support substrate. In this case, the coefficient of thermal expansion between the growth substrate and the support substrate is substantially the same, and when the support substrate is attached, the stress generated on the wafer when the growth substrate is removed is minimized, resulting in less wafer warpage, Alternatively, when manufacturing a chip-scale package, handling may be easy and yield may be improved.

30 is an exploded perspective view illustrating an example of a lighting device 3000 employing a light emitting device package according to an embodiment.

Referring to FIG. 30 , the lighting device 3000 is illustrated as a bulb-type lamp as an example, and includes a light emitting module 3003 , a driving unit 3008 , and an external connection unit 3010 . In addition, external structures such as the outer and inner housings 3006 and 3009 and the cover portion 3007 may be additionally included.

The light emitting module 3003 may include a light emitting device package 3001 and a circuit board 3002 on which the light emitting device package 3001 is mounted. The light emitting device package 2006 shown in FIG. 28 may be employed as the light emitting device package 3001 . However, the present invention is not limited thereto, and various types of light emitting device packages manufactured using the semiconductor buffer structure according to the embodiment may be employed. In the drawings, one light emitting device package 3001 is exemplified in a mounted form on the circuit board 3002 , but a plurality of light emitting device packages 3001 may be mounted as needed. In this case, the plurality of light emitting device packages 3001 may be of the same type that generates light of the same wavelength. Alternatively, it may be variously configured as a heterogeneous type that generates light of different wavelengths. For example, the light emitting device package 3001 is configured to include at least one of a light emitting device that emits white light by combining a blue LED with a yellow, green, red or orange phosphor and a purple, blue, green, red or infrared light emitting device. can be In this case, the lighting device 3000 can adjust the color rendering (CRI) from the sodium (Na) lamp 40 to the sunlight 100 level, and the color temperature from the candlelight (1500K) to the blue sky (12000K) level. A variety of white light can be generated. In addition, if necessary, purple, blue, green, red, or orange visible light or infrared light may be generated to adjust the lighting color according to the surrounding atmosphere or mood. It can also generate special wavelengths of light that can promote plant growth.

In addition, in the lighting device 3000 , the light emitting module 3003 may include an outer housing 3006 serving as a heat dissipating part, and the outer housing 3006 is in direct contact with the light emitting module 3003 to improve the heat dissipation effect. A heat dissipation plate 3004 may be included. Also, the lighting device 3000 may include a cover portion 3007 mounted on the light emitting module 3003 and having a convex lens shape. The driving unit 3008 may be mounted on the inner housing 3009 and connected to an external connection unit 3010 such as a socket structure to receive power from an external power source. In addition, the driving unit 3008 serves to convert and provide an appropriate current source capable of driving the semiconductor light emitting device 3001 of the light emitting module 3003 . For example, the driving unit 3008 may be composed of an AC-DC converter or a rectifier circuit component.

The semiconductor device according to the embodiment of the present invention has been described with reference to the embodiment shown in the drawings for better understanding, but this is merely exemplary, and those of ordinary skill in the art may make various modifications and equivalents therefrom. It will be appreciated that embodiments are possible. Accordingly, the true technical protection scope of the present invention should be defined by the appended claims.

100,100A,200,2000,2001,2002,2003,2004...Semiconductor device,
110,210...substrate, 113...nuclear growth layer
115,215,315,330,340,1200...buffer layer
120,220,ICL...interface control layer, 125,225,235...nitride laminate
230...active layer

Claims (21)

forming a buffer layer on a silicon substrate;
forming an interface control layer on the buffer layer under first growth conditions; and
and forming a nitride laminate on the interface control layer under a second growth condition different from the first growth condition;
The first growth condition and the second growth condition are adjusted so that the ratio of the minimum value of the reflectance vibration center value of the interface control layer to the maximum value of the reflectance vibration center value of the nitride laminate has a range of 0.8 or more,
The interface control layer is formed to have a thickness in the range of 2 ~ 320nm,
The interface control layer is formed at a first temperature in the range greater than 900 ℃ and less than 1050 ℃,
A method of manufacturing a semiconductor device, wherein a ratio of the roughness of the interface control layer to the roughness of the buffer layer is in a range of 3 or less. According to claim 1,
A method for manufacturing a semiconductor device, wherein a ratio of a minimum value of a reflectance vibration center of an interface control layer to a maximum value of a reflectance vibration center value of the nitride laminate is in a range of 0.9 or more. According to claim 1,
The interface control layer is a semiconductor device manufacturing method in which at least one of temperature, pressure, and thickness is formed under a condition different from that of the nitride laminate. According to claim 1,
The method for manufacturing a semiconductor device wherein the nitride laminate is formed at a second temperature higher than the first temperature. 5. The method of claim 4,
The interface control layer is formed at a first pressure in the range of 20 to 500 torr, and the nitride stack is formed at a second pressure equal to or higher than the first pressure. delete According to claim 1,
The interface control layer and the nitride laminate are formed of a group V/III compound, and when the interface control layer is grown, a molar composition ratio of the group V material and the group III material ranges from 20 to 2000. 8. The method according to any one of claims 1 to 5 and 7,
The method of manufacturing a semiconductor device in which the interface control layer is continuously stacked on the buffer layer without intervening other layers. 6. The method according to any one of claims 1 to 5,
A method for manufacturing a semiconductor device in which the nitride stack is continuously stacked on the interface control layer without intervening other layers. 10. The method of claim 9,
The nitride laminate includes at least one nitride semiconductor layer formed of a nitride containing gallium. 6. The method according to any one of claims 1 to 5,
The nitride laminate is a semiconductor device manufacturing method in which a plurality of nitride semiconductor layers formed of the same kind of nitride compound are sequentially stacked. 6. The method according to any one of claims 1 to 5,
The nitride laminate _{is a semiconductor device manufacturing method formed of Al x1} In _y1 Ga _1-x1-y1 N (0≤x1, y1≤1, x1+y1≤1). 6. The method according to any one of claims 1 to 5,
The buffer layer includes one layer or a plurality of layers, and is formed of Al _x2 In _y2 Ga _1-x2-y2 N (0≤x2, y2≤1, x2+y2≤1). 6. The method according to any one of claims 1 to 5,
A method of manufacturing a semiconductor device for forming a nucleation layer between the silicon substrate and the buffer layer. 15. The method of claim 14,
The nucleation layer is a semiconductor device manufacturing method formed of AlN. delete silicon substrate;
a buffer layer on the silicon substrate;
an interface control layer provided on the buffer layer; and
Including; a nitride laminate on the interface control layer;
The ratio of the maximum value of the reflectance vibration center of the interface control layer to the maximum value of the reflectance vibration center value of the nitride laminate has a range of 0.8 or more,
The interface control layer has a thickness in the range of 2 to 320 nm,
A ratio of the roughness of the interface control layer to the roughness of the buffer layer is 3 or less. 18. The method of claim 17,
The ratio of the minimum value of the reflectance vibration center of the interface control layer to the maximum value of the reflectance vibration center value of the nitride laminate has a range of 0.9 or more. 19. The method of claim 17 or 18,
The interface control layer is _{a semiconductor device formed of Al x3} In _y3 Ga _{1 -x3-y3} N (0≤x3, y3≤1, x3+y3<1). delete 19. The method of claim 17 or 18,
The interface control layer is formed of a group V/III compound, and when the interface control layer is grown, a molar composition ratio of the group V material and the group III material ranges from 20 to 2000.

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