KR102332310B1 - Display device - Google Patents

Abstract

A display device according to an exemplary embodiment includes a pixel circuit including a transistor and a capacitor and outputting an image, a data line extending in a first direction, and a gate line extending in a second direction perpendicular to the first direction. wherein a gate electrode of the transistor is connected to the gate line and extends in the first direction, a first electrode of the transistor is connected to the data line and extends in the second direction, and a second electrode of the transistor is connected to the data line and extends in the second direction. extends in the first direction and is connected to the first electrode of the capacitor, the second electrode of the capacitor is disposed below the first electrode of the capacitor, and the first electrode of the capacitor and the first electrode of the capacitor The second electrode extends in the first direction.

Description

display device {DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device having a reduced pixel pitch.

Recently, due to the expansion of the application range, high-quality and high-quality characteristics are increasingly required for displays. In particular, the demand for fast response speed, high contrast ratio, and wide viewing angle characteristics for displays applied to TVs and portable mobile devices is increasing.

In particular, as a high-resolution display is developed, a hologram can be implemented based on a panel having a high resolution. In the case of a hologram implemented with a pixel pitch of a general display, the viewing angle is only about 1°. Therefore, in order to increase the viewing angle in realizing the hologram, the pitch of the pixels should be reduced.

In general, in order to reduce the pitch of a pixel, it is necessary to reduce the length of a channel of a transistor in the pixel. However, since the direction of the current flowing in the transistor of the pixel (the direction of extension of the channel) is perpendicular to the direction of extension of the data line, there is a limit to reducing the length of the channel of the transistor in order to secure ON/OFF characteristics and efficiently drive the transistor. exist. Accordingly, a new method for reducing the pixel pitch is required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display device having a reduced pixel pitch. More specifically, the present invention provides a display device in which a pixel pitch is reduced by forming a current direction in a transistor parallel to an extension direction of a data line.

A display device according to an exemplary embodiment includes a pixel circuit including a transistor and a capacitor and outputting an image, a data line extending in a first direction, and a gate line extending in a second direction perpendicular to the first direction. wherein a gate electrode of the transistor is connected to the gate line and extends in the first direction, a first electrode of the transistor is connected to the data line and extends in the second direction, and a second electrode of the transistor is connected to the data line and extends in the second direction. extends in the first direction and is connected to the first electrode of the capacitor, the second electrode of the capacitor is disposed below the first electrode of the capacitor, and the first electrode of the capacitor and the first electrode of the capacitor The second electrode extends in the first direction.

In the pixel circuit, the second electrode of the transistor extends in a first direction, so that a current received from the data line flows in the first direction on the transistor, and the first electrode of the storage capacitor also has a second electrode in the same direction as the extending direction of the second electrode of the transistor. By extending in the first direction, the length of the pixel in the second direction is reduced. Accordingly, since the current flows in the first direction instead of the second direction on the transistor, the length of the pixel in the second direction is reduced. Nevertheless, the semiconductor layer of the transistor can secure a sufficient length, and it is more efficient than before. A pixel circuit can be designed. Furthermore, since the pixel pitch is reduced, a wider viewing angle can be secured in a high-resolution display through the structure.

1 is a schematic block diagram of a display device according to an exemplary embodiment.
FIG. 2 is a diagram illustrating an equivalent circuit diagram of the pixel illustrated in FIG. 1 .
FIG. 3 is a diagram illustrating a layout of the pixel illustrated in FIG. 1 .
4 is a cross-sectional view taken along line AA′ of FIG. 3 .

Advantages and features of the present invention, and a method for achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and those of ordinary skill in the art to which the present invention pertains. It is provided to fully inform the person of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

Reference to an element or layer “on” or “on” another element or layer includes not only directly on the other element or layer, but also with intervening other layers or elements. include all On the other hand, reference to an element "directly on" or "immediately on" indicates that no intervening element or layer is interposed. “and/or” includes each and every combination of one or more of the recited items.

Spatially relative terms "below", "beneath", "lower", "above", "upper", etc. It can be used to easily describe the correlation between an element or components and other elements or components. The spatially relative terms should be understood as terms including different orientations of the device during use or operation in addition to the orientation shown in the drawings. Like reference numerals refer to like elements throughout.

Although first, second, etc. are used to describe various elements, components, and/or sections, it should be understood that these elements, components, and/or sections are not limited by these terms. These terms are only used to distinguish one element, component, or sections from another.

Embodiments described herein will be described with reference to a plan view and a cross-sectional view, which are ideal schematic views of the present invention. Accordingly, the form of the illustrative drawing may be modified due to manufacturing technology and/or tolerance. Accordingly, embodiments of the present invention are not limited to the specific form shown, but also include changes in the form generated according to the manufacturing process. Accordingly, the regions illustrated in the drawings have a schematic nature, and the shapes of the illustrated regions in the drawings are for illustrating specific shapes of regions of the device, and not for limiting the scope of the invention.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

1 is a schematic block diagram of a display device 1000 according to an exemplary embodiment.

Referring to FIG. 1 , a display device 1000 according to an embodiment of the present invention includes a display panel 100 for displaying an image, a gate driver 200 and a data driver 300 for driving the display panel 100 , and a control unit 400 for controlling driving of the gate driver 200 and the data driver 300 .

The controller 400 receives input image data RGB and a plurality of control signals CS from the outside of the display device 1000 . The controller 400 converts the data format of the input image data RGB to meet the interface specification of the data driver 300 to generate image data ID, and transmits the image data ID to the data driver 300 . to provide.

In addition, the control unit 400 includes a data control signal (eg, an output start signal, a horizontal start signal, etc.) and a gate control signal (GCS, for example, a vertical start signal) based on the plurality of control signals CS. , a vertical clock signal, and a vertical clock bar signal). The data control signal DCS is provided to the data driver 300 , and the gate control signal GCS is provided to the gate driver 200 .

The gate driver 200 sequentially outputs gate signals in response to the gate control signal GCS provided from the controller 400 .

The data driver 300 converts the image data ID into data voltages in response to the data control signal DCS provided from the controller 400 and outputs the converted data voltages. The output data voltages are applied to the display panel 100 .

The display panel 100 includes a plurality of gate lines GL1 to GLn, a plurality of data lines DL1 to DLm, and a plurality of pixels PX. The plurality of pixels PX may display a main color. In detail, each of the pixels PX may display any one color of red, green, and blue.

The pixels PX are devices that display a unit image constituting an image, and the resolution of the display panel 100 may be determined according to the number of pixels PX included in the display panel 100 . In FIG. 1, only some of the pixels are shown, and the rest are omitted.

The plurality of gate lines GL1 to GLn extend in one direction and are parallel to each other in a direction perpendicular to the one direction. The plurality of gate lines GL1 to GLn are connected to the gate driver 200 to receive gate signals from the gate driver 200 .

The plurality of data lines DL1 to DLm extend in a direction parallel to the direction in which the plurality of gate lines GL1 to GLn are arranged, and are arranged in a direction parallel to the direction in which the plurality of gate lines GL1 to GLn are extended. do. The plurality of data lines DL1 to DLm are connected to the data driver 300 to receive data voltages from the data driver 300 .

Each of the pixels PX may be driven by being connected to a corresponding gate line among the plurality of gate lines GL1 to GLn and a corresponding data line among the plurality of data lines DL1 to DLm.

FIG. 2 is a diagram illustrating an equivalent circuit diagram of the pixel PX shown in FIG. 1 .

As illustrated in FIG. 2 , each of the pixels PX may include a pixel circuit. The pixel circuit may include a transistor TR and capacitors Cst and Clc.

The transistor TR is electrically connected to the i-th gate line GLi and the j-th data line DLj. The transistor TR outputs the data signal received from the j-th data line DLj in response to the gate signal received from the i-th gate line GLi.

The liquid crystal capacitor Clc charges a voltage corresponding to the data signal output from the j-th data line DLj. The arrangement of the liquid crystal director (not shown) included in the liquid crystal layer LC (shown in FIG. 4 ) is changed according to the amount of charge charged in the liquid crystal capacitor Clc. Light incident on the liquid crystal layer LC is transmitted or blocked according to the arrangement of the liquid crystal director.

The storage capacitor Cst maintains the arrangement of the liquid crystal director for a predetermined period. However, the storage capacitor Cst may not be included in the pixel PXij.

3 is a diagram illustrating a layout of the pixel PX illustrated in FIG. 1 .

FIG. 3 shows any one of the gate lines GL1 among the plurality of gate lines GL1 to GLn shown in FIG. 1 , and any one of the plurality of data lines DL1 to DLm shown in FIG. 1 . of the data line DL is shown. However, the gate line GL and the data line DL described in FIG. 3 may be applied to the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm, respectively.

2 and 3 , the data line DL may extend in the first direction DR1 . The gate line GL may extend in the second direction DR2 . The first direction DR1 and the second direction DR2 may be perpendicular to each other.

The gate electrode 302 of the transistor TR may be connected to the gate line GL. In more detail, the gate electrode 302 of the transistor TR may be branched from the gate line GL and may be electrically connected to the gate line GL. As an example of the present invention, the gate electrode 302 of the transistor TR may extend from the gate line GL in the first direction DR1 .

The first electrode 301 of the transistor TR may be connected to the data line DL. More specifically, the first electrode 301 of the transistor TR may be branched from the data line DL and electrically connected to the data line DL. As an example of the present invention, the first electrode 301 of the transistor TR may be a drain electrode and may extend from the data line DL in the second direction DR2 .

The first electrode 301 of the transistor TR may be connected to one end of the semiconductor layer 304 of the transistor TR, and the second electrode of the transistor TR may be connected to the other end of the semiconductor layer 304 of the transistor TR. 303 may be connected. When the gate voltage from the gate line GL is applied to the gate electrode 302 of the transistor TR to turn on the transistor TR, the semiconductor layer 304 of the transistor TR is A flow of charges may occur in a direction parallel to the first direction DR1 . In more detail, a current may flow from the first electrode 301 of the transistor TR to the semiconductor layer 304 and from the semiconductor layer 304 to the second electrode 303 of the transistor TR.

The second electrode 303 of the transistor TR may be connected to the semiconductor layer 304 . In more detail, one end of the second electrode 303 of the transistor TR may be connected to the semiconductor layer 304 , and the other end of the second electrode 303 of the transistor TR is the storage capacitor Cst. It may be connected to the first electrode 305 . As an example of the present invention, the second electrode 303 of the transistor TR may be a source electrode, and the second electrode 303 of the transistor TR and the first electrode 305 of the storage capacitor Cst are integrally formed. can be formed with

A second electrode 306 of the storage capacitor Cst may be disposed below the first electrode 305 of the storage capacitor Cst. The second electrode 306 of the storage capacitor Cst may include a conductive material. As an example of the present invention, the second electrode 306 of the storage capacitor Cst may include a metal material. The first electrode 305 of the storage capacitor Cst and the second electrode 306 of the storage capacitor Cst are configured to face each other and may have a constant capacitance.

A pixel electrode 310 may be disposed on the storage capacitor Cst. The pixel electrode 310 may be electrically connected to the first electrode 305 of the storage capacitor Cst through the contact hole CH. The pixel electrode 310 may receive an image signal from the second electrode 303 of the transistor TR. The pixel electrode 310 may be disposed above the transistor TR and the storage capacitor Cst. More specifically, the pixel electrode 310 may be disposed above the transistor TR and the storage capacitor Cst to cover both the transistor TR and the storage capacitor Cst. As an example of the present invention, the pixel electrode 310 may be a reflective electrode 310 .

As such, the second electrode 303 of the transistor TR extends in the first direction DR1 , so that the current received from the data line DL flows in the first direction DR1 on the transistor TR, and the storage capacitor The first electrode 305 of (Cst) also extends in the same first direction DR1 as the extending direction of the second electrode 303 of the transistor TR, so that the pixel PX moves in the second direction DR2 of the pixel PX. length will decrease. Accordingly, since the direction of the current flowing through the transistor TR becomes the first direction DR1 , the length of the pixel PX in the second direction DR2 also decreases, and the semiconductor layer 304 of the transistor TR becomes It is possible to secure a sufficient length in the first direction DR1 , so that it is possible to design a pixel circuit more efficient than the conventional one. Furthermore, since the pitch of the pixels PX is reduced, a wider viewing angle can be secured in the high-resolution display through the corresponding structure.

Also, in the present invention, the structure of the transistor TR and the capacitors Cst and Clc has been described on the premise of the liquid crystal display, but the contents may also be applied to the pixel structure of various display devices such as an organic light emitting diode display. is of course

4 is a cross-sectional view taken along line A-A' of FIG. 3 .

Referring to FIG. 4 , the gate electrode 302 of the transistor TR and the second electrode 306 of the storage capacitor Cst are disposed on the substrate BS. An insulating layer 401 may be formed on the gate electrode 302 of the transistor TR and the second electrode 306 of the storage capacitor Cst. In more detail, the insulating layer 401 may be formed entirely on the gate electrode 302 of the transistor TR and the second electrode 306 of the storage capacitor Cst. The insulating layer 401 may include silicon nitride (SiNx) and silicon oxide (SiOx).

A semiconductor layer 304 including amorphous silicon (a-Si:H) may be disposed on the insulating layer 401 . In addition, the first electrode 301 of the transistor TR and the second electrode 303 of the transistor TR may be formed on the semiconductor layer 304 . The first electrode 305 of the storage capacitor Cst extends from the second electrode 303 of the transistor TR and is disposed on the insulating layer 401 to overlap the second electrode 306 of the storage capacitor Cst. can be

A passivation layer 405 may be disposed on the transistor TR and the storage capacitor Cst. The passivation layer 405 may be entirely disposed on the substrate BS to cover the transistor TR and the storage capacitor Cst. The passivation layer 405 may include an organic insulating material such as benzocyclobutene (BCB) and an acryl-based resin.

The contact hole CH described with reference to FIG. 3 may be defined in the passivation layer 405 . The contact hole CH may be defined in a portion of the passivation layer 405 that overlaps the storage capacitor Cst. The pixel electrode 310 may be connected to the storage capacitor Cst through the contact hole CH. In more detail, the pixel electrode 310 may be electrically connected to the first electrode 305 of the storage capacitor Cst through the contact hole CH. As described above, the pixel electrode 310 may be the reflective electrode 310 and may include a conductive material having low resistance and excellent reflectance, such as aluminum (Al) or an aluminum alloy.

A liquid crystal layer LC may be formed on the pixel electrode 310 . A common electrode 311 may be formed on the liquid crystal layer LC. The common electrode 311 may form an electric field with the pixel electrode 310 . That is, each of the common electrode 311 and the pixel electrode 310 may be the first electrode and the second electrode of the liquid crystal capacitor Clc described with reference to FIG. 2 .

Although described with reference to the above embodiments, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. will be able In addition, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, and all technical ideas within the scope of the following claims and their equivalents should be construed as being included in the scope of the present invention. .

TR: transistor 310: pixel electrode
304: semiconductor layer CH: contact hole
Cst: storage capacitor LC: liquid crystal layer

Claims (10)

a pixel circuit including a transistor and a capacitor and outputting an image;
a data line extending in a first direction; and
a gate line extending in a second direction perpendicular to the first direction;
a gate electrode of the transistor is connected to the gate line and extends in the first direction;
a first electrode of the transistor is connected to the data line and extends in the second direction, the first electrode of the transistor is a drain electrode;
a second electrode of the transistor extends in the first direction and is connected to the first electrode of the capacitor, the second electrode of the transistor is a source electrode;
A second electrode of the capacitor is disposed below the first electrode of the capacitor, and the first electrode of the capacitor and the second electrode of the capacitor extend in the first direction. According to claim 1,
and a semiconductor layer electrically connecting the first electrode of the transistor and the second electrode of the transistor.
According to claim 1,
a pixel electrode on the capacitor;
The pixel electrode is electrically connected to the first electrode of the capacitor.
4. The method of claim 3,
a protective layer disposed on the first electrode of the transistor, the second electrode of the transistor, and the first electrode of the capacitor;
The passivation layer is disposed between the first electrode of the capacitor and the pixel electrode.
5. The method of claim 4,
The protective layer includes benzocyclobutene (BCB) or an acryl-based resin.
4. The method of claim 3,
The pixel electrode is a reflective electrode.
4. The method of claim 3,
and a liquid crystal layer on the pixel electrode.
8. The method of claim 7,
and a common electrode on the liquid crystal layer.
According to claim 1,
and an insulating layer disposed adjacent to the gate electrode of the transistor and the second electrode of the capacitor.
10. The method of claim 9,
The insulating layer includes a silicon nitride (SiNx) or a silicon oxide (SiOx).

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