KR102310801B1 - Methods for forming interconnect layers having tight pitch interconnect structures - Google Patents

Abstract

Processes are disclosed for forming interconnection layers having dense pitch interconnect structures in a dielectric layer, wherein trenches and vias used to form the interconnect structures have relatively low aspect ratios prior to metallization. Low aspect ratios can reduce or substantially eliminate the likelihood of voids forming in the metallization material as it is deposited. Embodiments herein may achieve these relatively low aspect ratios through processes that allow removal of structures used to form trenches and vias prior to metallization.

Description

METHODS FOR FORMING INTERCONNECT LAYERS HAVING TIGHT PITCH INTERCONNECT STRUCTURES

BACKGROUND Embodiments of the present description relate generally to the field of microelectronic device fabrication, and more particularly to forming interconnection layers having dense pitch interconnect structures in a dielectric layer. The trenches and vias used to form the interconnect structures are fabricated to have relatively low aspect ratios prior to metallization, where the low aspect ratios reduce or substantially reduce the likelihood of voids forming in the metallization material as it is deposited. removed with

The microelectronics industry is constantly striving to manufacture much faster and smaller microelectronic devices for use in a variety of mobile electronic products such as portable computers, electronic tablets, cellular phones, digital cameras, and the like. As these objectives are achieved, the fabrication of microelectronic devices becomes more difficult. One such area of challenge relates to interconnect layers used to connect discrete devices on a microelectronic chip and/or transmit and/or receive signals external to the discrete device(s). Interconnect layers generally include a dielectric material having conductive interconnects (lines), such as copper and copper alloy, that are connected to individual devices. The interconnects (lines) generally include a metal line portion and a metal via portion, the metal line portion formed in a trench in a dielectric material, and the metal via portion formed in a via opening extending from the trench through the dielectric material. It is understood that multiple interconnection layers (eg, 5 or 6 levels) may be formed to achieve the desired electrical connections.

As these interconnects are fabricated with smaller pitches (eg, narrower and/or closer together), it becomes increasingly difficult to properly align trenches and vias in and between the desired interconnect layer. In particular, during manufacturing, the position of via edges relative to an interconnect layer or line with which the via edges contact will fluctuate (eg, misalign) due to natural manufacturing variations. However, vias should allow connecting one interconnect layer to a desired underlying interconnect layer or line without erroneously connecting different interconnect layers or lines. If the vias are misaligned and contact the wrong metal feature (eg, failing to reach the underlying line and/or connecting two lines), the microelectronic chip can short circuit and degrade electrical performance. One solution to address this problem is to reduce the trench and via size (eg, make the via narrower). However, reducing the trench and via size means that the aspect ratio of the openings in the trench and via can be high. As will be appreciated by those skilled in the art, high aspect ratios can result in potential yield reductions due to voiding during deposition of the conductive material (metallization) used to form the interconnects.

The subject matter of the present disclosure is specifically pointed out and explicitly claimed in the concluding part of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims when taken in conjunction with the accompanying drawings. It is to be understood that the accompanying drawings illustrate only several embodiments in accordance with the present disclosure and should not be considered as limiting the scope thereof. The present disclosure will be described in further detail and detail with reference to the accompanying drawings so that the advantages of the present disclosure may be more readily ascertained.
1-28 illustrate cross-sectional views of a method of forming an interconnection layer in accordance with an embodiment of the present description.
29 is a flowchart of a process for manufacturing an interconnection layer according to an embodiment of the present description.
30 illustrates a computing device according to one implementation of the present description.

In the following detailed description, reference is made to the accompanying drawings, which show by way of illustration specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable any person skilled in the art to practice the subject matter. It should be understood that the various embodiments, while different, are not necessarily mutually exclusive. For example, in connection with one embodiment, a particular feature, structure, or characteristic described herein may be implemented in other embodiments without departing from the spirit and scope of the claimed subject matter. Reference to “one embodiment” or “an embodiment” in this specification is at least one specific feature, structure, or characteristic described in connection with this embodiment is included in this description. means to be included in the implementation of Therefore, use of the phrases “in one embodiment” or “in an embodiment” is not necessarily referring to the same embodiment. Additionally, it should be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. Therefore, the following detailed description is not to be taken in a limiting sense, the scope of the subject matter being defined only by the appended claims being properly construed, along with the full scope of equivalents to which they are assigned. In the drawings, like numbers refer to the same or similar elements or functionality throughout the several drawings, and the elements depicted therein are not necessarily to scale with one another, rather, individual elements refer to elements in the context of this description. It may be enlarged or reduced for ease of understanding.

As used herein, the terms “over”, “to”, “between” and “on” refer to the position of one layer relative to other layers. can be mentioned One layer that is "on" or "on" or bonded to" another layer may be in direct contact with the other layer, or may have one or more intervening layers. One layer “between” the layers may be in direct contact with these layers, or may have one or more intervening layers.

Embodiments of the present description include forming interconnection layers having dense pitch interconnect structures in a dielectric layer, wherein the trenches and vias used to form the interconnect structures have relatively low aspect ratios prior to metallization. Low aspect ratios can reduce or substantially eliminate the likelihood of voids forming in the metallization material as it is deposited. Embodiments of the present description may achieve these relatively low aspect ratios through processes that allow removal of structures used to form trenches and vias prior to metallization.

1 illustrates stacked layers for backbone patterning. The stacked layer 100 is a dielectric layer 104 formed on the substrate 102 , a first hardmask layer 106 formed on the dielectric layer 104 , and a backbone material formed on the first hardmask layer 106 . 108 , a second hardmask layer 112 formed on the backbone material 108 , a sacrificial hardmask layer 114 formed on the second hardmask layer 112 , and a sacrificial hardmask layer 114 formed on the sacrificial hardmask layer 114 . a first anti-reflective coating 116 , and a first photoresist material 118 patterned on the first anti-reflective coating 116 . The components of the stacked layer 100 may be deposited by any known techniques which will not be discussed herein for the sake of clarity and brevity.

The substrate 102 may be a microelectronic chip having circuit devices (not shown) including transistors and the like, a wafer substrate (eg, a portion of a silicon wafer), etc., and may include contact structures (first contact structures ( 120A) and second contact structure 120B) may be in electrical communication with circuit devices. Also, as discussed, the substrate 102 may be an interconnection layer, and the contact structures 120A, 120B may be interconnects.

In one embodiment, the dielectric layer 104 may be a material (eg, a “low k” dielectric material) with a dielectric constant k less than _{that of, for example, silicon dioxide (SiO 2 ).} . Representative low k dielectric materials include materials comprising silicon, carbon and/or oxygen, which are known in the art and may be referred to as polymers. In one embodiment, the dielectric layer 104 may be porous.

In one embodiment, the first hardmask layer 106 , the second hardmask layer 112 and the sacrificial hardmask layer 114 may be dielectric materials. Representative dielectric materials include various oxides, nitrides and carbides, eg, silicon oxide, titanium oxide, hafnium oxide, aluminum oxide, oxynitride, zirconium oxide, hafnium silicate, lanthanum oxide, silicon nitride, boron nitride, amorphous carbon, silicon carbide. , aluminum nitride, and other similar dielectric materials. In one embodiment, the first hardmask layer 106 serves as a mask for the underlying dielectric layer 104 (eg, undesirable modification of the dielectric material from energy used in subsequent process steps). to protect it from) to a predetermined thickness, for example by a plasma deposition process. In one embodiment, a representative thickness is a thickness that does not significantly affect the overall dielectric constant of the combined dielectric layer 104 and the first hardmask layer 106, but at most affects the overall dielectric constant. . In one embodiment, a representative thickness is about 30 Angstroms (Å)±20 Å. In another embodiment, an exemplary thickness is between about 2 and 5 nanometers (nm).

Backbone material 108 may include, but is not limited to, polysilicon, amorphous silicon, amorphous carbon, silicon nitride, silicon carbide, and germanium.

As shown in FIG. 2 , the stacked layer 100 of FIG. 1 may be etched, where the second hardmask layer 112 serves as an etch stop. The etching causes the pattern of the first photoresist material 118 to be transferred into the sacrificial hardmask layer 114 . As shown in FIG. 2 , the first photoresist material 118 and the first anti-reflective coating 116 may be removed, resulting in patterned sacrificial hardmask structures 122 .

As shown in FIG. 3 , a conformal spacer material layer 124 may be deposited over the structure shown in FIG. 2 . The conformal spacer material layer 124 may be deposited by any conformal deposition techniques known in the art, and may be deposited by any suitable material may be included. 4 , the conformal spacer material layer 124 may be anisotropically etched and the sacrificial hardmask structures 122 may be removed to form first spacers 126 .

As shown in FIG. 5 , the structure of FIG. 4 may be etched, where the first hardmask layer 106 serves as an etch stop. The etching causes the pattern of first spacers 126 to be transferred into the backbone material 108 , resulting in patterned backbone structures 128 capped as part of the second hardmask layer 112 . In one embodiment, the second hardmask layer 112 may remain to protect the backbone material 108 during subsequent processing, such as formation of trenches and vias, as discussed. In other embodiments, the second hardmask layer 112 may be removed.

As shown in FIG. 6 , a conformal side spacer material layer 132 may be deposited over the structure shown in FIG. 5 . The conformal side spacer material layer 132 may be deposited by any conformal deposition technique known in the art, including silicon dioxide, silicon nitride, titanium oxide, hafnium oxide, zirconium oxide, aluminum nitride, and amorphous silicon. It may include, but is not limited to, any suitable material.

7 , a third hardmask 134 may be deposited over the conformal side spacer material layer 132 , and a second antireflective coating 136 may be deposited over the third hardmask 134 . and a second photoresist material 138 can be patterned on the second anti-reflective coating 136 . As shown in FIG. 8 , the structure of FIG. 7 is etched away from the third hardmask 134 and a portion of the second antireflective coating 136 that is not protected by the patterned second photoresist material 138 . A portion may be removed (see FIG. 7 ), where the conformal side spacer material layer 132 serves as an etch stop. As shown in FIG. 9 , the structure of FIG. 8 comprises a layer of conformal side spacer material 132 between adjacent patterned backbone structures 128 , through a portion of the first hardmask layer 106 and A third hardmask may be anisotropically etched into the dielectric layer 104 to form at least one first trench 142 in the dielectric layer 104 , wherein portions of the conformal side spacer material layer 132 are patterned. It can be protected from etching by 134 . It is understood that trench 142 may extend vertically from the plane of FIG. 9 . Etching of the conformal side spacer material layer 132 may result in the formation of side spacers 144 along sides 146 of patterned backbone structures 128 .

As shown in FIG. 10 , the third hardmask 134 , the second anti-reflective coating 136 and the second photoresist material 138 may be removed, and a fourth hardmask 152 may be deposited. and a third anti-reflective coating 154 may be deposited over the fourth hardmask 152 , and a third photoresist material 156 may be patterned on the third anti-reflective coating 154 to form each of the first It may have at least one opening 158 therein aligned with the trench 142 . 11 and 12 , a portion of the fourth hardmask 152 may be etched through the opening 158 , and a further portion of the dielectric material 104 may be etched into the first trench 142 . A first via 160 extending from to each of the first contact structures 120A may be formed.

As shown in FIG. 13 , the fourth hardmask 152 , the third anti-reflective coating 154 and the third photoresist material 156 may be removed, and a via hardmask 162 may be deposited. . In one embodiment, the via hardmask 162 is any, such as the material used for the first hardmask layer 106 and the dielectric material 104 , and the material used for the contact structures 120A, 120B. may be selected from materials that may be selectively removable in the presence of the underlying metals of In an embodiment, the via hardmask 162 may be a carbon hardmask, such as an amorphous carbon material, as will be understood by one of ordinary skill in the art. In another embodiment, the via hardmask 162 may be a metal or metal nitrides that are selectively removable with respect to the underlying metals, such as titanium nitride, cobalt, ruthenium, or a combination thereof.

As shown in FIG. 14 , the via hardmask 162 is removed from the first trenches 142 while leaving a portion of the via hardmask 162 in the first via 160 . can be etched back to remove It is understood that a portion of the via hardmask 162 may remain in the first trenches 142 .

15 , a sacrificial material 164 may be deposited over the structure of FIG. 14 , where the sacrificial material 164 is disposed within the first trenches 142 . In one embodiment, the sacrificial material 164 is mechanically and chemically capable of withstanding additional processing steps, the material used for the dielectric layer 104 , and the contact structures 120A, 120B. It may be selected from materials that are selectively removable in the presence of any underlying metals, such as materials. In an embodiment, the sacrificial material 164 may include, but is not limited to, titanium oxide, titanium nitride, ruthenium, and cobalt.

As shown in FIG. 16 , the structure of FIG. 15 is polished, such as by chemical mechanical planarization, to remove a portion of the sacrificial material 164 and the second hardmask layer 112 (if present) and the backbone structures 128 . ) can be exposed.

17 , a fifth hardmask 166 , such as a carbon hardmask, may be deposited over the structure of FIG. 16 , and a fourth antireflective coating 168 may be deposited over the fifth hardmask 166 . and a fourth photoresist material 172 may be patterned on the fourth antireflective coating 168 to have at least one opening 174 therein. As shown in FIG. 18 , a fifth hardmask 166 may be etched to expose a desired portion of the structure shown in FIG. 17 . As shown in FIG. 19 , backbone structures 128 (see FIG. 18 ) may be etched, wherein the etching is the portion of the first hardmask layer 106 exposed by removal of the backbone structures 128 . continues through the dielectric layer 104 , thereby forming at least one second trench 176 in the dielectric layer 104 . In one embodiment, the structure of FIG. 19 includes the backbone structures 128 , the first hardmask layer 106 and the dielectric layer 104 without etching the side spacers 144 and the sacrificial material 164 . It may be exposed to a plasma of reactive gases (eg, fluorocarbon, oxygen, chlorine and/or boron trichloride) capable of etching to a desired depth.

As shown in FIG. 20 , the remaining fifth hardmask 166 and fourth antireflective coating 168 may be removed, and a sixth hardmask 178 , such as a carbon hardmask, is placed over the structure of FIG. 19 . may be deposited to fill the second trenches 176 , a fifth anti-reflective coating 182 may be deposited over the sixth hardmask 178 , and a fifth photoresist on the fifth anti-reflective coating 182 . Material 184 may be patterned to have at least one opening 186 therein aligned with each second trench 176 (see FIG. 19 ). 21 , a portion of the sixth hardmask 178 may be etched through the opening 186 , and a further portion of the dielectric material 104 is etched away from each of the second trenches 176 . A second via 188 extending to the second contact structure 120B may be formed.

As shown in FIG. 22 , the sixth hardmask 178 , the fifth anti-reflective coating 182 and the fifth photoresist material 184 (see FIG. 20 ) are removed, the second trenches 176 and may be replaced with a fill material 192 extending into the second vias 188 (see FIG. 21 ). In one embodiment, the filler material 192 may include a carbon hardmask, such as an amorphous carbon material. As shown in FIG. 23 , the fill material 192 is a side spacer leaving a portion of the eighth hardmask 192 in the second trenches 176 and the second vias 188 (see FIG. 21 ). They may optionally be etched back to expose the shards 144 .

24 , the structure of FIG. 23 may be polished, such as by chemical mechanical polishing, to expose the first hardmask layer 106 . The sacrificial material 164 may then be selectively removed from the first trenches 142 as shown in FIG. 25 . 26 , the eighth hardmask 192 may be selectively removed from the second trenches 176 and the second vias 188 , and the via hardmask 162 may be removed from the first vias. may be removed from 160 . In one embodiment, where eighth hardmask 192 and via hardmask 162 are carbon hardmasks as previously discussed, they may be removed using a single ashing and cleaning process as is known in the art. can

As shown in FIG. 27 , a conductive material 194 is deposited over the structure of FIG. 26 , such that first trenches 142 , first vias 160 , second trenches 176 and second vias are formed. (188) can be charged. Conductive material 194 may be any suitable conductive material, such as metals including, but not limited to, copper, aluminum, tungsten, cobalt, ruthenium, etc. with or without a liner material such as tantalum, tantalum nitride or titanium nitride. can be made with It is understood that the first hardmask layer 106 may be removed prior to deposition of the conductive material 194 .

As shown in FIG. 28 , the structure of FIG. 27 is polished to remove a portion of the conductive material 194 and the first hardmask layer 106 (if present) to expose the dielectric material 104 , thereby Interconnects 196 may be formed. Interconnects 196 may be, for example, wiring lines used to provide connections between and to devices connected to other interconnect layers or lines. The interconnects 196 may be of similar size and dimensions, and may also be parallel to each other. Also, the pitch P (see FIG. 23 ) of the interconnects 196 may be relatively small, whereby they are considered to have a tight pitch, such as an interconnect pitch P of less than about 80 nm, for example.

Referring again to FIG. 23 , prior to polishing to remove the side spacers 144 and other structures over the first hardmask layer 106 as shown in FIG. 24 , the trenches (the first trench in FIG. 26 ) are The aspect ratio (ie, height to width) of the trenches 142 and second trenches 176 ) may be greater than about 8:1 (eg, H1:W), and the vias (eg, the first The aspect ratio of vias 160 and second vias 188) may be greater than about 10:1 (eg, H2:W) for a trench having a pitch P of less than about 40 nm. 24 , after polishing, the aspect ratio of the trenches (ie, height to width) (eg, H1′:W) and the aspect ratio of the vias (eg, H2′:W) are about 4:1 may be smaller than As previously discussed, low aspect ratios may reduce or substantially eliminate the likelihood of voids forming in conductive material 194 as it is deposited (see FIG. 27 ).

29 is a flowchart of a process 200 for manufacturing a microelectronic structure in accordance with an embodiment of the present description. As shown in block 202 , a dielectric layer may be formed on the substrate. As shown at block 204 , a hardmask layer may be formed over the dielectric layer. As shown at block 206 , a plurality of backbone structures may be formed on the hardmask layer. As shown at block 208 , side spacers may be formed adjacent sides of each backbone structure of the plurality of backbone structures. As shown in block 210 , a portion of the first hardmask and a portion of the dielectric layer between adjacent side spacers between at least two adjacent backbone structures are etched to form at least one first trench in the dielectric layer. can be formed As shown at block 212 , a sacrificial material may be deposited in the at least one first trench. As shown at block 214 , at least one backbone structure may be removed, and a portion of the hardmask layer and dielectric layer underlying the backbone structure may be etched to form at least one second trench. As shown at block 216 , a fill material may be deposited in the at least one second trench. As shown in block 218 , the side spacers may be removed. As presented at block 220 , a sacrificial material may be removed from the at least one first trench. As shown in block 222 , fill material may be removed from the at least one second trench. As shown at block 224 , a conductive material may be deposited in the at least one first trench and the at least one second trench.

30 illustrates a computing device 300 according to an implementation of this description. Computing device 300 houses board 302 . The board 302 may include a number of components including, but not limited to, a processor 304 and at least one communication chip 306A, 306B. The processor 304 is physically and electrically coupled to the board 302 . In some implementations, at least one communication chip 306A, 306B is also physically and electrically coupled to the board 302 . In further implementations, the communication chip 306A, 306B is part of the processor 304 .

Depending on its applications, computing device 300 may include other components that may or may not be physically and electrically coupled to board 302 . These other components include volatile memory (eg, DRAM), non-volatile memory (eg, ROM), flash memory, graphics processor, digital signal processor, crypto processor, chipset, antenna, display, touch screen Displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard disk drives, compact disks (CDs) ), a digital versatile disk (DVD), etc.), but is not limited thereto.

Communication chips 306A, 306B enable wireless communication for the transfer of data to/from computing device 300 . The term "wireless" and its derivatives refers to circuits, devices, systems, methods, techniques, and communications capable of communicating data through the use of modulated electromagnetic radiation through a non-solid medium. It can be used to describe channels and the like. This term does not imply that the associated devices do not contain any wires, although in some embodiments the associated devices may not. Communication chip 306, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA may implement any of a number of wireless standards or protocols including, but not limited to, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols designated as 3G, 4G, 5G, and more. . Computing device 300 may include a plurality of communication chips 306A, 306B. For example, the first communication chip 306A may be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and the second communication chip 306B may be GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev- It may be dedicated to long-distance wireless communication, such as DO.

The processor 304 of the computing device 300 includes an integrated circuit die packaged within the processor 304 . In some implementations of this description, an integrated circuit die of a processor may be connected to other devices using one or more interconnection layers formed in accordance with the implementations described above. The term “processor” refers to any device or portion of a device that processes electronic data from registers and/or memory and converts that electronic data into other electronic data that may be stored in registers and/or memory. can do.

Communication chips 306A, 306B also include integrated circuit dies packaged within communication chips 306A, 306B. According to another implementation of the present description, an integrated circuit die of a communication chip may be connected to other devices using one or more interconnection layers formed according to the implementations described above.

In further implementations, another component housed within computing device 300 may include an integrated circuit die that includes an interconnect in accordance with embodiments of the present description.

In various implementations, computing device 300 may include a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, It may be a set-top box, an entertainment control unit, a digital camera, a portable music player or a digital video recorder. In further implementations, computing device 300 may be any other electronic device that processes data.

It is understood that the subject matter of the present description is not necessarily limited to the specific applications illustrated in FIGS. As will be appreciated by one of ordinary skill in the art, this subject matter may be applied to any suitable electronic application, as well as other microelectronic devices and assembly applications.

The following examples relate to further embodiments. Specifications in these examples may be used anywhere in one or more embodiments.

In Example 1, a method of forming a microelectronic structure includes forming a dielectric layer on a substrate; forming a hardmask layer on the dielectric layer; forming a plurality of backbone structures on the hardmask layer; forming side spacers adjacent sides of each backbone structure of the plurality of backbone structures; etching a portion of the first hardmask and a portion of the dielectric layer between adjacent side spacers between at least two adjacent backbone structures to form at least one first trench; depositing a sacrificial material in the at least one first trench; removing the at least one backbone structure and etching a portion of the hardmask layer and dielectric layer underlying the at least one backbone structure to form at least one second trench; depositing a fill material in the at least one second trench; removing the side spacers; removing the sacrificial material from the at least one first trench; removing fill material from the at least one second trench; and depositing a conductive material in the at least one first trench and the at least one second trench.

In Example 2, the subject matter of Example 1 provides that forming a plurality of backbone structures comprises: depositing a backbone material on a first hardmask; patterning spacers adjacent the backbone material; and etching the backbone material to transfer the pattern of spacers into the backbone material.

In Example 3, the subject matter of Example 2 provides that patterning the spacers adjacent the backbone material comprises: patterning sacrificial hardmask structures adjacent the backbone material; depositing a layer of conformal spacer material over the plurality of backbone structures; anisotropically etching the conformal spacer material layer; and removing the sacrificial hardmask structures.

In Example 4, the subject matter of any one of Examples 1-3 is provided, wherein the step of forming side spacers adjacent sides of each backbone structure of the plurality of backbone structures comprises: a conformal side spacer material over the plurality of backbone structures. depositing a layer; and anisotropically etching the conformal side spacer material layer.

In Example 5, the subject matter of any one of Examples 1-4 can optionally include that removing the side spacers comprises polishing the side spacers.

In Example 6, the subject matter of any one of Examples 1-5 provides that depositing a sacrificial material in the at least one second trench comprises depositing a material selected from the group consisting of titanium nitride, ruthenium, and cobalt. It may optionally be included.

In Example 7, the subject matter of any one of Examples 1-6 is provided that depositing a fill material in the at least one second trench comprises depositing a carbon hardmask in the at least one second trench. may optionally be included.

In Example 8, the subject matter of any one of Examples 1-7 can optionally include forming the dielectric layer on the substrate comprises forming a low k dielectric layer.

In Example 9, the subject matter of any one of Examples 1 to 8 provides that the step of forming the plurality of backbone structures on the hardmask layer comprises: polysilicon, amorphous silicon, amorphous carbon, silicon nitride, and germanium from the group consisting of: may optionally include forming a plurality of backbone structures from a selected material.

In Example 10, the subject matter of any one of Examples 1-9 optionally includes, wherein depositing a conductive material in the at least one first trench and the at least one second trench comprises depositing a metal. can do.

In Example 11, a method of forming a microelectronic structure includes: forming a dielectric layer on a substrate, the substrate comprising a first contact structure and a second contact structure; forming a hardmask layer on the dielectric layer; forming a plurality of backbone structures on the hardmask layer; forming side spacers adjacent sides of each backbone structure of the plurality of backbone structures; etching a portion of the first hardmask and a portion of the dielectric layer between adjacent side spacers between at least two adjacent backbone structures to form at least one first trench; forming a first via extending from the at least one first trench to a first contact structure in the substrate; depositing a sacrificial material in the at least one first trench; removing the at least one backbone structure and etching a portion of the hardmask layer and dielectric layer underlying the at least one backbone structure to form at least one second trench; forming a second via extending from the at least one second trench to a second contact structure in the substrate; depositing a fill material in the at least one second trench; removing the side spacers; removing the sacrificial material from the at least one first trench; removing fill material from the at least one second trench; and depositing a conductive material in the at least one first trench, the first via, the at least one second trench, and the second via.

In Example 12, the subject matter of Example 11 provides that forming the plurality of backbone structures comprises: depositing a backbone material on a first hardmask; patterning spacers adjacent the backbone material; and etching the backbone material to transfer the pattern of spacers into the backbone material.

In Example 13, the subject matter of Example 12 provides that patterning the spacers adjacent the backbone material comprises: patterning sacrificial hardmask structures adjacent the backbone material; depositing a layer of conformal spacer material over the plurality of backbone structures; anisotropically etching the conformal spacer material layer; and removing the sacrificial hardmask structures.

In Example 14, the subject matter of any one of Examples 11-13 provides that forming side spacers adjacent sides of each backbone structure of the plurality of backbone structures comprises: a conformal side spacer material over the plurality of backbone structures. depositing a layer; and anisotropically etching the conformal side spacer material layer.

In Example 15, the subject matter of any one of Examples 11-14 can optionally include removing the side spacers comprises polishing the side spacers.

In Example 16, the subject matter of any one of Examples 11-15 provides that depositing a sacrificial material in the at least one second trench comprises depositing a material selected from the group consisting of titanium nitride, ruthenium, and cobalt. It may optionally be included.

In Example 17, the subject matter of any one of Examples 11-16 is that depositing a fill material in the at least one second trench comprises depositing a carbon hardmask in the at least one second trench. may optionally be included.

In Example 18, the subject matter of any one of Examples 11-17 can optionally include forming the dielectric layer on the substrate comprises forming a low k dielectric layer.

In Example 19, the subject matter of any one of Examples 11 to 18 provides that the step of forming the plurality of backbone structures on the hardmask layer comprises: polysilicon, amorphous silicon, amorphous carbon, silicon nitride, and germanium from the group consisting of: may optionally include forming a plurality of backbone structures from a selected material.

In Example 20, the subject matter of any one of Examples 11-19 optionally includes, wherein depositing a conductive material in the at least one first trench and the at least one second trench comprises depositing a metal. can do.

In Example 21, a method of forming a microelectronic structure includes: forming a dielectric layer on a substrate, the substrate comprising a first contact structure and a second contact structure; forming a hardmask layer on the dielectric layer; forming a plurality of backbone structures on the hardmask layer; forming side spacers adjacent sides of each backbone structure of the plurality of backbone structures; etching a portion of the first hardmask and a portion of the dielectric layer between adjacent side spacers between at least two adjacent backbone structures to form at least one first trench; forming a first via extending from the at least one first trench to a first contact structure in the substrate; depositing a via hardmask material into the first via; depositing a sacrificial material in the at least one first trench; removing the at least one backbone structure and etching a portion of the hardmask layer and dielectric layer underlying the at least one backbone structure to form at least one second trench; forming a second via extending from the at least one second trench to a second contact structure in the substrate; depositing a fill material in the at least one second trench; removing the side spacers; removing the sacrificial material from the at least one first trench; removing the via hardmask material from the first via; removing fill material from the at least one second trench; and depositing a conductive material in the at least one first trench, the first via, the at least one second trench, and the second via.

In Example 22, the subject matter of Example 21 provides that removing the via hardmask material from the first via and removing the fill material from the at least one second trench comprises removing the via hardmask material from the first via. and simultaneously removing the fill material from the at least one second trench.

While embodiments of the present description have thus been described in detail, many obvious modifications thereof are possible without departing from the spirit or scope thereof, so that the present description, as defined by the appended claims, is limited by the specific details set forth in this description. It is understood that it will not

Claims (22)

A method of forming a microelectronic structure comprising:
forming a dielectric layer on the substrate;
forming a hardmask layer on the dielectric layer;
forming a plurality of backbone structures on the hardmask layer;
forming side spacers adjacent to sides of each backbone structure of the plurality of backbone structures;
etching a portion of the hardmask layer and a portion of the dielectric layer between adjacent side spacers between at least two adjacent backbone structures to form at least one first trench;
depositing a sacrificial material within the at least one first trench;
removing at least one backbone structure and etching a portion of the hardmask layer and the dielectric layer underlying the at least one backbone structure to form at least one second trench;
depositing a fill material in the at least one second trench;
removing the side spacers;
removing the sacrificial material from the at least one first trench;
removing the fill material from the at least one second trench; and
depositing a conductive material within the at least one first trench and the at least one second trench;
How to include. According to claim 1,
Forming the plurality of backbone structures comprises:
depositing a backbone material on the hardmask layer;
forming patterned spacers adjacent the backbone material; and
etching the backbone material to transfer the patterned pattern of spacers into the backbone material;
How to include. 3. The method of claim 2,
Adjacent to the backbone material, forming patterned spacers comprises:
forming patterned sacrificial hardmask structures adjacent the backbone material;
depositing a conformal spacer material layer over the patterned sacrificial hardmask structures;
anisotropically etching the conformal spacer material layer; and
removing the sacrificial hardmask structures;
How to include. According to claim 1,
forming side spacers adjacent to sides of each backbone structure in the plurality of backbone structures,
depositing a conformal side spacer material layer over the plurality of backbone structures; and
anisotropically etching the conformal side spacer material layer;
How to include. According to claim 1,
The method of removing the side spacers includes polishing the side spacers. According to claim 1,
Depositing a sacrificial material in the at least one first trench includes depositing a material selected from the group consisting of titanium nitride, titanium oxide, ruthenium, and cobalt. According to claim 1,
Depositing a fill material in the at least one second trench includes depositing a carbon hardmask in the at least one second trench. According to claim 1,
The method of forming a dielectric layer on the substrate includes forming a low k dielectric layer. According to claim 1,
The forming of the plurality of backbone structures on the hardmask layer may include forming the plurality of backbone structures with a material selected from the group consisting of polysilicon, amorphous silicon, amorphous carbon, silicon carbide, silicon nitride, and germanium. How to include. According to claim 1,
Depositing a conductive material in the at least one first trench and the at least one second trench includes depositing a metal. A method of forming a microelectronic structure comprising:
forming a dielectric layer on a substrate, the substrate comprising a first contact structure and a second contact structure;
forming a hardmask layer on the dielectric layer;
forming a plurality of backbone structures on the hardmask layer;
forming side spacers adjacent to sides of each backbone structure of the plurality of backbone structures;
etching a portion of the hardmask layer and a portion of the dielectric layer between adjacent side spacers between at least two adjacent backbone structures to form at least one first trench;
forming a first via extending from the at least one first trench to a first contact structure of the substrate;
depositing a sacrificial material within the at least one first trench;
removing at least one backbone structure and etching a portion of the hardmask layer and the dielectric layer underlying the at least one backbone structure to form at least one second trench;
forming a second via extending from the at least one second trench to a second contact structure of the substrate;
depositing a fill material in the at least one second trench;
removing the side spacers;
removing the sacrificial material from the at least one first trench;
removing the fill material from the at least one second trench; and
depositing a conductive material in the at least one first trench, the first via, the at least one second trench, and the second via;
How to include. 12. The method of claim 11,
Forming the plurality of backbone structures comprises:
depositing a backbone material on the hardmask layer;
forming patterned spacers adjacent the backbone material; and
etching the backbone material to transfer the patterned pattern of spacers into the backbone material;
How to include. 13. The method of claim 12,
Adjacent to the backbone material, forming patterned spacers comprises:
forming patterned sacrificial hardmask structures adjacent the backbone material;
depositing a conformal spacer material layer over the patterned sacrificial hardmask structures;
anisotropically etching the conformal spacer material layer; and
removing the sacrificial hardmask structures;
How to include. 12. The method of claim 11,
forming side spacers adjacent to sides of each backbone structure in the plurality of backbone structures,
depositing a layer of conformal side spacer material over the plurality of backbone structures; and
anisotropically etching the conformal side spacer material layer;
How to include. 12. The method of claim 11,
The method of removing the side spacers includes polishing the side spacers. 12. The method of claim 11,
Depositing a sacrificial material in the at least one first trench includes depositing a material selected from the group consisting of titanium nitride, titanium oxide, ruthenium, and cobalt. 12. The method of claim 11,
Depositing a fill material in the at least one second trench includes depositing a carbon hardmask in the at least one second trench. 12. The method of claim 11,
The method of forming a dielectric layer on the substrate includes forming a low k dielectric layer. 12. The method of claim 11,
The forming of the plurality of backbone structures on the hardmask layer may include forming the plurality of backbone structures with a material selected from the group consisting of polysilicon, amorphous silicon, amorphous carbon, silicon carbide, silicon nitride, and germanium. How to include. 12. The method of claim 11,
Depositing a conductive material in the at least one first trench and the at least one second trench includes depositing a metal. A method of forming a microelectronic structure comprising:
forming a dielectric layer on a substrate, the substrate comprising a first contact structure and a second contact structure;
forming a hardmask layer on the dielectric layer;
forming a plurality of backbone structures on the hardmask layer;
forming side spacers adjacent to sides of each backbone structure of the plurality of backbone structures;
etching a portion of the hardmask layer and a portion of the dielectric layer between adjacent side spacers between at least two adjacent backbone structures to form at least one first trench;
forming a first via extending from the at least one first trench to a first contact structure of the substrate;
depositing a via hardmask material into the first via;
depositing a sacrificial material within the at least one first trench;
removing at least one backbone structure and etching a portion of the hardmask layer and the dielectric layer underlying the at least one backbone structure to form at least one second trench;
forming a second via extending from the at least one second trench to a second contact structure of the substrate;
depositing a fill material in the at least one second trench;
removing the side spacers;
removing the sacrificial material from the at least one first trench;
removing the via hardmask material from the first via;
removing the fill material from the at least one second trench; and
depositing a conductive material in the at least one first trench, the first via, the at least one second trench, and the second via;
How to include. 22. The method of claim 21,
The steps of removing the via hardmask material from the first via and removing the fill material from the at least one second trench may include removing the via hardmask material from the first via while simultaneously removing the at least one via hardmask material. and removing the fill material from the second trench.

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