KR102310555B1 - Bit line sense amp - Google Patents

Abstract

The present invention relates to a bit line sense amplifier implemented in a way that a voltage boost function can be used through a boot-strap capacitor in the bit line sense amplifier, and to a bit line sense amplifier which includes: a first PMOS transistor; a second PMOS transistor; a first NMOS transistor; a second NMOS transistor; a bit bar line capacitor; a bit line capacitor; a cell capacitor; a cell transistor. The bit line sense amplifier further includes a bit bar line boot-strap unit and a bit line boot-strap unit formed between a first inverter unit including the first PMOS transistor and the first NMOS transistor and a second inverter unit including the second PMOS transistor and the second NMOS transistor. The bit bar line boot-strap unit and the bit line boot-strap unit each have a capacitor for a boot-strap and allow the capacitor for a boot-strap to be used as gate inputs of the first NMOS transistor and the second NMOS transistor, respectively. In accordance with the present invention, by means of the bit line sense amplifier, refresh characteristics of DRAM can be remarkably enhanced.

Description

Bit line sense amp

The technical field of the present invention relates to a bit line sense amplifier, and more particularly, to a bit line sense amplifier implemented to use a boost function through a boot-strap capacitor in the bit line sense amplifier. will be.

Korean Patent No. 10-0535124 (registered on Dec. 1, 2005) discloses a bit line sense amplifier for suppressing an increase in offset voltage and a method of forming the bit line sense amplifier, and Korean Patent No. 10-0911187 (Registered on July 31, 2009) discloses a latch structure capable of reducing variations in output current and preventing sensing errors and a bit line sense amplifier structure including the same.

As shown in FIG. 1 , the bit line sense amplifier 100 is a bit bar line of a first PMOS transistor 101 , a second PMOS transistor 102 , a first NMOS transistor 103 , a second NMOS transistor 104 , and 40fF. a capacitor (bit bar line capacitor) (Cb) 105, a bit line capacitor (Cb) 106 of 40 fF, a cell capacitor (Cs) 107 of 8 fF, and a cell transistor 108. have.

The first PMOS transistor 101 and the first NMOS transistor 103 serve as one inverter, and the second PMOS transistor 102 and the second NMOS transistor 104 also serve as another inverter, and each The input value is the opposite bit line (B) (or bit bar line (/B)), and the output value is the bit bar line (/B) (or bit line (B)) as well as the input value of the opposite inverter. It is a feedback structure. The inverter is a logic device that outputs logic opposite to the input logic, and is a logic circuit whose output value is “0” when “1” is input, and has a logic threshold value.

The logic threshold voltage of such an inverter is obtained as follows.

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를 구하면 된다. 이를 풀어서 정리를 하면,

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가 되어, 전원 전압(Vcore)의 센터 값에 로직 쓰레스홀드 값이 맞추어지게 된다. 정공(hole)의 모빌리티(mobility)가 전자(electron)의 모빌리티보다 거의 정확히 1/2이므로, NMOS와 PMOS의 랭스(length)가 동일할 때, PMOS 트랜지스터의 위스(width)를 NMOS 트랜지스터의 위스보다 2배 크게 사이징(sizing)하면

이 된다.When NMOS and PMOS are in saturation mode at the same time, the logic threshold voltage is determined under the condition that the two current values are the same,

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, and the logic threshold value is adjusted to the center value of the power supply voltage Vcore. Since the mobility of holes is almost exactly 1/2 that of electrons, when the lengths of NMOS and PMOS are the same, the width of the PMOS transistor is larger than that of the NMOS transistor. When sizing twice as large

becomes this

The first PMOS transistor 101 and the second PMOS transistor 102 have exactly the same characteristics (threshold voltage Vt, current, etc.), and the first NMOS transistor 103 and the second NMOS transistor 104 also have the same characteristics. Sensing offset characteristics (minimum sensing margin ΔV that can be normally sensed) are excellent only when they have exactly the same characteristics, but in reality, two PMOS transistors 101 and 102 or two NMOS transistors 103 and 104 There is a difference in characteristics between them. Here, the characteristic difference is the threshold voltage (Vt) and sub threshold leakage (sub threshold leakage), on current (on current), bit to bit bar line capacitance (bit vs bit bar line capacitance) mismatches, and the like.

The operation of the bit line sense amplifier 100 having the above-described configuration is as follows. Here, the sense amplifier power supply voltage (Vcore) is 1.1V, the bit line precharge voltage (Vblp) is set to 0.5V, and the two voltages are the Vcore generator and Vblp, which are the internal power generators of the chip, respectively. created by the generator.

First, first, the bit line (B) and the bit bar line (/B) stop being pre-charged with the same bit line precharge voltage (Vblp) (0.5V) and float ( make it floating). Here, the floating state means that the connection with the internal power generator is disconnected and there is no other current path.

Second, as the cell transistor 108 is opened and the “1” data or “0” data charged in the cell capacitor 107 is transferred to the bit line B, charge sharing occurs, so that the bit line The potential value remains at the bit line pre-charge voltage (Vblp) (0.5V) and then changes to “Vblp?ΔV”.

ΔV refers to the voltage value after the potential written to the cell capacitor 107 as a sensing margin is charge-shared with the bit line B, and is (Vs-Vblp)/1+r, " For 1" data, (1.1V-0.5V)/(1+5) = 100mV, and for "0" data, (0V-0.5V)/(1+5) = 83mV. At this time, Vs is the storage node write voltage. For “1” data, Vcore, which is the power supply voltage of the bit line sense amplifier, is 1.1V, for “0” data, it is 0V, which is the GND level, and r is the bit The ratio (40/8) of line capacitance (Cb) to cell capacitance (Cs) is 5.

Third, the restore voltage Vrestore and the sink voltage Vsink are equally at the bit line precharge voltage Vblp level, and the restore voltage Vrestore value is the bit line sense amplifier power supply voltage Vcore. As it rises to (1.1V) and the sink voltage Vsink transitions to 0V, which is a ground level (GND), a sensing operation occurs. At this time, where the logic threshold value of the sense amplifier inverter is set between 0V and Vcore affects the sensing operation.

The cell transistor on-gate voltage (Von) must be capable of turning on the cell transistor 108 having a high threshold voltage value (cell Vt), and can also sufficiently deliver the Vs voltages of 0V and 1.1V to the source and drain. It must have a high voltage. And the highest gate voltage required is "1" when writing data, since the source node must be the Vcore voltage, in this case the gate voltage must be Vcore + Vt_cell, and also the voltage difference between the source and the substrate at this time (Vsb = Vcore + Vbb ) and the rise of the threshold voltage due to the body effect must be considered. The first NMOS threshold voltage Vtn1 and the second NMOS threshold voltage Vtn2 are equal to 0.25 V, and the first PMOS threshold voltage Vtp1 and the second PMOS threshold voltage Vtp2 are 0.4 V They are identical to each other, and the NMOS-driven sensing is usually set to NMOS fast. At this time, in the case of a PMOS transistor, as a buried channel is formed, the threshold voltage (Vt) mismatch (mismatch) ) component usually has a larger value than that of NMOS. Making NMOS take the lead in the initial sensing operation is realized by activating Vsink before Vrestore and activating Vrestore after a delay for a certain period of time.

Fourth, as shown in FIG. 1, for example, a case of "1" data sensing in the cell capacitor 107 connected to the bit line B will be described.

When the cell transistor 108 is opened, “Vblp+100” mV (ie, 600 mV) is induced in the bit line B by charge sharing between the cell capacitor 107 and the bit line capacitor 106 , and , the bit line pre-charge voltage (Vblp) value of 0.5 V is applied to the opposite bit bar line (/B) as it is, and at this time, the induced potential value of the bit line (B) of 600 mV is applied to the first PMOS transistor 101 and the first NMOS transistor ( 103), the gate voltage values of the second PMOS transistor 102 and the second NMOS transistor 104 maintain the bit line pre-charge voltage (Vblp) value of 0.5V, and the NMOS gate voltage is The relatively high drain to source current (IDS) value of the first NMOS transistor 103 becomes greater than the IDS value of the second NMOS transistor 104 , which has the opposite role in the case of the PMOS transistors 101 and 102 (the gate voltage is high As the current decreases), the potential of the bit bar line (/B) gradually decreases and the potential of the bit line (B) gradually rises, so that the bit bar line (/B) eventually becomes 0V. Therefore, the potential difference between the bit line B and the bit line sense amplifier power supply voltage Vcore is widened. At this time, when Vresotre and Vsink are simultaneously activated without a time difference, when the logic threshold voltage (Vth) of the inverter is formed between Vblp+Δ and Vblp, the bit bar line (/B) and the bit line (B) are immediately connected to each other. The voltage difference is widened in the opposite direction, and when the Vsink voltage is activated before the Vrestore voltage (NMOS first), the voltages of both the bit bar line (/B) and the bit line (B) decrease together. However, since the voltage reduction slopes are different, if the bit bar line (/B) and bit line (B) voltages are placed before and after the logic threshold voltage when V restore is activated, the voltage difference is immediately spread in opposite directions and finally It is made with 0V and Vcore voltage, respectively.

Fifth, by setting the level of the bit line precharge voltage Vblp to a level slightly lower than the half level of the normal bit line sense amplifier power supply voltage Vcore, the “1” data is refreshed. ) characteristics, but in actual operation, as the precharge operation starts, BLEQ (bit line equalize) (bit line (B) and bit bar line (/B) After sensing as 0V, it is eventually set to "Vcore/2" by the process of shorting each other).

Charge sharing is Cs(Vs-Vblp)/(Cs+Cb) = (Vs-Vblp)/(1+r) and the sensing margin of “0” data becomes small. In the case of DRAM, since the refresh characteristic is determined by the “1” data, it is common to make the sensing margin on the “1” data side a little larger. Make it slightly lower than the half level of the supply voltage (Vcore). Here, Cs is a cell capacitance and Cb is a bit line capacitance.

Sixth, during the sensing operation, the sink voltage Vsink, which serves as an NMOS sink, is first dropped from the bit line pre-charge voltage Vblp to 0V, so that the NMOS transistors 103 and 104 lead to the bit line B and After making the bit bar line (/B) fall together (the potential difference between the bit line (B) and the bit bar line (/B) gradually increases while falling), the restore voltage (Vrestore) is set to the bit line precharge voltage (Vblp). ) to the bit line sense amplifier power supply voltage (Vcore), amplifying the voltage in different directions between the bit bar line (/B) and the bit line (B) to widen the voltage difference, thereby completing the sensing operation. .

The equation for calculating the above-described sensing margin ΔV is as follows.

When charges are shared between the cell capacitor 107 and the bit line capacitor 106 by charge sharing, V = Q/C, and the amount of charge component Q contributing to charge sharing becomes Cs (Vs-Vblp), Cell transistor 108 is opened and bitline capacitor 106 is added, resulting in a final combined capacitance value of Cs+Cb. Therefore, the sensing margin (ΔV) value becomes Csㅧ(Vs-Vblp)/(Cs+Cb), and when Cs is divided by the numerator denominator, (Vs-Vblp)/(1+Cb/Cs) becomes r = Cb The definition of /Cs results in a value of (Vs-Vblp)/(1+r). At this time, in the case of the storage node write voltage (Vs), the bit line sense amplifier power supply voltage (Vcore) value is at “1” data and 0V when “0” data is obtained. In addition, the sensing margin ΔV of the minimum value that can be normally sensed as “1” data (or “0” data) is called a sensing offset value for “1” data (or “0” data).

In the case of DRAM, there is a refresh characteristic, which corresponds to “1” data, and the storage node write voltage (Vs), which was at the level of the bit line sense amplifier supply voltage (Vcore) at the time of first writing, is leak (Junction LKG, Sub Threshold Leakage). etc.), and the like) is a case in which the sensing of "1" data fails as the potential value gradually decreases. Therefore, in order to improve the refresh characteristic of "1" data, the bit line precharge voltage Vblp is set to a value slightly lower than the half level of the bit line sense amplifier power supply voltage Vcore, which is the sensing margin (ΔV) value. Since the numerator of becomes (Vs-Vblp), the overall numerator value becomes large because the bitline pre-charge voltage (Vblp) at Vs-Vblp (i.e., Vcore (which drops in value by LKG) is a slightly lower value. Eventually, " The sensing margin (ΔV) value of the “1” data and the “0” data are not equal, and the sensing margin (ΔV) value of the “1” data is increased at the expense of the sensing margin (ΔV) of the “0” data. This is the normal operation of the DRAM bit line sense amplifier, but in reality, when the bit line sense amplifier power supply voltage (Vcore) is 1.1 V, the bit line precharge voltage (Vblp) set value is set to the bit line sense amplifier power supply voltage. Even if the target is set with the bit line pre-charge voltage (Vblp) generator to 0.5V lower than the half level (0.55V) of (Vcore), BLEQ, that is, the bit line (B) during DRAM operation ) and bit bar line (/B) are sensed to the bit line sense amplifier power supply voltage (Vcore) and 0V, respectively, and are eventually set to “Vblp/2” by the process of short-circuiting each other. This expected effect is not true. Here, the adjustment of the Vblp voltage has a trade-off relationship between the sensing margins of “1” data and “0” data, whereas by making Cs large, the Cb/Cs ratio is reduced. In the case of reduction, both “1” data and “0” data increase the sensing margin, but as DRAM process technology is scaled down more and more, the Cs value increases and the Cb/Cs value increases. In order to reduce the Cb value (reducing the Cb/Cs ratio, thereby increasing the sensing margin), the cell block It reduces the bit line length of (cell block), which results in a decrease in cell epitaxial time. This reduction in cell efficiency has the detrimental effect of reducing the number of net dies.

In the prior art as described above, as the technology shrink gradually becomes finer to the middle of 10 nm, the area on the plane for securing the cell capacitance is reduced, and eventually the height of the three-dimensional structure of the cell capacitor is increased. Attempts have been made to secure capacitance, but the problem of increasing the height of the cell capacitor has a problem of extremely increasing the difficulty of a subsequent process, such as a topology problem or contact formation, and the demand for process integrity increases as much. Therefore, when the process is not accurately controlled, the resulting process incompleteness acts as a factor causing various product defects, such as a bridge between a storage node and a wordline node or between a storage node and a bitline node. In addition, a process with high difficulty not only manifests as an immediate defect when the process is not completely controlled, but also has a latent defect pattern, which eventually leads to quality and reliability problems. As such, it becomes increasingly difficult to secure sufficient Cs values, and in the process of securing Cs values, various types of potential defects inevitably exist. According to this trend, an increase in the Cb/Cs ratio has a fatal problem in that the sensing margin (ΔV) is gradually reduced.

Korean Patent No. 10-0535124 Korean Patent Registration No. 10-0911187

The problem to be solved by the present invention is to solve the problems described above, and to provide a bit line sense amplifier implemented to use a boost function through a boot-strap capacitor in a bit line sense amplifier. will be.

As a means for solving the above problems, according to one aspect of the present invention, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a bit bar line capacitor, a bit line capacitor, a cell capacitor, and a cell transistor are included. 1 . A bit line sense amplifier comprising: a first inverter unit formed of the first PMOS transistor and the first NMOS transistor; and a second inverter unit formed of the second PMOS transistor and the second NMOS transistor; Provided is a bit line sense amplifier further comprising a bit bar line bootstrap unit and a bit line bootstrap unit, each having a bootstrap capacitor to be used as a gate input of the first NMOS transistor and the second NMOS transistor, respectively. .

In an embodiment, the bit bar line bootstrap unit and the bit line bootstrap unit do not directly connect the input of the first inverter unit and the bit line, and do not directly connect the input of the second inverter unit and the bit bar line. characterized by forming.

In an embodiment, the bit bar line bootstrap unit and the bit line bootstrap unit further amplify a voltage difference corresponding to a sensing margin created as a result of charge sharing by using the bootstrap capacitor. .

In an embodiment, the bit bar line bootstrap unit and the bit line bootstrap unit apply a sensing margin created as a result of charge sharing to the sense amplifier input as an amplified voltage using the bootstrap capacitor. do.

In an embodiment, the bootstrap capacitor connects and forms the first switch on the upper side and the second switch, the third switch, and the fourth switch in parallel on the lower side, and applies the upper voltage to the first switch. In the case of forming a connection with the first voltage through a connection and forming a connection with a lower voltage with a second voltage through a second switch, connection with a third voltage through a third switch, and forming a connection with a ground through a fourth switch, When the first and second switches are turned on and the third and fourth switches are turned off, the first voltage is applied to the upper voltage and the second voltage is applied to the lower voltage, and then the first switch, the second switch and the second switch are turned off. When switch 4 is turned off and only the third switch is turned on, the upper voltage is applied to the voltage obtained by subtracting the second voltage from the first voltage, and the lower voltage is changed from the second voltage to the third voltage, When the first switch, the second switch and the third switch are turned off and only the fourth switch is turned on, the upper voltage is applied to the voltage obtained by subtracting the second voltage from the first voltage, and the lower voltage is 0V from the second voltage It is characterized in that it allows to be changed to .

In an embodiment, the bit bar line bootstrap unit and the bit line bootstrap unit further include a plurality of switches for generating a bootstrap voltage, so that each bit bar line is connected to an inverter output according to a switching sequence using the switches. It is characterized in that the input voltage of the first inverter and the input voltage of the second inverter that the bit line is connected to the inverter output are extracted.

In an embodiment, the bit bar line bootstrap unit and the bit line bootstrap unit adjust p-well biases of the first NMOS transistor and the second NMOS transistor to corresponding bit bar line voltages and bit line voltages, respectively. It is characterized in that a well pick-up method is used to help the sensing operation by applying ?

In an embodiment, the bit bar line bootstrap unit connects and forms a first bit line switch between the upper side of the bootstrap capacitor and the bit line, and at the same time forms a first bit line switch between the lower side of the bootstrap capacitor and the bit bar line. A bit bar line switch is connected and formed, and a second bit line switch is connected between a lower side of the bootstrap capacitor and a bit line.

In an embodiment, the bit line bootstrap unit connects and forms a first bit bar line switch between the upper side of the bootstrap capacitor and the bit bar line, and at the same time forms a first bit bar line switch between the lower side of the bootstrap capacitor and the bit line. A bit line switch is connected and formed, and a second bit bar line switch is connected between the lower side of the bootstrap capacitor and the bit bar line.

In an embodiment, the bit bar line bootstrap unit and the bit line bootstrap unit change the order of mutually switching the bit bar line voltage and the bit line voltage at both terminals of the bootstrap capacitor, respectively, so that the first NMOS A voltage difference applied between the gate of the transistor and both ends of the gate of the second NMOS transistor is applied as a voltage difference that is three times greater than the initially formed sensing margin.

In an embodiment, the bit bar line bootstrap unit and the bit line bootstrap unit utilize respective upper voltages as the gate voltage of the first NMOS transistor and the gate voltage of the second NMOS transistor, respectively.

In an embodiment, the bit bar line bootstrap unit and the bit line bootstrap unit may include gates of the first and second NMOS transistors and an upper side of the bootstrap capacitor between the first NMOS transistor and the second NMOS transistor itself. It is characterized in that it is connected to a MOS capacitor formed at the gate terminal.

In an embodiment, the bit bar line bootstrap unit and the bit line bootstrap unit connect the gate and the bit line of the first inverter unit again through two switching transistors during a sense amplifier operation to generate a bootstrap voltage. The gate and the bit bar line of the second inverter are connected through two switching transistors, and the input and output values of the first and second inverters are driven to the existing switching transistor to make 0V and a power supply voltage, respectively. It is characterized in that it further comprises a signal.

In an embodiment, the bit bar line bootstrap unit forms a first switching transistor between an upper side of the bootstrap capacitor and a gate of the first NMOS transistor, and a first switching transistor between the upper side of the bootstrap capacitor and the bit line. A second switching transistor is formed, a third switching transistor is formed between the lower side of the bootstrap capacitor and the bit bar line, and a fourth switching transistor is formed between the lower side of the bootstrap capacitor and the bit line. do.

In an embodiment, the bit line bootstrap unit forms a first switching transistor between an upper side of the bootstrap capacitor and a gate of the second NMOS transistor, and a first switching transistor between the upper side of the bootstrap capacitor and the bit bar line. A second switching transistor is formed, a third switching transistor is formed between the lower side of the bootstrap capacitor and the bit line, and a fourth switching transistor is formed between the lower side of the bootstrap capacitor and the bit bar line. do.

In an embodiment, the switching transistor is an NMOS transistor.

As an effect of the present invention, by providing a bit line sense amplifier implemented to use a boost function through a boot-strap capacitor in the bit line sense amplifier, the cell capacitance value is not sufficiently secured, so that the Cb/Cs ratio is This means that the sensing failure that may occur due to the increase and the refresh characteristics of the DRAM can be significantly improved.

In the present invention, the increase of the Cb/Cs ratio may increase the Cb/Cs ratio because the Cs value of the denominator term is small or the Cb value of the numerator term is large, and the Cb value is a word line within one cell block. As the number of word lines, that is, the length of the bit line increases, it is directly affected and the Cb value increases accordingly. Therefore, even if the Cb/Cs ratio increases, if the advantage that enables normal sensing is used, the length of the bit line is extended. Therefore, since sensing is possible even when the Cb value increases, cell efficiency can be improved by about 3 times compared to the conventional one.

1 is a diagram for explaining a conventional bit line sense amplifier.
2 is a view for explaining a bit line sense amplifier according to an embodiment of the present invention.
3 and 4 are diagrams for explaining bootstrap capacitors respectively provided in the bit bar line bootstrap unit and the bit line bootstrap unit shown in FIG. 2 .
5 and 6 are diagrams for explaining switches respectively provided in the bit bar line bootstrap unit and the bit line bootstrap unit shown in FIG. 2 .
FIG. 7 is a view for explaining a bit bar line bootstrap unit and a bit line bootstrap unit shown in FIG. 2 .
FIG. 8 is a view for explaining timing of driving the switching transistor shown in FIG. 7 .
FIG. 9 is a view for explaining the inverter unit shown in FIG. 2 .

Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described in detail so that those of ordinary skill in the art to which the present invention pertains can easily implement them. However, since the description of the present invention is merely an embodiment for structural or functional description, the scope of the present invention should not be construed as being limited by the embodiment described in the text. That is, since the embodiment may have various changes and may have various forms, it should be understood that the scope of the present invention includes equivalents capable of realizing the technical idea. In addition, since the object or effect presented in the present invention does not mean that a specific embodiment should include all of them or only such effects, it should not be understood that the scope of the present invention is limited thereby.

The meaning of the terms described in the present invention should be understood as follows.

Terms such as “first” and “second” are for distinguishing one component from another, and the scope of rights should not be limited by these terms. For example, a first component may be termed a second component, and similarly, a second component may also be termed a first component. When a component is referred to as being “connected” to another component, it may be directly connected to the other component, but it should be understood that other components may exist in between. On the other hand, when it is mentioned that a certain element is "directly connected" to another element, it should be understood that the other element does not exist in the middle. Meanwhile, other expressions describing the relationship between elements, that is, “between” and “immediately between” or “neighboring to” and “directly adjacent to”, etc., should be interpreted similarly.

The singular expression is to be understood as including the plural expression unless the context clearly dictates otherwise, and terms such as "comprises" or "have" refer to the described feature, number, step, action, component, part or these It is intended to indicate that a combination exists, and it should be understood that it does not preclude the possibility of the existence or addition of one or more other features or numbers, steps, operations, components, parts, or combinations thereof.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. Terms defined in the dictionary should be interpreted as being consistent with the meaning of the context of the related art, and cannot be interpreted as having an ideal or excessively formal meaning unless explicitly defined in the present invention.

A bit line sense amplifier according to an embodiment of the present invention will now be described in detail with reference to the drawings.

FIG. 2 is a view for explaining a bit line sense amplifier according to an embodiment of the present invention, and FIGS. 3 and 4 are the bootstrap capacitors respectively provided with the bit bar line bootstrap unit and the bit line bootstrap unit shown in FIG. FIG. 5 and FIG. 6 are diagrams for explaining a switch provided in each of the bit bar line bootstrap unit and the bit line bootstrap unit shown in FIG. 2 .

2 to 6 , the bit line sense amplifier 200 includes a first PMOS transistor 101 , a second PMOS transistor 102 , a first NMOS transistor 103 , a second NMOS transistor 104 , and a bit bar line capacitor. (Cb) 105, bit line capacitor (Cb) 106, cell capacitor (Cs) 107, cell transistor 108, bit bar line bootstrap part (boot-strap) 230, bit line boot and a strap portion 240 . Here, the first PMOS transistor 101 , the second PMOS transistor 102 , the first NMOS transistor 103 , the second NMOS transistor 104 , the bit bar line capacitor 105 , the bit line capacitor 106 , and the cell capacitor 107 ) , cell transistor 108 has the same configuration as that of FIG. 1 , so for convenience, descriptions of the same contents are omitted and only different parts will be described.

The bit bar line bootstrap unit 230 or (or, and) the bit line bootstrap unit 240 includes a first inverter unit 210 including a first PMOS transistor 101 and a first NMOS transistor 103 , and a first formed between the second inverter unit 220 including the 2PMOS transistor 102 and the second NMOS transistor 104; The bit bar line bootstrap unit 230 includes a bootstrap capacitor (Cboot) shown in FIG. 3, and the bit line bootstrap unit 240 is a bootstrap capacitor shown in FIG. Cboot), so that the respective bootstrap capacitors Cboot are used as gate inputs of the first NMOS transistor 103 and the second NMOS transistor 104, respectively.

In one embodiment, the bit bar line bootstrap unit 230 or (or, and) the bit line bootstrap unit 240 does not directly connect the input of the first inverter unit 210 to the bit line B. In addition, the input of the second inverter unit 220 and the bit bar line (/B) may be formed so as not to be directly connected.

In an embodiment, the bit bar line bootstrap unit 230 or (or, and) bit line bootstrap unit 240 bootstraps the micro voltage difference created as a result of charge sharing by the bootstrap capacitor Cboot. Using the principle, it is possible to amplify the voltage of the micro voltage difference between both ends once more.

In an embodiment, the bit line bootstrap unit 230 or (or, and) the bit line bootstrap unit 240 sets the primary sensing margin ΔV created as a result of charge sharing, the bootstrap capacitor ( By using the bootstrap operation of Cboot) to apply the secondary amplified voltage to the input of the sense amplifier, normal sensing can be performed even with a sensing margin reduced to less than half even in a sense amplifier showing the same sensing offset characteristic. .

The bit line sense amplifier 200 having the configuration as described above uses the boost function through the bootstrap capacitor Cboot in the bit line sense amplifier 200, so that the cell capacitance value is not sufficiently secured, so Cb It is possible to significantly improve sensing failure and DRAM refresh characteristics that may occur due to an increase in the /Cs ratio.

The bootstrap capacitor (Cboot), as shown in FIG. 3 , its bootstrap operation is as follows.

First, after charging is completed with external power supply voltages V1 and V2 at both ends of the bootstrap capacitor Cboot (hereinafter referred to as V- node (lower node) and V+ node (upper node)), respectively, the V- node and When a voltage fluctuation (ΔV) is generated in one of the V+ nodes, the same amount of voltage fluctuation (ΔV) appears in the other node as well. At this time, the variable voltage component is constant, that is, V2 = V2 + ΔV. In the case where the bootstrapped voltage node is a floating node without any current path with the outside, this changed voltage state is maintained as it is.

The time to maintain this voltage state depends only on leakage current parasitic at the node, and in the case of an ideal floating node having no leakage current, the changed voltage state is maintained. This means that the voltage difference across the bootstrap capacitor (Cboot) is proportional only to the relative difference component of the amount of charge accumulated in each node (the difference in the accumulated charge forms the charge amount ΔQ = C(V2-V1)). , because the charge amount is determined by the charge amount during charging, and the charge charge amount (ΔQ) is kept constant thereafter.

) 또한, 이러한 전기장의 방향이 +Q와 -Q와 같은 극성 차이로 표현된다. 그리고 이것은 부트스트랩용 커패시터(Cboot) 양단의 전압이 동일한 값으로 충전된 경우에서도 마찬가지다.The difference between these two accumulated charges, i.e., the amount of charged charges, generates an electric field (the non-uniformity of the electric charge soon forms an electric field), and this electric field is stored in the bootstrap capacitor (Cboot) in the form of energy.

) Also, the direction of this electric field is expressed as a difference in polarity such as +Q and -Q. And this is the same even when the voltage across the bootstrap capacitor (Cboot) is charged to the same value.

After charging is completed, when the voltage of one node changes to an arbitrary value (for example, V- = Vx), the voltage of the other node also changes to the same value (for example, V+ = Vx), so the amount of charge charged ΔQ = 0 = C(Vx - Vx) remains the same and does not change.

)와 전하량 모두 보존 법칙이 성립한다. 이에 반해, 차지 쉐어링은 전후의 (충전) 에너지의 보존 법칙은 성립하지 않고, 다만 전하량 보존 법칙만 성립한다. 차지 쉐어링 과정은 필연적으로 전하의 이동, 즉 전류를 수반하여 줄히팅(joule heating)과 같은 열 손실로 에너지 일부를 잃기 때문이다.In the bootstrap operation of the bootstrap capacitor (Cboot) as described above, energy (ie, charging energy =

) and the amount of charge both hold the law of conservation. On the other hand, in charge sharing, the law of conservation of energy before and after (charge) does not hold, only the law of conservation of charge. This is because the charge-sharing process inevitably loses some of its energy due to the transfer of electric charge, ie, heat loss such as joule heating, which accompanies electric current.

In an embodiment, as shown in FIG. 4 , the bootstrap capacitor Cboot connects the upper voltage Vx with the first voltage V1 through the first switch SW1 and simultaneously forms a lower side voltage Vx. The voltage Vs is connected to the second voltage V2 through the second switch SW2, connected to the third voltage V3 through the third switch SW3, and connected to the ground through the fourth switch SW4. When the connection is formed, as shown in Table 1 below, when the first switch SW1 and the second switch SW2 are turned on and the third switch SW3 and the fourth switch SW4 are turned off, the upper voltage Vx ), the first voltage V1 is applied and the lower voltage Vs is subjected to the second voltage V2, and then the first switch SW1, the second switch SW2 and the fourth switch SW4 are turned off. And when only the third switch SW3 is turned on, the upper voltage (Vx) applies the voltage V1+ (V3-V2) and the lower voltage (Vs) changes from the second voltage (V2) to the third voltage (V3). , alternatively, when the first switch SW1, the second switch SW2 and the third switch SW3 are turned off and only the fourth switch SW4 is turned on, the upper voltage Vx is V1+ (0V-V2). and the lower voltage Vs is changed from the second voltage V2 to 0V.

SW1 SW2 SW3 SW4 Vx Vs ON ON OFF OFF V1 V2 OFF OFF ON OFF V1+ (V3-V2) V2 -> V3 OFF OFF OFF ON V1+(0V-V2) V2 -> 0V

As shown in FIG. 5 , the bit bar line bootstrap unit 230 or (or, and) the bit line bootstrap unit 240 includes a plurality of switches (/SW1, /SW2, SW1) for generating a bootstrap voltage. , SW2), and by implementing FIG. 4 as a bootstrap capacitor (Cboot), the bootstrap voltage ( Vx) and the bootstrap voltage (Vy) of the bit line are extracted.

The bit bar line bootstrap unit 230 connects and forms the first bit line switch SW1 between the upper side of the bootstrap capacitor Cboot and the bit line B, and at the same time forms the bootstrap capacitor Cboot. After charging by connecting the first bit bar line switch (/SW1) between the lower side and the bit bar line (/B), the second bit line switch (/SW1) between the lower side of the bootstrap capacitor (Cboot) and the bit line (B) SW2) is connected so that the upper voltage of the bootstrap capacitor (Cboot) changes to Vx.

The bit line bootstrap unit 240 connects and forms the first bit bar line switch (/SW1) between the upper side of the bootstrap capacitor (Cboot) and the bit bar line (/B), and at the same time forms the bootstrap capacitor ( After charging by connecting the first bit line switch SW1 between the lower side of Cboot and the bit line B, the second bit bar between the lower side of the bootstrap capacitor Cboot and the bit bar line /B By connecting the in switch (/SW2), the upper voltage of the bootstrap capacitor (Cboot) changes to Vy.

In an embodiment, the bit bar line bootstrap unit 230 or (or, and) the bit line bootstrap unit 240 provides a bit at both terminals of the bootstrap capacitor Cboot, as shown in Table 2 below. By changing the order of mutually switching the bar line (/B) voltage and the bit line (B) voltage, the voltage difference applied between the gate of the first NMOS transistor 103 and the gate of the second NMOS transistor 104 is reduced. It can be applied with a large voltage difference of 3ΔV, which is three times higher than the initially formed sensing margin (ΔV). In other words, the upper voltage of the bit bar line bootstrap unit 230 is made Vx, the upper voltage of the bit line bootstrap unit 240 is made Vy, and then the voltage Vx is the gate voltage of the first NMOS transistor 103 . , and the voltage Vy is input as the gate voltage of the second NMOS transistor 104 . The sequence of just switching the bit bar line (/B) voltage and the bit line (B) voltage through the switches (/SW1, /SW2, SW1, SW2) using the bootstrap principle of the two bootstrap capacitors (Cboot) By controlling only , it is possible to create a voltage difference (Vx-Vy) that is three times higher than the initially formed sensing margin (ΔV).

Initial value (SW1) After bootstrap (SW2+(V+) node floating) data /B B Vx Vy Vx-Vy One "1"@B vblp Vblp+1△ Vblp+2△ Vblp-1△ +3△ 2 "0"@B vblp Vblp-1△ Vblp-2△ Vblp+1△ -3△ 3 "1"@/B Vblp+1△ vblp Vblp-1△ Vblp+2△ -3△ 4 "0"@/B Vblp-1△ vblp Vblp+1△ Vblp-2△ +3△

The bit bar line bootstrap unit 230 or (or, and) the bit line bootstrap unit 240 is for bit bar lines of the two bootstrap capacitors (Cboot) extracted in FIG. 5 as shown in FIG. 6 . The voltage Vx and the voltage Vy for the bit line are used as the gate of the first NMOS transistor 103 and the gate of the second NMOS transistor 104 , respectively. That is, by inserting the bootstrap capacitor (Cboot) into the sense amplifier, the two bootstrap voltages Vx and Vy are utilized in the sense amplifier.

2 and 6, the capacitance Cb of the bit bar line capacitor 105 and the bit line capacitor 106 is maintained at 40 fF, and the cell capacitance Cs of the cell capacitor 107 is changed from 8 fF to 4 fF. In order to show that it is possible to secure more than the same level of sensing margin compared to the existing one, even in a situation where the Set to 0.55V, which is Vcore/2, which is the voltage during actual operation. In this case, the sensing margin (ΔV) of “1” data and “0” data is equally 0.55V/(1+10)=0.55/11=0.05V, that is, 50mV.

= 17[fF/㎛2]*W[㎛]*L[㎛] = 0.017[fF]이다. 단, 게이트와 소스 그리고 게이트와 드레인 노드 사이의 밀러(Miller) 커패시턴스 성분은 그 값이 충분히 작으므로 무시한다. MOS 커패시터(Cox)는 모든 MOS 트랜지스터들에 반드시 존재하는 원천적인 성분이며, 트랜지스터로서 온/오프 작동을 하기 위한 트랜지스터의 게이트와 실리콘 사이에 자연 발생하는 기본적인 커패시터 부하(load)이다.The bit bar line bootstrap unit 230 or (or, and) bit line bootstrap unit 240 is a MOS capacitor (Cox) that is inherently present at the gate terminals of the first NMOS transistor 103 and the second NMOS transistor 104 . ) (refer to FIG. 7) and the upper side of the bootstrap capacitor (Cboot), and the capacitance value of the MOS capacitor (Cox) at the transistor gate terminal, the capacitance value of the bootstrap capacitor (Cboot), and the cell capacitor 107 ), the capacitance value of the bootstrap capacitor (Cboot) is set so that the following multiple relationship is established between the cell capacitance value (Cs) of the bit line capacitor (106) and the bit line capacitance value (Cb) of the bit line capacitor 106, for example, Set to display Cs/Cboot = n, Cb/Cs = r, and Cboot/Cox = M. Here, n, r, and M are set to at least 20 or more, and the MOS capacitor Cox seen at the gate terminal of the transistor can be calculated as follows. When the thickness (t) of the gate oxide is 20 Å, when the width (W) and the length (L) of the transistor are composed of W = 0.1 μm and L = 0.1 μm, respectively, the MOS capacitor ( The capacitance value of Cox) is

= 17[fF/μm2]*W[μm]*L[μm] = 0.017[fF]. However, since the value of the Miller capacitance component between the gate and the source and the gate and the drain node is sufficiently small, it is ignored. The MOS capacitor (Cox) is a fundamental component necessarily present in all MOS transistors, and is a basic capacitor load naturally occurring between the gate and silicon of the transistor for on/off operation as a transistor.

When one cell connected to the bit bar line (/B) or bit line (B) is selected and charge sharing occurs between the cell capacitor and the bit line capacitor, the total capacitance value of the line (/B or B) in which the cell is selected is Since it is synthesized in parallel with the cell capacitor 107, it becomes Cb + Cs, and the capacitance value of the opposite line in which the cell is not selected maintains the Cb state. This also acts as a large capacitance mismatch factor between the bit bar line (/B) and the bit line (B) during the sensing operation.

5 shows a bit bar line bootstrap voltage (Vx) and a bit line bootstrap voltage (Vy) according to each switching order when an external power supply voltage is applied to both ends of the bootstrap capacitor (Cboot). In this case, the bit The bar line bootstrap unit 230 or (or, and) the bit line bootstrap unit 240 applies the bit bar line bootstrap voltage Vx to the gate of the first NMOS transistor 103 of the bit bar line /B. voltage, and the bit line bootstrap voltage Vy is applied to the gate voltage of the second NMOS transistor 104 of the bit line, so that the difference between the gate voltages of the first NMOS transistor 103 and the second NMOS transistor 104 is is applied to the gate voltage of the first NMOS transistor 103 and the second NMOS transistor 104 as a voltage difference (3ΔV) increased three times from the conventional sensing margin (ΔV), and the sensing margin is increased by 3 times; gives the same effect. However, in the embodiment of the present invention, it is not connected to an external power supply voltage, but a capacitor for bootstrap (Cboot) and a bit line capacitance (Cb), and a large difference in capacitance between Cox and Cboot (Cb/Cboot≥20) , Cboot/Cox≥20) is used, so it is not exactly 3ΔV as shown in Table 2, but the actual realizable 3ΔV according to the values of n, r, and M mentioned above. It should be well understood that sizes may vary. However, in an example to be described later, it can be concluded that there is little difference from that shown in Table 2 even if nr≥20 or more.

The following describes the process of obtaining the bit bar line bootstrap voltage Vx used as the gate voltage of the first NMOS transistor 103 when sensing data “1” on the bit bar line /B as an example. same as

The sensing margin (ΔV) of “1” data and “0” data is 50 mV in common under the aforementioned conditions. First, the anode of the bootstrap capacitor (Cboot) has BLEQ on, and at the same time, the first signal switch (T232, T233) is a transistor that serves as two switches, but the control signal line for these two transistors shares the first signal line. It should be noted that it is distinguished from naming a one-signal switch, and in the following, T231 to T234 are respectively named as first to fourth switching transistors. is transferred to the anode of the bit bar line, bit line, and the anode of the bootstrap capacitor are equally precharged to the bit line precharge voltage (Vblp), then when BLEQ is turned off and the word line is opened immediately, Since the first two switches are still on, the bit bar line (/B) voltage is connected to the lower node (V-) of the bootstrap capacitor (Cboot) through the first switching transistor of T233, and the bit line (B) ) is connected to the upper node (V+) of the bootstrap capacitor (Cboot) through the first switching transistor of T232, and enters a charged state.

), 제1전압(

)과 커패시턴스가 상대적으로 작은 노드(

), 제2전압(

)을 서로 연결할 때 커패시턴스가 상대적으로 큰 노드의 제1전압(V1)으로 변하되, 단

만큼 차감되어 변동한다. 따라서 두 커패시턴스의 비가 크면 클수록 차감 성분은 줄어들고, 커패시턴스 값이 상대적으로 더 큰 노드의 제1전압(V1)과 거의 같아진다.At this time, since the bit line (B) voltage and the upper node of the bootstrap capacitor maintain the same bit line pre-charge voltage (Vblp), there is no voltage fluctuation at all, and the bit bar line (/B) voltage opens the cell data. When Vblp changes from Vblp to Vblp+ΔV, and this changed bit bar line (/B) is connected to the lower node (V-) of the bootstrap capacitor (Cboot) that was precharged with the Vblp voltage, charge sharing occurs first. it happens once For reference, charge-sharing occurs between all capacitors whose voltages at the two nodes are not equal, and the voltage after charge-sharing is applied to nodes with relatively large capacitance (

), the first voltage (

) and a node with relatively small capacitance (

), the second voltage (

), the capacitance changes to the first voltage (V1) of the node having a relatively large capacitance,

It is deducted and fluctuates. Accordingly, as the ratio of the two capacitances increases, the subtraction component decreases, and the capacitance value becomes almost equal to the first voltage V1 of the node having a relatively larger capacitance.

만큼 차감되어

만큼만 변화된다. 여기서, 비트바라인(/B)의 커패시턴스는 셀 커패시턴스가 병렬 합성되므로, Cb가 아닌 Cs+Cb이다. 즉, 차지 쉐어링 이후 부트스트랩용 커패시터(Cboot)의 하측(V-) 노드 전압과 비트바라인(/B)의 전압은 아래의 수학식 1과 같이 된다.The capacitance of the bootstrap capacitor (Cboot) is always smaller than the capacitance of the bit bar line (/B) and the bit line (B) (nr > 20), so the lower (V-) node of the bootstrap capacitor (Cboot) When connecting the voltage (Vblp) and the voltage (Vblp+ΔV) of the bit bar line (/B), the lower (V-) node voltage (Vblp) of the bootstrap capacitor (Cboot) is the voltage of the bit bar line (/B) It does not have the same value as the voltage (Vblp+ΔV), and it is higher than the sensing margin (ΔV) as described above.

deducted as much

change only as much Here, the capacitance of the bit bar line (/B) is Cs+Cb, not Cb, since the cell capacitances are combined in parallel. That is, after charge sharing, the voltage of the lower side (V-) node of the bootstrap capacitor (Cboot) and the voltage of the bit bar line (/B) are expressed by Equation 1 below.

In Equation 1, the larger the nr value, the greater the nr value is approximately equal to the n(r+1) value.

가 된다.For example, when n = 4, r = 10 (nr = 40), the voltage at the lower side (V-) node of the bootstrap capacitor (Cboot) and the bit bar line (/B) after charge sharing according to Equation 1 the voltage of

becomes

가 된다.As another example, when n = 4, r = 5 (nr = 20), the voltage of the lower side (V-) node of the bootstrap capacitor (Cboot) and the bit bar line (/B) after charge sharing according to Equation 1 the voltage of

becomes

After that, the voltage change generated at the lower (V-) node of the bootstrap capacitor (Cboot) is bootstrapped again as it is and is added to the upper (V+) node of the bootstrap capacitor (Cboot). The high side (V+) node rises by the voltage calculated by Equation 1 from the bit line precharge voltage Vblp of the precharge period, and is again connected to the bit line B at the bit line precharge voltage Vblp. By connecting again, charge sharing takes place again.

만큼 살짝 올라간 값이 된다. 이때, 비트라인(B)의 커패시턴스는 Cb 값 그대로 이다. 즉, 부트스트랩용 커패시터(Cboot)의 상측(V+) 노드 전압과 비트라인(B) 전압은 아래의 수학식 2와 같이 된다.As a result, the voltage of the upper (V+) node of the bootstrap capacitor (Cboot) is not exactly equal to the precharge voltage (Vblp) of the bit line (B), and is higher than the precharge voltage (Vblp) of the bit line (B).

It will be a slightly increased value. At this time, the capacitance of the bit line B remains the same as the Cb value. That is, the upper (V+) node voltage and the bit line (B) voltage of the bootstrap capacitor Cboot are expressed in Equation 2 below.

가 된다.For example, when n = 4, r = 10 (nr = 40), the upper (V+) node voltage and the bit line (B) voltage of the bootstrap capacitor Cboot according to Equation 2 are

becomes

가 된다.As another example, when n = 4, r = 5 (nr = 20), the upper (V+) node voltage and the bit line (B) voltage of the bootstrap capacitor Cboot according to Equation 2 are

becomes

The above two results are not significantly different from the results obtained by switching each node of the bootstrap capacitor (Cboot) with the actual external power supply voltage. It can be seen that the difference in the result obtained by charge sharing between two capacitors using a difference in capacitance of at least 20 times or more is in a negligible range compared to the time of switching to the power supply voltage. That is, it may be interpreted as charge sharing between the first voltage V1 having an infinite capacitance and the second voltage V2 having a finite C1 capacitance.

Therefore, in the following description, it is assumed that n = 4, r = 5 (nr = 20) close to the lower limit value within the practically applicable range is assumed to explain the rest of the process of extracting the voltage (Vx) for the bit bar line with the actual calculated value. do. What has been done so far corresponds to the initial state of charge, and then switches to the lower (V-) node of the bootstrap capacitor (Cboot) and the bit line (B), and the upper voltage (Vx) of the bootstrap capacitor of the final bit bar line The process of obtaining

The lower (V-) node of the bootstrap capacitor (Cboot) is connected to the bit bar line (/B) and is at 0.598V, and the upper (V+) node of the bootstrap capacitor (Cboot) is connected to the bit line (B). connected and at 0.552V. At this time, it is a value assuming the case where n = 4, r = 5, and nr = 20.

가 되고, 해당 부트스트랩용 커패시터(Cboot)의 하측(V-) 노드의 전압 변동이 그대로 부트스트랩용 커패시터(Cboot)의 상측(V+) 노드에서도 나타나므로, 초기 상태의 부트스트랩용 커패시터(Cboot)의 하측(V-) 노드 전압 0.598V와 이후 최종 전압 0.554V간의 전압 변동분이 0.598V - 0.554V = 44mV이 생긴다. 이에, 부트스트랩용 커패시터(Cboot)의 상측(V+) 노드의 전압 0.552V에서 부트스트랩용 커패시터(Cboot)의 하측(V-) 노드에서의 전압 변동량이 그대로 반영되어, 0.552V - 44mV = 0.508V가 된다.Then, by switching the bit line (B) to the lower (V-) node of the bootstrap capacitor (Cboot), the voltage at the lower (V-) node of the bootstrap capacitor (Cboot) is

Since the voltage fluctuation of the lower (V-) node of the corresponding bootstrap capacitor (Cboot) appears in the upper (V+) node of the bootstrap capacitor (Cboot) as it is, the bootstrap capacitor (Cboot) in the initial state. The voltage variation between the lower (V-) node voltage of 0.598V and the final voltage of 0.554V thereafter is 0.598V - 0.554V = 44mV. Accordingly, the voltage variation at the lower (V-) node of the bootstrap capacitor (Cboot) is reflected as it is at the voltage of 0.552V at the upper (V+) node of the bootstrap capacitor (Cboot), 0.552V - 44mV = 0.508V becomes

From the above-described calculation formula, it can be well understood that the result values obtained in the table of Table 2 are almost the same. Therefore, the bootstrap voltage (Vx) of the bit bar line and the bootstrap voltage (Vy) of the bit line, which are extracted by switching to the node of the bootstrap capacitor (Cboot) with the external power supply voltage, have a large capacitance difference under the condition that nr > 20 , there is only a difference in mV unit from that obtained as a result of charge sharing, and it can be confirmed that there is no problem in applying the values presented in Table 2 as they are.

Thereafter, the bootstrap voltage (Vx) of the bit bar line and the bootstrap voltage (Vy) of the bit line induced in the bootstrap capacitor (Cboot), that is, the bootstrap voltage (Vx) of the bit bar line are respectively applied to the first NMOS transistor ( 103) and the process of transferring the bootstrap voltage Vy of the bit line to the gate of the second NMOS transistor 104 is also a charge-sharing process.

Since the gate of the first NMOS transistor 103 and the gate of the second NMOS transistor 104 also have a capacitance component called the MOS capacitor Cox, the bootstrap voltage Vx of the bit bar line of the bootstrap capacitor Cboot or The voltage Vgs applied to the gates of the final first NMOS transistor 103 and the second NMOS transistor 104 is determined according to the result of charge-sharing the bootstrap voltage Vy of the bit line with the MOS capacitor Cox.

The gate of the first NMOS transistor 103 and the gate of the second NMOS transistor 104 have the same capacitance corresponding to the MOS capacitor Cox, and the MOS capacitor Cox is also precharged with the bit line precharge voltage Vblp. Then, the bootstrap capacitor (Cboot) is connected to the bootstrap voltage (Vx) of the bit bar line or the bootstrap voltage (Vy) of the bit line.

만큼 차감되고, 전압 변동이 △V가 발생한 경우에는

만큼 차감된 전압이 트랜지스터의 게이트로 인가되므로, 부트스트랩용 커패시터(Cboot)에 형성된 전압이 거의 그대로 게이트로 인가된다고 할 수 있다.Since the bootstrap voltage (Vx) of each bit bar line and the bootstrap voltage (Vy) of the bit line can vary by 2ΔV and ΔV respectively in the table of Table 2 compared to the bit line precharge voltage (Vblp), When the Cboot/Cox ratio (M) is also assumed to be about 20, if the voltage fluctuation is 2ΔV,

is subtracted by the amount, and when the voltage fluctuation ΔV occurs,

Since the subtracted voltage is applied to the gate of the transistor, it can be said that the voltage formed in the bootstrap capacitor Cboot is applied to the gate as it is.

FIG. 7 is a view for explaining a bit bar line bootstrap unit and a bit line bootstrap unit shown in FIG. 2 .

Referring to FIG. 7 , the bit bar line bootstrap unit 230 or (or, and) the bit line bootstrap unit 240 includes a plurality of switching transistors T231 for implementing the switching operation described in FIG. 6 as an actual circuit. ~ T234, T241 ~ T244) is made to further include. In other words, FIG. 7 shows a significant difference in capacitance between the MOS capacitor Cox and the bit bar line capacitor Cb 105 provided between the bootstrap capacitor Cboot and the first NMOS transistor 103, and the bootstrap capacitor. It is a diagram implemented as an actual circuit using a significant difference in capacitance between the MOS capacitor (Cox) and the bit line capacitor (Cb) 106 provided between (Cboot) and the second NMOS transistor 104 .

The switching transistors T231 to T234 and T241 to T244 connect the gate of the first inverter unit 210 to the bit line B during the sense amplifier operation to create a bootstrap voltage, and the second inverter unit ( 220) is connected to the bit bar line (/B), so that the input and output values of the inverter units 210 and 220 are set to 0V and the power supply voltage (Vcore), respectively.

The first switching transistor T231 of the bit bar line bootstrap unit 230 is formed between the upper side of the bootstrap capacitor Cboot and the gate of the first NMOS transistor 103, and the second switching transistor T232 is the boot Formed between the upper side of the strap capacitor (Cboot) and the bit line (B), the third switching transistor (T233) is formed between the lower side of the bootstrap capacitor (Cboot) and the bit bar line (/B), The 4-switching transistor T234 is formed between the lower side of the bootstrap capacitor Cboot and the bit line B.

The first switching transistor T241 of the bit line bootstrap unit 240 is formed between the upper side of the bootstrap capacitor Cboot and the gate of the second NMOS transistor 104, and the second switching transistor T242 is bootstrapped. It is formed between the upper side of the capacitor Cboot and the bit bar line /B, and the third switching transistor T243 is formed between the lower side of the bootstrap capacitor Cboot and the bit line B, and the fourth The switching transistor T244 is formed between the lower side of the bootstrap capacitor Cboot and the bit bar line /B.

In an embodiment, the switching transistors T231 to T234 and T241 to T244 are NMOS transistors as transistors required for a switching operation, and can be configured as a transistor of a minimum size used as the cell transistor 108 , and more Since it can be implemented with a smaller transistor, it is okay to design the transistor with the minimum size allowed by the process technology.

The bit bar line bootstrap unit 230 or (or, and) bit line bootstrap unit 240 having the configuration as described above adds a bootstrap capacitor Cboot, respectively, so that the cell capacitance in the sense amplifier is reduced. By using the bootstrap principle of the bootstrap capacitor (Cboot), the sensing margin (ΔV), which is bound to decrease along with the decrease, has the same effect as that of a three-fold increase, and at the same time, the sensing margin is boosted. In order to obtain , four switching transistors (T231 to T234, T241 to T244), which are NMOS transistors of the size of a cell transistor required for bootstrap switching, are added each, and the timing control required for switching is performed. In addition, if the cell capacitance can be secured to a certain extent, normal sensing is possible even when the bit line capacitance is increased by extending the bit line length. In the laminate structure of tungsten (W) and polysilicon used as bit line materials, the RC-delay of the bit line (sensing margin (ΔV) formed in the cell furthest from the sense amplifier) extends to the input of the sense amplifier. Transmission time delay) weakens the part that acts as a decisive limiting factor for the extension of the bit line length. has been As described above, an increase in the Cb/Cs ratio reduces the sensing margin ΔV.

The bit bar line bootstrap unit 230 or (or, and) bit line bootstrap unit 240 having the above-described configuration includes the thresholds of the switching transistors T231 to T234 and T241 to T244 for switching. Also in the voltage Vt control, there is little influence on the fluctuation components, and the current driving ability may be extremely small, thereby minimizing the area added to the sense amplifier and making the process control technology also not burdensome. However, the substrate effect (body effect) of the first NMOS transistor 103 and the second NMOS transistor 104 is further increased in the direction of widening the voltage difference between the bit bar line (/B) and the bit line (B). It allows the bit bar line (/B) and bit line (B) voltages to be applied as a p-well bias.

For example, when "1" data is sensed on the bit line B, the threshold voltage Vt of the second NMOS transistor 104 is slightly higher than that of the first NMOS transistor 103, and the first NMOS transistor By changing the threshold voltage (Vt) of (103) to a lower value, the IDS of the first NMOS transistor 103 is increased and the second NMOS transistor 104 is decreased to form a substrate effect. give.

FIG. 8 is a view for explaining the timing of driving the switching transistor shown in FIG. 7 , and FIG. 9 is a view for explaining the inverter unit shown in FIG. 2 .

8 and 9, in configuring the bit line sense amplifier 200, the bootstrap voltage (Vx) of the bit bar line and the bootstrap voltage (Vy) of the bit line of the bootstrap capacitor (Cboot) are In order to extract, driving timings for each of the switching transistors T231 to T234 and T241 to T244 that are NMOS transistors performing a switching role can be checked.

되지 않는다), 비트바라인(/B)과 비트라인(B)의 전압의 하강 슬로프를 크게 벌어지게 하고, 이후 제2신호(t2)가 0V로 천이된 상태에서 제1신호(t1)와 제3신호(t3)가 동시에 활성화되는 제3시구간(③) 이후부터는, 비트바라인(/B)의 전압을 제2PMOS 트랜지스터(102)와 제2NMOS 트랜지스터(104)로 구성된 제2인버터부(220)의 게이트 입력으로 그대로 전압이 전달(즉, 전원 전압(Vcore)이 그대로 전달)되게 하고, 비트라인(B)의 전압을 제1PMOS 트랜지스터(101)와 제1NMOS 트랜지스터(103)로 구성된 제1인버터부(210)의 게이트 입력으로 그대로 전압이 전달되게 함으로써, CMOS 인버터부(210, 220)의 구성된 양 입력단에 완전한 전원 전압(Vcore)과 0V로 입력되어, 비트바라인용 전압과 비트라인용 전압을 전원 전압(Vcore)과 0V 전압으로 각각 만들어 주기 위한 것이다.Each voltage value is Vpp (3.0V), which corresponds to the activation signal voltage of the cell word line at 0V. This is because the gate voltage difference between the first NMOS transistor 103 and the second NMOS transistor 104 at the beginning of sensing is applied to a voltage close to 3Δ from the existing ΔV, so that the IDS of the first NMOS transistor 103 and the second NMOS transistor 104 is applied. Make the current difference value at least 6 times larger (since it is in saturation mode, the current varies greatly in proportion to the square of (Vgs-Vtn), and exactly according to the Vtn value

not), widening the falling slope of the voltage of the bit bar line (/B) and the bit line (B), and then, in a state in which the second signal t2 transitions to 0V, After the third time period (③) in which the three signals t3 are simultaneously activated, the voltage of the bit bar line (/B) is applied to the second inverter unit 220 including the second PMOS transistor 102 and the second NMOS transistor 104 . ), the voltage is transferred as it is (that is, the power supply voltage Vcore is transferred as it is), and the voltage of the bit line B is transferred to the first inverter composed of the first PMOS transistor 101 and the first NMOS transistor 103 . By allowing the voltage to be directly transferred to the gate input of the unit 210, the complete power supply voltage Vcore and 0V are input to both input terminals of the CMOS inverter units 210 and 220, and the voltage for the bit bar and the voltage for the bit line are obtained. This is to make the power supply voltage (Vcore) and 0V voltage respectively.

The first signal t1 is a signal that gives a common input to the second switching transistors T232 and T242 and the third switching transistors T233 and T243. The second signal t2 is a signal that gives a common input to the fourth switching transistors T234 and T244. The third signal t3 is a signal that gives a common input to the first switching transistors T231 and T241.

During the first time period (①), all of the first signal t1, the second signal t2, and the third signal t3 are active, and the bit line equalize (BLEQ) is also turned on, so that the boot Both terminals of the strap capacitor (Cboot), the bit bar line (/B) and the bit line (B), and the restore voltage (Vrestore) and the sink voltage (Vsink) are both at the bit line pre-charge voltage (Vblp) level. This is the section where the charge operation is performed. Here, since the first, second, and third signals are all connected to the gate of the NMOS transistor, the active state means that the NMOS transistor is in a Vpp voltage state, which is a signal level that turns on, and the inactive state is a signal level that turns off the NMOS transistor. It means that it is in the 0V voltage state.

Afterwards, in the second time period (②), the second signal t2 and the third signal t3 are deactivated, and the word line of the cell is opened in a state where only the first signal t1 is in the active signal and the bit bar line ( /B) and the bit line (B), the sensing margin (ΔV) is induced, the bootstrap capacitor (Cboot) is an operation period in which charge sharing is performed in the initial state of charge.

Then, when the first signal t1 is deactivated and the second signal t2 is activated, the third signal t3 is also activated at the same time (or after a slight time delay), so for bootstrap The bootstrap voltage Vx of the bit bar line and the bootstrap voltage Vy of the bit line that are bootstrapped at the upper (V+) node of the capacitor Cboot are formed, and the first NMOS transistor 103 and the second NMOS transistor ( 104) is applied to the gate. Thereafter, the sink voltage Vsink is shifted from the bit line pre-charge voltage Vblp to 0V to drive the first NMOS transistor 103 and the second NMOS transistor 104, and then the restore voltage Vrestore is applied to the bit line pre-charge voltage Vblp. The first PMOS transistor 101 and the second PMOS transistor 102 are also driven by increasing the charge voltage Vblp to the power supply voltage Vcore.

During the third time period (③), while the third signal t3 maintains the active signal as it is, the first signal t1 is activated again, and at the same time, the second signal t2 is deactivated, so that the bit bar line (/B) is connected to the input of the second inverter unit 220 via two first and second switch transistors T241 and T242, and also the first and second switch transistors T231 and T232 2 The bit line (B) is connected to the input of the first inverter unit 210 via the , so that it is maintained until the final sensing.

In FIG. 8, after the voltage of the upper (V+) node of the bootstrap capacitor Cboot is boosted to the bootstrap voltage Vx of the bit bar and the bootstrap voltage Vy of the bit line, the boot of the bit bar The time required to maintain the strap voltage (Vx) and the bootstrap voltage (Vy) of the bit line is several ns, and the bootstrap voltage (Vx) of the bit bar and the bootstrap voltage (Vy) of the bit line are maintained for several ns. The leakage current generated in the upper side (V+) node is controlled to be less than a preset range according to the capacitance value of the bootstrap capacitor (Cboot).

이므로,

, 즉 수 ns 이후 mV에 해당하는 전압 변동을 줄 수 있는 정도이기 때문이다.When the bootstrap capacitor (Cboot) has a range of several fF, the leakage amount allows it to have an order of nA or less. This means that if a current of the order of nA flows for several ns that the voltage must be maintained, the amount of charge lost is

Because of,

, that is, it is the degree to which a voltage fluctuation corresponding to mV can be given after several ns.

오더 이상으로 작은 값을 가진다.Since the switching transistors T231 to T234 and T241 to T244, which are NMOS transistors to be used for actual switching, are used in a cell array, the leakage amount is higher than the above-described leakage.

It has a smaller value than the order.

In the CMOS inverter units 210 and 220 , a general relationship between elements, design model parameters, and logic threshold values of the inverter units 210 and 220 is shown in FIG. 9 .

Above, the embodiment of the present invention is not implemented only through the above-described apparatus and/or operation method, but through a program for realizing a function corresponding to the configuration of the embodiment of the present invention, a recording medium in which the program is recorded, etc. It may be implemented, and such an implementation can be easily implemented by an expert in the technical field to which the present invention pertains from the description of the above-described embodiments. Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improved forms of the present invention are also provided by those skilled in the art using the basic concept of the present invention as defined in the following claims. is within the scope of the right.

200: beatline sense amplifier
101: first PMOS transistor
102: second PMOS transistor
103: first NMOS transistor
104: second NMOS transistor
105: bit bar line capacitor
106: bit line capacitor
107: cell capacitor
108: cell transistor
210: first inverter unit
220: second inverter unit
230: bit bar line bootstrap unit
240: bit line bootstrap unit
Cboot: capacitor for bootstrap
SW1, SW2, SW3, SW4: switch
SW1, SW2: bit line switch
/SW1, /SW2: bit bar line switch
Cox: MOS capacitor
T231 to T234, T241 to T244: switching transistors

Claims (6)

The first PMOS transistor 101 , the second PMOS transistor 102 , the first NMOS transistor 103 , the second NMOS transistor 104 , the bit bar line capacitor 105 , the bit line capacitor 106 , the cell capacitor 107 , the cell A bit line sense amplifier including a transistor (108), comprising: a first inverter unit (210) comprising the first PMOS transistor (101) and the first NMOS transistor (103); formed between the second inverter units 220 including 2NMOS transistors 104; A bit bar line bootstrap unit 230 and a bit line boot each having a bootstrap capacitor Cboot, respectively, to be used as gate inputs of the first NMOS transistor 103 and the second NMOS transistor 104, respectively. It further includes a strap portion 240;
The bit bar line bootstrap unit 230 and the bit line bootstrap unit 240 do not directly connect the input of the first inverter unit 210 and the bit line B, and the second inverter unit ( 220) is formed so as not to directly connect the input of the bit bar line (/B); Further comprising switching transistors T231 to T234, T241 to T244 for creating a bootstrap voltage, each bit bar line (/B) is an inverter according to the switching sequence using the switching transistors T231 to T234, T241 to T244 extracting the input voltage of the first inverter unit 210 connected to the output and the input voltage of the second inverter unit 220 connected to the bit line B through the inverter output; a voltage difference corresponding to a sensing margin created as a result of charge sharing is further amplified by using the bootstrap capacitor (Cboot); a sensing margin created as a result of charge sharing is applied to the sense amplifier input as an amplified voltage using the bootstrap capacitor (Cboot); a voltage difference applied between both ends of the gate of the first NMOS transistor 103 and the gate of the second NMOS transistor 104 is applied with a voltage difference three times greater than the initially formed sensing margin;
The bit bar line bootstrap part 230 forms a first switching transistor T231 between an upper side of one bootstrap capacitor Cboot and the gate of the first NMOS transistor 103, A second switching transistor T232 is formed between the upper side of the capacitor Cboot and the bit line B, and a third switching transistor T232 is formed between the lower side of the bootstrap capacitor Cboot and the bit bar line /B. T233), forming a fourth switching transistor (T234) between the lower side of the bootstrap capacitor (Cboot) and the bit line (B);
The bit line bootstrap unit 240 forms a first switching transistor T241 between the upper side of the other bootstrap capacitor Cboot and the gate of the second NMOS transistor 104, A second switching transistor T242 is formed between the upper side of the capacitor Cboot and the bit bar line /B, and a third switching transistor T242 is formed between the lower side of the bootstrap capacitor Cboot and the bit line B. T243) and forming a fourth switching transistor (T244) between the lower side of the bootstrap capacitor (Cboot) and the bit bar line (/B). delete delete delete delete delete

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