KR102307161B1 - Multilayer ceramic electronic component - Google Patents

Abstract

To provide a multilayer ceramic electronic component capable of suppressing grain growth of ceramic particles in an inner layer portion while making a side margin portion dense.
A multilayer ceramic electronic component of the present invention includes a multilayer body, a first external electrode provided on a first end surface of the multilayer body, and a second external electrode provided on a second end surface of the multilayer body. The laminate includes an inner layer portion in which the first inner electrode layer and the second inner electrode layer face each other with a dielectric ceramic layer therebetween, an outer layer portion disposed to sandwich the inner layer portion in a stacking direction, and a width of the inner layer portion and the outer layer portion It includes a side margin arranged to fit in the direction. The side margin portion is composed of a plurality of ceramic layers laminated in the width direction, and as the ceramic layer, an inner layer disposed at the innermost side of the multilayer body, and an innermost layer disposed at the outermost side of the multilayer body, the content of the sintering aid element an outer layer greater than the inner layer; and a buffer layer disposed between the inner layer and the outer layer and having a content of the sintering aid element less than that of the outer layer.

Description

Multilayer ceramic electronic component {MULTILAYER CERAMIC ELECTRONIC COMPONENT}

The present invention relates to a multilayer ceramic electronic component.

A multilayer ceramic capacitor may be mentioned as an example of a multilayer ceramic electronic component. In the multilayer ceramic capacitor, for example, a multilayer body in which dielectric ceramic layers and internal electrode layers are alternately stacked, and dielectric ceramic layers are stacked on upper and lower surfaces thereof, and external electrodes formed on both end surfaces of the stacked body. contains In such a multilayer ceramic capacitor, a ceramic layer called a side margin portion is formed on the side surface of the multilayer ceramic capacitor to prevent the internal electrode layer from being connected to the external electrode.

For example, in Patent Document 1, the side margin portion has a plurality of side margin layers, and the Si content of the side margin layer other than the side margin layer on the internal electrode side is higher than that of the side margin layer closest to the internal electrode. A multilayer ceramic capacitor is disclosed.

Patent Document 2 discloses a laminate comprising a plurality of ceramic layers made of first ceramics having a first average grain size and stacked in a first direction, and an internal electrode disposed between the plurality of ceramic layers, and a second average crystal. A third ceramics comprising a second ceramics having a grain size, a side margin portion covering the laminated portion in a second direction orthogonal to the first direction, and a third average grain size larger than the first and second average grain sizes. Disclosed is a multilayer ceramic capacitor comprising:

Japanese Patent Laid-Open No. 2017-28013 Japanese Patent Laid-Open No. 2017-147429

In the multilayer ceramic capacitor described in Patent Document 1, by increasing the content of Si in the side margin layer other than the side margin layer on the internal electrode side, the strength of the side margin portion can be improved, so that the flexural strength of the multilayer ceramic capacitor can be improved. have. Furthermore, it is said that the insulation of the multilayer ceramic capacitor can be secured because cracks and cracks are less likely to occur in the side margin portion, and the ingress of moisture can be prevented.

However, if a large amount of Si is contained in the side margin portion, Si diffuses from the side margin layer side to the dielectric ceramic layer side of the inner layer portion when the portion of the laminate where the internal electrodes face each other with the dielectric ceramic layer interposed therebetween as the inner layer portion. there is a risk of becoming When Si diffuses into the dielectric ceramic layer side of the inner layer portion, grain growth of the ceramic particles of the inner layer portion proceeds, and there is a concern that the quality of the multilayer ceramic capacitor is deteriorated.

Further, in the multilayer ceramic capacitor described in Patent Document 2, a junction portion made of ceramics having an average grain size larger than that of the ceramic layer of the laminate and the ceramics constituting the side margin portion is disposed between the laminate portion and the side margin portion. . As a result, the number of grains in contact with the lamination portion and the side margin portion at both interfaces of the joint portion decreases, that is, the number of grain boundaries likely to become a starting point when cracks or peeling of the stack portion and the side margin portion occur at both interfaces of the joint portion decreases. For this reason, it is said that the favorable bonding state of a lamination|stacking part and a side margin part is maintained through a joint part.

However, in Patent Document 2, it is not recognized about relieving the stress applied to the side margin portion from the outside, and there is room for improvement in that it is difficult to cause cracks or cracks in the multilayer ceramic capacitor.

On the other hand, the above problem is not limited to the multilayer ceramic capacitor, and is a problem common to multilayer ceramic electronic components other than the multilayer ceramic capacitor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in the first aspect, an object of the present invention is to provide a multilayer ceramic electronic component capable of suppressing grain growth of ceramic particles in an inner layer portion while making a side margin portion dense.

In a second aspect, an object of the present invention is to provide a multilayer ceramic electronic component capable of relieving stress applied to a side margin portion from the outside.

In a first aspect, a multilayer ceramic electronic component of the present invention includes a plurality of dielectric ceramic layers and a plurality of pairs of first and second internal electrode layers stacked in a stacking direction, and a first main surface facing in the stacking direction ( a main surface and a second main surface, first and second side surfaces facing each other in a width direction perpendicular to the lamination direction, and a first end surface facing each other in a longitudinal direction orthogonal to the lamination direction and the width direction and a laminate having a second cross-section, a first external electrode provided on the first end surface of the laminate and connected to the first internal electrode layer at the first end surface, and provided on the second end surface of the laminate and a second external electrode connected to the second internal electrode layer at the second end surface. The laminate includes an inner layer portion in which the first inner electrode layer and the second inner electrode layer face each other with the dielectric ceramic layer interposed therebetween, an outer layer portion disposed to sandwich the inner layer portion in the stacking direction, the inner layer portion and the and a side margin portion disposed to sandwich the outer layer portion in the width direction. The side margin portion is composed of a plurality of ceramic layers laminated in the width direction, and the ceramic layer includes an inner layer disposed at the innermost side of the multilayer body, and an inner layer disposed at the outermost side of the multilayer body, wherein the content of the sintering aid element is an outer layer greater than the inner layer; and a buffer layer disposed between the inner layer and the outer layer and having a content of the sintering aid element less than that of the outer layer.

In a second aspect, a multilayer ceramic electronic component of the present invention includes a plurality of dielectric ceramic layers stacked in a stacking direction, and a plurality of pairs of first and second internal electrode layers, a first main surface facing in the stacking direction, and A laminate having a second main surface, first and second side surfaces facing each other in a width direction perpendicular to the lamination direction, and first and second end surfaces facing each other in a longitudinal direction orthogonal to the lamination direction and the width direction a sieve; a first external electrode provided on the first end surface of the laminate and connected to the first internal electrode layer at the first end surface; and a second external electrode connected to the second internal electrode layer. The laminate includes an inner layer portion in which the first inner electrode layer and the second inner electrode layer face each other with the dielectric ceramic layer interposed therebetween, an outer layer portion disposed to sandwich the inner layer portion in the stacking direction, the inner layer portion and the and a side margin portion disposed to sandwich the outer layer portion in the width direction. The side margin part is composed of a plurality of ceramic layers stacked in the width direction, and includes an inner layer disposed at the innermost side of the multilayer body as the ceramic layer, an outer layer disposed at the outermost side of the multilayer body, and the inner layer and a buffer layer disposed between the layer and the outer layer and having a lower elastic modulus than the inner layer and the outer layer.

According to the first aspect of the present invention, it is possible to provide a multilayer ceramic electronic component capable of suppressing grain growth of ceramic particles in the inner layer portion while making the side margin portion dense.

According to the second aspect of the present invention, it is possible to provide a multilayer ceramic electronic component capable of relieving stress applied to the side margin portion from the outside.

1 is a perspective view schematically showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention.
FIG. 2 is a perspective view schematically showing an example of a laminate constituting the multilayer ceramic capacitor shown in FIG. 1 .
FIG. 3 is a cross-sectional view taken along line AA of the multilayer ceramic capacitor shown in FIG. 1 .
FIG. 4 is a cross-sectional view taken along line BB of the multilayer ceramic capacitor shown in FIG. 1 .
5A, 5B and 5C are plan views schematically showing an example of a ceramic green sheet.
It is an exploded perspective view which shows typically an example of a mother block.
7 is a perspective view schematically showing an example of a green chip.

Hereinafter, a multilayer ceramic electronic component of the present invention will be described.

However, the present invention is not limited to the following structures, and can be applied with appropriate modifications within the scope not changing the gist of the present invention. In addition, it is also this invention to combine two or more of each preferable structure described below.

Each embodiment shown below is an illustration, and it cannot be overemphasized that partial substitution or combination of the structure shown by another embodiment is possible. After the second embodiment, descriptions of matters common to the first embodiment will be omitted, and only differences will be described. In particular, the same operation and effect by the same structure are not mentioned sequentially for every embodiment.

As an embodiment of the multilayer ceramic electronic component of the present invention, a multilayer ceramic capacitor will be described as an example. Meanwhile, the present invention can also be applied to multilayer ceramic electronic components other than multilayer ceramic capacitors. Examples of such a multilayer ceramic electronic component include an inductor, a piezoelectric element, and a thermistor.

(First embodiment)

[Multilayer Ceramic Capacitor]

1 is a perspective view schematically showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 2 is a perspective view schematically showing an example of a laminate constituting the multilayer ceramic capacitor shown in FIG. 1 . FIG. 3 is a cross-sectional view taken along line A-A of the multilayer ceramic capacitor shown in FIG. 1 . 4 is a cross-sectional view taken along line B-B of the multilayer ceramic capacitor shown in FIG. 1 .

In the present specification, in the multilayer ceramic capacitor 1 shown in FIG. 1 and the multilayer body 10 shown in FIG. 2, the directions of lamination, width, and length of the multilayer ceramic capacitor and the multilayer body are indicated by arrows T, W, and L, respectively. in the direction determined by Here, the stacking (T) direction, the width (W) direction, and the length (L) direction are orthogonal to each other. The stacking (T) direction is a direction in which a plurality of dielectric ceramic layers 20 and a plurality of pairs of first internal electrode layers 21 and second internal electrode layers 22 are stacked.

The multilayer ceramic capacitor 1 shown in FIG. 1 includes a multilayer body 10 and a first external electrode 51 and a second external electrode 52 provided on both end surfaces of the multilayer body 10 , respectively.

The size of the multilayer ceramic capacitor 1 is, for example, 1.6 mm x 0.8 mm x 0.8 mm, when expressed by the dimension in the length (L) direction x the dimension in the width (W) direction x the dimension in the lamination (T) direction. Sizes, such as 1.0 mm x 0.5 mm x 0.5 mm, 0.6 mm x 0.3 mm x 0.3 mm, 0.4 mm x 0.2 mm x 0.2 mm, 0.2 mm x 0.1 mm x 0.1 mm, are mentioned.

As shown in FIG. 2 , the laminate 10 has a rectangular parallelepiped shape or a substantially rectangular parallelepiped shape, and includes a first main surface 11 and a second main surface 12 facing in the lamination (T) direction, and the lamination (T). The first side 13 and the second side 14 facing each other in the width (W) direction orthogonal to the direction, and the stacking (T) direction and the second side facing in the length (L) direction orthogonal to the width (W) direction It has a first end face 15 and a second end face 16 .

In the present specification, the cut surfaces of the multilayer ceramic capacitor 1 or the multilayer body 10 perpendicular to the first end surface 15 and the second end surface 16 and parallel to the lamination (T) direction are defined in the length (L) direction and the lamination. The cut surface in the (T) direction is called the LT cut surface. In addition, the cross-section of the multilayer ceramic capacitor 1 or the multilayer body 10 perpendicular to the first side surface 13 and the second side surface 14 and parallel to the lamination (T) direction is shown in the width (W) direction and the lamination ( The cut surface in the T) direction is called the WT cut surface. In addition, the multilayer ceramic capacitor 1 or the laminate ( The cut surface of 10) is called the LW cut surface, which is the cut surface in the length (L) direction and the width (W) direction. Accordingly, FIG. 3 is a LT cross-section of the multilayer ceramic capacitor 1 , and FIG. 4 is a WT cross-section of the multilayer ceramic capacitor 1 .

As for the laminated body 10, it is preferable that the corner|angular part and the ridge part are made into a round shape. The corner portion is a portion where three surfaces of the laminate cross each other, and the ridge portion is a portion where two surfaces of the laminate cross each other.

2 , 3 and 4 , the laminate 10 includes a plurality of dielectric ceramic layers 20 stacked in the stacking (T) direction, and a plurality of dielectric ceramic layers formed along the interface between the dielectric ceramic layers 20 . It has a stacked structure including a pair of first internal electrode layers 21 and second internal electrode layers 22 . The dielectric ceramic layer 20 extends along the width (W) direction and the length (L) direction, and each of the first internal electrode layer 21 and the second internal electrode layer 22 is a flat plate along the dielectric ceramic layer 20 . extended in shape.

The first internal electrode layer 21 is drawn out to the first end surface 15 of the laminate 10 . On the other hand, the second internal electrode layer 22 is drawn out to the second end face 16 of the laminate 10 .

The first internal electrode layer 21 and the second internal electrode layer 22 face each other in the stacking (T) direction with the dielectric ceramic layer 20 interposed therebetween. Capacitance is generated in portions where the first internal electrode layer 21 and the second internal electrode layer 22 face each other with the dielectric ceramic layer 20 interposed therebetween.

Each of the first internal electrode layer 21 and the second internal electrode layer 22 preferably includes a metal such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au. Each of the first internal electrode layer 21 and the second internal electrode layer 22 may include the same dielectric ceramic material as that of the dielectric ceramic layer 20 in addition to the above metal.

The thickness of each of the first internal electrode layer 21 and the second internal electrode layer 22 is preferably 0.3 μm or more and 2.0 μm or less.

The first external electrode 51 is provided on the first end surface 15 of the laminate 10 , and in FIG. 1 , the first main surface 11 , the second main surface 12 , the first side surface 13 , and the second It has a part which turned into each part of the side surface 14. The first external electrode 51 is connected to the first internal electrode layer 21 at the first end surface 15 .

The second external electrode 52 is provided on the second end surface 16 of the laminate 10 , and in FIG. 1 , the first main surface 11 , the second main surface 12 , the first side surface 13 , and the second It has a part which turned into each part of the side surface 14. The second external electrode 52 is connected to the second internal electrode layer 22 at the second end face 16 .

Each of the first external electrode 51 and the second external electrode 52 includes, for example, a base electrode layer containing Cu formed by baking, from the end surface side of the laminate 10 , and a surface of the base electrode layer. It has a three-layer structure including a first plating layer formed and a second plating layer formed on a surface of the first plating layer.

3 and 4, in the laminate 10, the first internal electrode layer 21 and the second internal electrode layer 22 face each other with the dielectric ceramic layer 20 interposed therebetween. and the outer layer portions 31 and 32 arranged to sandwich the inner layer portion 30 in the stacking (T) direction, and the inner layer portion 30, the outer layer portion 31 and the outer layer portion 32 in the width (W) direction. It includes side margins 41 and 42 that are arranged to be sandwiched with. In FIGS. 3 and 4 , the inner layer part 30 includes the first inner electrode layer 21 closest to the first main surface 11 and the first inner closest to the second main surface 12 along the stacking (T) direction. It is a region sandwiched by the electrode layer 21 . Although not shown, each of the outer layer part 31 and the outer layer part 32 is preferably composed of a plurality of dielectric ceramic layers 20 stacked in the stacking (T) direction.

The dielectric ceramic layers (20) constituting the inside layer portion 30 is, for _{example, BaTiO 3, CaTiO 3, SrTiO} 3, is composed of a dielectric ceramic material as a main component, such as CaZrO _3. The dielectric ceramic layer 20 constituting the inner layer portion 30 may further contain a sintering aid element, which will be described later.

The thickness of the dielectric ceramic layer 20 constituting the inner layer portion 30 is preferably 0.2 µm or more and 10 µm or less.

The dielectric ceramic layers (20) constituting the outer layer section 31 and outer section 32 is, for _{example, BaTiO 3, CaTiO 3, SrTiO} 3, is composed of a dielectric ceramic material as a main component, such as CaZrO _3. The dielectric ceramic layer 20 constituting the outer layer portion 31 and the outer layer portion 32 may further contain a sintering aid element, which will be described later.

The dielectric ceramic layer 20 constituting the outer layer portion 31 and the outer layer portion 32 is preferably made of the same dielectric ceramic material as the dielectric ceramic layer 20 constituting the inner layer portion 30, but the inner layer portion ( It may be composed of a dielectric ceramic material different from the dielectric ceramic layer 20 constituting 30).

The thickness of each of the outer layer portions 31 and 32 is preferably 15 µm or more and 40 µm or less. In addition, each of the outer layer parts 31 and 32 may have a single-layer structure instead of a multi-layer structure.

Each of the side margin part 41 and the side margin part 42 is composed of a plurality of ceramic layers stacked in the width (W) direction. In FIG. 4 , the side margin part 41 is the ceramic layer, and includes an inner layer 41a disposed at the innermost side of the multilayer body 10 , an outer layer 41b disposed at the outermost side of the multilayer body 10 , and , a three-layer structure including a buffer layer 41c disposed between the inner layer 41a and the outer layer 41b. Similarly, the side margin portion 42 is the ceramic layer, and includes an inner layer 42a disposed on the innermost side of the laminate 10 , an outer layer 42b disposed on the outermost side of the laminate body 10 , It has a three-layer structure including a buffer layer 42c disposed between the inner layer 42a and the outer layer 42b. On the other hand, the side margin portion is not limited to a three-layer structure including an inner layer, an outer layer, and a buffer layer as a ceramic layer, but four or more layers including another ceramic layer between the inner layer and the buffer layer or between the outer layer and the buffer layer. It may be a structure. Further, the number of ceramic layers may be different in the side margin portion on the first side surface side and the side margin portion on the second side surface side of the laminate.

When the side margin portion has a three-layer structure including an inner layer, an outer layer, and a buffer layer, from the difference in sintering properties in the inner layer, the outer layer and the buffer layer, by observing using an optical microscope or an electron microscope, it is a three-layer structure can be checked The same applies to the case where the side margin portion has a structure of four or more layers.

The inner layer (41a) and an inner layer (42a) is, for _{example, BaTiO 3, CaTiO 3, SrTiO} 3, is composed of a dielectric ceramic material as a main component, such as CaZrO _3. The inner layer 41a and the inner layer 42a may further contain a sintering aid element to be described later.

The inner layer 41a and the inner layer 42a are preferably composed of the same dielectric ceramic material as the dielectric ceramic layer 20 constituting the inner layer portion 30, the outer layer portion 31 and the outer layer portion 32, It may be composed of a dielectric ceramic material different from the dielectric ceramic layer 20 constituting the inner layer portion 30 , the outer layer portion 31 , and the outer layer portion 32 .

The outer layer (41b) and outer layer (42b) is, for _{example, BaTiO 3, CaTiO 3, SrTiO} 3, is composed of a dielectric ceramic material as a main component, such as CaZrO _3. The outer layer 41b and the outer layer 42b further contain a sintering aid element, which will be described later. The outer layer 41b and the outer layer 42b are preferably composed of the same dielectric ceramic material as the inner layer 41a and the inner layer 42a, but a dielectric ceramic different from the inner layer 41a and the inner layer 42a. It may consist of a material. The outer layer 41b and the outer layer 42b are preferably composed of the same dielectric ceramic material as the dielectric ceramic layer 20 constituting the inner layer portion 30, the outer layer portion 31 and the outer layer portion 32, It may be composed of a dielectric ceramic material different from the dielectric ceramic layer 20 constituting the inner layer portion 30 , the outer layer portion 31 , and the outer layer portion 32 .

In the multilayer ceramic capacitor 1, the outer layer 41b has a greater content of the sintering aid element than the inner layer 41a. In addition, the outer layer 42b has more content of the sintering aid element than the inner layer 42a.

Accordingly, the sinterability of the outer layer may be increased compared to that of the inner layer. In addition, the hardness of the outer layer may be higher than that of the inner layer. As a result, the outer layer can be made dense.

As a sintering auxiliary element, Si, B, Li, K, Na, Mn, Mg, Ho, Ca, V etc. are mentioned, for example. The number of sintering auxiliary elements may be one, and 2 or more types may be sufficient as them. When there are two or more types of sintering aid elements, it is preferable that the content of at least one of these elements in the outer layer is greater than that in the inner layer. The same applies to the relationship between the content of the sintering aid element in the other ceramic layers.

On the other hand, when the content of the sintering aid element in the outer layer of either side side is greater than the content of the sintering aid element in the inner layer, the content of the sintering aid element in the outer layer of the other side side is the content of the sintering aid element in the inner layer It may be the same as content of a sintering auxiliary|assistant element, and may be less than content of a sintering auxiliary|assistant element in an inner layer.

Regarding the type and content of the sintering aid element contained in each ceramic layer, after exposing the WT cut surface at approximately the center of the length (L) direction of the multilayer ceramic capacitor, elemental analysis by wavelength-dispersive X-ray analysis (WDX) It can be obtained by performing

In the multilayer ceramic capacitor 1, the buffer layer 41c has a smaller content of the sintering aid element than the outer layer 41b. In addition, the buffer layer 42c has less content of a sintering aid element than the outer layer 42b. The buffer layers 41c and 42c do not need to contain a sintering aid element.

By disposing a buffer layer containing a smaller content of the sintering aid element than the outer layer between the inner layer and the outer layer, the sintering aid element contained in the outer layer is fixed in the buffer layer, and diffusion of the sintering aid element to the dielectric ceramic layer side of the inner layer is prevented. can do. As a result, grain growth of ceramic particles in the inner layer portion can be suppressed.

From the viewpoint of preventing diffusion of the sintering aid element to the dielectric ceramic layer side of the inner layer portion, the buffer layer 41c preferably contains a smaller content of the sintering aid element than the inner layer 41a. Moreover, it is preferable that content of a sintering auxiliary agent is less in the buffer layer 42c than the inner layer 42a.

Moreover, it is preferable that the content of each of the buffer layer 41c and the buffer layer 42c of the sintering aid element is smaller than that of the dielectric ceramic layer 20 . The content of the sintering aid element in the dielectric ceramic layer 20 may be the same as or different from the content of the sintering aid element in each of the inner layers 41a and 42a.

A buffer layer (41c) and the buffer (42c), for _{example, BaTiO 3, CaTiO 3, SrTiO} 3, is composed of a dielectric ceramic material as a main component, such as CaZrO _3. The buffer layer 41c and the buffer layer 42c may or may not contain a sintering aid element further.

The buffer layer 41c and the buffer layer 42c are preferably made of the same dielectric ceramic material as the inner layer 41a, the inner layer 42a, the outer layer 41b and the outer layer 42b, but the inner layer 41a , may be composed of a dielectric ceramic material different from the inner layer 42a, the outer layer 41b, and the outer layer 42b. The buffer layer 41c and the buffer layer 42c are preferably made of the same dielectric ceramic material as the dielectric ceramic layer 20 constituting the inner layer portion 30, the outer layer portion 31 and the outer layer portion 32, but the inner layer portion (30), the dielectric ceramic layer 20 constituting the outer layer portion 31 and the outer layer portion 32 may be made of a dielectric ceramic material different from that of the dielectric ceramic material.

On the other hand, when the content of the sintering aid element in the outer layer of either side is the same as the content of the sintering aid element in the inner layer, or is less than the content of the sintering aid element in the inner layer, the side margin on the side The portion need not include a buffer layer. In addition, even if the side margin part on the side side includes a buffer layer, the content of the sintering aid element in the buffer layer on the side side may be the same as the content of the sintering aid element in the outer layer, or the sintering aid element in the outer layer. It may be more than the content.

From the viewpoint of maintaining the shape and performance of the multilayer ceramic capacitor 1, the inner layer 41a is preferably thinner than the outer layer 41b. Likewise, the inner layer 42a is preferably thinner than the outer layer 42b.

The buffer layer 41c may be thicker or thinner than the inner layer 41a. Further, the buffer layer 41c may be thicker or thinner than the outer layer 41b. Similarly, the buffer layer 42c may be thicker or thinner than the inner layer 42a. Further, the buffer layer 42c may be thicker or thinner than the outer layer 42b.

The thickness of each of the inner layers 41a and 42a is preferably 0.1 µm or more and 10 µm or less. The thicknesses of the inner layers 41a and 42a are preferably equal to each other.

The thickness of each of the outer layers 41b and 42b is preferably 5 mu m or more and 20 mu m or less. The thicknesses of the outer layers 41b and 42b are preferably equal to each other.

The thickness of each of the buffer layers 41c and 42c is preferably 0.1 µm or more and 10 µm or less. The thicknesses of the buffer layers 41c and 42c are preferably equal to each other.

It is preferable that they are 5 micrometers or more and 40 micrometers or less, and, as for the thickness of each of the side margin parts 41 and 42, it is more preferable that they are 5 micrometers or more and 20 micrometers or less. The thicknesses of the side margin portions 41 and 42 are preferably equal to each other.

The thickness of each ceramic layer of the side margin part means an average value when the thickness of each ceramic layer of the side margin part is measured at multiple places along the lamination|stacking (T) direction.

Specifically, the WT cut surface is exposed at approximately the center of the multilayer ceramic capacitor in the length (L) direction, and the width (W) end and either side of the first and second internal electrode layers of the WT cut surface are exposed. An image is taken using an optical microscope or an electron microscope so that the margin part enters the same field of view. As imaging locations, in the stacking (T) direction, three locations, the upper part, the central part, and the lower part, are respectively imaged. In the upper part, the central part, and the lower part, a plurality of line segments parallel to the width (W) direction are drawn from the ends in the width (W) direction of the first and second internal electrode layers toward the side surface of the laminate, and the length of each line segment is measured do. For the length of the measured line segment, the average value of each of the upper part, the central part, and the lower part is calculated. By further averaging the respective average values, the thickness of each ceramic layer is obtained.

The composition of the ceramic constituting each ceramic layer of the side margin portion 41 may be different from the composition of the ceramic constituting the dielectric ceramic layer 20 . In this case, the composition of the ceramic constituting at least one of the inner layer 41a and the outer layer 41b may be different from the composition of the ceramic constituting the dielectric ceramic layer 20 .

Similarly, the composition of the ceramic constituting each ceramic layer of the side margin portion 42 may be different from the composition of the ceramic constituting the dielectric ceramic layer 20 . In this case, the composition of the ceramic constituting at least one of the inner layer 42a and the outer layer 42b may be different from the composition of the ceramic constituting the dielectric ceramic layer 20 .

When the side margin portion 41 is composed of three layers of the inner layer 41a, the outer layer 41b, and the buffer layer 41c, the average particle diameter of the ceramic particles constituting the inner layer 41a is the outer layer 41b. It is preferable to be larger than the average particle diameter of the ceramic particles constituting the , the average particle diameter of the ceramic particles constituting the buffer layer 41c, and the average particle diameter of the ceramic particles constituting the dielectric ceramic layer 20 . The average particle diameter of the ceramic particles constituting the outer layer 41b and the average particle diameter of the ceramic particles constituting the dielectric ceramic layer 20 may be the same or different.

Similarly, when the side margin portion 42 is composed of three layers of the inner layer 42a, the outer layer 42b, and the buffer layer 42c, the average particle diameter of the ceramic particles constituting the inner layer 42a is the outer layer ( It is preferable to be larger than the average particle diameter of the ceramic particles constituting 42b), the average particle diameter of the ceramic particles constituting the buffer layer 42c, and the average particle diameter of the ceramic particles constituting the dielectric ceramic layer 20 . The average particle diameter of the ceramic particles constituting the outer layer 42b and the average particle diameter of the ceramic particles constituting the dielectric ceramic layer 20 may be the same or different.

On the other hand, the average particle diameter of the ceramic particles constituting each ceramic layer is determined by selecting some ceramic particles of arbitrary size from an image obtained by imaging the WT cut surface of the multilayer ceramic capacitor at a predetermined magnification with a scanning electron microscope (SEM). The particle diameter was measured and the average value was computed.

Specifically, the WT cut surface is exposed at approximately the center of the multilayer ceramic capacitor in the longitudinal (L) direction, and the dielectric ceramic layer, the inner layer, and the outer layer at approximately the center of the multilayer (T) direction are each 3 at a magnification of 10000 times. Fifteen or more ceramic particles are selected from the images obtained by imaging at various locations. The average particle diameter is obtained by measuring the particle diameter of the selected ceramic particles by image analysis and calculating an average value.

[Manufacturing method of multilayer ceramic capacitor]

The manufacturing method of the multilayer ceramic capacitor according to the first embodiment of the present invention preferably comprises:

It has a stacked structure comprising a plurality of dielectric ceramic layers in an unfired state and a plurality of pairs of first and second internal electrode layers, and has first and second side surfaces facing each other in a width direction perpendicular to the stacking direction. preparing a green chip in which the first internal electrode layer and the second internal electrode layer are exposed;

manufacturing an unbaked laminate by forming unbaked side margin portions on the first side surface and the second side surface of the green chip;

a step of firing the unfired laminate,

In the process of manufacturing the unfired laminate, an unfired inner layer is formed on the first side and the second side surface, an unfired outer layer is formed on the outermost side, and an unfired inner layer is formed between the inner layer and the outer layer. By forming the buffer layer, the unfired side margin portion is formed.

Hereinafter, an example of the manufacturing method of the multilayer ceramic capacitor 1 shown in FIG. 1 is demonstrated.

First, a ceramic green sheet to be the dielectric ceramic layer 20 is prepared. The ceramic green sheet includes a binder and a solvent in addition to the ceramic raw material including the dielectric ceramic material described above. The ceramic green sheet is formed, for example, on a carrier film using a die coater, a gravure coater, a micro gravure coater, or the like.

5A, 5B and 5C are plan views schematically showing an example of a ceramic green sheet.

5A, 5B and 5C, respectively, a first ceramic green sheet 101 for forming the inner layer portion 30, a second ceramic green sheet 102 for forming the inner layer portion 30, and an outer layer portion ( A third ceramic green sheet 103 for forming 31 or 32 is shown.

5A, 5B, and 5C , the first ceramic green sheet 101 , the second ceramic green sheet 102 , and the third ceramic green sheet 103 are not cut for each multilayer ceramic capacitor 1 . 5A, 5B, and 5C show cutting lines X and Y at the time of dividing each multilayer ceramic capacitor 1 . The cutting line X is parallel to the length L direction, and the cutting line Y is parallel to the width W direction.

As shown in FIG. 5A , an unbaked first internal electrode layer 121 corresponding to the first internal electrode layer 21 is formed on the first ceramic green sheet 101 . As shown in FIG. 5B , an unbaked second internal electrode layer 122 corresponding to the second internal electrode layer 22 is formed on the second ceramic green sheet 102 . As shown in FIG. 5C , the unfired internal electrode layer 121 or 122 is not formed on the third ceramic green sheet 103 corresponding to the outer layer part 31 or 32 .

The first internal electrode layer 121 and the second internal electrode layer 122 may be formed using any conductive paste. For the formation of the first internal electrode layer 121 and the second internal electrode layer 122 using the conductive paste, for example, a method such as a screen printing method or a gravure printing method may be used.

The first internal electrode layer 121 and the second internal electrode layer 122 are disposed over two regions adjacent to the length (L) direction partitioned by the cutting line (Y), and have a band shape in the width (W) direction. is extended The first internal electrode layer 121 and the second internal electrode layer 122 are set aside in the length L direction for each row of regions partitioned by the cutting line Y. That is, the cutting line Y passing through the center of the first internal electrode layer 121 passes through the region between the second internal electrode layers 122 and the cutting line Y passing through the center of the second internal electrode layer 122 . ) passes through the region between the first internal electrode layers 121 .

Thereafter, the mother block is manufactured by laminating the first ceramic green sheet 101 , the second ceramic green sheet 102 , and the third ceramic green sheet 103 .

It is an exploded perspective view which shows typically an example of a mother block.

6 , the first ceramic green sheet 101 , the second ceramic green sheet 102 , and the third ceramic green sheet 103 are disassembled and illustrated for convenience of explanation. In the actual mother block 104 , the first ceramic green sheet 101 , the second ceramic green sheet 102 , and the third ceramic green sheet 103 are compressed and integrated by means such as a hydrostatic press.

In the mother block 104 shown in FIG. 6 , the first ceramic green sheet 101 and the second ceramic green sheet 102 corresponding to the inner layer part 30 are alternately laminated in the lamination (T) direction. In addition, on the upper and lower surfaces of the alternately stacked first ceramic green sheets 101 and second ceramic green sheets 102 in the stacking (T) direction, third ceramic green sheets 103 corresponding to the outer layer portions 31 and 32 . ) are stacked. Meanwhile, in FIG. 6 , three third ceramic green sheets 103 are stacked, respectively, and the number of third ceramic green sheets 103 may be appropriately changed.

A plurality of green chips are produced by cutting the obtained mother block 104 along the cutting lines X and Y (see Figs. 5A, 5B and 5C). Methods, such as dicing, pressing, and laser cutting, are applied to this cutting|disconnection, for example.

7 is a perspective view schematically showing an example of a green chip.

The green chip 110 shown in FIG. 7 has a stacked structure including a plurality of dielectric ceramic layers 120 in an unbaked state, and a plurality of pairs of first and second internal electrode layers 121 and 122 . The first side surface 113 and the second side surface 114 of the green chip 110 are surfaces exposed by cutting along the cutting line X, and the first end surface 115 and the second end surface 116 are the cutting lines. The face revealed by the cut along (Y). The first internal electrode layer 121 and the second internal electrode layer 122 are exposed on the first side surface 113 and the second side surface 114 . In addition, only the first internal electrode layer 121 is exposed on the first end surface 115 , and only the second internal electrode layer 122 is exposed on the second end surface 116 .

An unfired laminate is produced by forming unfired side margin portions on the first side surface 113 and the second side surface 114 of the obtained green chip 110 . The unfired side margin portion is formed by, for example, attaching a ceramic green sheet for the side margin portion to the first and second side surfaces of the green chip.

For example, when the side margin portion is composed of three layers of an inner layer, an outer layer, and a buffer layer, first, in order to produce a ceramic green sheet for the inner layer, in addition to a ceramic raw material including a dielectric ceramic material containing _{BaTiO 3 or the like as a main component,} , to prepare a ceramic slurry containing a binder and a solvent. A sintering aid may be added to the ceramic slurry for the inner layer. The inner layer serves to adhere to the green chip 110 .

Next, in order to fabricate the ceramic green sheet for the outer layer, a ceramic slurry including a binder and a solvent in addition to a ceramic raw material including a dielectric ceramic material containing _{BaTiO 3 or the like as a main component is prepared.} A sintering aid is added to the ceramic slurry for the outer layer.

In addition, in order to fabricate the ceramic green sheet for the buffer layer, a ceramic slurry including a binder and a solvent in addition to a ceramic raw material including a dielectric ceramic material containing _{BaTiO 3 as a main component is prepared.} A sintering aid may or may not be added to the ceramic slurry for buffer layers.

Here, the content of the sintering aid in the ceramic slurry for the outer layer is higher than the content of the sintering aid in the ceramic slurry for the inner layer, and the content of the sintering aid in the ceramic slurry for the buffer layer is less than the content of the sintering aid in the ceramic slurry for the outer layer . Moreover, it is preferable to make the content of the sintering aid in the ceramic slurry for buffer layers smaller than the content of the sintering aid in the ceramic slurry for inner layers. On the other hand, it is not necessary to add a sintering aid to the ceramic slurry for buffer layers.

A ceramic green sheet for the outer layer is formed by coating the ceramic slurry for the outer layer on the surface of the resin film and drying it. The ceramic green sheet for the buffer layer is formed by coating and drying the ceramic slurry for the buffer layer on the surface of the ceramic green sheet for the outer layer on the resin film. The ceramic green sheet for the inner layer is formed by coating and drying the ceramic slurry for the inner layer on the surface of the ceramic green sheet for the buffer layer. As a result, a ceramic green sheet for side margin portions having a three-layer structure is obtained.

On the other hand, the ceramic green sheet for the side margin portion having a three-layer structure can be obtained by, for example, forming each of a ceramic green sheet for an outer layer, a ceramic green sheet for a buffer layer, and a ceramic green sheet for an inner layer in advance, and then bonding them together. is obtained In addition, the ceramic green sheet for side margin parts is not limited to three layers, Multiple layers of four or more layers may be sufficient.

Thereafter, the ceramic green sheet for side margin portions is peeled from the resin film.

Next, the unfired side margin portion 41 is formed by facing the ceramic green sheet for the inner layer of the ceramic green sheet for the side margin portion and the first side surface 113 of the green chip 110 and pressing and punching. Furthermore, the unfired side margin portion 42 is formed by pressing and punching the ceramic green sheet for the inner layer of the ceramic green sheet for the side margin portion with respect to the second side surface 114 of the green chip 110 . At this time, it is preferable to apply an organic solvent to be an adhesive on the side surface of the green chip in advance.

The green chips 110 on which the unfired side margins 41 and 42 are formed are, for example, degreased under a predetermined condition in a nitrogen atmosphere, and then fired at a predetermined temperature in a nitrogen-hydrogen-water vapor mixed atmosphere. Thereby, the sintered laminated body 10 (refer FIG. 2) is obtained.

An external electrode paste containing Cu as a main component is coated and baked on each of the first end face 15 and the second end face 16 of the obtained laminate 10, and the base electrode layer connected to the first internal electrode layer 21; , a base electrode layer connected to the second internal electrode layer 22 is formed. Furthermore, a first plating layer by Ni plating is formed on the surface of each base electrode layer, and a second plating layer by Sn plating is formed on the surface of the first plating layer. Accordingly, the first external electrode 51 and the second external electrode 52 are formed.

As described above, the multilayer ceramic capacitor 1 shown in FIG. 1 is manufactured.

In addition, the unfired side margin part may be formed by sticking ceramic green sheets for side margin parts on both sides of a green chip, and may be formed by apply|coating ceramic slurry for side margin parts.

When the unfired side margin portion is formed by applying the ceramic slurry for the side margin portion, the ceramic slurry for the inner layer is respectively applied to both sides of the green chip and dried. Furthermore, after the ceramic slurry for the buffer layer is applied to the surface of the inner layer and dried, the ceramic slurry for the outer layer is applied to the surface of the buffer layer.

In addition, after masking both end surfaces of the green chip with resin, the side margin part is dipping and drying the whole green chip in the ceramic slurry for the inner layer, and furthermore, after dipping and drying in the ceramic slurry for the buffer layer, You may form by dipping in a ceramic slurry. In this case, the inner layer, the buffer layer, and the outer layer are also formed on the outer layer portion to form a four-layer structure.

(Second embodiment)

[Multilayer Ceramic Capacitor]

In the multilayer ceramic capacitor according to the second embodiment of the present invention, unlike the multilayer ceramic capacitor according to the first embodiment of the present invention, the side margin portion is composed of a plurality of ceramic layers laminated in the width direction, and the ceramic layer is An inner layer disposed on the innermost side of the sieve, an outer layer disposed on the outermost side of the laminate, and a buffer layer disposed between the inner layer and the outer layer and having a lower elastic modulus than the inner layer and the outer layer.

1 to 4 are diagrams schematically showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. Except for the following points, the multilayer ceramic capacitor 1 shown in Fig. 1 has a configuration common to that of the first embodiment of the present invention.

The inner layer (41a) and an inner layer (42a) is, for _{example, BaTiO 3, CaTiO 3, SrTiO} 3, is composed of a dielectric ceramic material as a main component, such as CaZrO _3. The inner layer 41a and the inner layer 42a may further contain a sintering aid element to be described later.

The inner layer 41a and the inner layer 42a are preferably composed of the same dielectric ceramic material as the dielectric ceramic layer 20 constituting the inner layer portion 30, the outer layer portion 31 and the outer layer portion 32, It may be composed of a dielectric ceramic material different from the dielectric ceramic layer 20 constituting the inner layer portion 30 , the outer layer portion 31 , and the outer layer portion 32 .

The outer layer (41b) and outer layer (42b) is, for _{example, BaTiO 3, CaTiO 3, SrTiO} 3, is composed of a dielectric ceramic material as a main component, such as CaZrO _3. It is preferable that the outer layer 41b and the outer layer 42b further contain a sintering aid element, which will be described later.

The outer layer 41b and the outer layer 42b are preferably composed of the same dielectric ceramic material as the inner layer 41a and the inner layer 42a, but a dielectric ceramic different from the inner layer 41a and the inner layer 42a. It may consist of a material. The outer layer 41b and the outer layer 42b are preferably composed of the same dielectric ceramic material as the dielectric ceramic layer 20 constituting the inner layer portion 30, the outer layer portion 31 and the outer layer portion 32, It may be composed of a dielectric ceramic material different from the dielectric ceramic layer 20 constituting the inner layer portion 30 , the outer layer portion 31 , and the outer layer portion 32 .

In the multilayer ceramic capacitor 1, the buffer layer 41c has a lower elastic modulus than the inner layer 41a and the outer layer 41b. In addition, the buffer layer 42c has a lower elastic modulus than the inner layer 42a and the outer layer 42b.

By disposing a buffer layer having a lower elastic modulus than the inner layer and the outer layer between the inner layer and the outer layer, the stress applied to the side margin portion from the outside can be relieved by the buffer layer. As a result, cracks or cracks in the multilayer ceramic capacitor are less likely to occur.

In the present specification, the elastic modulus means a Young's modulus (longitudinal elastic modulus).

On the other hand, when the elastic modulus in the buffer layer on either side side is lower than that of the inner layer and the outer layer, the side margin portion on the other side side does not need to include the buffer layer. In addition, even when the side margin part on the other side side contains a buffer layer, the elastic modulus in the said side buffer layer may be the same as an inner layer and an outer layer, and may be higher than an inner layer and an outer layer.

The buffer layer 41c and the buffer layer 42c are preferably made of a dielectric ceramic material different from the inner layer 41a, the inner layer 42a, the outer layer 41b and the outer layer 42b. The buffer layer 41c and the buffer layer 42c are made of, for example, a flexible ceramic material having two or more types of ceramic components having different coefficients of thermal expansion. The buffer layer 41c and the buffer layer 42c may or may not contain the sintering aid element mentioned later further.

Specifically, the buffer layer 41c and the buffer layer 42c have a ^{low thermal expansion ceramic component having a thermal expansion coefficient of 2×10 -6} /°C or less, and a high heat having a thermal expansion coefficient of 5×10 ^-6 /°C or more higher than that of the low thermal expansion ceramic component. It is preferably composed of a flexible ceramic material having an expandable ceramic component.

As described in Japanese Patent Application Laid-Open No. 4381760, the flexible ceramic material includes ceramic particles having an average particle diameter of one component of 100 μm or more and 500 μm or less and the other component having an average particle diameter of 10 μm or less. After mixing, it is obtained by shaping|molding and baking. A ceramic material having flexibility is obtained because cracks as three-dimensionally continuous open pores occur due to the difference in the coefficient of thermal expansion between the particles at the grain boundary. It is preferable that the flexible ceramic material obtained in this way has 5 vol% or more and 20 vol% or less of the above-mentioned cracks.

The combination of the ceramic components to be composited is: (1) ceramic particles having an average particle diameter of 100 μm or more and 500 μm or less of the low thermal expansion ceramic component and the high thermal expansion ceramic component as the grain boundary phase having an average particle diameter of 10 μm Combination of ceramic particles having an average particle size of about 100 μm or more and less than or equal to 500 μm, or (2) ceramic particles having an average particle diameter of about 100 μm or more and 500 μm or less, and a ceramic having an average particle diameter of about 10 μm or less of the low thermal expansion ceramic component as a grain boundary phase It is a combination of particles. In addition, an average particle diameter is a number average particle diameter. The lower limit of the ceramic particles having the smaller average particle size is not particularly limited, but there is no particular problem even if it is about 0.1 µm.

In the flexible ceramic material, ceramic particles having a small average particle diameter are filled in gaps filled with ceramic particles having a large average particle diameter. Usually, when ceramic particles are filled, the volume fraction is about 50 vol% or more and 60 vol% or less, and the remaining 40 vol% or more and 50 vol% or less becomes the gap. Since ceramic particles with a small average particle size fill the gap, the proportion of ceramic particles with a small average particle diameter to that of a large average particle diameter is not more than about 50% by volume, the entirety is not dense and the holes are not cracks. this remains

On the other hand, the occurrence of cracks is related to the difference between the average particle diameter and the coefficient of thermal expansion, and as the average particle diameter increases, cracks occur even if the difference in the coefficient of thermal expansion is small. If the difference between the coefficients of thermal expansion between the two is 5×10 ^-6 /℃ or more and 10×10 ^-6 /℃ or less, the average particle diameter of one ceramic particle is 100 μm or more and 500 μm or less, and the average particle diameter of the other ceramic particle is If it is 10 micrometers or less, a crack will generate|occur|produce.

In particular, the flexible ceramic material preferably has a ^{low thermal expansion ceramic component having a thermal expansion coefficient of 2×10 -6} /°C or less and a high thermal expansion ceramic component having a thermal expansion coefficient of 20×10 ^-6 /°C or more. By using these low thermal expansion ceramic components and high thermal expansion ceramic components, it becomes easy to generate|occur|produce a crack at a grain boundary.

Examples of the low thermal expansion ceramic component include potassium zirconium phosphate (KZr ₂ (PO ₄ ) ₃ ) having a ^{thermal expansion coefficient of -0.4×10 -6 /°C.} Further, examples of the high thermal expansibility ceramic component include leucite (KAlSi ₂ O ₆ ) having a ^{thermal expansion coefficient of 25×10 −6 /°C.}

As the composite ceramic particles, it is preferable to select those in which two types of components do not react during the firing process. The ceramic particles having an average particle diameter of 100 μm or more and 500 μm or less are preferably obtained by sintering single-phase particles having an average particle diameter of less than 100 μm. After preparing large secondary particles having an average particle diameter of 100 μm or more and 500 μm or less, mixing with the other component, ceramic particles having a small average particle diameter, and then sintering only the small ceramic particles to solidify the whole , it is possible to prevent the reaction of two types of components in the firing process.

After sintering using this combination of ceramic components and cooling, three-dimensional cracks are generated at the grain boundaries of the sintered body. Regarding the occurrence of microcracks, at the interface of two components, the stress is determined by (difference in thermal expansion coefficient) × (particle size) × (final temperature difference between the firing temperature and the temperature after cooling (usually room temperature)). Speed doesn't really matter.

Regarding the porosity, it is preferable that the porosity is about 5% by volume or more and 20% by volume or less, which is about the same level as natural and flexible konjac stone (ital columite). The porosity is the open porosity measured by the Archimedes method using the weight of the sample, the external volume, and the like.

It is preferable that the outer layer 41b has more content of a sintering auxiliary agent than the inner layer 41a. Moreover, it is preferable that the content of the sintering aid element in the outer layer 42b is larger than that of the inner layer 42a.

In this case, the sinterability of the outer layer can be increased compared to that of the inner layer. In addition, the hardness of the outer layer may be higher than that of the inner layer. As a result, the outer layer can be made dense.

As a sintering auxiliary element, Si, B, Li, K, Na, Mn, Mg, Ho, Ca, V etc. are mentioned, for example. The number of sintering auxiliary elements may be one, and 2 or more types may be sufficient as them. When there are two or more types of sintering aid elements, it is preferable that the content of at least one of these elements in the outer layer is greater than that in the inner layer. The same applies to the relationship between the content of the sintering aid element in the other ceramic layers.

On the other hand, when the content of the sintering aid element in the outer layer of either side side is greater than the content of the sintering aid element in the inner layer, the content of the sintering aid element in the outer layer of the other side side is the content of the sintering aid element in the inner layer The content of the sintering aid element may be the same as that of the sintering aid element, or it may be less than the content of the sintering aid element in the inner layer.

From the viewpoint of maintaining the shape and performance of the multilayer ceramic capacitor 1, the inner layer 41a is preferably thinner than the outer layer 41b. Likewise, the inner layer 42a is preferably thinner than the outer layer 42b.

The buffer layer 41c may be thicker or thinner than the inner layer 41a. Further, the buffer layer 41c may be thicker or thinner than the outer layer 41b. Similarly, the buffer layer 42c may be thicker or thinner than the inner layer 42a. Further, the buffer layer 42c may be thicker or thinner than the outer layer 42b.

The thickness of each of the inner layers 41a and 42a is preferably 0.1 µm or more and 10 µm or less. The thicknesses of the inner layers 41a and 42a are preferably equal to each other.

The thickness of each of the outer layers 41b and 42b is preferably 5 mu m or more and 20 mu m or less. The thicknesses of the outer layers 41b and 42b are preferably equal to each other.

The thickness of each of the buffer layers 41c and 42c is preferably 0.1 µm or more and 10 µm or less. The thicknesses of the buffer layers 41c and 42c are preferably equal to each other.

It is preferable that they are 5 micrometers or more and 40 micrometers or less, and, as for the thickness of each of the side margin parts 41 and 42, it is more preferable that they are 5 micrometers or more and 20 micrometers or less. The thicknesses of the side margin portions 41 and 42 are preferably equal to each other.

The composition of the ceramic constituting each ceramic layer of the side margin portion 41 may be different from the composition of the ceramic constituting the dielectric ceramic layer 20 . In this case, the composition of the ceramic constituting at least one of the inner layer 41a and the outer layer 41b may be different from the composition of the ceramic constituting the dielectric ceramic layer 20 .

Similarly, the composition of the ceramic constituting each ceramic layer of the side margin portion 42 may be different from the composition of the ceramic constituting the dielectric ceramic layer 20 . In this case, the composition of the ceramic constituting at least one of the inner layer 42a and the outer layer 42b may be different from the composition of the ceramic constituting the dielectric ceramic layer 20 .

When the side margin portion 41 is composed of three layers of the inner layer 41a, the outer layer 41b, and the buffer layer 41c, the average particle diameter of the ceramic particles constituting the inner layer 41a is the outer layer 41b. It is preferable to be larger than the average particle diameter of the ceramic particles constituting the , the average particle diameter of the ceramic particles constituting the buffer layer 41c, and the average particle diameter of the ceramic particles constituting the dielectric ceramic layer 20 . The average particle diameter of the ceramic particles constituting the outer layer 41b and the average particle diameter of the ceramic particles constituting the dielectric ceramic layer 20 may be the same or different.

Similarly, when the side margin portion 42 is composed of three layers of the inner layer 42a, the outer layer 42b, and the buffer layer 42c, the average particle diameter of the ceramic particles constituting the inner layer 42a is the outer layer ( It is preferable to be larger than the average particle diameter of the ceramic particles constituting 42b), the average particle diameter of the ceramic particles constituting the buffer layer 42c, and the average particle diameter of the ceramic particles constituting the dielectric ceramic layer 20 . The average particle diameter of the ceramic particles constituting the outer layer 42b and the average particle diameter of the ceramic particles constituting the dielectric ceramic layer 20 may be the same or different.

[Manufacturing method of multilayer ceramic capacitor]

The method for manufacturing a multilayer ceramic capacitor according to the second embodiment of the present invention preferably comprises:

It has a stacked structure comprising a plurality of dielectric ceramic layers in an unbaked state and a plurality of pairs of first and second internal electrode layers, and the first and second surfaces are disposed on first and second sides facing each other in a width direction orthogonal to the stacking direction. 1 A step of preparing a green chip in which the internal electrode layer and the second internal electrode layer are exposed;

manufacturing an unbaked laminate by forming unbaked side margin portions on the first side surface and the second side surface of the green chip;

a step of firing the unfired laminate,

In the process of manufacturing the unfired laminate, an unfired inner layer is formed on the first side and the second side surface, an unfired outer layer is formed on the outermost side, and an unfired inner layer is formed between the inner layer and the outer layer. By forming the buffer layer, the unfired side margin portion is formed.

In the second embodiment of the present invention, unlike the first embodiment of the present invention, in order to manufacture the ceramic green sheet for the buffer layer, in addition to the ceramic raw material containing the above-described low thermal expansion ceramic component and high thermal expansion ceramic component, a binder, a solvent, etc. To prepare a ceramic slurry containing A sintering aid may be added to the ceramic slurry for buffer layers.

Except for the above points, the multilayer ceramic capacitor according to the second embodiment of the present invention can be manufactured by the same method as in the first embodiment of the present invention.

The present invention is not limited to the above embodiments, and various applications and modifications can be made within the scope of the present invention with respect to the configuration and manufacturing conditions of multilayer ceramic electronic components including multilayer ceramic capacitors.

In the embodiment described above, the mother block 104 is cut along the cutting lines X and Y to obtain a plurality of green chips, and then unfired side margin portions are formed on both sides of the green chips. do.

That is, by cutting the mother block along only the cutting line (X), a plurality of rod-shaped green blocks in which the first internal electrode layer and the second internal electrode layer are exposed on the side exposed by the cutting along the cutting line (X) are obtained. Then, unbaked side margins are formed on both sides of the green block body, and then cut along the cutting line Y to obtain a plurality of unbaked laminates, and then the unbaked laminates may be fired. After firing, a multilayer ceramic electronic component such as a multilayer ceramic capacitor can be manufactured by performing the same steps as in the above-described embodiment.

1: multilayer ceramic capacitor 10: laminated body
11: 1st main surface of laminated body 12: 2nd main surface of laminated body
13: first side of laminate 14: second side of laminate
15: first cross-section of laminate 16: second cross-section of laminate
20: dielectric ceramic layer 21: first internal electrode layer
22: second inner electrode layer 30: inner layer portion
31, 32: outer layer part 41, 42: side margin part
41a, 42a: inner layer 41b, 42b: outer layer
41c, 42c: buffer layer 51: first external electrode
52: second external electrode 101: first ceramic green sheet
102: second ceramic green sheet 103: third ceramic green sheet
104: mother block 110: green chip
113: the first side of the green chip 114: the second side of the green chip
115: first cross-section of the green chip 116: second cross-section of the green chip
120: unfired dielectric ceramic layer 121: unfired first internal electrode layer
122: unfired second internal electrode layer X, Y: cutting line

Claims (8)

A plurality of dielectric ceramic layers and a plurality of pairs of first and second internal electrode layers stacked in a stacking direction, the first and second main surfaces facing each other in the stacking direction, and a plurality of first and second major surfaces facing in the stacking direction; A laminate having first and second side surfaces facing each other in a width direction orthogonal to each other, and a first end surface and a second end surface facing each other in a longitudinal direction orthogonal to the lamination direction and the width direction;
a first external electrode provided on the first end face of the laminate and connected to the first internal electrode layer at the first end face;
A multilayer ceramic electronic component including a second external electrode provided on the second end surface of the laminate and connected to the second internal electrode layer on the second end surface,
The laminate includes an inner layer portion in which the first inner electrode layer and the second inner electrode layer face each other with the dielectric ceramic layer interposed therebetween, an outer layer portion disposed to sandwich the inner layer portion in the stacking direction, the inner layer portion and the It includes a side margin portion arranged to sandwich the outer layer portion in the width direction,
The side margin portion is composed of a plurality of ceramic layers laminated in the width direction, and the ceramic layer includes an inner layer disposed at the innermost side of the multilayer body, and an inner layer disposed at the outermost side of the multilayer body, wherein the content of the sintering aid element is A multilayer ceramic electronic component comprising: an outer layer greater than the inner layer; and a buffer layer disposed between the inner layer and the outer layer and having a content of the sintering aid element less than that of the outer layer. According to claim 1,
The said buffer layer has less content of the said sintering aid element than the said inner layer, The multilayer ceramic electronic component. A plurality of dielectric ceramic layers and a plurality of pairs of first and second internal electrode layers stacked in a stacking direction, the first and second main surfaces facing each other in the stacking direction, and a plurality of first and second major surfaces facing in the stacking direction; A laminate having first and second side surfaces facing each other in a width direction orthogonal to each other, and a first end surface and a second end surface facing each other in a longitudinal direction orthogonal to the lamination direction and the width direction;
a first external electrode provided on the first end face of the laminate and connected to the first internal electrode layer at the first end face;
A multilayer ceramic electronic component including a second external electrode provided on the second end surface of the laminate and connected to the second internal electrode layer on the second end surface,
The laminate includes an inner layer portion in which the first inner electrode layer and the second inner electrode layer face each other with the dielectric ceramic layer interposed therebetween, an outer layer portion disposed to sandwich the inner layer portion in the stacking direction, the inner layer portion and the It includes a side margin portion arranged to sandwich the outer layer portion in the width direction,
The side margin part is composed of a plurality of ceramic layers stacked in the width direction, and includes an inner layer disposed at the innermost side of the multilayer body as the ceramic layer, an outer layer disposed at the outermost side of the multilayer body, and the inner layer A multilayer ceramic electronic component comprising: a buffer layer disposed between a layer and the outer layer and having a lower elastic modulus than that of the inner layer and the outer layer. 4. The method of claim 3,
The buffer layer is flexible having a low thermal expansion ceramic component having a thermal expansion coefficient of 2×10 ^-6 /°C or less, and a high thermal expansion ceramic component having a thermal expansion coefficient of 5×10 ^-6 /°C or more larger than that of the low thermal expansion ceramic component. ) A multilayer ceramic electronic component composed of a ceramic material. 5. The method of claim 3 or 4,
The said outer layer has more content of a sintering auxiliary agent than the said inner layer, The multilayer ceramic electronic component. 5. The method according to any one of claims 1 to 4,
and the inner layer is thinner than the outer layer. 5. The method according to any one of claims 1 to 4,
A composition of a ceramic constituting each ceramic layer of the side margin portion is different from a composition of a ceramic constituting the dielectric ceramic layer. 5. The method according to any one of claims 1 to 4,
The side margin portion is composed of three layers of the inner layer, the outer layer and the buffer layer,
and an average particle diameter of ceramic particles constituting the inner layer is larger than an average particle diameter of ceramic particles constituting the outer layer and an average particle diameter of ceramic particles constituting the dielectric ceramic layer.

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