KR102304423B1 - Cyclic analog-to-digital converter using ternary device and ternary encoder included in the same - Google Patents

Abstract

According to an embodiment of the present invention, a cyclic analog-to-digital converter includes: an input terminal to which a first analog signal is applied; an analog-to-ternary converter (ATC) which ternary-converts the first analog signal to output ternary data; a first capacitor to which the ternary data is applied; and an output terminal for outputting a third analog signal calculated based on the first analog signal and the ternary data. The ternary data is a signal corresponding to a second analog signal which is analogized by matching an output voltage of the ATC. Accordingly, it is possible to improve the accuracy of data conversion by adjusting a size of a semiconductor element in an inverter.

Description

Cyclic analog-to-digital converter using ternary element and ternary encoder included therein

The present invention relates to a cyclic analog-to-digital converter using a ternary element and a ternary encoder included therein.

BACKGROUND ART Electronic devices such as smart phones, laptops, and tablet PCs have been miniaturized and improved in performance as various functions are added. Accordingly, power consumption and the size of a sensor are emerging as important factors in electronic devices. Accordingly, the need for reducing the size and power consumption of an analog-to-digital converter, which is a major element of a sensor, is increasing.

Cyclic Analog-to-Digital Converter (Cyclic ADC), which is a type of analog-to-digital converter, consumes large power because it includes an analog amplifier, a comparator, and a reference voltage generating circuit, and has limitations in miniaturization. have.

An object of the present invention is to provide a cyclic analog-to-digital converter capable of minimizing the size and reducing power consumption by mutually converting between analog data and digital data using a ternary element.

Another object of the present invention is to provide a ternary encoder with improved data conversion accuracy by adjusting the size of a semiconductor element in the inverter.

A cyclic analog to digital converter (ADC) according to an embodiment of the present invention includes an input terminal to which a first analog signal is applied; an analog-to-ternary converter (ATC) that ternary-converts the first analog signal to output ternary data; a first capacitor to which the ternary data is applied; and an output terminal for outputting a third analog signal calculated based on the first analog signal and the ternary data, wherein the ternary data is matched to the output voltage of the ATC and converted to an analog second analog signal. corresponding signal.

The ATC may include a first ternary inverter and a second ternary inverter connected to each other in series, and the first ternary inverter may ternarily convert the first analog signal to output first ternary data.

The second ternary inverter outputs second ternary data by inverting the first ternary data, and matches the second ternary data to an analog voltage corresponding to each of the second ternary data. A second analog signal may be output.

The first capacitor obtains a residual voltage by subtracting the second analog signal from the first analog signal, one end of the first capacitor is connected to the input terminal, and the other end of the first capacitor is connected to an amplifier connected, the amplifier may output the third analog signal by double amplifying the residual voltage.

The ADC further includes a ternary encoder that converts the second analog signal generated by the ATC into binary data, and converts the binary data to analog using the ternary encoder to obtain a fourth analog voltage can be printed out.

A path switch may be disposed between the output terminal and the input terminal, and when the path switch is turned on, the third analog signal may be re-applied to the input terminal.

A ternary encoder according to an embodiment of the present invention includes an input terminal receiving ternary data; a conversion unit including a first inverter and a second inverter respectively connected to the input terminal, and converting the ternary data into binary data; and an output terminal for outputting an analog signal in which the binary data is analog-converted.

A first threshold voltage of the first inverter has a value lower than a reference threshold voltage, the first threshold voltage is a voltage that determines binary data output by the first inverter, and a second boundary voltage of the second inverter The voltage may have a higher value than the reference threshold voltage, and the second threshold voltage may be a voltage that determines binary data output by the second inverter.

The converter may include: a third inverter connected in series with the first inverter and re-inverting the ternary data output by the first inverter; and a fourth inverter connected in series with the second inverter and re-inverting the ternary data output by the second inverter.

The cyclic analog-to-digital converter according to embodiments of the present invention can minimize the size and reduce power consumption by converting between analog data and digital data using a ternary element.

In addition, the ternary encoder according to embodiments of the present invention may improve the accuracy of data conversion by adjusting the size of the semiconductor element in the inverter.

1 is a circuit diagram showing the structure of an analog-to-digital converter according to an embodiment of the present invention.
2 is a graph illustrating input/output characteristics of a ternary element included in an analog ternary converter according to an embodiment of the present invention.
3 is a graph illustrating input/output characteristics of an analog ternary converter according to an embodiment of the present invention.
4 is a circuit diagram illustrating an operation mode of an analog-to-digital converter according to an embodiment of the present invention.
5 is a circuit diagram for explaining another operation mode of the analog-to-digital converter according to an embodiment of the present invention.
6 is a circuit diagram showing the structure of an analog-to-digital converter according to another embodiment of the present invention.
7 is a structural diagram schematically illustrating the configuration of a ternary encoder according to an embodiment of the present invention.
8 is a graph illustrating input/output characteristics of an inverter according to an embodiment of the present invention.
9 is a graph illustrating input/output characteristics of a ternary encoder according to an embodiment of the present invention.

Since the present invention can apply various transformations and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail in the detailed description. Effects and features of the present invention, and a method of achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, and when described with reference to the drawings, the same or corresponding components are given the same reference numerals, and the overlapping description thereof will be omitted. .

In the following embodiments, terms such as first, second, etc. are used for the purpose of distinguishing one component from another, not in a limiting sense. In the following examples, the singular expression includes the plural expression unless the context clearly dictates otherwise. In the following embodiments, terms such as include or have means that the features or components described in the specification are present, and the possibility of adding one or more other features or components is not excluded in advance. In the drawings, the size of the components may be exaggerated or reduced for convenience of description. For example, since the size and shape of each configuration shown in the drawings are arbitrarily indicated for convenience of description, the present invention is not necessarily limited to the illustrated bar.

1 is a circuit diagram showing the structure of an analog-to-digital converter (hereinafter referred to as 'ADC') according to an embodiment of the present invention, and FIG. 2 is an analog ternary according to an embodiment of the present invention. It is a graph showing the input/output characteristics of the ternary element included in the converter.

ADC 1000 has an input terminal I, ATC (Analog to Ternary Converter; hereinafter referred to as 'ATC') 100, a first capacitor C1, a second capacitor C2, a first switch pair ( S1), the second switch pair (S2), the amplifier 300, and may include an output terminal (Y).

The ADC 1000 may receive the first analog signal Va1 through the input terminal I when the input switch S0 is turned on. The input terminal I may be connected to the first terminal A1 of the ATC 100 .

The ATC 100 converts the first analog signal Va1 into a ternary signal by using the ternary inverters 110 and 120 (hereinafter, it may be briefly described as 'ternary conversion'). to output the ternary data, and the ATC 100 may finally output the second analog signal Va2 by matching the ternary data to an analog signal corresponding to each ternary data. The operation of the ATC 100 will be described in more detail with reference to FIG. 3 to be described later. The ATC 100 may include a first ternary inverter 110 and a second ternary inverter 120 .

The input/output characteristics of the ternary inverters 110 and 120 will be described with reference to FIG. 2 together. The first ternary inverter 110 and the second ternary inverter 120 may include a ternary element capable of processing ternary data.

Referring to FIG. 2 , input/output profiles G1 and G2 of two cases of a semiconductor device are shown. In the case of a binary device, like the first profile G1, it shows input/output characteristics of writing and reading binary data of 0 or 1. On the other hand, the ternary device according to an embodiment of the present invention exhibits input/output characteristics of writing and reading ternary data of 0 (P1), 1/2 (P2), and 1 (P3) like the second profile G2. can Hereinafter, 'ternary data' may be understood as a concept including data of three states labeled 0, 1/2, and 1.

In the case of the ternary inverters 110 and 120, the ternary data (or trit data) can be stored/processed, so it has a storage space 1.5 times larger than that of a binary device of the same size and has the advantage of miniaturization. . Hereinafter, the ternary data of 0, 1/2, and 1 may be described as ternary data of 0, 1, and 2 for convenience of description. When a voltage for driving the ADC 1000 according to an embodiment of the present invention is referred to as a driving voltage VDD, each of the ternary data labeled 0, 1/2, and 1 is 0 and a half driving voltage in that order. (VDD/2) may correspond to data having a driving voltage VDD.

Referring back to FIG. 1 , the first ternary inverter 110 may ternarily convert the first analog signal Va1 applied through the input terminal I to output the first ternary data Vt1 . The input/output characteristics of the first ternary inverter 110 will be described in more detail with reference to FIG. 3 to be described later.

The second ternary inverter 120 may be connected in series with the first ternary inverter 110 . The second ternary inverter 120 may output the second ternary data Vt2 to the second terminal A2 of the ATC 100 by inverting the first ternary data Vt1 . The second ternary inverter 120 inverts the ternary-converted first ternary data Vt1 again, so that the voltage magnitude trend of the signal output by the ATC 100 is the initial input signal, the first analog signal It can be made to correspond to (Va1). For example, when the first analog signal Va1 is converted from '0' to '1' during ternary conversion through the first ternary inverter 110, the second ternary inverter 120 returns '1' again. It may be inverted to '0' to correspond to the first analog signal Va1.

The second ternary data Vt2 by the ATC 100 may be data of '0, 1, 2' as treatment data, but from the viewpoint of an analog signal, data of '0, 1, 2' It may correspond to 0, VDD/2, VDD'. The second ternary inverter 120 may operate each of the generated second ternary data Vt2 of '0, 1, 2' as an analog signal of '0, VDD/2, VDD'. As such, the ATC 100 may have the same function as a 1.5-bit analog-to-digital converter by outputting three 2-bit digital signals.

The first capacitor C1 may obtain the residual voltage Vres by calculating a difference between the first analog signal Va1 and the second analog signal Va2 output by the ATC 100 . One end A3 of the first capacitor C1 is connected to the input terminal I of the ADC 1000, and the other end A4 of the first capacitor C1 is connected to the switches S1-1 and S2-2. It can be connected to each end. A first analog signal Va1 or a second analog signal Va2 may be stored at one end A3 of the first capacitor C1, and the other end A4 is provided with a first through negative feedback. When the -1 switch S1-1 or the 2-2 switch S2-2 is connected, the reference voltage Vcm may be fixed. The reference voltage Vcm is a voltage connected to the positive input terminal of the amplifier 300 and may be determined in consideration of the operating region of the amplifier 300 and the maximum magnitude of the input signal of the ADC 1000 . For example, the reference voltage Vcm may be a half driving voltage VDD/2.

An operation relationship between both ends A3 and A4 of the first capacitor C1 and the switches will be described in more detail with reference to FIGS. 4 and 5 to be described later.

Thereafter, the residual voltage Vres may be transferred to the amplifier 300 by the operation of the switches S1-1 and S2-2.

The first switch pair S1 may include a 1-1 switch S1-1 and a 1-2 switch S1-2 (hereinafter, may be referred to as a 'path switch'). The first clock signal CLK1 having the same timing may be applied through the first switch pair S1 . The second switch pair S2 may include a 2-1 th switch S2-1 and a 2-2 th switch S2-2. A second clock signal CLK2 having the same timing may be applied through the second switch pair S2 , and the second clock signal CLK2 may be a signal having a timing different from that of the above-described first clock signal CLK1 . The operation of each switch pair S1 and S2 will be described in more detail with reference to FIGS. 4 and 5 to be described later.

The amplifier 300 may output a third analog signal Va3 calculated based on the first analog signal and the second analog signal. Specifically, the amplifier 300 may amplify the residual voltage Vres and output the third analog signal Va3 through the output terminal Y, which may be referred to as one 'cycle' of the ADC 1000 . One end of the amplifier 300 may be connected to the other end of each of the switches S1-1 and S2-2, and the other end of the amplifier 300 may be connected to the output terminal Y. At this time, according to the cyclic ADC 1000 according to an embodiment of the present invention, the third analog signal Va3 may be re-applied to the input terminal I again. Here, one end of the 1-2 switch (S1-2) is connected to the output terminal (Y) and the other terminal to the input terminal (I), so as to apply the output signal of the previous cycle as the input signal of the next cycle. can do.

The second capacitor C2 may be connected in parallel with the reset switch Sr, and may transfer the residual voltage Vres obtained by the first capacitor C1 to the output terminal Y. The reset switch Sr may serve to reset the second capacitor C2 for the operation of the next cycle.

3 is a graph illustrating input/output characteristics of the ATC 100 according to an embodiment of the present invention. The horizontal axis of the graph of FIG. 3 represents the input voltage Vin(V) to the ATC 100 , and the vertical axis represents the output voltage Vout(V) of the ATC 100 .

The input voltage Vin may be an analog signal having a voltage of 0 or more and VDD(V) or less. As a reference voltage for ternary conversion, a first reference voltage Vr1 and a second reference voltage Vr2 greater than the first reference voltage Vr1 are determined according to a preset reference in a range less than or equal to the driving voltage VDD. can The output voltage Vout may be determined according to the voltage value of the input voltage Vin.

More specifically, when the input voltage Vin is greater than or equal to 0 and less than the first reference voltage Vr1 (0≤Vin<Vr1), the output voltage V _out of 0 (V) may be output. Input voltage (Vin) may be the output voltage (V _out) of a first reference voltage (Vr1) less than when the second reference voltage (Vr2) (Vr1≤Vin <Vr2) , VDD / 2 (V) is output. When the input voltage (Vin) is equal to or less than the second reference voltage (Vr2) at least the drive voltage (VDD) (Vr2≤Vin≤VDD), has an output voltage (V _out) of the VDD (V) can be output. For example, the first reference voltage Vr1 may be 3/8×VDD and the second reference voltage Vr2 may be 5/8×VDD, but the reference voltages Vr1 and Vr2 and the driving voltage VDD The relationship between them is not necessarily limited thereto.

Referring again to FIG. 1 , the input voltage Vin is the first analog signal Va1 applied to the first ternary inverter 110 , and the output voltage Vout is the first and second ternary inverters 110 . , 120 may be a voltage of the second ternary data Vt2 outputted through it. The second ternary data Vt2 may be analogized to match the analog signals 0, VDD/2, VDD corresponding to the output voltage Vout of the ATC 100 and output as the second analog signal Va2. have. The second ternary data Vt2 and the second analog signal Va2 may be substantially the same signal.

As described above, according to the ATC 100 according to an embodiment, ternary data of 0, VDD/2, and VDD is converted by ternary conversion of the analog signal Vin based on preset reference voltages Vr1 and Vr2. can be printed out. That is, by using the output voltage (0, VDD/2, VDD) of the ATC 100 as it is, an analog voltage (0) corresponding to each ternary data (0, 1, 2) without using an external reference voltage generating circuit , VDD/2, VDD), thereby simplifying and simplifying the design of the ADC 1000 . In addition, by using the ternary inverters 110 and 120 that process ternary data, the sensor including the ADC 1000 can be miniaturized and reduced in power.

Hereinafter, the operation of the ADC 1000 will be described with reference to FIGS. 4 and 5 . Descriptions of the same contents as those described above in FIGS. 1 to 3 will be simplified or omitted.

4 is a circuit diagram illustrating a first mode M1 that is an operation mode of an ADC according to an embodiment of the present invention. The first mode M1 may be referred to as a sampling mode. In the sampling mode, the first switch pair S1 may be turned on while the second switch pair S2 is off.

Hereinafter, the operation of the first cycle in the sampling mode will be described. When the first switch pair S1 is turned on in the sampling mode, the first analog signal Va1 may be sampled and stored in the first capacitor C1. At the same time, the ATC 100 may determine which data among the ternary data of 0, 1, and 2 is the sampled first analog signal Va1. Here, the ATC 100 determines the state of the ternary data using the reference voltages Vr1 and Vr2 designed by the circuit built in the above-described ternary inverters 110 and 120, so that the conventional There is an advantage in that the design of the ADC 1000 can be simplified and simplified by omitting the reference voltage generating circuit of .

When the first capacitor C1 receives and samples the first analog signal Va1, the other terminal A4 of the first capacitor C1 is connected to the aforementioned reference voltage through the 1-1 switch S1-1. (Vcm) value can be fixed. At this time, a charge of C1*(Va1-Vcm) may be stored in the first capacitor C1, and the stored charge may be constantly maintained.

5 is a circuit diagram illustrating a second mode M2, which is another operation mode of the ADC 1000 according to an embodiment of the present invention. The second mode M2 may be referred to as a charge transfer mode.

While the ADC 1000 operates in the above-described sampling mode, the first switch pair S1 is turned off, and the second switch pair S2 is turned on by the next clock signal (eg, CLK2) to operate in the charge transfer mode. can

The second analog signal Va2 (or the second ternary data Vt2) output by the ATC 100 to one end A3 of the first capacitor C1 by the 2-1 switch S2-1 ) can be applied and held. The first capacitor C1 may obtain a residual voltage Vres by subtracting the second analog voltage Va2 from the first analog signal Va1 held in the sampling mode, and transmit it to the amplifier 300 . More precisely, according to the law of conservation of the amount of charge, the sum of the charges of the first capacitor C1 and the second capacitor C2 is the same in each of the first mode M1 and the second mode M2, so the following equation can be developed can (In this case, in the following equations, Vy denotes a voltage output to the output terminal Y, and C1 and C2 denote capacitances of capacitors.)

According to Equation 2, the residual voltage (Vres=(Va1-Va2)) may be amplified and output to the output terminal Y according to the ratio of the capacitances of the capacitors C1 and C2.

The amplifier 300 may double amplify the magnitude of the residual voltage Vres provided from the first capacitor C1 to output the third analog signal Va3 having a double gain. Referring back to FIG. 4 , the third analog signal Va3 is again applied to the input terminal I to become an input voltage of the second cycle (next cycle), and feedback sampling may be performed. As described above, by amplifying the residual voltage Vres and performing analog-to-digital conversion while repeating the cycle, it is possible to increase the resolution of data.

As the path switch S1-2 is turned on according to the number of bits processed by the cyclic ADC with respect to the output third analog voltage Va3, one cycle described above may be repeated. For example, if it is assumed that the number of processing bits of the cyclic ADC is (M+1) bits (M is a natural number greater than or equal to 1), the above-described cycle may be processed to be repeated a total of M times. While repeating this cycle, the ADC 1000 may finally convert the initially input first analog signal Va1 into a digital signal.

As described above, according to the ADC 1000 according to an embodiment of the present invention, by using the ATC 100 to perform the functions of analog-ternary conversion, ternary-analog conversion, and reference voltage generation circuit at once, cycle ADC can be miniaturized and low power consumption.

6 is a circuit diagram showing the structure of an ADC according to another embodiment of the present invention. Hereinafter, descriptions of overlapping contents of the same configuration as those of the above-described embodiment may be simplified or omitted, and the description will be made focusing on features that distinguish them from the above-described embodiment.

The ADC 1000 may further include a ternary encoder 400 and a reference voltage unit 500 .

Due to the input/output characteristics of the ternary element included in the ternary inverters 110 and 120 according to an embodiment of the present invention, when '1/2' ternary data is output, the voltage value of VDD/2 of the corresponding data is can be unstable. Accordingly, in the charge transfer mode, the accuracy of the second analog signal Va2 stored in the first capacitor C1 may decrease, and as a result, the resolution of the ADC 1000 may decrease. Accordingly, the present disclosure intends to improve the accuracy of analog-to-digital conversion of the ADC 1000 by using the ternary encoder 400 as will be described later. In addition, compatibility with digital circuit devices can be facilitated by using the ternary encoder 400 .

The ternary encoder 400 converts the second analog signal Va2 output by the ATC 100 into 2-bit binary data, and an analog input to the reference voltage unit 500 based on the binary data. The fourth analog voltage Va4 may be output by selecting one of the signals (eg, VDD, VDD/2, 0). One end A5 of the ternary encoder 400 may be connected to the second end A2 of the ATC 100 , and the other end A6 may be connected to the 2-1 th switch S2-1. The other terminal A6 may be an output terminal to which the fourth analog voltage Va4 is output by the ternary encoder 400 .

A reference voltage unit 500 is connected to the ternary encoder 400 to receive a reference voltage (eg, VDD, VDD/2, 0) from the reference voltage unit 500 . The ternary encoder 400 matches each of the second ternary data Vt2 received from the ATC 100 with the analog reference voltages VDD, VDD/2, 0 and converts the analog to the fourth analog voltage Va4 ) can be created. For example, if the second ternary data Vt2 is '1', it is VDD(V), if it is '1/2', it is VDD/2(V), and if it is '0', it is an analog signal of 0(V). can be converted In the present embodiment, when the 2-1 switch S2-1 is turned on to the first capacitor C1, the fourth analog voltage Va4 is applied instead of the aforementioned second analog signal Va2, and accordingly, the second analog voltage Va4 is applied. A residual voltage (Vres=Va1-Va4) between the first and fourth analog signals Va1 and Va4 may be obtained. The residual voltage Vres may be transmitted to the amplifier 300 , and the amplifier 300 may double amplify the residual voltage Vres to generate a third analog signal Va3 .

As described above, according to an embodiment of the present invention, by connecting the ternary encoder 400 and the reference voltage unit 500 to the ATC 100, the inaccuracy of '1/2' of the ternary data is removed and the first capacitor ( It is possible to supply an accurate voltage to C1), thereby improving the accuracy of the output signal by the output terminal (Y).

In the above, it has been described that the cyclic ADC 1000 includes the reference voltage unit 500 as an example, but instead of the reference voltage unit 500, the DAC includes a Digital-Analog Converter (DAC). Analog conversion can also be performed.

Hereinafter, the ternary encoder 400 according to an embodiment will be described with reference to FIGS. 7 to 9 . 7 is a structural diagram schematically showing the configuration of a ternary encoder 400 according to an embodiment of the present invention, FIG. 8 is a graph showing input/output characteristics of an inverter according to an embodiment of the present invention, and FIG. 9 is It is a graph showing input/output characteristics of a ternary encoder according to an embodiment of the present invention.

The ternary encoder 400 includes an input terminal I1 for receiving ternary data, a converter E for converting the ternary data into binary data, and an output terminal for outputting an analog signal in which the binary data is analog-converted ( O) may be included. The signal applied to the input terminal I1 may be the second analog signal Va2 output from the aforementioned ATC 100 .

The converter (E) includes four inverters (410, 420, 430, 440), and can convert ternary data into binary data using the inverters (410, 420, 430, 440). have. In the present disclosure, an 'inverter' may be a CMOS inverter including two transistors (not shown) of an NMOS transistor and a PMOS transistor. In the CMOS inverter, the NMOS transistor and the PMOS transistor may be connected in series.

More specifically, the converter E may include a first inverter 410 and a second inverter 420 , and the first inverter 410 and the second inverter 420 are signaled through the input terminal I1 . can each be authorized. The converter E may further include a third inverter 430 connected in series with the first inverter 410 and a fourth inverter 440 connected in series with the second inverter 420 . The third inverter 430 inverts the binary (binary) data output by the first inverter 410 again, and similarly, the fourth inverter 440 inverts the binary data output by the second inverter 420 again. can be booted

Referring to FIG. 8 together, the first inverter 410 and the second inverter 420 may be designed to have different input/output characteristics. The horizontal axis of the graph of FIG. 8 represents the input voltage Vin1 applied to the inverters 410 and 420 , and the vertical axis represents the output voltage Vout1 by the inverters 410 and 420 .

The first curve L1 represents the input/output profile of the first inverter 410 , and the second curve L2 represents the input/output profile of the second inverter 420 . The reference curve L0 is a comparison object with the first and second curves L1 and L2, and an inverter having the same or substantially similar current driving capability of the NMOS and PMOS in the inverter (hereinafter referred to as a 'reference inverter'). ) of the input/output profile. Vb indicated on the horizontal axis may mean a 'boundary voltage' for determining which binary data among 0 and 1 data to be output by the inverter. The boundary voltage Vb includes a reference boundary voltage Vb0 on the reference curve L0, a first boundary voltage Vb1 on the first curve L1, and a second boundary voltage Vb2 on the second curve L2. can be explained as a concept.

In the present disclosure, as an example, the boundary voltage Vb may be adjusted by designing the relative sizes of the NMOS and the PMOS included in each of the inverters 410 and 420 to be different from each other. When the width of the gate terminal of the transistor is W and the length is L, the boundary voltage Vb is determined by the W/L value (W/L_n) of the NMOS of the inverter and the W/L value (W/L_p) of the PMOS. can

For example, the first inverter 410 sets the first threshold voltage Vb1 to be higher than the reference threshold voltage Vb0 by designing 'W/L_p' to be greater than 'W/L_n' (W/L_p>W/L_n). can be lowered Conversely, the second inverter 420 increases the second threshold voltage Vb2 higher than the reference threshold voltage Vb0 by designing 'W/L_p' to be smaller than 'W/L_n' (W/L_p < W/L_n). can In this case, assuming that the reference boundary voltage Vb0 is the half driving voltage VDD/2 (Vb0=VDD/2), the inverters 410 and 420 satisfy the relational expressions of Vb1<VDD/2, Vb2>VDD/2. ) can be adjusted. At this time, only the boundary voltages Vb1 and Vb2 of the inverters 410 and 420 of the front stage are adjusted, and the boundary voltage of the inverters 430 and 440 of the rear stage can be designed as the reference boundary voltage Vb0 of the reference inverter. have.

In the above, an embodiment in which the boundary voltages of the first and second inverters 410 and 420 are adjusted has been described as an example, but depending on the embodiment, the boundary voltages of the third and fourth inverters 430 and 440 may be adjusted together. and the inverter controlling the boundary voltage is not necessarily limited thereto.

Hereinafter, input/output characteristics of the ternary encoder 400 including the inverter described above will be described with reference to FIG. 9 together. The horizontal axis of the graph of FIG. 9 represents the input voltage Vin2 applied to the ternary encoder 400 , and the vertical axis represents the output voltage Vout2 by the ternary encoder 400 . As an example, referring together with FIG. 6 , the input voltage Vin2 may correspond to the second analog signal Va2 , and the output voltage Vout2 may correspond to the fourth analog signal Va4 .

The 1-1 profile M1 is an input/output profile of the first and third inverters 410 and 430 , and the 2-1 profile M2 is an input/output profile of the second and fourth inverters 420 and 440 . Binary data of '00' in the first region D1, '01' in the second region D2, and '11' in the third region D3 may be output by the two profiles M1 and M2. .

By adjusting the boundary voltages Vb1 and Vb2 in the second region D2 as described above, the input voltage Vin2 is the half driving voltage VDD/2 or a voltage having a slight error based on VDD/2. However, even if the two boundary voltages (range between Vb1 and Vb2) are applied, '1' is outputted by the first inverter 410 and '0' is outputted by the second inverter 420 and finally '01' Binary data of ' can be output. In other words, during analog conversion in the ATC 100, the treatment data of '1' (the second ternary data Vt2) cannot be accurately matched with the analog signal of 'VDD/2' (the second analog signal Va2). However, if the second analog signal Va2 is in a range between the first threshold voltage Vb1 and the second threshold voltage Vb2, it may be converted into binary data of '01'. As such, the accuracy of ternary-analog conversion may be improved through the ternary encoder 400 .

According to an exemplary embodiment, when the magnitude relation between the first boundary voltage Vb1 and the second boundary voltage Vb2 is reversed, data of '10' may be output from the second region D2.

Referring back to FIG. 7 , the above-described binary data may be output by the output terminal O of the ternary encoder 400 , and the output terminal O includes the first output terminal O1 and the second output terminal O2. may include The first bit B1 by the first inverter pair 410 and 430 may be output through the first output terminal O1, and the first bit B1 may be output by the second inverter pair 420 and 440 through the second output terminal O2. The second bit B2 may be output. By designing the two inverter pairs 410, 430, 420, and 440 to be sequentially connected, 2-bit binary data consisting of two bits B1 and B2 can be output, and the output value of each bit B1, B2 According to this, 1.5 bit data can be known. The ternary encoder 400 may analog-convert the binary data by matching the binary data with the reference voltage provided from the above-described reference voltage unit 500 to output the above-described fourth analog signal Va4. By controlling a switch in the ternary encoder 400 with the two bit values (B1, B2), the reference voltage unit 500 converts an analog signal (eg, VDD, VDD/2, 0) to the ternary encoder 400 . ), it is possible to control whether to apply to the other end (A6). As described above, the fourth analog signal Va4 may be output through the other terminal A6 according to the analog signal selected according to the values of the two bits B1 and B2.

As described above, in the present disclosure, input/output characteristics (for example, boundary voltage (Vb)) of the inverters 410 and 420 are differentially designed by adjusting the relative sizes of the NMOS and PMOS in the inverter, and as a result, the ternary encoder 400 is Through this, ternary-analog conversion is possible, and furthermore, the accuracy of ternary-analog conversion can be improved. In the above-described embodiment, designing the first boundary voltage Vb1 to be smaller than the second boundary voltage Vb2 has been described as an example, but the opposite case is also possible.

In addition, although preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the technical field to which the present invention pertains without departing from the gist of the present invention as claimed in the claims Various modifications are possible by those of ordinary skill in the art, and these modifications should not be individually understood from the technical spirit or prospect of the present invention.

Therefore, the spirit of the present invention should not be limited to the above-described embodiments, and not only the claims described below, but also all scopes equivalent to or changed from the claims described below are the scope of the spirit of the present invention. would be said to belong to the category.

1000: ADC
100: ATC
300: amplifier
400: ternary encoder
410, 420, 430, 440: inverter
500: reference voltage unit
C1: first capacitor
C2: second capacitor

Claims (9)

an input terminal to which a first analog signal is applied;
an analog-to-ternary converter (ATC) that ternary-converts the first analog signal to output ternary data;
a first capacitor to which the ternary data is applied; and
an output terminal for outputting a third analog signal calculated based on the first analog signal and the ternary data;
The ternary data is a signal corresponding to a second analog signal that is analogized by matching the output voltage of the ATC, a cyclic analog to digital converter (ADC). According to claim 1,
The ATC includes a first ternary inverter and a second ternary inverter connected in series with each other,
The first ternary inverter ternary-converts the first analog signal to output first ternary data, a cyclic analog-to-digital converter. 3. The method of claim 2,
The second ternary inverter outputs second ternary data by inverting the first ternary data, and matches the second ternary data to an analog voltage corresponding to each of the second ternary data. A cyclic analog-to-digital converter that outputs a second analog signal. 4. The method of claim 3,
The first capacitor is
obtaining a residual voltage by subtracting the second analog signal from the first analog signal;
One end of the first capacitor is connected to the input terminal, the other end of the first capacitor is connected to an amplifier, and the amplifier doubles the residual voltage to output the third analog signal. converter. 4. The method of claim 3,
The ADC is
Further comprising a ternary encoder for converting the second analog signal generated by the ATC into binary data,
A cyclic analog-to-digital converter for analog-converting the binary data using the ternary encoder to output a fourth analog voltage. According to claim 1,
a path switch is disposed between the output terminal and the input terminal;
and the third analog signal is re-applied to the input terminal when the path switch is turned on. According to claim 1,
The ADC further includes a ternary encoder that converts the ternary data output by the ATC to analog;
The ternary encoder is
an input terminal receiving the ternary data;
a conversion unit including a first inverter and a second inverter respectively connected to the input terminal, and converting the ternary data into binary data; and
The cyclic analog-to-digital converter comprising a; 8. The method of claim 7,
A first threshold voltage of the first inverter has a value lower than a reference threshold voltage, and the first threshold voltage is a voltage that determines binary data output by the first inverter,
A second threshold voltage of the second inverter has a value higher than the reference threshold voltage, and the second threshold voltage is a voltage that determines binary data output by the second inverter. 9. The method of claim 8,
The conversion unit,
a third inverter connected in series with the first inverter and inverting the binary data output by the first inverter again; and
The cyclic analog-to-digital converter further comprising; a fourth inverter connected in series with the second inverter and inverting the binary data output by the second inverter again.

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