TWI542158B - Analog to digital converter and converting method thereof - Google Patents

Description

Analog digital conversion circuit and conversion method thereof

The invention relates to an analog digital conversion circuit and a conversion method thereof, in particular to a two-step analog-to-digital converter.

Due to the wide range of analog digital converters, analog digital converters are available in a variety of specifications and architectures, such as flash analog-to-digital converters (Flash ADCs), pipelined analog-to-digital converters (Pipeline ADCs), and continuous The Approximation Register (SAR ADC) and the two-step analog converter (Two-Step ADC) have their own suitable applications. Among them, the continuous approximate analog digital converter has the advantages of low power consumption, small area and low cost compared with other architectures.

Traditionally, the continuous approximation analog-to-digital converter uses a Binary Search Algorithm to obtain a digital output that matches the analog input signal. However, each conversion of the architecture of a continuous approximation analog-to-digital converter requires more bit periods to be output, and the time required for each conversion is proportional to the number of bits. Therefore, if you want to use the continuous approximation analog-to-digital converter in high-speed operation, it is necessary to shorten each bit period to achieve high-speed operation, but this will inevitably increase the overall power consumption. In addition, the higher the number of bits in the continuous approximation analog-to-digital converter, the more it is needed The longer the conversion period, the additional clock generator is needed to generate a clock signal with a duty cycle other than 50% for continuous approximate analog digital converters.

In the conventional two-step analog-to-digital converter design, a two-stage analog-to-digital converter is connected using a Closed-Loop Operating Amplifier to amplify the analog converter from the first stage. The Residue signal is provided to the analog converter of the second stage. However, because closed-loop operational amplifiers require longer settling times, the speed of the two-step analog digital converter is limited.

Therefore, how to make the analog digital converter have high speed and low overall power consumption to break the limitation of the operating speed of the analog digital converter, which is a key issue for those skilled in the art.

In an embodiment, an analog-to-digital conversion method includes analog-to-digital conversion of an analog input signal by using a first analog-to-digital converter to generate a first digital signal and an analog residual signal, and an analog-to-residue residual signal is amplified by an open loop amplifier. The signal, the analog-to-digital conversion of the analog residual signal is performed by the second analog-to-digital converter to generate a second digital signal, and the first digital signal and the second digital signal are combined to generate a digital output signal.

In one embodiment, an analog to digital conversion circuit includes a first analog to digital converter, an open loop amplifier, a second analog to digital converter, and an output unit. The first analog-to-digital converter is configured to sample the analog input signal to generate the first digital signal and the analog residual signal. The open loop amplifier is used to amplify the analog residual signal as an analog residual signal. The second analog-to-digital converter is configured to sample the analog residual signal to generate a second digital signal. Output unit for junction The first digit signal and the second digit signal are combined to generate a digital output signal.

In summary, an analog-to-digital conversion circuit and a conversion method thereof according to an embodiment of the present invention use an open-loop amplifier to connect a two-stage analog-to-digital converter to accelerate the amplification speed of a residual voltage between two stages, and to enhance analogous digits. The overall operating speed of the conversion circuit, combined with the operation time of the two-stage analog converter in the clock signal cycle, to directly use the 50% duty cycle signal without additional high power consumption. The clock generator generates a clock signal, thereby reducing the overall power consumption of the analog digital conversion circuit. In addition, debugging is aided by the use of an Arbitrary Weight Capacitor Array (AWCA) architecture to eliminate additional correction circuitry.

The detailed features and advantages of the present invention are described in detail in the embodiments of the present invention. The objects and advantages associated with the present invention can be readily understood by those skilled in the art.

100‧‧‧ analog digital conversion circuit

110‧‧‧First analog-to-digital converter

111, 111A, 111B‧‧‧ first capacitor array

112‧‧‧ first comparison unit

113‧‧‧First logical unit

114, 114A, 114B‧‧‧ input switch

120‧‧‧Open loop amplifier

130‧‧‧Second analog-to-digital converter

131, 131A, 131B‧‧‧ second capacitor array

132‧‧‧Second comparison unit

133‧‧‧Second logic unit

134, 134A, 134B‧‧‧ input switch

140‧‧‧Output unit

150‧‧‧Control unit

A _in ‧‧‧ analog input signal

A _in+ ‧‧‧ Positive input signal

A _in ‧‧‧n negative input signal

CM6~CM1, CL6~CL1‧‧‧ Capacitor Module

D1‧‧‧ first digit signal

D2‧‧‧ second digit signal

D _out ‧‧‧ digital output signal

M3A~M1A, M3B~M1B‧‧‧O crystal

Q1‧‧‧First logic signal

Q1 ₆ ~Q1 ₁ ‧‧‧ bits

Q2‧‧‧Second logic signal

Q2 ₆ ~Q2 ₁ ‧‧‧ bits

R1‧‧‧ first comparison result

R2‧‧‧ second comparison result

S1‧‧‧ first control signal

S2‧‧‧second control signal

V1‧‧‧ Common mode potential

V _B1 ‧‧‧First bias

V _B2 ‧‧‧second bias

VR1‧‧‧ analog ratio residual signal

VR1 ₊ ‧‧‧ positive terminal residual signal

VR1‧‧‧ Negative residual signal

VR2‧‧‧ analog ratio signal

VR2 ₊ ‧‧‧ positive terminal residual signal

VR2‧‧‧negative residual signal

VS1‧‧‧ analog voltage signal

VS1 ₊ ‧‧‧ positive terminal voltage signal

VS1‧‧‧ Negative voltage signal

WM6~WM1, WL6~WL1‧‧‧ switch module

[Fig. 1] is a schematic diagram showing an analog-to-digital conversion circuit according to an embodiment of the present invention.

[Fig. 2] is a schematic diagram showing an embodiment of the first analog-to-digital converter, the open-loop amplifier, and the second analog-digital converter in Fig. 1.

[Fig. 3] is a timing chart showing the operation of the first analog-to-digital converter and the second analog-to-digital converter in a clock cycle when the analog-to-digital conversion circuit is implemented according to an embodiment of the present invention.

1 is a summary of an analog digital conversion circuit in accordance with an embodiment of the present invention. schematic diagram. Referring to FIG. 1 , the analog digital conversion circuit 100 is mainly used to convert the analog input signal Ain into a digital output signal Dout. The analog digital conversion circuit 100 includes a first analog digital converter 110, an open loop amplifier 120, a second analog digital converter 130, and an output unit 140. The first analog-to-digital converter 110 is coupled between the pre-stage circuit (not shown) and the output unit 140. The open loop amplifier 120 is coupled between the first analog digital converter 110 and the second analog digital converter 130. The second analog-to-digital converter 130 is coupled between the open loop amplifier 120 and the output unit 140.

The first analog-to-digital converter 100 receives the analog input signal Ain from the pre-stage circuit and performs analog-like digital conversion of the input signal Ain to generate a first digital signal D1 and an analog residual signal VR1. The open loop amplifier 120 amplifies the analog residual signal VR1 into an analog residual signal VR2. The second analog-to-digital converter 130 receives the analog residual signal VR2 from the open loop amplifier 120 and performs analog-to-digital conversion of the residual signal VR2 to generate a second digital signal D2. After the analog digital conversion is completed, the output unit 140 combines the received first digital signal D1 and the second digital signal D2 into a digital output signal Dout.

In this case, the digital output signal Dout is formed by concatenating the first digital signal D1 and the second digital signal D2, wherein the first digital signal D1 is the high-order portion of the digital output signal Dout, and the second digital signal D2 is digital. The lower bit portion of the output signal Dout.

In some embodiments, the first analog-to-digital converter 110 and the second analog-to-digital converter 130 may be a continuous approximate analog digital converter that performs analog-to-digital conversion using a Continuous Approximation Register (SAR) technique ( SAR ADC). Here, the operation of the continuous approximation analog-to-digital converter is well known in the art and will not be described again. In addition, the open loop amplifier 120 utilizes its open loop characteristic to accelerate the amplification of the analog residual signal VR1 to the analog residual signal VR2 and to the next stage. The analog-to-digital converter of the segment (ie, the second analog-to-digital converter 130) shortens the steady-state time required for the conventional two-stage analog-to-digital conversion circuit to use a closed-loop amplifier, thereby improving the analog-to-digital conversion circuit 100. Overall operating speed.

In an embodiment, the first analog-to-digital converter 110 includes an input switch 114, a first capacitor array 111, a first comparison unit 112, and a first logic unit 113, and the input switch 114, the first capacitor array 111, and the first comparison. The unit 112 and the first logic unit 113 are sequentially connected in series between the front stage circuit (not shown) and the output unit 140. The second analog-to-digital converter 130 includes an input switch 134, a second capacitor array 131, a second comparison unit 132, and a second logic unit 133, and the input switch 134, the second capacitor array 131, the second comparison unit 132, and the second logic The unit 133 is serially connected between the open loop amplifier 120 and the output unit 140.

The first end of the input switch 114 is electrically connected to the front stage circuit (not shown) and receives the analog input signal Ain from the front stage circuit. The second end of the input switch 114 is electrically connected to the input end of the first capacitor array 111. The control terminal of the input switch 114 is electrically connected to a control circuit (not shown), and receives the first control signal S1 from the control circuit to determine whether the analog input signal Ain is transmitted to the first capacitor array 111 via the input switch 114. The output end of the first capacitor array 111 is electrically connected to the input end of the first comparison unit 112 and the input end of the open loop amplifier 120. The control terminal of the first capacitor array 111 is electrically connected to the output of the first logic unit 113 and receives the first logic signal Q1 from the first logic unit 113. The first capacitor array 111 adjusts the analog input signal Ain to the analog residual signal VR1 according to the first logic signal Q1. The first comparison unit 112 receives the analog residual signal VR1 from the first capacitor array 111, and the first comparison unit 112 generates a first comparison result R1 (ie, the ith comparison) by comparing the received analog residual signal VR1. The input end of the first logic unit 113 is electrically connected to the output end of the first comparison unit 112, and receives the first comparison result R1 from the first comparison unit 112. Therefore, the first logic unit 113 is based on the first ratio of the first comparison unit 112. The result R1 generates a first digital signal D1 and a first logical signal Q1. Then, the first capacitor array 111 switches according to the first logic signal Q1 to convert the analog input signal Ain into the analog residual signal VR1 (ie, the i+1th sampling) and successively perform the next comparison (ie, the i+th) 1 comparison). Where i is a positive integer and is equivalent to the number of bits of the first digit signal D1. In other words, the first logic unit 113 determines the corresponding bit in the first digital signal D1 according to the first comparison result R1 of each comparison. The first analog-to-digital converter 110 repeats sampling and comparison until all bits in the first digital signal D1 are determined.

The input of the open loop amplifier 120 is electrically coupled to the output of the first capacitor array 111 of the first analog converter 110 and receives the analog residual signal VR1 from the first capacitor array 111. Here, the open loop amplifier 120 amplifies the received analog residual signal VR1 into an analog residual signal VR2.

The first end of the input switch 134 is electrically coupled to the output of the open loop amplifier 120 and receives the analog residual signal VR2 from the open loop amplifier 120. The second end of the input switch 134 is electrically connected to the second capacitor array 131. The control terminal of the input switch 134 is electrically connected to the control circuit (not shown), and receives the second control signal S2 from the control circuit to determine whether the analog residual signal VR2 is transmitted to the second capacitor array 131 via the input switch 134. The second capacitor array 131 receives the analog residual signal VR2 via the input switch 134. The control terminal of the second capacitor array 131 is electrically connected to the output of the second logic unit 133 and receives the second logic signal Q2 from the second logic unit 133. The second capacitor array 131 adjusts the analog residual signal VR2 to the analog voltage signal VS1 according to the second logic signal Q2. The input end of the second comparison unit 132 is electrically connected to the output end of the second capacitor array 131 and receives the analog voltage signal VS1 from the second capacitor array 131. The second comparison unit 132 generates a second comparison result R2 (ie, the jth comparison) by comparing the received analog voltage signal VS1. The input end of the second logic unit 133 is electrically connected to the output end of the second comparison unit 132, and receives the second comparison The second comparison result R2 of unit 132. Therefore, the second logic unit 133 generates the second digital signal D2 and the second logic signal Q2 according to the second comparison result R2 of the second comparison unit 132. Then, the second capacitor array 131 is switched according to the second logic signal Q2, so that the analog residual signal VR2 is converted into the analog voltage signal VS1 (ie, the j+1th sampling) and the next comparison is performed (ie, the j+th) 1 sampling). Where j is a positive integer and is equivalent to the number of bits of the second digit signal D2. In other words, the second logic unit 133 determines the corresponding bit in the second digital signal D2 according to the second comparison result R2 of each comparison. The second analog-to-digital converter 130 repeats sampling and comparison until all bits in the second digital signal D2 are determined.

The two input ends of the output unit 140 are electrically connected to the output end of the first logic unit 113 and the output end of the second logic unit 133, respectively. The output unit 140 receives the first digital signal D1 from the first logic unit 113 and the second digital signal D2 of the second logic unit 133, and combines the first digital signal D1 with the second digital signal D2 to generate the digital output signal Dout.

See Figure 2 for matching. The following description is made by taking a 6-bit first analog-to-digital converter 110 and a 6-bit second analog-bit converter 130 as an example. Therefore, the digital output signal Dout finally output by the analog-to-digital conversion device 100 is 12 bits. The invention is not limited thereto. In terms of differential, the analog input signal Ain has a positive input signal Ain+ and a negative input signal Ain-, the analog residual signal VR1 has a positive residual signal VR1+ and a negative residual signal VR1-, and the analog residual signal VR2 has a positive residual The signal VR2+ and the negative residual signal VR2-, and the analog voltage signal VS1 have a positive terminal voltage signal VS1+ and a negative terminal voltage signal VS1-.

The first analog-to-digital converter 110 includes two input switches 114A, 114B, two first capacitor arrays 111A, 111B, a first comparison unit 112, and a first logic unit 113. Each of the first capacitor arrays 111A, 111B includes six capacitor modules CM6~CM1 and six The switch modules WM6~WM1, and the capacitor modules CM6~CM1 correspond one-to-one to the switch modules WM6~WM1. In the first capacitor array 111A, the first end of the capacitor module CM6~CM1 is coupled to the first input end of the first comparing unit 112 and the second end of the input switch 114A. The positive input signal Ain+ is transmitted to the capacitor modules CM6~CM1 via the input switch 114A, and then converted into the positive end residual signal VR1+, and then input to the first input end of the first comparison unit 112. The second end of the capacitor module CM6~CM1 is coupled to the first end of the corresponding switch module WM6~WM1. The second end of the switch module WM6~WM1 is coupled to one of the complex levels, for example, one of a reference potential and a common mode potential or one of a reference potential, a common mode potential, and a floating connection. The control terminals of the switch modules WM6~WM1 are coupled to the first logic unit 113 and respectively receive the bits Q16~Q11 of the first logic signal Q1. Similarly, in the first capacitor array 111B, the first ends of the capacitor modules CM6-CM1 are coupled to the second input end of the first comparing unit 112 and the second end of the input switch 114B. The negative input signal Ain- is transmitted to the capacitor modules CM6~CM1 via the input switch 114B, and then converted to the negative residual signal VR1-, and then input to the second input end of the first comparison unit 112. The second ends of the capacitor modules CM6~CM1 are coupled to the first ends of the corresponding switch modules WM6~WM1, and respectively receive the bits Q16~Q11 of the first logic signal Q1.

The first comparison unit 112 generates a first comparison result R1 by comparing the positive terminal residual signal VR1+ received by the first input terminal with the negative terminal residual signal VR1- received by the second input terminal. The first logic unit 113 generates the first digital signal D1 and the first logic signal Q1 (ie, the bits Q16~Q11) according to the first comparison result R1, and sequentially controls the switch by using the bits Q16~Q11 of the first logic signal Q1. The switching of the modules WM6~WM1 determines the ratio of the analog input signal Ain to the analog residual signal VR1.

The first logic unit 113 is coupled to the control terminals of the switch modules WM6 to WM1, and the first logic unit 113 outputs the bits of the first logic signal Q1 one-to-one. The control terminals of the control modules WM6~WM1 are coupled to the common mode potential V1 or the reference potential (eg, ground). The first logic unit 113 outputs the highest bit Q16 of the first logic signal Q1 to the switch module WM6, so that the switch module WM6 switches according to the highest bit Q16 of the first logic signal Q1. The first logic unit 113 outputs the next highest bit Q15 of the first logic signal Q1 to the switch module WM5, so that the switch module WM5 switches according to the next highest bit Q15 of the first logic signal Q1. The first logic unit 113 outputs the lowest bit Q11 of the first logic signal Q1 to the switch module WM1, so that the switch module WM1 switches according to the lowest bit Q11 of the first logic signal Q1. Basically, in the initial state, the second ends of the switch modules WM6~WM1 are coupled to the reference potential.

Here, each comparison result sequentially determines a bit in the first logical signal Q1 and a bit in the first digital signal D1. Therefore, for each of the first capacitor arrays 111A and 111B, the capacitor modules CM6~CM1 sequentially correspond to the highest bit to the lowest bit of the first digital signal D1, in other words, each of the capacitor modules CM6~CM1 corresponds to the first digit. One bit in signal D1. In terms of 6 bits, the sixth capacitor module CM6 corresponds to the highest bit (6th bit) of the first digit signal D1, and the fifth capacitor module CM5 corresponds to the next highest bit of the first digit signal D1. (5th bit), the fourth capacitor module CM4 corresponds to the 4th bit in the first digit signal D1, and the third capacitor module CM3 corresponds to the 3rd bit in the first digit signal D1, the second capacitor The module CM2 corresponds to the first bit in the first digital signal D2, and the first capacitive module CM1 corresponds to the lowest bit (first bit) in the first digital signal D1.

Therefore, the first analog-to-digital converter 110 sequentially outputs the bits Q16-Q11 in the first logic signal by using the analog-digital conversion technique of the first logic unit 113 to sequentially switch the first capacitor arrays 111A, 111B. The switch modules WM6~WM1 control the first comparison unit 112 via the corresponding capacitor modules CM6~CM1 Electrically connected to the common mode potential V1 to generate a first digital signal D1. In response to the differential architecture, the analog digital conversion circuit 100 uses two open loop amplifiers 120A, 120B. The input end of the open loop amplifier 120A is coupled to the first end of the capacitor module CM6~CM1 of the first capacitor array 111A and the first input end of the first comparison unit 112 to receive and amplify the positive end residual signal VR1+ The positive residual signal VR2+. Similarly, the input end of the open loop amplifier 120B is coupled to the first end of the capacitor module CM6~CM1 of the first capacitor array 111B and the second end of the first comparing unit 112 to receive and amplify the negative residual signal VR1 - is the negative residual signal VR2-.

In some embodiments, the open loop amplifiers 120A, 120B can be source followers to accelerate the amplification of the analog residual signal VR1 (the positive residual signal VR1+) by utilizing the characteristics of its open loop and voltage gain (Gain) being one. The negative residual signal VR1-) is an analog analog residual signal VR2 (positive terminal residual signal VR2+ and negative residual signal VR2-). Here, the source follower composed of three transistors is used as the open loop amplifiers 120A, 120B. In the case of the open loop amplifier 120A, the first bias voltage VB1 is coupled to the control terminal of the transistor M3A. The second bias voltage VB2 is coupled to the control terminal of the transistor M2A. The analog residual signal VR1+ is connected to the control terminal of the transistor M1A. The first end of the transistor M3A is connected to the supply voltage, and the second end of the transistor M3A is connected to the first end of the transistor M2A. The second end of the transistor M2A is connected to the first end of the transistor M1A to output an analog residual signal VR2+. The second end of the transistor M1A is connected to ground. Similarly, in the case of the open loop amplifier 120B, the first bias voltage VB1 is connected to the control terminal of the transistor M3B. The second bias voltage VB2 is coupled to the control terminal of the transistor M2B. The analog residual signal VR1 - is connected to the control terminal of the transistor M1B. The first end of the transistor M3B is connected to the power supply voltage, and the second end of the transistor M3B is connected to the first end of the transistor M2B. The second end of the transistor M2B is connected to the first end of the transistor M1B to output an analog residual signal VR2-. The second end of the transistor M1B is connected to ground. Here, open loop The transistors M3A, M2A, M3B, and M2B of the amplifiers 120A and 120B are used as current sources of the open loop amplifiers 120A and 120B, respectively.

The second analog-to-digital converter 130 includes two input switches 134A, 134B, two second capacitor arrays 131A, 131B, a second comparison unit 132, and a second logic unit 133. Each of the second capacitor arrays 131A and 131B includes six capacitor modules CL6 to CL1 and six switch modules WL6 to WL1, and the capacitor modules CL6 to CL1 correspond to the switch modules WL6 to WL1 in a one-to-one manner. In the second capacitor array 131A, the first ends of the capacitor modules CL6-CL1 are coupled to the first input end of the second comparing unit 132 and the second end of the input switch 134A. The positive-end residual signal VR2+ is transmitted to the capacitor modules CL6-CL1 via the input switch 134A, and then converted to the positive-end voltage signal VS1+, and then input to the first input terminal of the second comparison unit 132. The second ends of the capacitor modules CL6~CL1 are coupled to the first ends of the corresponding switch modules WL6~WL1. The second end of the switch module WL6~WL1 is coupled to one of the complex levels, for example, one of a reference potential and a common mode potential or one of a reference potential, a common mode potential, and a floating connection. The control terminals of the switch modules WL6 WL WL1 are coupled to the second logic unit 133 and respectively receive the bits Q26 ～ Q21 of the second logic signal Q2. Similarly, in the second capacitor array 131B, the first ends of the capacitor modules CL6-CL1 are coupled to the second input end of the second comparing unit 132 and the second end of the input switch 134B. The negative residual signal VR2 is transmitted to the capacitor modules CL6~CL1 via the input switch 134B, and then converted to the negative terminal voltage signal VS1-, and then input to the second input terminal of the second comparison unit 132. The second ends of the capacitor modules CL6~CL1 are coupled to the first ends of the corresponding switch modules WL6~WL1, and receive the bits Q26~Q21 of the second logic signal Q2, respectively.

The second comparator 132 generates a second comparison result R2 by comparing the positive terminal voltage signal VS1+ received by the first input terminal with the negative terminal voltage signal VS1- received by the second input terminal. The second logic unit 133 generates the second digital signal D2 and the second according to the second comparison result R2. The two logic signals Q2 (ie, bits Q26~Q21), and sequentially control the switching of the switch modules WL6~WL1 by using the bits Q26~Q21 of the second logic signal Q2 to determine the conversion of the analog residual signal VR2 into an analog voltage signal. The ratio of VS1.

Here, the second logic unit 133 is coupled to the control terminals of the switch modules WL6 WL WL1, and the second logic unit 133 outputs the bits Q26 ～ Q21 of the second logic signal Q2 to the corresponding switch module WL6~ The control terminal of the WL1 is coupled to the common mode potential V1 or the reference potential (eg, ground) by the second terminal of the control switch module WL6~WL1. The second logic unit 133 outputs the highest bit Q26 of the second logic signal Q2 to the switch module WL6, so that the switch module WL6 switches according to the highest bit Q26 of the second logic signal Q2. The second logic unit 133 outputs the second highest bit Q25 of the second logic signal Q2 to the switch module WL5, so that the switch module WL5 switches according to the next highest bit Q25 of the second logic signal Q2. The second logic unit 133 outputs the lowest bit Q21 of the second logic signal Q2 to the switch module WL1, so that the switch module WL1 switches according to the lowest bit Q21 of the second logic signal Q2. Basically, in the initial state, the second ends of the switch modules WL6 WL WL1 are coupled to the reference potential.

Here, each comparison result sequentially determines one bit in the second logical signal Q2 and one bit in the second digital signal D2. Therefore, for each of the second capacitor arrays 131A and 131B, the capacitor modules CL6~CL1 sequentially correspond to the highest bit to the lowest bit of the second digital signal D2, in other words, each of the capacitor modules CL6~CL1 corresponds to the second digit. One bit in signal D2. In the case of 6 bits, the sixth capacitor module CL6 corresponds to the highest bit (6th bit) of the second digit signal D2, and the fifth capacitor module CL5 corresponds to the next highest bit of the second digit signal D2. (5th bit), the fourth capacitor module CL4 corresponds to the 4th bit in the second digit signal D2, and the third capacitor module CL3 corresponds to the 3rd bit in the second digit signal D2, the second capacitor The module CL2 corresponds to the second bit in the second digital signal D2, and the first capacitive module CL1 corresponds to the lowest bit (1st bit) of the second digit signal D2.

Therefore, the second analog-to-digital converter 130 sequentially outputs the bits Q26-Q21 in the second logic signal by using the analog digital conversion technique of the continuous logic approximation 133 to sequentially switch the second capacitor arrays 131A, 131B. The switch module WL6~WL1 generates a second digital signal D2 by controlling the second comparison unit 132 to be electrically connected to the common mode potential V1 via the corresponding capacitors CL6~CL1.

In addition, the analog digital conversion circuit 100 further includes a control unit 150 (ie, the aforementioned control circuit). The control unit 150 is electrically connected to the first analog bit converter 110 and the second analog bit converter 130 to control the operation sequence of the first analog bit converter 110 and the second analog bit converter 130. Here, the control terminals of the input switches 114A, 114B of the first analog-to-digital converter 110 are electrically connected to the first output of the control unit 150, and the control terminals of the input switches 114A, 114B receive the first control from the control unit 150. Signal S1. The control terminals of the input switches 134A, 134B of the second analog-to-digital converter 130 are electrically coupled to the second output of the control unit 150, and the control terminals of the input switches 134A, 134B receive the second control signal S2 from the control unit 150.

Please refer to Figure 3 together. In the first time slot T1, the voltage of the first control signal S1 output by the control unit 150 is a high level (ie, logic 1), and the voltage of the second control signal S2 is a low level (ie, a logic 0). Therefore, the input switches 114A, 114B of the first analog-to-digital converter 110 are controlled to be turned off by the first control signal S1, so that the first capacitor arrays 111A, 111B of the first analog-to-digital converter 110 can be respectively connected via the input switches 114A, 114B. The positive input signal Ain+ and the negative input signal Ain- are received, and the positive input signal Ain+ and the negative input signal Ain- are respectively sampled. The input switches 134A, 134B of the second analog-to-digital converter 130 are turned on by the second control signal S2, so that the second analog-to-digital converter 130 enters the comparison mode and uses the analog approximation of the continuous approximation to the positive terminal. The remainder signal VR2+ and the negative residual signal VR2- are converted to generate a second digital signal D2. Therefore, in the first time slot T1, the first analog-to-digital converter 110 enters the sampling mode (to perform the Nth sampling), and the second analog-digital converter 130 simultaneously enters the comparison mode (to perform the N-1th comparison) ).

In the second time slot T2, the voltage of the first control signal S1 output by the control unit 150 is a low level (ie, logic 0), and the voltage of the second control signal S2 is a high level (ie, logic 1). Therefore, the input switches 114A, 114B of the first analog-to-digital converter 110 are turned on by the first control signal S1, so that the first analog-to-digital converter 110 enters the comparison mode and uses the analog approximation analog-to-digital conversion technique to sample the samples. The positive input signal Ain+ and the negative input signal Ain- are converted to generate the first digital signal D1. The input switches 134A, 134B of the second analog-to-digital converter 130 are turned off by the second control signal S2, so that the second capacitor arrays 131A, 131B of the second analog-to-digital converter 130 can be received via the input switches 134A, 134B. The positive-end residual signal VR2+ and the negative-end residual signal VR2- from the open loop amplifier 120 sample the positive-end residual signal VR2+ and the negative-end residual signal VR2-. Therefore, in the second time slot T2, the first analog-to-digital converter 110 enters the compare mode (to perform the Nth comparison), and the second analog-bit converter 130 simultaneously enters the sampling mode (to perform the Nth sampling).

In other words, when the second analog-to-digital converter performs the N-1th comparison procedure, the first control signal S1 output by the control unit 150 enables the input switches 114A, 114B to cause the first digit converter 110 to perform the Nth Subsampling procedure. Similarly, when the first digitizer 110 completes the Nth sampling procedure and continues the Nth comparison procedure, the second control signal S2 output by the control unit 150 enables the input switches 134A, 134B to promote the second analogy. The digital converter 130 continues the N-1th comparison procedure to perform the Nth sampling procedure.

Here, the open loop amplifier 120 is coupled to the first analog digital converter. Between the first analog converter and the second analog converter 130, the analog digital converter circuit 100 can reduce the settling time required by the conventional closed loop by the open loop characteristic of the open loop amplifier 120, so that the first analog converter 110 performs The comparison procedure can be performed in conjunction with the open loop amplifier 120 for the amplification procedure. Therefore, the analog-to-digital conversion circuit 100 can directly control the operation of the first analog-to-digital converter 110 and the second analog-to-digital converter 130 by using a signal with a duty cycle of 50% without additionally using a high-power clock generator. This produces, and in turn reduces, the overall power consumption of the analog digital conversion circuit 100.

In some embodiments, the control unit 150 can enable the input switch 134A of the second analog-to-digital converter 130 by using the second control signal S2 when the first analog-to-digital converter 110 generates the lowest bit of the first digital signal D1. 134B causes the second analog-to-digital converter 130 to begin sampling the analog residual signal VR2.

In some embodiments, the first capacitor arrays 111A, 111B and the second capacitor arrays 131A, 131B are implemented by an Arbitrary Weight Capacitor Array (AWCA) architecture to help improve the analog digital converter circuit 100. Overall linearity.

Referring to FIG. 2, the capacitance of the a-th capacitor module is smaller than the sum of all the capacitance values of the a-1th capacitor module to the first capacitor module. Where a is a positive integer greater than 2 and a is less than or equal to i or j (ie, the number of groups of all capacitor modules; that is, the total number of bits of the first digit signal D1 or the total number of bits of the second digit signal D2) . Taking the first capacitor array 111A or 111B as an example, i is equal to 6 and a is between 2 and 6 (ie, a is greater than 2 and a is less than or equal to 6). The capacitance value of the sixth capacitor module CM6 is smaller than the sum of all the capacitance values of the fifth capacitor module CM5 to the first capacitor module CM1, and the capacitance value of the fifth capacitor module CM5 is smaller than the fourth capacitor module CM4 to The total capacitance of the first capacitor module CM1, the capacitance value of the fourth capacitor module CM4 is smaller than the capacitance values of the third capacitor module CM3 to the first capacitor module CM1. The total capacitance of the third capacitor module CM3 is smaller than the sum of all the capacitance values of the second capacitor module CM2 to the first capacitor module CM1. For example, the ratio of the capacitance values of all the capacitor modules CM6~CM1 in the first capacitor array 111A or 111B may be 15:8:4:2:2:1, but the invention is not limited thereto. In this way, the comparison error of the high-order portion can be avoided. For example, when the first comparison unit 112 has a fault in the high-order portion, it can be remedied by the subsequent algorithm, and has the effect of debugging.

Taking the second capacitor array 131A or 131B as an example, j=6, and a is between 2 and 6 (ie, a is greater than 2 and a is less than or equal to 6). The capacitance value of the sixth capacitor module CL6 is smaller than the sum of all the capacitance values of the fifth capacitor module CL5 to the first capacitor module CL1, and the capacitance value of the fifth capacitor module CL5 is smaller than the fourth capacitor module CL4 to The sum of all the capacitance values of the first capacitor module CL1, the capacitance value of the fourth capacitor module CL4 is smaller than the sum of all the capacitance values of the third capacitor module CL3 to the first capacitor module CL1, and the third capacitor The capacitance of the module CL3 is smaller than the sum of all the capacitance values of the second capacitor module CL2 to the first capacitor module CL1. For example, the ratio of the capacitance values of all the capacitor modules CL6~CL1 in the second capacitor array 131A or 131B may be 15:8:4:2:2:1, but the invention is not limited thereto. In this way, the comparison error of the high-order portion can be avoided. For example, when the second comparison unit 132 has a fault in the high-order portion, it can be remedied by the subsequent algorithm, and has the effect of debugging.

In some embodiments, each of the capacitor modules CM6~CM1, CL6~CL1 can have one or more capacitors in parallel with each other. Each switch module can be implemented with one or more switches. When using multiple switches, all switches in the same switch module have the same function.

In some embodiments, if the two inputs of the first comparator 112 are implemented by PMOS (P-type MOS), a plurality of additional capacitor modules may be connected in parallel to the first capacitor array 111A or 111B for use. The technique of Level Shift accelerates the action of the first comparator 112. Here, the additional capacitor modules correspond to the adjusted signals. Additional switch modules for control. Therefore, when the first analog-to-digital converter 110 enters the comparison mode, the adjustment signal can switch the additional switch module so that the input end of the first comparator 112 can be coupled to the ground via the additional capacitor module to offset the positive offset The potential of the terminal residual signal VR1+ or the potential of the negative terminal residual signal VR1- is accelerated to accelerate the action of the first comparator 112.

Similarly, in some embodiments, if the two inputs of the second comparator 132 are implemented by PMOS (P-type MOS), a plurality of additional capacitance modes may be connected in parallel to the second capacitor array 131A or 131B. In the group, the technique of the offset potential (Level Shift) is used to accelerate the action of the second comparator 132. Here, the additional capacitor modules also correspond to additional switch modules controlled by the adjusted signals. Therefore, when the second analog-to-digital converter 130 enters the comparison mode, the adjustment signal switches the additional switch module such that the input of the second comparator 132 can be coupled to the ground via the additional capacitor module to offset the positive end downward. The potential of the voltage signal VS1+ or the potential of the negative terminal voltage signal VS1- accelerates the action of the second comparator 132.

In summary, an analog-to-digital conversion circuit and a conversion method thereof according to an embodiment of the present invention use an open loop amplifier to connect a two-stage analog-to-digital converter (the aforementioned first analog-to-digital converter and second analog-to-digital converter) to accelerate The amplification speed of the Residue Voltage between the two stages, and the overall operation speed of the analog digital conversion circuit is improved, and the operation time in the cycle of the clock signal is reconfigured with the analogy of the two-stage analog converter to directly use the work. The clock signal with a period of 50% does not require the use of a high-powered clock generator to generate a clock signal, thereby reducing the overall power consumption of the analog-to-digital conversion circuit. In addition, debugging is aided by the use of an Arbitrary Weight Capacitor Array (AWCA) architecture to eliminate additional correction circuitry.

The technical contents of the present invention have been disclosed in the preferred embodiments as described above, and are not intended to limit the present invention. Any modifications and refinements made by those skilled in the art without departing from the spirit of the present invention should be Within the scope of the invention, therefore the scope of protection of the present invention This is subject to the definition of the scope of the patent application.

100‧‧‧ analog digital conversion circuit

110‧‧‧First analog-to-digital converter

111‧‧‧First Capacitor Array

112‧‧‧ first comparison unit

113‧‧‧First logical unit

114‧‧‧Input switch

120‧‧‧Open loop amplifier

130‧‧‧Second analog-to-digital converter

131‧‧‧Second capacitor array

132‧‧‧Second comparison unit

133‧‧‧Second logic unit

134‧‧‧Input switch

140‧‧‧Output unit

A _in ‧‧‧ analog input signal

D1‧‧‧ first digit signal

D2‧‧‧ second digit signal

D _out ‧‧‧ digital output signal

Q1‧‧‧First logic signal

Q2‧‧‧Second logic signal

R1‧‧‧ first comparison result

R2‧‧‧ second comparison result

S1‧‧‧ first control signal

S2‧‧‧second control signal

VR1‧‧‧ analog ratio residual signal

VR2‧‧‧ analog ratio signal

VS1‧‧‧ analog voltage signal

Claims (12)

An analog-to-digital conversion method includes: sampling a analog input signal by using a first analog-to-digital converter and comparing the sampled analog input signals to generate a first digital signal and an analog residual signal; The open loop amplifier amplifies the analog residual signal as an analog residual signal; the analog analog signal is sampled by a second analog digital converter and the sampled residual signal is compared to generate a second digital signal; The first digital signal and the second digital signal are used to generate a digital output signal; wherein the comparing step of comparing the sampled analog residual signal with the next sampling step of the analog input signal is performed simultaneously . The analog digital conversion method of claim 1, wherein the comparing step of the sampled analog input signal is performed in synchronization with the sampling step of the analog residual signal. The analog digital conversion method of claim 1, wherein the sampling step of the analog residual signal is performed when the comparing step of the sampled analog input signal is performed until a lowest bit value in the first digital signal is generated. The analog digital conversion method of claim 1, wherein the generating step of the first digital signal and the second digital signal is performed by a continuous approximation analog digital conversion technique. An analog-to-digital conversion circuit includes: a first analog-to-digital converter for performing analog-to-digital conversion of an analog input signal to generate a first digital signal and an analog residual signal; an open loop amplifier for amplifying the The analog residual signal is an analogy residual signal; a second analog-to-digital converter for performing analog-to-digital conversion of the analog residual signal to generate a second digital signal; an output unit for combining the first digital signal and the second digital signal to generate a digital output And a control unit electrically connected to the first analog-to-digital converter and the second analog-to-digital converter, wherein when the first analog-to-digital converter generates the first digital signal according to the analog input signal, The control unit activates the second analog-to-digital converter to sample the analog residual signal, and when the second analog-to-digital converter generates the second digital signal according to the analog residual signal, the control unit activates the first analog digital converter The next sampling action is performed on the analog input signal. The analog-to-digital conversion circuit of claim 5, wherein the control unit activates the second analog-to-digital converter to sample the analogy when the first analog-to-digital converter generates the lowest bit value of the first digital signal The remainder signal. The analog-to-digital conversion circuit of claim 5, wherein the first analog-to-digital converter and the second analog-to-digital converter are continuous approximate analog digital converters. The analog-to-digital conversion circuit of claim 5, wherein the open loop amplifier is a source follower, the source follower input receives the analog residual signal, and the source follower amplifies the analog residual The signal outputs the analog residual signal. The analog-to-digital conversion circuit of claim 5, wherein the first analog-to-digital converter comprises a first capacitor array, a first comparison unit and a first logic unit, and the first capacitor array receives the analog input signal. The first comparison unit generates a first comparison result by comparing the received analog residual signals, and the first logic unit generates the first digital signal and a first logic signal according to the first comparison result, and uses the First logic The number is controlled to switch the first capacitor array to convert the analog input signal into the analog residual signal. The analog-digital conversion circuit of claim 9, wherein the first capacitor array comprises: a plurality of capacitance modules respectively corresponding to the plurality of bits of the first digital signal, wherein the a-th bit of the bits corresponds to The capacitance value of the capacitor module is smaller than the capacitance value of the capacitor module corresponding to the capacitor module corresponding to the a-1th bit of the bits to the lowest bit of the bits. The sum, where a is greater than 2 and a is less than or equal to the total number of the bits of the first digit signal. The analog-to-digital conversion circuit of claim 5, wherein the second analog-to-digital converter comprises a second capacitor array, a second comparison unit and a second logic unit, the second capacitor array receiving the analog residual signal, The second comparison unit generates a second comparison result by comparing the received analog voltage signals, and the second logic unit generates the second digital signal and a second logic signal according to the second comparison result, and uses the The second logic signal controls switching of the second capacitor array to convert the analog residual signal into the analog voltage signal. The analog-digital conversion circuit of claim 11, wherein the second capacitor array comprises: a plurality of capacitance modules respectively corresponding to the plurality of bits of the second digital signal, wherein the a-th bit of the bits corresponds to The capacitance value of the capacitor module is smaller than the capacitance value of the capacitor module corresponding to the capacitor module corresponding to the a-1th bit of the bits to the lowest bit of the bits. The sum, where a is greater than 2 and a is less than or equal to the total number of the bits of the second digit signal.