KR102301999B1 - Driver, display panel, and display device - Google Patents

Abstract

The present embodiments relate to a driver, a display panel, and a display device having a pad structure that enables a stable signal supply while reducing the size of a source driver and a source printed circuit board.

Description

Driver, display panel and display device {DRIVER, DISPLAY PANEL, AND DISPLAY DEVICE}

The present embodiments relate to a driver, a display panel, and a display device.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and liquid crystal display devices (LCDs), plasma display devices, organic light emitting display devices ( Various types of display devices such as OLED: Organic Light Emitting Display Device) are being used.

Such a display device may include a source driver implemented in a Chip On Film (COF) method to drive the display panel. These source drivers are connected to the source printed circuit board and the display panel, respectively, and supply various signals (power, etc.) output from the timing controller, power management integrated circuit, etc. to themselves as well as the display panel and gate driver. .

In order to supply such a signal, one side and the other side of the source driver are respectively connected to the display panel and the source printed circuit board through pads.

Among the various signals supplied to the source driver, there is a signal with high voltage or high current compared to other signals. this is connected

Accordingly, in order to supply a signal between the source driver and the source printed circuit board, the plurality of pads in the source driver and the plurality of pads in the source printed circuit board should be bonded to each other in correspondence with each other.

However, during this pad bonding process, a situation may occur in which alignment between the plurality of pads in the source driver and the plurality of pads in the source printed circuit board does not match. have.

In addition, in order to supply a signal between the source driver and the source printed circuit board, since the plurality of pads in the source driver and the plurality of pads in the source printed circuit board must correspond to and contact each other, due to the plurality of pads, the source printed circuit board There has also been a problem in that the size of the substrate and the source driver has to be increased.

It is an object of the present embodiments to provide a driver, a display panel, and a display device having a pad structure that enables stable signal supply.

Another object of the present embodiments is to provide a driver, a display panel, and a display device having a pad structure that enables a stable signal supply and reduces the size of a source driver and a source printed circuit board.

In one embodiment, a display panel having a plurality of data lines and a plurality of gate lines disposed thereon, a source printed circuit board, a film connected to the display panel on one side and a source printed circuit board on the other side, and a plurality of data lines to output a data voltage, and including a source driver integrated circuit chip mounted on a film, and in each of the source printed circuit board and the film, one or more pads for first signals that correspond to and contact each other exist, and are in contact with each other. There is provided a display device characterized in that two or more second signal pads exist, and a width of each first signal pad is wider than a width of each second signal pad.

In another embodiment, one side is connected to the display panel, the other side includes a film connected to the source printed circuit board, and a source driver integrated circuit chip mounted on the film, wherein the film includes a plurality of pieces in contact with the source printed circuit board. A pad is present, and at least one of the plurality of pads has a different width than the others.

Another embodiment includes a substrate on which a plurality of data lines are disposed, a source printed circuit board, a film connected to the substrate on one side and a source printed circuit board on the other side, and a film for outputting data voltages to the plurality of data lines Including a source driver integrated circuit chip mounted thereon, each of the film and the source printed circuit board, a plurality of pads corresponding to and contacting each other exist, and at least one of the plurality of pads has a different width from the others A display panel is provided.

According to the present embodiments as described above, it is possible to provide a driver, a display panel, and a display device having a pad structure that enables stable signal supply.

Also, according to the present embodiments, it is possible to provide a driver, a display panel, and a display device having a pad structure that enables a stable signal supply and reduces the size of the source driver and the source printed circuit board.

1 is a schematic system configuration diagram of a display device according to example embodiments.
2 and 3 are exemplary views of a sub-pixel structure of a display device according to example embodiments.
4 is a schematic diagram exemplarily illustrating application of a signal through a source printed circuit board and a source driver in a display device according to embodiments.
5 and 6 are enlarged views of the second pad contact portion A2 for applying two or more types of signals among the contact portions between the source printed circuit board and the source driver in the display device according to the exemplary embodiment.
7 and 8 are other enlarged views of the second pad contact portion A2 for applying two or more types of signals among the contact portions between the source printed circuit board and the source driver in the display device according to the exemplary embodiment.
9 and 10 illustrate a first signal and a second contact portion A2 of a second pad contact portion A2 for applying two or more types of signals among contact portions between a source printed circuit board and a source driver in the display device according to the embodiments. It is an exemplary diagram showing the supply of a signal.
11 to 16 are enlarged examples of a first pad contact portion A1 having a pad for a first signal for applying a first signal among contact portions between a source printed circuit board and a source driver in a display device according to embodiments; It is also
17 to 19 are diagrams for explaining the effect of stably supplying power and reducing the size according to the structure of a wide pad for applying the first signal among the contact portions between the source printed circuit board and the source driver in the display device according to the embodiments; .

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It will be understood that each component may be “interposed” or “connected”, “coupled” or “connected” through another component.

1 is a schematic system configuration diagram of a display device 100 according to example embodiments.

Referring to FIG. 1 , a display device 100 according to example embodiments includes a display panel 110 on which a plurality of data lines and a plurality of gate lines are disposed, and a plurality of sources for outputting data voltages to the plurality of data lines. A driver (Source Driver) 120, a plurality of gate drivers (Gate Driver) 130 for outputting scan signals to a plurality of gate lines, and a timing for controlling the plurality of source drivers 120 and the plurality of gate drivers 130 controller 140 and the like.

Referring to FIG. 1 , a plurality of gate drivers 130 are drivers for driving a plurality of gate lines disposed on the display panel 110 , and may be connected to one side of the display panel 110 as shown in FIG. 1 , In some cases, it may be connected to both sides of the display panel 110 .

Referring to FIG. 1 , each of the plurality of source drivers 120 is a driver for driving a plurality of data lines disposed on the display panel 110 , and is implemented by, for example, a Chip On Film (COF) method. can be That is, each of the plurality of source drivers 120 may include a film 121 and a source driver integrated circuit (S-DIC) chip 122 mounted on the film 121 .

Referring to FIG. 1 , each of the plurality of source drivers 120 has one side connected to the display panel 110 , and the other side connected to a source printed circuit board (S-PCB) 150 . Here, the source printed circuit board (S-PCB, 150) is also referred to as a source board, and there may be at least one in the display device 100 .

That is, the film 121 of each of the plurality of source drivers 120 has one side connected to the display panel 110 and the other side connected to the source printed circuit board 150 .

Referring to FIG. 1 , the timing controller 140 is disposed on a Control Printed Circuit Board (C-PCB) 160 . Here, the control printed circuit board (C-PCB, 160) is also called a control board (Control Board).

In addition to outputting data to the plurality of source drivers 120 , the timing controller 140 controls the operation timings of the plurality of source drivers 120 and the plurality of gate drivers 130 , the data control signal ( Various control signals such as a Data Control Signal (DCS) and a Gate Control Signal (GCS) may be output.

Referring to FIG. 1 , a power management integrated circuit (PMIC) 180 may be further disposed on the control printed circuit board (C-PCB) 160 .

Referring to Figure 1, the source printed circuit board 150 and the control printed circuit board 160 is a flexible flat cable (FFC: Flexibl Flat Cable) or a flexible printed circuit (FPC: Flexible Printed Circuit) connecting means 170, such as connected through Here, at least one connection means 170 may be present in the display device 100 .

Accordingly, the timing controller 140 , the power management integrated circuit 180 , etc. disposed on the control printed circuit board 160 , the plurality of source drivers 120 , the plurality of gate drivers 130 , and the display panel 110 . ) can be transmitted between signals.

Here, the preferred transmission means transmission of all electrical signals including various power sources (voltage, current), control signals, sensing signals, data, and the like.

Meanwhile, the source driver 120 may be used as a transmission path of various control signals to be supplied to the gate driver 130 in addition to data, power, and signals for driving data.

In addition, the source driver 120 may transmit and receive signals related to various functions such as panel sensing and compensation with the timing controller 140 .

Meanwhile, in the display panel 110 , a plurality of data lines and a plurality of gate lines are disposed, a plurality of sub-pixels (SP) are defined, and circuit elements such as transistors are disposed in each sub-pixel area.

Each of these subpixels receives a data voltage from one data line and one or more scan signals from one or more gate lines.

Each of these subpixels may be composed of various circuit elements such as one or more transistors and one or more capacitors.

The number and type of circuit elements in each sub-pixel may vary depending on the type of the display device 100 , a pixel design, and a sub-pixel design method.

Each of these sub-pixels is supplied with various types of power in addition to data voltages and scan signals according to internal circuit elements.

Meanwhile, referring to FIG. 1 , the display panel 110 includes a plurality of data lines, a plurality of gate lines, a substrate 111 on which circuit elements such as transistors are disposed in each sub-pixel SP region, and the substrate. other configurations 112 on 111 . Here, the other components 112 may vary depending on the type of the display device 100 (organic light emitting display device, liquid crystal display device, plasma display device, etc.). When the display device 100 is a liquid crystal display device, , a color filter substrate facing the substrate 111 , and when the display device 100 is an organic light emitting display device, an encapsulation layer and the like may be included.

2 and 3 are exemplary views of a sub-pixel structure of the display device 100 according to example embodiments.

2 and 3 are diagrams exemplarily illustrating the structure of each sub-pixel when the display device 100 according to the exemplary embodiment is an organic light emitting display device.

2 and 3 , when the display device 100 according to the embodiments is an organic light emitting display device, each sub-pixel is an organic light emitting diode (OLED). and driving circuit elements for driving the same.

Each sub-pixel of the organic light emitting diode display may have a different sub-pixel structure because the type and number of driving circuit elements are different according to a design method or a function provided.

2 is a diagram illustrating an example of a subpixel structure of an organic light emitting diode display.

Each subpixel of the organic light emitting diode display illustrated in FIG. 2 may include an organic light emitting diode (OLED), two transistors T1 and T2 and a capacitor C1 to drive the OLED. Such a sub-pixel structure is called a 2T (Transistor) 1C (Capacitor) structure.

Referring to FIG. 2 , a first transistor T1 among two transistors T1 and T2 is a driving transistor for driving an organic light emitting diode (OLED), and a driving voltage line (DVL) ) or a pattern connected to the driving voltage line DVL and the organic light emitting diode OLED.

2, the second transistor T2 among the two transistors T1 and T2 is turned on or off depending on the presence or absence of a scan signal through a gate line (GL), When turned on, a switching transistor for turning on-off the first transistor T1 by applying the voltage of the second node (N2, gate node) of the first transistor T1 corresponding to the driving transistor transistor), which is connected between a data line DL supplying the data voltage Vdatga and the second node N2 of the first transistor T1.

Referring to FIG. 2 , the first node N1 of the first transistor T1 is a drain node or a source node, and is a node connected to a first electrode (eg, an anode electrode or a cathode electrode) of the organic light emitting diode (OLED). am. Here, the ground voltage EVSS is applied to the second electrode (eg, a cathode electrode or an anode electrode) of the organic light emitting diode (OLED). The second node N2 of the first transistor T1 is a gate node, and the data voltage Vdata supplied from the data line DL through the turned-on second transistor T2 is applied. The third node N3 of the first transistor T1 is a source node or a drain node, and the driving voltage EVDD supplied from the driving voltage line DVL or a pattern connected thereto is applied thereto.

Referring to FIG. 2 , one capacitor C1 is connected between the second node N2 and the third node N3 of the first transistor T1 corresponding to the driving transistor, and for a predetermined time (eg, one frame time) to maintain a constant voltage.

Referring to FIG. 2 , the timing of changes in various signals (EVDD, EVSS, Vdata, Scan Signal, etc.) required to drive a subpixel of a 2T1C structure is controlled by the timing controller 140 .

3 is a diagram illustrating an example of a sub-pixel structure of an organic light emitting diode display.

Each subpixel of the organic light emitting diode display illustrated in FIG. 3 may include an organic light emitting diode (OLED), three transistors T1 , T2 , T3 and a capacitor C1 to drive the same. . Such a subpixel structure is called a 3T1C structure.

Referring to FIG. 3 , a first transistor T1 among three transistors T1 , T2 , and T3 is a driving transistor for driving an organic light emitting diode OLED, and a driving voltage line DVL: Driving Voltage Line) or the pattern connected to the driving voltage line (DVL) and the organic light emitting diode (OLED).

Referring to FIG. 3 , the second transistor T2 among the three transistors T1 , T2 , and T3 is turned on or on depending on the presence or absence of a scan signal through the first gate line GL. It is turned off, and when turned on, the voltage of the second node (N2, gate node) of the first transistor T1 corresponding to the driving transistor is applied to turn the first transistor T1 on-off. As a switching transistor, it is connected between a data line DL supplying the data voltage Vdatga and the second node N2 of the first transistor T1 .

Referring to FIG. 3 , the first node N1 of the first transistor T1 is a drain node or a source node, and is a node connected to a first electrode (eg, an anode electrode or a cathode electrode) of the organic light emitting diode (OLED). am. Here, the ground voltage EVSS is applied to the second electrode (eg, a cathode electrode or an anode electrode) of the organic light emitting diode (OLED). The second node N2 of the first transistor T1 is a gate node, and the data voltage Vdata supplied from the data line DL through the turned-on second transistor T2 is applied. The third node N3 of the first transistor T1 is a source node or a drain node, and the driving voltage EVDD supplied from the driving voltage line DVL or a pattern connected thereto is applied thereto.

Referring to FIG. 3 , the third transistor T3 among the three transistors T1 , T2 , and T3 is a fourth transistor to which a reference voltage Vref is supplied from a reference voltage line (RVL) or a pattern connected thereto. It is connected between the node N4 and the first node N1 of the first transistor T1.

Here, the switch SW is connected to the end of the reference voltage line RVL electrically connected to the fourth node N4. The switch SW selectively connects the reference voltage line RVL to a supply point of the reference voltage Vref and one of an analog digital converter (ADC).

The third transistor T3 is a sensing transistor involved in compensating for the luminance deviation of the corresponding sub-pixel, and a sense signal, which is a type of scan signal, is supplied from the second gate line GL′. It is turned on or off depending on presence or absence, and when turned on, serves to apply the reference voltage Vref to the first node N1 of the first transistor T1, or a first node of the first transistor T1. It may serve to allow the voltage of (N1) to be sensed by an analog-to-digital converter (ADC).

The analog-to-digital converter (ADC) mentioned above senses the voltage of the first node N1 of the first transistor T1 and converts it into a digital value to generate sensed data, and uses the generated sensed data to the timing controller 140 . send to

The timing controller 140 receives the sensed data and performs a compensation process for compensating for deviations in intrinsic characteristics such as threshold voltage and mobility of the first transistor T1 corresponding to the driving transistor in each sub-pixel based on the received sensing data. do. Here, the compensation process determines the data compensation amount that compensates for the deviation of the intrinsic characteristic values such as the threshold voltage and the mobility of the first transistor T1, and according to the determined data compensation amount, data to be supplied to the corresponding sub-pixel It is changed and supplied to the corresponding source driver 120 .

Referring to FIG. 3 , one capacitor C1 is connected between the second node N2 and the third node N3 of the first transistor T1 corresponding to the driving transistor, and for a predetermined time (eg, one frame time) to maintain a constant voltage.

Referring to FIG. 3 , the timing of changes in various signals (EVDD, EVSS, Vdata, Scan Signal, Sense Signal, etc.) required to drive the subpixel of the 3T1C structure is controlled by the timing controller 140 .

As described above with reference to FIGS. 2 and 3 , various signals are supplied to the display panel 110 .

These various signals are supplied through the source driver 120 and the gate driver 130 . The source driver 120 receives data and various signals from the timing controller 140 to supply the data voltage. The gate driver 130 may receive various signals for generating a scan signal to be supplied from the timing controller 140 through the source driver 120 . In addition, other signals (EVDD, EVSS, etc.) for driving the display panel 110 are also supplied to the display panel 110 through the source driver 120 .

As such, various signals for driving the display panel 110 are supplied to the display panel 110 through the source driver 120 .

A signal to be supplied to the display panel 110 or a signal for generating the same is not input to the source driver 120 , but only a signal between the timing controller 140 and the source driver 120 for compensation and status check. also exchange

As described above, for driving the display panel 110 and for supplying a signal to the source driver 120 , the film 120 of the source driver 120 includes a plurality of pads, and the source printed circuit board 150 . ) also has a plurality of pads, so that the plurality of pads of the film 120 of the source driver 120 and the plurality of pads of the source printed circuit board 150 correspond to each other and contact each other, so that the timing controller 140 or power management is integrated Various signals output from the circuit 180 and the like may be supplied to the source driver 120 .

Meanwhile, among various signals supplied to the source driver 120 for driving the display panel 110 , there are signal(s) of relatively high voltage or large current compared to other signals.

For example, the driving voltage EVDD applied to the first transistor T1 , which is a driving transistor in the subpixel, is a signal having a relatively high voltage or a large current compared to other signals.

Below, a signal having a relatively high voltage or large current compared to other signals, such as a driving voltage signal, is referred to as a “first signal S1”, a lock signal, a gamma signal, and a reference voltage ( Vref), a signal having a relatively low voltage or small current compared to the first signal is referred to as a “second signal S2”.

4 is a schematic diagram exemplarily illustrating signal application through the source printed circuit board 150 and the source driver 120 in the display device 100 according to the exemplary embodiment.

Referring to FIG. 4 , in the contact portion 400 where each source driver 120 and the source printed circuit board 150 are connected, a plurality of pads and the source printed on the film 121 of each source driver 120 are provided. A plurality of pads on the circuit board 150 correspond to and contact each other.

Referring to FIG. 4 , the first signal S1 of relatively high voltage or high current is supplied to the contact portion 400 between each source driver 120 and the source printed circuit board 150 , compared to the second signal S2 . There is a first pad contact portion A1 having the pad(s) serving as a path, and pad(s) serving as a supply path of the first signal S1 of high voltage or high current, and is relatively relative to the first signal S1. As a result, there is a second pad contact portion A2 with pads serving as a supply path for the second signal S2 of low voltage or low current.

5 and 6 show a first signal for application of a first signal and a second signal among the contact portions 400 between the source printed circuit board 150 and the source driver 120 in the display device 100 according to the embodiments. 2 It is an enlarged illustration of the pad contact part A2. 7 and 8 show the second pad contact of the first signal and the second signal among the contact portions 400 between the source printed circuit board 150 and the source driver 120 in the display device 100 according to the exemplary embodiment. It is another exemplary view in which the part A2 is enlarged. However, with reference to FIGS. 5 to 8 , only a portion in which one source driver 120 is present will be described, and this description may be equally applied to other source drivers 120 .

As shown in FIGS. 5 and 6 , in the portion with one source driver 120 , each of the source printed circuit board 150 and the film 121 has one first signal pad ( P1/P1'), and two or more second signal pads P2a/P2a', P2b/P2b', P2c/P2c', and P2d/P2d' that correspond to and contact each other.

5 and 6, in the portion where one source driver 120 is located, one first signal pad P1 on the source printed circuit board 150 in the S-PCB pad area and In the COF pad area, one pad P1' for the first signal on the film 121 is in contact with each other. In addition, two or more second signal pads P2a, P2b, P2c, P2d on the source printed circuit board 150 in the S-PCB pad area, and two or more second signal pads P2a on the film 121 in the COF pad area. ', P2b', P2c', P2d') correspond to and contact each other.

On the other hand, in FIGS. 5 and 6 , in the portion where one source driver 120 is located, the first signal pad serving as the first signal supply path is provided on each of the source printed circuit board 150 and the film 121 . Although shown separately, this is only an example for convenience of description, and in some cases, in the portion where one source driver 120 is located, the source printed circuit board 150 and the film 121 are respectively There may be two or more pads for the first signal serving as a supply path.

7 and 8, in the portion where one source driver 120 is located, each of the source printed circuit board 150 and the film 121 has two pads for the first signal serving as a supply path of the first signal. It is also an example.

7 and 8, in each of the source printed circuit board 150 and the film 121, two or more first signal pads P1a/P1a', P1b/P1b' that correspond to and contact each other are present, There may be two or more second signal pads P2a/P2a', P2b/P2b', P2c/P2c', and P2d/P2d' that correspond to and contact each other.

5 to 8 , in the portion where one source driver 120 is provided, whether there is only one pad for the first signal on each of the source printed circuit board 150 and the film 121 , or two or more pads each However, the width W1 of one pad for the first signal is wider than the width W2 of the pad for the second signal.

Accordingly, the area of one pad for the first signal becomes larger than the area of the pad for the second signal.

As described above, the width W1 of one pad for the first signal is made wider than the width W2 of the pad for the second signal, so that the resistance of one pad for the first signal is equal to the resistance of the pad for the second signal. It can be further reduced, and the first signal can be stably supplied through the pad for the first signal. In addition, through this structure, the total length of the pad part can be reduced while maintaining the same overall pad contact area, so that the size of the source printed circuit board 150 can be reduced, and cost can also be reduced.

9 and 10 illustrate a first signal and a second contact portion A2 of a second pad contact portion A2 for applying two or more types of signals among contact portions between a source printed circuit board and a source driver in the display device according to the embodiments. It is an exemplary diagram showing the supply of a signal.

Referring to FIG. 9, the first signal applied to each pad for the first signal (P1/P1' in FIGS. 5 and 6, P1a/P1a', and P1b/P1b' in FIGS. 7 and 8) is, Compared to the second signal applied to the signal pad (P2a/P2a', P2b/P2b', P2c/P2c', P2d/P2d' in FIGS. 5 to 8), a high voltage (eg, 20V to 24V) or a large current (10A to 20A).

Accordingly, it is possible to stably supply the first signal having a relatively high voltage or high current compared to the second signal through the first signal pad having a wider width than the second signal pad.

Referring to FIG. 10 , when the display panel 110 is an organic light emitting display panel, each pad for the first signal (P1/P1' in FIGS. 5 and 6, P1a/P1a', P1b/P1b in FIGS. 7 and 8) ') is the third node of the first transistor T1 corresponding to the driving transistor connected to the first electrode (eg, anode electrode or cathode electrode) of the organic light emitting diode (OLED) in each sub-pixel. It may be a driving voltage EVDD supplied to (N3, a drain node or a source node).

Accordingly, the driving voltage EVDD having a relatively high voltage/high current may be stably supplied to the sub-pixels through the first signal pad, which is wider than the second signal pad.

11 to 16 show pad(s) for a first signal for applying a first signal among the contact portions 400 between the source printed circuit board 150 and the source driver 120 in the display device 100 according to the exemplary embodiment. ) is an enlarged view of the first pad contact portion A1 with .

However, in FIGS. 11 to 16 , in the portion with one source driver 120 , the first pad contact portion A1 among the contact portions 400 between the source printed circuit board 150 and the source driver 120 has , for convenience of explanation, as shown in FIGS. 5 and 6 , one pad for the first signal P1/P1 ′ on each of the film 121 of the source printed circuit board 150 and the source driver 120 . Assume that there is

Referring to FIG. 11 , among the contact portions 400 between the source printed circuit board 150 and the source driver 120 , the first pad contact portion A1 for applying the first signal is a first contact portion of the S-PCB pad area. The signal pad P1 and the first signal pad P1' in the COF pad area correspond to each other and are in contact (bonding).

11, in order to supply the first signal of high voltage or high current, the width W1 of the first signal pad P1/P1' is changed to the second signal pad P2a/P2a' for the second signal supply. , P2b/P2b', P2c/P2c', P2d/P2d') By making the width W2 wider than the width W2, a relatively high voltage or high current first signal can be stably supplied through the source driver 120. .

However, as shown in FIG. 11 , the first signal pad P1 on the source printed circuit board 150 and the first signal pad P1 ′ on the film 121 of the source driver 120 cover the entire area. Since they must be in contact, the first signal pad P1 on the source printed circuit board 150 and the first signal pad P1 ′ on the film 121 of the source driver 120 are bonded using a conductive ball. In this case, many conductive balls cannot stay between the first signal pad P1 and the first signal pad P1 ′ on the film 121 of the source driver 120 .

For this reason, pad bonding between the first signal pad P1 and the first signal pad P1 ′ on the film 121 of the source driver 120 does not work well, so there is a slight possibility that a pad bonding defect occurs. As described above, when the pad-bundling defect occurs, there may be a problem in that conductivity through the first signal pads P1/P1' is deteriorated.

Accordingly, as shown in FIGS. 12 to 16 , in the present embodiments, at least one of the source printed circuit board 150 and the film 121 in the portion where the one source driver 120 is located, one In the above first signal pad (P1/P1' in FIGS. 5 and 6, P1a/P1a', and P1b/P1b' in FIGS. 7 and 8), conductive balls such as at least one hole or at least one groove stay A space H may be formed.

That is, in the portion where the one source driver 120 is located, at least one pad for the first signal on the source printed circuit board 150 (P1 in FIGS. 5 and 6, P1a, P1b in FIGS. 7 and 8) is at least There are a plurality of conductive ball positioning spaces H, such as one hole or at least one groove, or at least one pad for the first signal on the film 121 (P1 ′ in FIGS. 5 and 6 , and in FIGS. 7 and 8 ). There may be at least one conductive ball position space H such as at least one hole or at least one groove in P1a' and P1b'.

In some cases, at least one hole or at least one groove in at least one first signal pad (P1 in FIGS. 5 and 6, P1a, P1b in FIGS. 7 and 8) on the source printed circuit board 150, such as There is a conductive ball position region H, and at least one hole or at least one first signal pad on the film 121 (P1' in FIGS. 5 and 6, P1a', P1b' in FIGS. 7 and 8) There may be at least one conductive ball position space H, such as at least one groove.

However, in FIGS. 12 to 16 , at least one pad for the first signal (P1 in FIGS. 5 and 6 , FIGS. 7 and 8 ) on the source printed circuit board 150 in a portion where one source driver 120 is located. It is a view exemplarily showing a case where there is at least one conductive ball position space H such as at least one hole or at least one groove only in P1a and P1b).

As such, in at least one of the source printed circuit board 150 and the film 121, one or more first signal pads (P1/P1' in FIGS. 5 and 6, P1a/P1a', P1b in FIGS. 7 and 8) In /P1b'), a conductive ball position space (H) in which a conductive ball can stay, such as at least one hole or at least one groove, is formed, thereby pad bonding between the film 121 and the source printed circuit board 150 ( Bonding), more conductive balls can stay, so pad bonding defects between the film 121 and the source printed circuit board 150 can be reduced, and high conductivity can be secured.

Meanwhile, in at least one of the source printed circuit board 150 and the film 121, one or more first signal pads (P1/P1' in FIGS. 5 and 6, P1a/P1a', P1b/ in FIGS. If there is a plurality of conductive ball position spaces (H) such as a plurality of holes or a plurality of grooves in each of P1b'), as shown in FIG. 12, a plurality of conductive ball positions such as a plurality of holes or a plurality of grooves The space H may be arranged in two or more rows and two or more columns.

As such, in each of the one or more first signal pads (P1/P1' in FIGS. 5 and 6, P1a/P1a', and P1b/P1b' in FIGS. 7 and 8), a plurality of holes or a plurality of grooves When forming the conductive ball position space H of It is easy to pattern P1 of 6, P1a, P1b of FIGS. 7 and 8), and the number of positions where the conductive ball stays increases, so the pad for the first signal of the source printed circuit board 150 (FIG. 5 and FIG. Bad bonding between P1 in FIG. 6, P1a, P1b in FIGS. 7 and 8) and the first signal pad of the film 121 (P1' in FIGS. 5 and 6, P1a', P1b' in FIGS. 7 and 8) probability may be reduced.

Meanwhile, in at least one of the source printed circuit board 150 and the film 121, one or more first signal pads (P1/P1' in FIGS. 5 and 6, P1a/P1a', P1b/ in FIGS. In each of P1b'), a plurality of conductive ball location spaces H, such as a plurality of holes or a plurality of grooves, are arranged in two or more rows and two or more columns, as shown in FIG. , in odd-numbered rows, conductive ball position spaces (H) such as holes or grooves are arranged only in odd-numbered columns or even-numbered columns, and in even-numbered rows, conductive ball position spaces (H) such as holes or grooves are arranged only in even-numbered columns or odd columns. can

As such, in each of the one or more first signal pads (P1/P1' in FIGS. 5 and 6, P1a/P1a', and P1b/P1b' in FIGS. 7 and 8), as shown in FIG. 13, odd rows In , by arranging holes or grooves only in odd-numbered columns or even-numbered columns, and in even-numbered rows, by arranging holes or grooves only in even-numbered columns or odd-numbered columns, while securing space for many conductive balls to stay, the pad for the first signal (Fig. 5 and Fig. In P1/P1' of 6, P1a/P1a', and P1b/P1b' of FIGS. 7 and 8), the application area of the first signal can be further increased, so that higher conductivity can be obtained.

Meanwhile, in at least one of the source printed circuit board 150 and the film 121, one or more first signal pads (P1/P1' in FIGS. 5 and 6, P1a/P1a', P1b/ in FIGS. If there are a plurality of conductive ball position spaces (H) such as a plurality of holes or a plurality of grooves in each of P1b'),

Each of the plurality of conductive ball location spaces (H), such as a plurality of holes or a plurality of grooves, has a vertical bar shape, as shown in FIG. 14, or horizontally as shown in FIG. It may have a bar shape in the direction.

As such, in each of the one or more first signal pads (P1/P1' in FIGS. 5 and 6, P1a/P1a', and P1b/P1b' in FIGS. 7 and 8), a plurality of holes or a plurality of grooves When the conductive ball position space H of It is easy to pattern (Patterning), and the conductive ball stays in more places, so the first signal pad (P1 in FIGS. 5 and 6, P1a in FIGS. 7 and 8, P1a in FIGS. P1b) and the first signal pad of the film 121 (P1' in FIGS. 5 and 6, P1a', and P1b' in FIGS. 7 and 8) can be significantly reduced.

Meanwhile, in each of the one or more first signal pads (P1/P1' in FIGS. 5 and 6, P1a/P1a', and P1b/P1b' in FIGS. 7 and 8), a plurality of holes or a plurality of grooves are provided. When forming the conductive ball positioning space H, as shown in FIG. 16 , each conductive ball positioning space H, that is, a hole or a groove may be formed in a circular shape.

As described above, when forming each conductive ball position space (H), that is, a hole or a groove, it may be formed in a short bar shape as in FIGS. 12 and 13, and as in FIGS. 14 and 15, a long bar It may be formed in a shape, may be formed in a circular shape as shown in FIG. 16, and in addition to the illustrated shape, any shape is possible as long as the conductive ball can stay.

In addition, the conductive ball position space H, that is, the number and position of the holes or grooves, may be variously determined according to pad contact and conductivity.

On the other hand, each of the pad for the first signal of the source printed circuit board 150 and the pad for the first signal of the film 121 are equal to the width of the pad for the second signal, and instead of supplying the first signal of high voltage or high current For this reason, the number may be increased.

However, the pad for the first signal of the source printed circuit board 150 (P1 in FIGS. 5 and 6, P1a, P1b in FIGS. 7 and 8) of the above-described source printed circuit board 150 and the pad for the first signal of the film 121 (FIG. 5) and P1' in FIG. 6, and P1a' and P1b' in FIGS. 7 and 8) each is wider than the width of the pad for the second signal, so that a large number of pads for the first signal are reduced in number such as one or two. It can be said to have an integrated "integrated pad structure" or "wide pad structure".

Below, with reference to FIGS. 17 to 19 , each of the source printed circuit board 150 and the film 121 has about 20 pads for the first signal having a narrow width (the same as the width W2 of the pad for the second signal). For the case where many are arranged (narrow pad structure) and when only one pad for the first signal of the wide width W1 is arranged on each of the source printed circuit board 150 and the film 121 (wide pad structure), the power supply The stability of the supply and the size and size are compared and explained.

17 to 19 show a stable structure according to a wide pad structure for applying a first signal among the contact portions 400 between the source printed circuit board 150 and the source driver 120 in the display device 100 according to the exemplary embodiment. It is a diagram for explaining the effect of power supply and size reduction.

Referring to FIG. 17 , in the above narrow pad structure, 20 first signal pads P1a to P1t on the source printed circuit board 150 and 20 first signal pads P1a on the film 121 . '~P1t') each has a pad width of 0.15 mm. The 20 first signal pads P1a to P1t on the source printed circuit board 150 and the 20 first signal pads P1a' to P1t' on the film 121 correspond to and contact each other, The total contact width of the 20 first signal pads P1a to P1t on the printed circuit board 150 and the 20 first signal pads P1a' to P1t' on the film 121 is 3 mm (=20) ×0.15 mm).

Referring to FIG. 17 , in the wide pad structure below, one first signal pad P1 on the source printed circuit board 150 and one first signal pad P1 ′ on the film 121 are each , has a pad width W1 of 3 mm. One first signal pad P1 on the source printed circuit board 150 and one first signal pad P1 ′ on the film 121 correspond to each other and contact each other. The total contact width of one first signal pad P1 on the film 121 and one first signal pad P1' on the film 121 is 3 mm.

Referring to FIG. 17 , in both the narrow pad structure and the wide pad structure, the pad contact area for the first signal is equal to 3 mm.

Referring to FIG. 17 , in the case of the narrow pad structure, 20 first signal pads P1a to P1t on the source printed circuit board 150 and 20 first signal pads P1a ′ on the film 121 . ~P1t'), each is spaced apart by 0.15mm in order to secure a space for the conductive ball to stay. For this reason, the total length of the pad part becomes 6 mm (= 20 x 0.15 mm + 20 x 0.15 mm).

In contrast, in the case of the wide pad structure, one first signal pad P1 on the source printed circuit board 150 and one first signal pad P1 ′ on the film 121 each have a narrow pad structure. It can be seen that the overall length of the pad part is very short to 3.15mm because it has a width (3mm) that is much wider than the pad width (0.15mm) of have.

That is, as in the present embodiments, by applying the wide pad structure, it is possible to reduce the overall pad part length while maintaining the same narrow pad structure and the overall pad contact width (3 mm), so that the source printed circuit board 150 . size can be reduced, and cost can also be reduced.

Referring to FIG. 18 , during a bonding process between the S-PCB pad region and the COF pad region, mis-alignment may occur. If the degree of such mis-alignment is large, the signal supply may become unstable or not at all.

Accordingly, the minimum overlap ratio or the maximum misalignment ratio between each pad for the first signal on the source printed circuit board 150 and each pad for the first signal on the film 121 is set as a design value.

In Fig. 18, the minimum overlap ratio is 30% and the maximum misalignment ratio is 70%.

Referring to FIG. 18 , in the case of the narrow pad structure, each pad for the first signal in the source printed circuit board 150 and each pad for the first signal in the film 121 are 30% of the pad length (converted to the length, If only 0.045mm=0.15mm×0.3) are in contact, considering all the 20 first signal pads on the source printed circuit board 150 and the 20 first signal pads on the film 121, the total pad contact length It can be seen that the total pad contact length (3mm) without misalignment decreased to 0.9mm (=0.15mm×0.3×20).

On the other hand, in the case of the wide pad structure, when the narrow pad structure and the misalignment degree are the same, one first signal pad P1 in the source printed circuit board 150 and one first signal pad P1 in the film 121 One signal pad P1' does not contact by 70% of 0.15 mm (in terms of length, 0.105 mm = 0.15 mm x 0.7).

Therefore, in the case of the wide pad structure, assuming that the narrow pad structure and the degree of misalignment are the same, one first signal pad P1 on the source printed circuit board 150 and one first signal pad P1 on the film 121 . It can be seen that the total pad contact length of the signal pad P1' is 2.9 mm (=3 mm-(0.15 mm×0.7)).

That is, when misalignment occurs by a length of 0.105 mm, in the case of the narrow pad structure, the total pad contact length becomes 0.9 mm, and in the case of the wide pad structure, the total pad contact length becomes 2.9 mm.

As described above, in the case of the wide pad structure, even if misalignment occurs during the pad bonding process, the total pad contact length does not decrease much, so the possibility of pad bonding failure is considerably lowered, and high conductivity can be provided. and it can enable stable signal supply.

Meanwhile, as shown in FIGS. 17 and 18 , the size (length) of the source printed circuit board 150 can be significantly reduced while maintaining the entire pad contact length.

As such, when using the wide pad structure according to the present embodiments, as shown in FIG. 19, the size (length) of the source printed circuit board 150 can be significantly reduced from L1 to L2 (< L1), Accordingly, the cost of the source printed circuit board 150 can be significantly reduced.

As described above, the display panel 110 according to the present exemplary embodiments includes a substrate 111 on which a plurality of data lines are disposed, at least one source printed circuit board 150 , and one side of the substrate 111 . ) and a film 121 connected to the corresponding source printed circuit board 150 on the other side, and a source driver integrated circuit chip 122 mounted on the film 121 and outputting data voltages to a plurality of data lines. and the like.

Here, in each of the film 121 and the source printed circuit board 150 of the source driver 120 , a plurality of pads (at least one pad for the first signal and two or more pads for the second signal) that correspond to and contact each other are present. .

At least one of the plurality of pads (ie, the pad for the first signal) present in each of the film 121 and the source printed circuit board 150 of the source driver 120 has a different width than the other (ie, the pad for the second signal). can

As described above, it is possible to provide the display panel 110 having a stable signal supply structure using a pad wider than other pads.

Meanwhile, as described above, each source driver 120 according to the present embodiments includes a film 121 and a source driver integrated circuit chip 122 mounted on the film 121, It is implemented in an on-film (COF) method.

One side of the film 121 is connected to the display panel 110 and the other side is connected to the source printed circuit board 150 .

In the film 121 , a plurality of pads (at least one pad for a first signal and a plurality of pads for a second signal) in contact with the source printed circuit board 150 are present.

At least one of the plurality of pads on the film 121 (ie, at least one pad for the first signal) has a different width from the other (ie, the plurality of pads for the second signal).

As described above, it is possible to provide the source driver 120 capable of stably supplying a signal using a pad wider than other pads.

Meanwhile, at least one (ie, at least one first signal pad) having a width different from the rest of the plurality of pads on the film 121 may have one or more conductive ball position spaces H such as one or more holes or grooves. .

Here, one or more holes or grooves formed in at least one (that is, at least one pad for the first signal) having a different width from the rest of the plurality of pads on the film 121 may include the film 121 and the source printed circuit board 150 . This is the area where the conductive ball for the pad bonding of the liver can stay.

As described above, by forming one or more holes or grooves in at least one (ie, at least one first signal pad) having a width different from the rest of the plurality of pads on the film 121 , the film 121 and the source printed circuit board During pad bonding between the 150 , more conductive balls can stay, thereby reducing a pad bonding defect between the film 121 and the source printed circuit board 150 , and ensuring high conductivity. .

According to the present exemplary embodiments as described above, it is possible to provide the source driver 120 , the display panel 110 , and the display device 100 having a pad structure that enables stable signal supply.

In addition, according to the present exemplary embodiments, the source driver 120 and the display panel ( 110) and the display device 100 may be provided.

The above description and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains can combine the configuration within a range that does not depart from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: display device
110: display panel
120: source driver
120: film
122: source driver integrated circuit chip
130: gate driver
140: timing controller
150: source printed circuit board
160: control printed circuit board

Claims (10)

a display panel on which a plurality of data lines and a plurality of gate lines are disposed;
source printed circuit board;
a film connected to the display panel on one side and connected to the source printed circuit board on the other side; and
and a source driver integrated circuit chip that outputs a data voltage to the plurality of data lines and is mounted on the film;
In each of the source printed circuit board and the film,
one or more first signal pads to which the driving voltage EVDD supplied to the drain node or the source node of the driving transistor connected to the first electrode of the organic light emitting diode in each sub-pixel is in contact with each other, and is in correspondence with each other, and is in contact with each other; , a lock signal, a gamma signal, or two or more pads for a second signal to which a reference voltage Vref is applied;
The width of the pad for the first signal is wider than the width of the pad for the second signal, and only the pad for the first signal is provided with a plurality of conductive ball location spaces in which conductive balls can stay, and is located in the plurality of conductive ball location spaces. A display device, characterized in that the conductivity between the source printed circuit board and the film is improved by the conductive ball. delete According to claim 1,
The plurality of conductive ball position spaces are arranged in two or more rows and two or more columns. 4. The method of claim 3,
The plurality of conductive ball location spaces
A display device, characterized in that it is arranged only in odd columns or even columns in odd rows, and is arranged only in even columns or odd columns in even rows. According to claim 1,
The plurality of conductive ball position spaces have a bar shape. delete delete a film having one side connected to the display panel and the other side connected to the source printed circuit board; and
a source driver integrated circuit chip mounted on the film;
In the film,
at least one pad for a first signal in contact with the source printed circuit board and to which a driving voltage EVDD supplied to a drain node or a source node of a driving transistor connected to a first electrode of an organic light emitting diode in each sub-pixel is applied; There are two or more pads for second signals that are in contact with the source printed circuit board and to which a lock signal, a gamma signal, or a reference voltage Vref is applied,
The width of the pad for the first signal is wider than the width of the pad for the second signal, and only the pad for the first signal is provided with a plurality of conductive ball location spaces in which conductive balls can stay, and is located in the plurality of conductive ball location spaces. The source driver, characterized in that the conductivity between the source printed circuit board and the film is improved by the conductive ball. delete a substrate on which a plurality of data lines are disposed;
source printed circuit board;
a film connected to the substrate on one side and connected to the source printed circuit board on the other side; and
and a source driver integrated circuit chip that outputs a data voltage to the plurality of data lines and is mounted on the film;
Each of the film and the source printed circuit board,
one or more first signal pads to which the driving voltage EVDD supplied to the drain node or the source node of the driving transistor connected to the first electrode of the organic light emitting diode in each sub-pixel is in contact with each other, and is in correspondence with each other, and is in contact with each other; At least two pads for second signals to which a lock signal, a gamma signal, or a reference voltage Vref are applied;
The width of the pad for the first signal is wider than the width of the pad for the second signal, and only the pad for the first signal is provided with a plurality of conductive ball location spaces in which conductive balls can stay, and is located in the plurality of conductive ball location spaces. A display panel characterized in that conductivity between the source printed circuit board and the film is improved by the conductive ball.

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