KR102300452B1 - Display device - Google Patents

Abstract

An embodiment of the present invention relates to a display device capable of preventing external static electricity from being applied to signal lines in an edge region of one side of a lower substrate to which a chip-on-film on which a driving circuit is mounted is attached in a borderless manner. A display device according to an embodiment of the present invention includes a lower substrate, an upper substrate, signal lines, and a ground line. The upper substrate is disposed on the lower substrate. The signal lines and the ground line are provided on the lower substrate. The ground line is disposed outside the lower substrate than the signal lines. Signal lines not covered by the upper substrate are covered by an insulating layer, and ground lines not covered by the upper substrate are exposed without being covered by the insulating layer.

Description

display device {DISPLAY DEVICE}

An embodiment of the present invention relates to a display device.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms, and in recent years, a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting Various display devices such as a diode display (OLED: Organic Light Emitting Diode) are being used.

Among various display devices, a liquid crystal display includes a display panel, a backlight unit, driving circuits for driving the display panel, a guide for supporting the display panel and the backlight unit, and a case member. The liquid crystal display device may further include an external cover for enclosing the display panel and the backlight unit in order to be finished products such as a notebook computer, a monitor, and a TV.

Recently, in order to enhance aesthetics, the thickness of the liquid crystal display is getting thinner and the bezel area of the liquid crystal display is decreasing. The bezel area of the liquid crystal display is an edge of the liquid crystal display and corresponds to a non-display area covered by an external cover without displaying an image. Recently, in order to minimize the bezel area of the liquid crystal display, a borderless liquid crystal display device in which a top case covering the upper edge of the liquid crystal display panel is removed has been released.

The borderless liquid crystal display device has a disadvantage in that it is vulnerable to external static electricity because the top case is removed. Conventionally, a discharge path is formed using a conductive tape to protect the display panel from external static electricity. However, in this case, an increase in cost may occur due to the addition of the conductive tape. Accordingly, in the related art, a discharge line is formed to surround the edge of the display panel in order to protect the display panel from external static electricity without increasing the cost.

Meanwhile, in a borderless liquid crystal display device, an edge region of one side of a lower substrate to which a chip on film on which a driving circuit is mounted is attached is exposed. The discharge line is also formed in the area of one edge of the exposed lower substrate. However, in the related art, since the discharge lines and signal lines formed on one edge region of the exposed lower substrate are all covered with the insulating film, when external static electricity is applied from the top surface rather than the side surface, the external static electricity is generated from the discharge line and not the discharge line. may be applied to signal lines. That is, when external static electricity is applied from the upper surface, the discharge line does not function properly as a discharge path. When static electricity is applied to the signal lines, the display panel may be damaged.

An embodiment of the present invention provides a display device capable of preventing external static electricity from being applied to signal lines in an edge region of one side of a lower substrate to which a chip-on-film on which a driving circuit is mounted is attached in a borderless manner.

A display device according to an embodiment of the present invention includes a lower substrate, an upper substrate, signal lines, and a ground line. The upper substrate is disposed on the lower substrate. The signal lines and the ground line are provided on the lower substrate. The ground line is disposed outside the lower substrate than the signal lines. Signal lines not covered by the upper substrate are covered by an insulating layer, and ground lines not covered by the upper substrate are exposed without being covered by the insulating layer.

A display device according to another embodiment of the present invention includes a lower substrate, an upper substrate, signal lines, and a ground line. The upper substrate is disposed on the lower substrate. The signal lines and the ground line are provided on the lower substrate. The ground line is disposed outside the lower substrate than the signal lines. Signal lines not covered by the upper substrate are covered by an insulating layer, and ground lines not covered by the upper substrate are exposed without being covered by the insulating layer through a plurality of contact holes.

In the embodiment of the present invention, the signal lines are covered by the insulating film, and all or part of the ground line is not covered by the insulating film. That is, in the embodiment of the present invention, all or part of the ground line is exposed through the contact hole, so that when external static electricity is applied to an area not covered by the upper substrate, it can be discharged through the ground line. As a result, the embodiment of the present invention can prevent external static electricity from being applied to the signal lines. Accordingly, the exemplary embodiment of the present invention can prevent the display panel from being damaged.

In addition, in the embodiment of the present invention, the length of the contact hole is formed to be longer than or equal to the length between the contact holes. For this reason, according to the embodiment of the present invention, external static electricity may be discharged to the ground line through the contact holes without being induced between the contact holes. As a result, the embodiment of the present invention can prevent static electricity from being applied to the signal lines, thereby preventing the display panel from being damaged.

Also, according to an embodiment of the present invention, the lengths of the contact holes of the first group and the lengths of the contact holes of the second group are respectively longer than or equal to the lengths between the contact holes of the first group and the contact holes of the second group. do. Accordingly, according to the embodiment of the present invention, external static electricity may be discharged to the ground line through the contact holes without being induced between the first group of contact holes and the second group of contact holes. As a result, the embodiment of the present invention can prevent static electricity from being applied to the clock lines, thereby preventing the display panel from being damaged.

1 is a perspective view showing a display device according to an embodiment of the present invention;
FIG. 2 is an exploded perspective view of the display device of FIG. 1 ;
FIG. 3 is a cross-sectional view taken along line I-I' of FIG. 1;
4 is a plan view illustrating a lower substrate of a display device according to an exemplary embodiment;
5 is a plan view illustrating a lower substrate of a display device according to another exemplary embodiment;
FIG. 6 is an exemplary view showing the pixels of FIGS. 4 and 5 in detail;
7 is a plan view illustrating an example of a ground pad, a ground line connected thereto, and gate pads and clock lines connected thereto in a region not covered by the upper substrate of FIGS. 4 and 5 ;
FIG. 8 is a cross-sectional view taken along line I-I' of FIG. 7;
9 is a plan view illustrating an example of a ground pad, a ground line connected thereto, and gate pads and clock lines connected thereto in an area not covered by the upper substrate of FIGS. 4 and 5 ;
FIG. 10 is a cross-sectional view showing II-II' of FIG. 9;
11 is a plan view illustrating an example of a ground pad, a ground line connected thereto, and gate pads and clock lines connected thereto in an area not covered by the upper substrate of FIGS. 4 and 5 ;
12 is a cross-sectional view showing III-III' of FIG. 11;

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and thus the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

"X-axis direction", "Y-axis direction" and "Z-axis direction" should not be construed only as a geometric relationship in which the relationship between each other is vertical, and is wider than within the range where the configuration of the present invention can function functionally. It may mean having a direction.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It may mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a perspective view showing a display device according to an embodiment of the present invention. FIG. 2 is an exploded perspective view of the display device of FIG. 1 . FIG. 3 is a cross-sectional view taken along line I-I' of FIG. 1 .

A display device according to an embodiment of the present invention is any one of a liquid crystal display, an organic light emitting display, a field emission display, and an electrophoresis display. It may be implemented as one. 1 to 3, the description has been focused on that the display device according to the embodiment of the present invention is a liquid crystal display device.

1 to 3 , a display device according to an embodiment of the present invention includes a display panel 100 , a driving circuit unit for driving the display panel 100 , a backlight unit 300 , and a case member 400 . include The liquid crystal display according to an embodiment of the present invention may be formed in a borderless manner in which a top case is removed.

The display panel 100 includes a lower substrate 110 , an upper substrate 120 , and a liquid crystal layer interposed between the lower substrate 110 and the upper substrate 120 . The lower substrate 110 and the upper substrate 120 may be formed of glass or plastic.

The size of the lower substrate 110 may be larger than the size of the upper substrate 120 . For this reason, the source flexible films 220 may be attached to one edge of the upper surface of the lower substrate 110 that is not covered by the upper substrate 120 . The upper surface of the lower substrate 110 corresponds to the surface facing the upper substrate 120 .

Signal lines and pixels are provided on the upper surface of the lower substrate 110 of the display panel 100 . The signal lines may include data lines and gate lines crossing each other, a common line for supplying a common voltage to the common electrodes, and gate control signal lines supplied as a control signal to the gate driving circuit. Pixels may be disposed at intersections of data lines and gate lines. Each of the pixels includes a thin film transistor (TFT), a pixel electrode, and a common electrode. The thin film transistor supplies the data voltage of the data line to the pixel electrode in response to the gate signal of the gate line. The liquid crystal of the liquid crystal layer is driven by an electric field generated by a potential difference between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode, and thus the amount of light transmitted from the backlight unit can be adjusted.

A black matrix and a color filter may be provided on a lower surface of the upper substrate 120 of the display panel 100 . A lower surface of the upper substrate 120 corresponds to a surface facing the lower substrate 110 . However, when the display panel 100 is formed by a color filter on TFT array (COT) method, the black matrix and the color filter may be provided on the upper surface of the lower substrate 110 . The common electrode is provided on the lower surface of the upper substrate 120 in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode and It may be provided on the upper surface of the lower substrate 110 in the same horizontal electric field driving method. Also, an alignment layer for setting a pretilt angle of the liquid crystal may be formed on the upper surface of the lower substrate 110 and the lower surface of the upper substrate 120 of the display panel 100 .

A lower polarizing plate 140 is attached to a lower surface of the lower substrate 110 of the display panel 100 . The transparent electrode 130 is formed on the entire upper surface of the upper substrate 120 of the display panel 100 , and the upper polarizing plate 150 is attached on the transparent electrode 130 . The transparent electrode 130 may be connected to a ground to discharge static electricity applied to the upper substrate 120 of the display panel 100 . The lower polarizing plate 140 may be formed in a size smaller than that of the lower substrate 110 , and the upper polarizing plate 150 may be formed in a size smaller than that of the upper substrate 120 .

The driving circuit unit includes a gate driving circuit, source driving circuits 210 , source flexible films 220 , a circuit board 230 , and a light source driving unit 240 .

The gate driving circuit supplies gate signals to the gate lines of the lower substrate 110 . When the gate driving circuit is implemented as a driving chip, it may be mounted on the gate flexible film in a chip on film (COF) method, and the gate flexible films are the lower substrate 110 not covered by the upper substrate 120 . ) can be attached to the edge of the upper surface. Alternatively, the gate driving circuit may be directly formed on the upper surface of the lower substrate 110 by a gate driver in panel (GIP) method. In this case, the gate flexible films may be omitted.

The source driving circuits 210 supply data voltages to the data lines of the lower substrate 110 . When each of the source driving circuits 210 is implemented as a driving chip, they may be mounted on the source flexible film 220 in a chip on film (COF) method. Alternatively, the source driving circuits 210 may be adhered to the upper surface of the lower substrate 110 by a chip on glass (COG) method or a chip on plastic (COP) method. The source flexible films 220 may be attached to one edge of the upper surface of the lower substrate 110 not covered by the upper substrate 120 and to the circuit board 230 . The circuit board 230 may be implemented as a printed circuit board.

The light source driver 240 includes a light source driver circuit 241 and a light source circuit board 242 . The light source driving circuit 240 supplies driving currents to the light sources 310 to emit light. The light source driving circuit 240 may be mounted on the light source circuit board 242 . Alternatively, the light source driving circuit 240 may be mounted on the circuit board 230 , and in this case, the light source circuit board 242 may be omitted.

The driving circuit unit may further include a timing control circuit and a control circuit board on which the timing control circuit is mounted. In this case, the control circuit board may be connected to the circuit board 230 through a predetermined flexible cable.

The backlight unit 300 includes light sources 310 , a light source circuit board 320 , a light guide plate 330 , a reflective sheet 340 , and optical sheets 350 . The backlight unit 300 converts light from the light sources 310 into a uniform surface light source through the light guide plate 320 and the optical sheets 350 to irradiate the display panel 100 with light. 2 and 3 , it should be noted that the backlight unit may be implemented as an edge type, but is not limited thereto, and may be implemented as a direct type.

The light sources 310 may be implemented as light emitting diodes. The light sources 310 are disposed on at least one side surface of the light guide plate 320 to irradiate light to the side surface of the light guide plate 320 . The light sources 310 are mounted on the light source circuit board 320 , and are turned on and off by receiving a driving current from the light source driving circuit 241 . The light source circuit board 320 is connected to the light source driver 240 .

The light guide plate 320 converts light from the light sources 310 into a planar light source and irradiates the light to the display panel 100 . The reflective sheet 340 is disposed on the lower surface of the light guide plate 330 to reflect light from the light guide plate 330 downward of the light guide plate 330 toward the light guide plate 330 .

Optical sheets 345 are disposed between the light guide plate 330 and the display panel 100 . The optical sheets 350 include one or more prism sheets and one or more diffusion sheets to diffuse light incident from the light guide plate 330 and transmit the light at an angle substantially perpendicular to the light incident surface of the display panel 100 . The path of light is refracted so that it is incident. In addition, the optical sheets 350 may include a dual brightness enhancement film.

The case member 400 includes a bottom cover 410 and a support frame 420 .

The bottom cover 410 is made of metal having a rectangular frame and covers the side and lower surfaces of the backlight unit 300 as shown in FIG. 3 . The bottom cover 410 may be made of a high-strength steel sheet, for example, electro-galvanized steel sheet (EGI), stainless steel (SUS), galvalume (SGLC), aluminum-plated steel sheet (aka ALCOSTA), tin-coated steel sheet (SPTE), etc. can be made with

The support frame 420 supports the lower surface of the lower substrate 110 of the display panel 100 . The support frame 420 may be fixed by being coupled to the bottom cover 410 and the fixing member. The support frame 420 may be made of a square frame in which glass fibers are mixed in synthetic resin such as polycarbonate, plastic, or the like, or made of stainless steel (Steel Use Stainless, SUS). Meanwhile, in order to protect the lower substrate 110 of the display panel 100 from being impacted by the support frame 420 , a buffer member 421 is disposed between the lower substrate 110 and the support frame 420 as shown in FIG. 3 . can be provided.

4 is a plan view illustrating a lower substrate of a display device according to an exemplary embodiment. 4 illustrates that the gate driving circuits 111 and 112 are provided on both sides of the display area DA in which the pixels P are formed, but the present invention is not limited thereto. That is, the gate driving circuit may be provided only outside one side of the display area DA. In addition, although FIG. 4 illustrates that the gate driving circuits 111 and 112 are provided on the lower substrate 110 in the GIP method, the present invention is not limited thereto. That is, the gate driving circuits 111 and 112 may be manufactured as a driving chip and mounted on the gate flexible film, and the gate flexible films are the edges of the upper surface of the lower substrate 110 that are not covered by the upper substrate 120 . can be attached to

Referring to FIG. 4 , the data lines DL and the gate lines GL are disposed to cross each other on the upper surface of the lower substrate 110 . Each of the data lines DL is connected to each of the data pads DP. Each of the data lines DL may receive a data voltage through each of the data pads DP. The gate lines GL are connected to the gate driving circuits 111 and 112 . The gate lines GL may receive gate signals from the gate driving circuits 111 and 112 .

The common line CL is disposed parallel to the gate lines GL. The common line CL is bundled together outside both sides of the display area DA and is connected to the common pads CP. The common line CL may receive a common voltage through the common pads CP.

The ground line GDP is formed outside the common line CL and the gate drivers 111 and 112 . That is, the ground line GDP is formed at the outermost portion of the lower substrate 110 . The ground line GDP is connected to the ground pads GDP and may receive a ground voltage through the ground pads GDP.

The ground pads GDP are connected to the ground line GNDL, and the common pads CP are connected to the common line CL. The gate pads GP are connected to gate control signal lines GCL connected to the gate driving circuits 111 and 112 . The gate control signal lines GCL may include a start signal line for supplying a start signal and clock lines for supplying clock signals. The data pads DP are connected to the data lines DL.

Ground pads GDP, common pads CP, gate pads GP, and data pads DP may be formed in the area NCA not covered by the upper substrate 120 . Accordingly, the ground pads GDP, common pads CP, gate pads GP, and data pads DP may be exposed without being covered by the upper substrate 120 . In addition, a portion of the ground line GNDL connected to the ground pads GDP, a portion of the common line CL connected to the common pad CP, and the gate control signal line GCL connected to the gate pads GP ) and a portion of the data lines DL connected to the data pads DP are formed in the area NCA not covered by the upper substrate 120 , and thus are not covered by the upper substrate 120 . may be exposed.

In the display area DA, pixels P are provided at intersections of the data lines DL and the gate lines GL. The pixel P may be connected to a gate line GL and a data line DL different from the pixel P adjacent thereto as shown in FIG. 4 .

Each of the pixels P is connected to one data line DL, one gate line GL, and a common line CL. Each of the pixels P includes a thin film transistor T, a pixel electrode 11 , a common electrode 12 , and a liquid crystal cell 13 as shown in FIG. 6 . The thin film transistor T supplies the data voltage of the data line DL to the pixel electrode 11 in response to the gate signal of the gate line GL. The liquid crystal of the liquid crystal cell 13 is driven by an electric field generated by the potential difference between the data voltage supplied to the pixel electrode 11 and the common voltage supplied to the common electrode 12 , and thereby the light incident from the backlight unit is reduced. The amount of transmission can be adjusted.

5 is a plan view illustrating a lower substrate of a display device according to another exemplary embodiment of the present invention. The data lines DL, gate lines GL, common line CL, and ground line GNL shown in FIG. 5 are substantially the same as those shown in FIG. 4 , and thus detailed descriptions thereof will be omitted. do. In addition, the gate driving circuits 111 and 112 , the ground pad GDP, the gate pads GP, the common pad CP, the data pads DP, and the gate control signal line GCL shown in FIG. 5 . Since they are substantially the same as those shown in FIG. 4 , detailed descriptions thereof will be omitted.

Referring to FIG. 5 , in the display area DA, pixels P are provided at intersections of the data lines DL and the gate lines GL. The pixels P may be arranged as shown in FIG. 5 to drive in a double ratio driving (DRD) method. In the DRD method, pixels P adjacent to each other in the direction of the gate line GL may be connected to the same data line DL. Also, in the DRD method, pixels P adjacent to each other in the gate line GL direction and connected to the same data line DL may be connected to different gate lines GL. Accordingly, in the DRD method, two pixels P adjacent to each other in the direction of the gate line GL may receive the data voltage using one data line DL. ) method, the number of data lines DL can be reduced by half. For this reason, the DRD method can reduce the number of source driving circuits by half compared to the general driving method.

Meanwhile, in the DRD method, since the number of source driving circuits is reduced by half, the length of the common line CL and the length of the gate control signal lines GCL that are not covered by the upper substrate 120 and the length of the gate control signal lines GCL is the general driving method. can be further increased. In this case, if a discharge path to the ground line GNDL is not made, the probability that external static electricity is applied to the common line CL and the gate control signal lines GCL increases. Therefore, the embodiment of the present invention is essential in the DRD method. However, the embodiment of the present invention may be applied not only to the DRD method but also to the general driving method.

Each of the pixels P is connected to one data line DL, one gate line GL, and a common line CL. Each of the pixels P includes a thin film transistor T, a pixel electrode 11 , a common electrode 12 , and a liquid crystal cell 13 as shown in FIG. 6 . The thin film transistor T supplies the data voltage of the data line DL to the pixel electrode 11 in response to the gate signal of the gate line GL. The liquid crystal of the liquid crystal cell 13 is driven by an electric field generated by the potential difference between the data voltage supplied to the pixel electrode 11 and the common voltage supplied to the common electrode 12 , and thereby the light incident from the backlight unit is reduced. The amount of transmission can be adjusted.

7 is a plan view illustrating an example of a ground pad, a ground line connected thereto, and gate pads and clock lines connected thereto in a region not covered by the upper substrate of FIGS. 4 and 5 . FIG. 8 is a cross-sectional view taken along line I-I' of FIG. 7 . Hereinafter, the ground pad, the ground line and gate pads connected thereto, and the clock lines connected thereto according to an embodiment of the present invention will be described in detail with reference to FIGS. 7 and 8 .

7 and 8 illustrate the clock lines CL1 to CL6 connected to the gate pads GP as lines adjacent to the ground line GNL connected to the ground pad GDP, but the present invention is not limited thereto. That is, lines adjacent to the ground line GNL connected to the ground pad GDP are connected to other gate control signal lines such as the start signal line, the common line connected to the common pad CP, and the data pads DP. It may be other signal lines such as the data lines DL.

7 and 8 , the ground line GNDL is connected to the ground pad GDP, and the clock lines CL1 to CL6 are connected to the gate pads GP. The ground line GNDL receives a ground voltage through the ground pad GDP. The clock lines CL1 to CL6 may receive clock signals whose phases are sequentially delayed through the gate pads GP.

The ground line GNDL is disposed at an edge of the lower substrate 110 rather than the clock lines CL1 to CL6 . Each of the ground line GNDL and the clock lines CL1 to CL6 is spaced apart from the line(s) adjacent thereto by a predetermined distance. In order to stably supply the ground voltage to the ground line GNLD, the width of the ground line GNLD may be wider than the width of each of the clock lines CL1 to CL6 .

As shown in FIG. 8 , the ground line GNDL and the clock lines CL1 to CL6 may be formed of the same metal as the gate line GL on the lower substrate 110 . The clock lines CL1 to CL6 are covered by the insulating layer GI and the passivation layer PAS, but all of the ground lines GNDL are not covered by the insulating layer GI and the passivation layer PAS. The clock lines CL1 to CL6 may be protected because they are covered by the insulating layer GI and the passivation layer PAS. Also, since the ground line GNDL is not covered by the insulating layer GI and the passivation layer PAS, when external static electricity is applied to an area not covered by the upper substrate, it may be discharged through the ground line GNDL. . For this reason, the embodiment of the present invention may prevent external static electricity from being applied to signal lines such as the clock lines CL1 to CL6. Accordingly, the exemplary embodiment of the present invention can prevent the display panel from being damaged.

9 is a plan view illustrating an example of a ground pad, a ground line connected thereto, and gate pads and clock lines connected thereto in a region not covered by the upper substrate of FIGS. 4 and 5 . FIG. 10 is a cross-sectional view taken along line II-II' of FIG. 9 . Hereinafter, the ground pad, the ground line and gate pads connected thereto, and the clock lines connected thereto according to another embodiment of the present invention will be described in detail with reference to FIGS. 9 and 10 .

9 and 10 illustrate the clock lines CL1 to CL6 connected to the gate pads GP as lines adjacent to the ground line GNL connected to the ground pad GDP, but the present invention is not limited thereto. That is, lines adjacent to the ground line GNL connected to the ground pad GDP are connected to other gate control signal lines such as the start signal line, the common line connected to the common pad CP, and the data pads DP. It may be other signal lines such as the data lines DL.

9 and 10 , the ground line GNDL is connected to the ground pad GDP, and the clock lines CL1 to CL6 are connected to the gate pads GP. The ground line GNDL receives a ground voltage through the ground pad GDP. The clock lines CL1 to CL6 may receive clock signals whose phases are sequentially delayed through the gate pads GP.

The ground line GNDL is disposed at an edge of the lower substrate 110 rather than the clock lines CL1 to CL6 . Each of the ground line GNDL and the clock lines CL1 to CL6 is spaced apart from the line(s) adjacent thereto by a predetermined distance. In order to stably supply the ground voltage to the ground line GNLD, the width of the ground line GNLD may be wider than the width of each of the clock lines CL1 to CL6 .

10 , the ground line GNDL and the clock lines CL1 to CL6 may be formed of the same metal as the gate line GL on the lower substrate 110 . The clock lines CL1 to CL6 are covered by the insulating layer GI and the passivation layer PAS, but a part of the ground line GNDL is exposed by the contact holes CNT to the insulating layer GI and the passivation layer PAS. not covered by The clock lines CL1 to CL6 may be protected because they are covered by the insulating layer GI and the passivation layer PAS. Also, since a portion of the ground line GNDL is not covered by the insulating layer GI and the passivation layer PAS by the contact holes CNTs, when external static electricity is applied to an area not covered by the upper substrate, the ground It may be discharged through the line GNDL. For this reason, the embodiment of the present invention may prevent external static electricity from being applied to signal lines such as the clock lines CL1 to CL6. Accordingly, the exemplary embodiment of the present invention can prevent the display panel from being damaged.

On the other hand, when the length w1 of the contact holes CNT is shorter than the length w2 between the contact holes CNT, when external static electricity is applied between the contact holes CNT, through the contact holes CNTs. The possibility of being induced without being discharged to the ground line GNDL increases. Static electricity induced without being discharged to the ground line GNDL may be applied to the clock lines CL1 to CL6 . Accordingly, in the embodiment of the present invention, the length w1 of the contact holes CNT is longer than or equal to the length w2 between the contact holes CNT. For this reason, in the embodiment of the present invention, external static electricity is discharged to the ground line GNDL through the contact holes CNT without being induced between the contact holes CNT, so that static electricity is transferred to the clock lines CL1 ~CL6) can be prevented from being applied.

Also, as the area of the ground line GNDL exposed due to the contact holes CNTs increases, the probability of being discharged through the ground line GNDL when external static electricity is applied increases. However, a ground voltage is not supplied to the ground line GNDL during the manufacturing process of the lower substrate 110 . Accordingly, during the manufacturing process of the lower substrate 110 , the ground line GNDL does not function as a discharge path. Accordingly, as the area of the ground line GNDL exposed due to the contact holes CNT decreases, when external static electricity is applied to the ground line GNDL during the manufacturing process of the lower substrate 110 , the ground line GNDL becomes smaller. It may be less likely to be damaged. Therefore, the exposed area of the ground line GNDL may be set in consideration of whether static electricity is often applied during a manufacturing process or static electricity is often applied to a finished product.

11 is a plan view illustrating an example of a ground pad, a ground line connected thereto, and gate pads and clock lines connected thereto in a region not covered by the upper substrate of FIGS. 4 and 5 . 12 is a cross-sectional view showing III-III' of FIG. 11 . Hereinafter, the ground pad, the ground line and gate pads connected thereto, and the clock lines connected thereto according to another embodiment of the present invention will be described in detail with reference to FIGS. 11 and 12 .

11 and 12 illustrate the clock lines CL1 to CL6 connected to the gate pads GP as lines adjacent to the ground line GNL connected to the ground pad GDP, but the present invention is not limited thereto. That is, lines adjacent to the ground line GNL connected to the ground pad GDP are connected to other gate control signal lines such as the start signal line, the common line connected to the common pad CP, and the data pads DP. It may be other signal lines such as the data lines DL.

11 and 12 , the ground line GNDL is connected to the ground pad GDP, and the clock lines CL1 to CL6 are connected to the gate pads GP. The ground line GNDL receives a ground voltage through the ground pad GDP. The clock lines CL1 to CL6 may receive clock signals whose phases are sequentially delayed through the gate pads GP.

The ground line GNDL is disposed at an edge of the lower substrate 110 rather than the clock lines CL1 to CL6 . Each of the ground line GNDL and the clock lines CL1 to CL6 is spaced apart from the line(s) adjacent thereto by a predetermined distance. In order to stably supply the ground voltage to the ground line GNLD, the width of the ground line GNLD may be wider than the width of each of the clock lines CL1 to CL6 .

12 , the ground line GNDL and the clock lines CL1 to CL6 may be formed of the same metal as the gate line GL on the lower substrate 110 . The clock lines CL1 to CL6 are covered by the insulating layer GI and the passivation layer PAS, but a part of the ground line GNDL is exposed by the contact holes CNT to the insulating layer GI and the passivation layer PAS. not covered by The clock lines CL1 to CL6 may be protected because they are covered by the insulating layer GI and the passivation layer PAS. In addition, since a portion of the ground line GNDL is not covered by the insulating layer GI and the passivation layer PAS by the contact hole CNT, when external static electricity is applied to an area not covered by the upper substrate, the ground line (GNDL) can be discharged. For this reason, the embodiment of the present invention may prevent external static electricity from being applied to signal lines such as the clock lines CL1 to CL6. Accordingly, the exemplary embodiment of the present invention can prevent the display panel from being damaged.

Meanwhile, the contact holes CNT may be divided into a first group of contact holes G1_CNT and a second group of contact holes G2 to CNT. The length w3 of the first group of contact holes G1_CNT and the length of the second group of contact holes G2_CNT are respectively the first group of contact holes G1_CNT and the second group of contact holes G2_CNT. ) is preferably longer than or equal to the length between them. The length w3 of the first group of contact holes G1_CNT and the length of the second group of contact holes G2_CNT are respectively the first group of contact holes G1_CNT and the second group of contact holes G2_CNT. ), when external static electricity is applied between the first group of contact holes G1_CNT and the second group of contact holes G2_CNT, through the contact holes CNT to the ground line GNDL. It is more likely to be induced without being discharged. Static electricity induced without being discharged to the ground line GNDL may be applied to the clock lines CL1 to CL6 . Accordingly, according to the embodiment of the present invention, the length w3 of the first group of contact holes G1_CNT and the length of the second group of contact holes G2_CNT are respectively the first group of contact holes G1_CNT and the second group of contact holes G1_CNT. The length between the two groups of contact holes G2_CNT is equal to or longer than the length between them. For this reason, in the embodiment of the present invention, external static electricity is not induced between the first group of contact holes G1_CNT and the second group of contact holes G2_CNT, and the ground line GNDL passes through the contact holes CNT. ), it is possible to prevent static electricity from being applied to the clock lines CL1 to CL6. In this case, the length of the contact hole CNT in each of the first group of contact holes G1_CNT and the second group of contact holes G2_CNT is preferably longer than or equal to the length between the contact holes CNT. do.

Also, as the area of the ground line GNDL exposed due to the contact holes CNTs increases, the probability of being discharged through the ground line GNDL when external static electricity is applied increases. However, a ground voltage is not supplied to the ground line GNDL during the manufacturing process of the lower substrate 110 . Accordingly, during the manufacturing process of the lower substrate 110 , the ground line GNDL does not function as a discharge path. Accordingly, as the area of the ground line GNDL exposed due to the contact holes CNT decreases, when external static electricity is applied to the ground line GNDL during the manufacturing process of the lower substrate 110 , the ground line GNDL becomes smaller. It may be less likely to be damaged. Therefore, the exposed area of the ground line GNDL may be set in consideration of whether static electricity is often applied during a manufacturing process or static electricity is often applied to a finished product.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: lower substrate
120: upper substrate 130: transparent electrode
140: lower polarizing plate 150: upper polarizing plate
210: source driving circuit 220: source flexible film
230: circuit board 240: light source driver
241: light source driving circuit 242: light source circuit board
300: backlight unit 310: light source
320: light source circuit board 330: light guide plate
340: reflective sheet 350: optical sheets
400: case member 410: bottom cover
420: support frame

Claims (12)

lower substrate;
an upper substrate having a size smaller than that of the lower substrate and covering the lower substrate;
signal lines provided on the lower substrate; and
a ground line provided on the lower substrate and disposed outside the lower substrate than the signal lines;
one edge of the lower substrate is exposed without being covered by the upper substrate, and includes pads connected to each of the signal lines and the ground line;
At one edge of the lower substrate, a portion of the signal lines is covered by an insulating layer, and all or a part of the ground line is not covered by the insulating layer and is exposed on the lower substrate. lower substrate;
an upper substrate having a size smaller than that of the lower substrate and covering the lower substrate;
signal lines provided on the lower substrate; and
a ground line provided on the lower substrate and disposed outside the lower substrate than the signal lines;
one edge of the lower substrate is exposed without being covered by the upper substrate, and includes pads connected to each of the signal lines and the ground line;
At one edge of the lower substrate, the signal lines are covered by an insulating layer, and all or part of the ground line is exposed on the lower substrate through a plurality of contact holes formed in the insulating layer. 3. The method of claim 2,
A length of any one of the plurality of contact holes is greater than or equal to a length between the one of the contact holes and a contact hole adjacent thereto. 3. The method of claim 2,
The plurality of contact holes are divided into a first group of contact holes and a second group of contact holes adjacent thereto. 5. The method of claim 4,
A length of the first group of contact holes is greater than or equal to a length between the first group of contact holes and the second group of contact holes. 3. The method according to claim 1 or 2,
gate lines provided on the lower substrate; and
Further comprising a gate driver for outputting gate signals to the gate lines,
The signal lines are connected to the gate driver. 7. The method of claim 6,
data lines provided on the lower substrate and intersecting the gate lines; and
Further comprising pixels provided in the intersection region of the data lines and the gate lines,
Pixels adjacent to each other in the gate line direction are connected to one of the data lines and connected to different gate lines.
3. The method according to claim 1 or 2,
The external static electricity applied to one edge of the lower substrate is discharged through all or part of the ground line exposed on the lower substrate without being covered by the insulating layer. lower substrate; and
an upper substrate disposed on the lower substrate;
The lower substrate is
an area covered by the upper substrate;
an exposed area not covered by the upper substrate;
It includes a plurality of signal lines provided on the exposed area,
The plurality of signal lines include a common line connected to a common pad, a data line connected to the data pad, a gate control signal line connected to the gate pad, and a ground line connected to the ground pad,
the ground line is adjacent to one of the common line, the data line, and the gate control signal line, the ground line is spaced apart from each other by a predetermined distance, and is disposed outside the lower substrate;
All or part of the ground line is not covered by an insulating layer and is exposed on the lower substrate. 10. The method of claim 9,
A width of the ground line is wider than a width of the adjacent signal line. 10. The method of claim 9,
a signal line adjacent to the ground line among the plurality of signal lines is the gate control signal line;
The ground line is disposed at an edge of the lower substrate than the gate control signal line. 12. The method according to any one of claims 9 to 11,
The external static electricity applied to the exposed area is discharged through all or a part of the ground line exposed on the lower substrate without being covered by the insulating layer.

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