KR102299155B1 - Organic Light Emitting Diode - Google Patents

Abstract

As a means for solving the above problems, the organic light emitting diode display device of the present invention includes a driving transistor and a driving transistor for controlling a driving current provided to the organic light emitting diode by receiving a high potential voltage received from an organic light emitting diode and a high potential voltage source as a drain electrode. a first transistor positioned between the drain electrode and the high potential voltage source and connecting the high potential voltage source and the drain electrode of the driving transistor in response to the emission control signal provided to the gate electrode; and a stage outputting the emission control signal. The stage includes a scan signal generator and a light emission control signal generator. The light emission control signal generator receives a variable voltage that maintains a low potential voltage from after power input to before the image display period through the variable voltage terminal, and outputs the variable voltage in response to the emission clock.

Description

Organic light emitting diode display {Organic Light Emitting Diode}

The present invention relates to an organic light emitting diode display.

Flat panel displays (FPDs) are widely used in portable computers such as notebook computers and PDAs, mobile phone terminals, etc. as well as monitors of desktop computers due to their advantages in miniaturization and weight reduction. Such a flat panel display device is a liquid crystal display device; LCD), Plasma Display Panel (PDP), Field Emission Display; FED) and an organic light emitting diode display (OLED).

Among them, the organic light emitting diode display has advantages of fast response speed, high luminance efficiency, and a large viewing angle. In general, an organic light emitting diode display applies a data voltage to a gate electrode of a driving transistor using a transistor turned on by a scan signal, and charges the data voltage supplied to the driving transistor to a storage capacitor. Then, the organic light emitting diode emits light by outputting the data voltage charged in the storage capacitor using the light emission control signal.

In a power-off state, the driving transistor of the organic light emitting diode display and the initial state of the organic light emitting diodes may be different from each other. At the moment when the pixels are powered on, the driving transistor operates even before normal data is provided, so that the organic light emitting diode display device may undesirably emit light. Therefore, before the display panel displays a normal image, the panel may partially flicker.

The present invention for solving the problems of the above-described background art is to provide an organic light emitting diode display device for improving the occurrence of flickering on the screen before the normal image display.

As a means for solving the above problems, the organic light emitting diode display device of the present invention includes a driving transistor and a driving transistor for controlling a driving current provided to the organic light emitting diode by receiving a high potential voltage provided from an organic light emitting diode and a high potential voltage source as a drain electrode. a first transistor positioned between the drain electrode and the high potential voltage source and connecting the high potential voltage source and the drain electrode of the driving transistor in response to the emission control signal provided to the gate electrode; and a stage outputting the emission control signal. The stage includes a scan signal generator and a light emission control signal generator. The light emission control signal generator receives a variable voltage maintaining a low potential voltage from after power input to before the image display period through the variable voltage terminal, and outputs the variable voltage in response to the emission clock.

The present invention can prevent the organic light emitting diode from emitting light even when the driving transistor operates by maintaining the light emission control signal at a low potential level from after power is supplied to before the image display period.

1 is a view showing the configuration of an organic light emitting diode display according to the present invention.
FIG. 2 is a view showing an example of the pixel structure shown in FIG. 1;
3 is a diagram illustrating a power-on sequence according to the present invention;
4 is a diagram showing a power-off sequence according to the present invention;
FIG. 5 is a diagram illustrating timings of a scan signal and an emission control signal for driving the pixel shown in FIG. 2;
6 is a circuit configuration diagram of an i-th stage according to the present invention.
FIG. 7 is an operation timing diagram of an i-th stage shown in FIG. 6 ;

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

1 is a block diagram showing the configuration of a display device according to the present invention.

Referring to FIG. 1 , the display device according to the present invention includes a display panel 100 , a timing controller 110 , a data driver 120 , and scan drivers 130 and 140 .

The display panel 10 includes a display area 100A in which sub-pixels are formed and a non-display area 100B in which various signal lines or pads are formed outside the display area 100A. The display area 100A includes a plurality of pixels P, and displays an image based on a gray level displayed by each pixel P. A plurality of pixels P are arranged in a matrix form on each of the horizontal lines. Each of the pixels P is connected to the data line part DL and the gate line part GL orthogonal to each other. The data line part DL connected to each pixel P includes an initialization line 14a and a data line 14b, and the gate line part GL includes a previous gate line 15a and a current gate line 14a. 15b) and an emission line 15c. Each of the pixels P includes an organic light emitting diode OLED, a driving transistor DT, first to third transistors T1, T2, and T3, a storage capacitor Cst, and an auxiliary capacitor Csub. The driving transistor DT and the first to third transistors T1, T2, and T3 may be implemented as an oxide thin film transistor (hereinafter, TFT) including an oxide semiconductor layer.

The timing controller 110 provides timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a dot clock (DLCK) through an LVDS or MIPI interface receiving circuit connected to the image board. is input. The timing controller T110 includes a data control signal DDC for controlling the operation timing of the data driver 120 based on the input timing signal and a gate control signal GDC for controlling the operation timing of the scan driver 130 and 140 . create

The data driver 120 includes a plurality of source drive integrated circuits (ICs). The source drive ICs receive digital video data RGB and a source timing control signal DDC from the timing controller 110 . The source drive ICs generate a data voltage by converting the digital video data RGB into a gamma voltage in response to the source timing control signal DDC, and transmit the data voltage through the data lines DL of the display panel 100 . supply

The scan drivers 130 and 140 include a level shifter 130 and a shift register 140 . In the scan driver 130 , the level shifter 130 and the shift register 140 are separated, and the shift register 140 is formed in the non-display area 100B of the display panel 100 . Panel; hereinafter GIP) is formed.

The level shifter 130 is formed on a printed circuit board (not shown) connected to the display panel 100 in the form of an IC. The level shifter 130 level-shifts the clock signals CLK and the start signal VST under the control of the timing controller 11 , and then supplies them to the shift register 140 . The shift register 140 is formed by a combination of a plurality of thin film transistors (hereinafter, TFTs) in the non-display area 100B of the display panel 100 by the GIP method. The shift register 140 includes stages that shift and output the scan signal in response to the clock signals CLK and the start signal VST. The stages included in the shift register 140 sequentially output the scan signal Scan and the emission control signal EM through output terminals.

FIG. 2 is a diagram illustrating an example of the pixel P shown in FIG. 1 .

Referring to FIG. 2 , a pixel P according to an embodiment of the present invention includes an organic light emitting diode (OLED), a driving transistor DT, first to third transistors T1 to T3, a storage capacitor Cst, and An auxiliary capacitor Csub is provided.

The organic light emitting diode OLED emits light by a driving current supplied from the driving transistor DT. A multi-layered organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode (OLED). The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL). The anode electrode of the organic light emitting diode OLED is connected to the source electrode of the driving transistor DT, and the cathode electrode is connected to the ground terminal VSS.

The driving transistor DT controls a driving current applied to the organic light emitting diode OLED by its gate-source voltage. To this end, the gate electrode of the driving transistor DT is connected to the input terminal of the data voltage Vdata, the drain electrode is connected to the input terminal of the driving voltage VDD, and the source electrode is connected to the low voltage driving voltage VSS.

The first transistor T1 controls a current path between the driving voltage VDD input terminal and the driving transistor DT in response to the emission control signal EM. To this end, the gate electrode of the first transistor ST1 is connected to the emission line EL, the drain electrode is connected to the driving voltage VDD input terminal, and the source electrode is connected to the driving transistor DT.

The second transistor T2 provides the initialization voltage Vini received from the initialization line 14a to the second node n2 in response to the previous stage scan signal Scan(n-1). To this end, the gate electrode of the second transistor T2 is connected to the previous gate line GL[n-1], the drain electrode is connected to the initialization line 14a, and the source electrode is connected to the second node n2.

The third transistor 1T3 provides the reference voltage Vref or the data voltage Vdata received from the data line 14b to the driving transistor DT in response to the current stage scan signal Scan(n). To this end, the gate electrode of the third transistor T3 is connected to the current gate line GLn, the drain electrode is connected to the data line 14b, and the source electrode is connected to the driving transistor DT.

The storage capacitor Cst maintains the data voltage Vdata received from the data line 14b for one frame so that the driving transistor DT maintains a constant voltage. To this end, the storage capacitor Cst is connected to the gate electrode and the source electrode of the driving transistor DT. The auxiliary capacitor Csub is connected in series with the storage capacitor Cst at the second node n2 to increase the efficiency of the data voltage Vdata.

3 is a diagram illustrating a power-on sequence according to the present invention.

Referring to FIG. 3 , the reference voltage Vref of the organic light emitting diode display maintains the ground voltage GND during the driving preparation period after being powered on. And the reference voltage Vref maintains the reference voltage level during the image display period. The reference voltage level may vary depending on the panel, and may be, for example, a voltage level of 3V.

The initialization voltage Vini maintains the base voltage GND during the driving preparation period. In addition, the initialization voltage Vini maintains the initialization voltage level during the image display period. The initialization voltage level may be a negative (-) bias voltage.

The data driver 120 does not output the data voltage Data during the driving preparation period, but outputs the data voltage Data during the image display period.

The scan signal SCAN is not output during the driving preparation period, but is output during the image display period. The scan signal SCAN may be output during the scan period at the beginning of each image frame.

The light emission control signal EM is not output during the driving preparation period, but is output during the image display period. The emission control signal EM is output during the emission period of each image frame and provided to the gate electrode of the first transistor T1 shown in FIG. 2 .

Since the emission control signal EM is not output during the driving preparation period, the drain electrode of the driving transistor DT shown in FIG. 2 does not receive the high potential voltage VDD during the driving preparation period. Accordingly, during the driving preparation period, even if the driving transistor DT operates unintentionally, the high potential voltage VDD is not provided to the organic light emitting diode OLED. That is, since the organic light emitting diode OLED does not emit light regardless of whether the driving transistor DT is in operation during the driving preparation period, it is possible to prevent flickering in the display panel before the image display period.

In order to prevent the emission control signal EM from being output during the driving preparation period, the stage outputting the emission control signal EM is provided with a low potential voltage during the driving preparation period. The variable voltage VAC provided to the stage during the driving preparation period will be described later.

4 is a diagram illustrating a power-off sequence according to the present invention.

According to the power-off sequence according to the present invention, the reference voltage Vref and the initialization voltage Vini are lowered to the ground voltage GND when the power is turned off. The reference voltage Vref and the initialization voltage Vini may be synchronized with the Display Off signal or the Sleep In State signal, or may be lowered after a predetermined period of time after the Display Off signal or the Sleep In State signal is applied.

When the power is turned off, the emission control signal EM is lowered to a low potential voltage level after a certain period of time has elapsed. A voltage level of the emission control signal may be lowered in synchronization with a sleep mode control signal (sleep in state).

The data driver 120 outputs a black data voltage for a predetermined period after power-off, for example, one frame or more, and the scan drivers 130 and 140 are provided to the pixel P while the black data voltage is output. . Accordingly, for a predetermined period after power-off, the gate electrode n1 of the driving transistor DT is initialized.

The operation of the pixel P during the image display period in such an organic light emitting diode display device is as follows. FIG. 5 is a waveform diagram illustrating signals EM, SCAN, INIT, and DATA applied to the pixel P of FIG. 2 and potential changes of the gate electrode and the source electrode of the driving transistor DT accordingly.

Referring to FIG. 5 , the operation of the pixel P according to the present invention includes an initialization period Ti in which the gate-source potential of the driving transistor DT is initialized to a specific voltage, and the threshold voltage of the driving transistor DT is detected and The sampling period (Ts) for storing, the writing period (Tw) for applying the data voltage (Vdata), and the driving current applied to the organic light emitting diode (OLED) using the threshold voltage and the data voltage (Vdata) are irrespective of the threshold voltage. It includes a light emission period Te for compensating for light emission.

During the initialization period Ti, the second transistor T2 supplies the initialization voltage Vini received from the initialization line 14a to the second node n2 in response to the previous stage scan signal Scan[n-1]. do. Accordingly, the source voltage Vs of the driving transistor DT, which is the voltage of the second node n2, has a potential of the initialization voltage Vini. In addition, the third transistor T3 applies the reference voltage Vref received from the data line 14b in response to the current stage scan signal Scan[n] to the first node n1 of the gate electrode of the driving transistor DT. supply to Accordingly, the gate voltage Vg of the driving transistor DT, which is the voltage of the first node n1, has a potential of the reference voltage Vref.

The initialization voltage Vini supplied to the second node n2 in the initialization period Ti is to initialize the pixel P to a certain level, and in this case, the magnitude of the initialization voltage Vini is determined by the organic light emitting diode OLED. It is set to a voltage value smaller than the operating voltage of the organic light emitting diode (OLED) so as not to emit light. For example, the initialization voltage Vini may be set to a voltage having a magnitude of -1 to +1 (V).

During the sampling period Ts, the third transistor T3 supplies the reference voltage Vref received from the data line 14b to the first node n1 in response to the current stage scan signal Scan[n]. . In addition, the first transistor T1 supplies the driving voltage EVDD to the driving transistor DT in response to the emission control signal EM. At this time, the driving transistor gate electrode voltage Vg maintains the reference voltage Vref. In addition, as the second node n2 is in a floating state, the voltage of the second node n2 accumulates current flowing through the first transistor T1 and the driving transistor DT from the driving voltage EVDD. do. The voltage increased through the sampling period Ts is saturated with a voltage having a magnitude corresponding to the difference between the reference voltage Vref and the threshold voltage Vth of the driving transistor DT. That is, through the sampling period Ts, the potential difference between the gate and the source of the driving transistor DT becomes the threshold voltage Vth.

During the writing period Tw, the first and second transistors T1 and T2 are turned off. Then, the third transistor T3 is turned on and supplies the data voltage Vdata received from the data line 14b to the first node n1. At this time, the voltage of the second node n2 in the floating state is coupled by the ratio of the storage capacitor Cs and the auxiliary capacitor Csub to rise or fall.

During the light emission period Te, the second transistor T2 is turned off, the third transistor T3 is turned off, and the first transistor T1 is turned on. During the light emission period, the data voltage Vdata stored in the storage capacitor Cs is supplied to the organic light emitting diode OLED, and accordingly, the organic light emitting diode OLED emits light with a brightness proportional to the data voltage Vdata. At this time, a current flows in the driving transistor DT by the voltages of the first node n1 and the second node 2 determined in the writing period Tw, and a desired current is supplied to the organic light emitting diode (OLED). Therefore, the organic light emitting diode (OLED) can adjust the brightness by the data voltage (Vdata).

6 is a circuit configuration diagram of an i-th stage according to the present invention.

Referring to FIG. 6 , the shift register 140 according to the present invention includes a plurality of stages STG[1] to STG[i]. Each of the stages STG[1] to STG[i] uses five-phase gate clocks GCLK1 to GCLK5, five-phase emission clocks ECLK1 to ECLK5, a low potential voltage and a start signal VST. A scan signal Scan and an emission control signal EM are output.

The scan signal generator 140a of the ith stage STG[i] includes a start signal VST or G[i-1], an ith gate clock GCLKi, and a (i+2)th gate clock GCLK[ i+2]) and the (i+3)th gate clock GCLK[i+3] to generate the i-th scan signal Scani.

The ith gate clock GCLKi input to the ith stage STG[i] determines the output period of the ith scan signal Scani. The (i+2)th gate clock GCLK[i+2] determines the end time of the i-th scan signal Scani, and the (i+4)th gate clock GCLK[i+4]) An operation of charging the first Q node Q is performed before the output of the scan signal Scani.

The emission control signal generator 140b of the ith stage STG[i] generates an ith scan signal Scani, an ith emission clock ECLKi, and an (i+2)th emission clock ECLK[i+. 2]), the ith emission control signal EMi using the (i+1)th emission clock ECLK[i+1] and the (i+4)th emission clock ECLK[i+4]. create

The ith emission clock ECLKi input to the ith stage STG[i] determines the output timing of the ith emission control signal EMi. The (i+2)th emission clock ECLK[i+2] determines the end time of the emission control signal EM output in the previous frame. The (i+1)th emission clock ECLK[i+1] and the (i+4)th emission clock ECLK[i+4] are configured so that the i-th emission control signal EMi maintains a high level. Control.

In an embodiment of the present invention, the gate clock GCLK and the emission clock ECLK are implemented in five phases, and each clock signal is continuous. Accordingly, a clock signal having (i+k) (k is a natural number 1<k<5) greater than 5 uses an ordinal clock signal obtained by subtracting 5. For example, in the third stage STG3 , the (i+4)th gate clock GCLK[i+4] corresponds to the second gate clock GCLK2.

Due to this regularity, the scan signal generator 140a of the first stage STG1 generates the start signal VST, the first gate clock GCLK1, the third gate clock GCLK3, and the fifth gate clock GCLK5. is used to output the first scan signal Scan1. In addition, the emission control signal generator 140b of the first stage STG1 generates a first scan signal Scan1, a first emission clock ECLK1, a second emission clock ECLK2, and a third emission clock ECLK3. ) and the fifth emission clock ECLK5 to output the first emission control signal EM1. Also, the emission control signal generator 140b of the first stage STG1 initializes the first emission control signal EM1 using the emission reset ERST.

The plurality of stages STG[1] to STG[i] are dependently connected so that the rear end uses the scan signal output from the output end of the previous stage. For example, the scan signal G[i] output from the i-th stage STG[i] is supplied to the input terminal of the start signal VST of the (i+1)-th stage STG[i+1].

A detailed circuit configuration of the i-th stage STG[i] is as follows. In FIG. 6 , the auxiliary transistors Tbv, which always maintain the turn-on state by the high potential voltage VDD, are for circuit stabilization, and since the auxiliary transistors Tbv always maintain the turn-on state, the equivalent circuit is It will be described as a short-circuit condition.

The scan signal generator 140a of the i-th stage STG[i] uses the clock signals input through the first to fourth terminals 4 to output the first to fourth scan signals Scani as the i-th scan signal Scani. and eighth transistors T101 to T108.

The first electrode of the first transistor T101 is connected to the high potential voltage source VDD, the second electrode is connected to the first electrode of the second transistor T102, and the gate electrode is connected to the first terminal 1 . do. The second electrode of the second transistor T102 is connected to the first Q node Q1 , and the gate electrode is connected to the fourth terminal 4 . Since the first and second transistors T102 are connected in series with each other, when the first and second transistors T102 are simultaneously turned on, the high potential voltage VDD is charged to the first Q node Q1. do. That is, the first and second transistors T102 have a start signal VST (or an (i-1)th scan signal Scan[i-1]) and an (i+4)th gate clock GCLK[i+ 4]) is synchronized to charge the first Q node Q1.

The first electrode of the third transistor T103 is connected to the first Q node Q1 , the second electrode is connected to the low potential voltage VSS, and the gate electrode is connected to the first QB node QB1 . Accordingly, the third transistor T103 discharges the potential of the Q node to the low potential voltage VSS in response to the potential of the first QB node QB1 .

The fourth transistor T104 receives the high potential voltage VDD through the first electrode, the second electrode is connected to the first QB node QB1, and the gate electrode is the (i+2)th gate clock GCLK [i+2]). Accordingly, the fourth transistor T104 charges the first QB node QB1 in response to the (i+2)th gate clock GCLK[i+2]. That is, the fourth transistor T104 discharges the first output terminal n11 in response to the (i+2)th gate clock GCLK[i+2], thereby generating the i-th scan signal Scani of the low potential level. to output

The first electrode of the fifth transistor T105 is connected to the first QB node QB1 , the second electrode is connected to the low potential voltage VSS, and the gate electrode receives a start signal through the first terminal 1 . get input The fifth transistor T105 charges the first QB node QB1 to a low potential voltage in response to the start signal VST or the (i-1)th scan signal Scan[i+1].

The gate electrode of the sixth transistor T106 is connected to the first Q node Q, the first electrode is connected to the second terminal 2, and the second electrode is connected to the first output terminal n11. Accordingly, the sixth transistor T106 outputs the i-th gate clock GCLKi in response to the potential of the first Q node Q1.

The seventh transistor T107 has a gate electrode connected to the first QB node QB, a low potential voltage VSS is provided through the first electrode, and a second electrode connected to the first output terminal n11. Accordingly, the seventh transistor T107 discharges the potential of the first output terminal n11 to the low potential voltage VSS in response to the potential of the first QB node QB1 .

The eighth transistor T108 has a first electrode connected to the first QB node QB1 , a second electrode connected to the low potential voltage VSS, and a gate electrode connected to the first Q node Q1 . Accordingly, the eighth transistor T108 discharges the potential of the first Q node Q1 to the low potential voltage VSS in response to the potential of the first Q node Q1.

The emission control signal generator 140b of the i-th stage STG[i] is configured to output the ith emission control signal EMi using clock signals input through the fifth to ninth terminals 9 . 9 to 14 transistors T9 to T14 are included.

The first electrode of the clock response transistor T109 is connected to the high potential voltage VDD, the second electrode is connected to the second Q node Q2, and the gate electrode is connected to the ith emission clock ECLKi. . Accordingly, the clock response transistor T109 charges the second Q node Q2 in response to the ith emission clock ECLKi.

The first electrode of the tenth transistor T110 is connected to the second Q node Q2 , the second electrode is connected to the low potential voltage VSS, and the gate electrode is connected to the second QB node QB2 . Accordingly, the tenth transistor T110 discharges the potential of the second Q node Q2 to the low potential voltage VSS in response to the potential of the second QB node QB2 .

The first electrode of the eleventh transistor T11 is connected to the high potential voltage VDD, the second electrode is connected with the second electrode of the thirteenth transistor T11, and the gate electrode is connected to the second output terminal n12. do.

A first electrode of the pull-up transistor T112 is connected to the high potential voltage VDD, a second electrode is connected to the second output terminal n12 , and a gate electrode is connected to the second Q node Q2 . Accordingly, the pull-up transistor T112 outputs the ith emission control signal EMi corresponding to the high potential voltage VDD to the second output terminal n12 in response to the potential of the second Q node Q2 .

The thirteenth and fourteenth transistors T114 that are pull-down transistors are connected in series with each other, the gate electrode of each of the thirteenth and fourteenth transistors T114 is connected with the second QB node QB2 , and the thirteenth transistor T113 . ) is connected to the second output terminal n12 , and the second electrode of the fourteenth transistor T114 is connected to the low potential voltage VSS. Accordingly, the thirteenth and fourteenth transistors T114 discharge the potential of the second output terminal n12 to the low potential voltage VSS in response to the potential of the second QB node QB2 .

FIG. 7 is an operation timing diagram of the stage shown in FIG. 6 . An operation process of the stage STG1 will be described with reference to FIGS. 5 to 7 .

First, a process in which the scan signal generator 140a outputs the first scan signal Scan1 will be described as follows.

The start signal VST has the same phase as the first to fifth gate clocks GCLK1 to GCLK5. During the first period t1, the first and second transistors T102 are turned on in response to the high-level start signal VST and the fifth gate clock GCLK5, respectively, and the first Q node Q1 to charge

During the third and fourth period t4 after the first transition period t2, the first and second transistors T102 are turned on again, and the first Q node Q1 is charged again. The first Q node Q1 is sufficiently charged during the third and fourth periods t4 following the first period t1 before the first Q node Q1 is discharged by the third gate clock GCLK3 Until the sixth transistor T106 is turned on. Accordingly, the sixth transistor T106 outputs the first gate clock GCLK1 to the first output terminal n11 before the sixth period t6. The first gate clock GCLK1 maintains a high level during the third period t3, the fifth and sixth periods t6, and accordingly, during the third period t3, the fifth and sixth periods t6. The first scan signal Scan1 maintains a high level.

The third period t3 is the initialization period Ti of the first gate line GL1 , the fifth period t5 is the sampling period Ts of the first gate line GL1 , and the sixth period t6 is is the data writing period Tw of the first gate line GL1.

After the sixth period t6, the third gate clock GCLK3 swings to a high level potential, so that the fourth transistor T104 is turned on. Accordingly, the fourth transistor T104 provides the high potential voltage VDD to the first QB node QB1. As the first QB node QB1 is charged, the seventh transistor T107 is turned on, and the voltage of the first output terminal n11 is discharged to the low potential voltage VSS. That is, during the seventh period t7 , the first output terminal n11 outputs the first scan signal Scan1 of the low potential voltage VSS. The seventh period t7 is the light emission period Te of the first gate line GL1 .

A process in which the light emission control signal generator 140b outputs the first light emission control signal EM1 is as follows.

During the first period t1 , the eleventh transistor T111 is turned on by the third emission clock ECLK3 to provide the start signal VST to the thirteenth and fourteenth transistors T114 . Since the start signal VST maintains a high level during the first period t1, the thirteenth and fourteenth transistors T114 are turned on. That is, the potential of the second output terminal n12 maintained at the high level during the light emission period Te of the previous frame period is discharged to the low potential voltage VSS. Accordingly, during the first period t1, which is the start of the j-th frame, the first emission control signal EM1 of the low potential voltage is output.

During the third period t3 after the first transition period t2, the seventeenth transistor T117 is turned on in response to the fifth emission clock ECLK5, and the seventeenth transistor T117 is turned on. Thus, the second QB node QB2 maintains the low potential voltage VSS.

During the fifth period t5 , the ninth transistor T109 is turned on by the first emission clock ECLK1 . That is, the ninth transistor T109 receives the high potential voltage VDD in response to the high-level first emission clock ECLK1 to charge the second Q node Q2 . As the second Q node Q2 is charged, the twelfth transistor T112 is turned on, and the high potential voltage VDD is output to the second output terminal n12 via the twelfth transistor T112. That is, during the fifth period t5 , the second output terminal n12 outputs the first emission control signal EM1 having a voltage level of the high potential voltage VDD.

During the sixth period t6, each of the fifteenth and scan synchronization transistors T115 and T116 is turned on in response to the emission reset ERST and the first scan signal Scan1 having a high potential. Accordingly, the second QB node QB2 is charged, and accordingly, the thirteenth and fourteenth transistors T113 and T114 are turned on. As the thirteenth and fourteenth transistors T113 and T114 are turned on, the second output terminal n12, which outputs the voltage level of the high potential voltage VDD during the fifth period t5, is converted to the low potential voltage VSS. discharged That is, during the sixth period t6, the high potential emission reset ERST and the high potential first scan signal Scan1 discharge the first emission control signal EM1 to a low potential, while the second output terminal n12 ) is initialized.

During the seventh period t7, the ninth transistor T109 again outputs the high potential voltage VDD to the second output terminal n12 in response to the first emission clock ECLK1 having the high potential voltage level.

Also, during the seventh period t7, the nineteenth transistor T119 is turned on in response to the second emission clock ECLK2 having a high potential voltage level and maintains the second QB node QB2 at a low potential. That is, during the seventh period t7, the nineteenth transistor T119 maintains the thirteenth and fourteenth transistors T114 in the turned-off state.

In addition, during the light emission period Te, the sixth terminal 6 and the eighth terminal 8 receive the second emission clock ECLK2 and the fifth emission clock ECLK5 at regular intervals, respectively. That is, the light emission period ( During Te), the seventeenth transistor T117 and the nineteenth transistor T119 are alternately turned on to maintain the second QB node QB2 at a low potential voltage, and accordingly, the thirteenth and fourteenth transistors T114 . (EM1) is output.

Since the first scan signal Scan1 maintains a low potential during the light emission period Te, the second QB node QB2 is in a floating state. Therefore, during the light emission period Te, the potential of the second QB node QB2 may be in an unstable state. The shift register 140 of the first embodiment emits light using the second and fifth emission clocks ECLK2 to ECLK5. During the period Te, the potential of the second QB node QB2 may be stabilized. Accordingly, the shift register 140 according to the first embodiment stably outputs the first emission control signal EM1 having a high potential through the second output terminal n12 during the emission period Te.

As described above, the second pull-up transistor T112 of the emission control signal generator 140b outputs the variable voltage VAC to the output terminal n12 through the variable voltage terminal 6 . The variable voltage VAC maintains a low potential state before the image display period as shown in FIG. 3 . For example, the ground voltage GND is maintained when power is supplied, and a negative bias is maintained after a certain period of time.

Before the image display period, the second pull-up transistor T112 and the clock response transistor T109 must remain in a non-operational state. However, since the gate-source potential of the transistor is in an unspecified state, it may operate unintentionally. When the clock response transistor T109 operates before the image display period, the second Q node Q2 receives the variable voltage. Therefore, if the variable voltage is a high level voltage, the second Q node Q2 may be charged even during the image display period. When the second Q node Q2 is charged, the second pull-up transistor T112 also operates to output the variable voltage VAC to the second output terminal n12 . That is, when the variable voltage VAC is a high level voltage, a high level light emission control signal EM may be output due to a malfunction of the clock response transistor T109 . In addition, if the driving transistor DT also malfunctions while the emission control signal EM is output at a high level, the organic light emitting diode OLED operates and emits light. That is, the pixel P emits light before the image display period, and flickering may occur.

However, in the present invention, the potential of the variable voltage VAC is maintained as a low potential voltage before the image display period. In particular, even if the clock response transistor T109 malfunctions because the negative bias is maintained for more than a predetermined period, the second Q node Q2 is not charged. Since the second Q node Q2 is not charged, the second pull-up transistor T112 does not operate, and thus the second output terminal n12 does not output the emission control signal EM. Also, even if the second pull-up transistor T112 malfunctions, the second output terminal n12 does not output the high-level light emission control signal EM because the variable voltage VAC is a low potential voltage before the image display period. .

As described above, since the present invention can prevent the emission control signal EM from being output before the image display period, the current path between the high potential voltage VDD and the driving transistor DT shown in FIG. can be blocked Accordingly, it is possible to prevent the organic light emitting diode (OLED) from emitting light before the image display period and causing the flickering phenomenon to occur.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention can be changed to other specific forms by those skilled in the art to which the present invention pertains without changing the technical spirit or essential features of the present invention. It will be appreciated that this may be practiced. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention.

Claims (6)

organic light emitting diode;
a driving transistor receiving a high potential voltage provided from a high potential voltage source to a drain electrode and controlling a driving current provided to the organic light emitting diode;
a first transistor positioned between the drain electrode of the driving transistor and the high potential voltage source and connecting the high potential voltage source and the drain electrode of the driving transistor in response to a light emission control signal provided to the gate electrode; and
a stage for outputting the light emission control signal;
the stage is
scan signal generator; and
and a light emission control signal generator configured to receive a variable voltage maintaining a low potential voltage from a power input to before an image display period through a variable voltage terminal and output the variable voltage in response to an emission clock,
The light emission control signal generating unit
a clock response transistor receiving an emission clock to a gate electrode, a first electrode connected to the variable voltage terminal, and a second electrode connected to a Q node;
a pull-up transistor having a gate electrode connected to the Q node, a first electrode connected to the variable voltage terminal, and a second electrode connected to an output terminal; and
and a pull-down transistor receiving an output of the scan signal generator as a gate electrode, a first electrode connected to the output terminal, and a second electrode connected to a low potential voltage source.
The method of claim 1,
The variable voltage maintains a negative bias for at least a predetermined period before an image display period.
delete The method of claim 1,
The organic light emitting diode display device
a second transistor receiving a (n-1)th scan signal through a gate electrode, a first electrode connected to an initialization line, and a second electrode connected to a source electrode of the driving transistor; and
The organic light emitting diode display further comprising a third transistor receiving an nth scan signal through a gate electrode, a first electrode connected to a data line, and a second electrode connected to a gate electrode of the driving transistor.
5. The method of claim 4,
The initialization line is an organic light emitting diode display that provides a base voltage before an image display period.
5. The method of claim 4,
The data line is an organic light emitting diode display that provides a base voltage before an image display period.

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