KR102298263B1 - Membrane gate thin film transistor and method of fabricating the same - Google Patents

Abstract

A method of manufacturing a membrane gate thin film transistor according to an aspect of the present invention comprises: forming a semiconductor substrate; forming an etch stop layer on the semiconductor substrate; forming a sacrificial layer on the etch stop layer; forming a membrane layer on the sacrificial layer; forming an etching hole exposing the sacrificial layer in the membrane layer; removing the sacrificial layer through the etch hole; forming a sealing layer for sealing the etch hole to form a vacuum gap between the membrane layer and the semiconductor substrate; forming vias by patterning at least a portion of the membrane layer; and forming an electrode layer on the electrode of the semiconductor substrate exposed through the via, the inner wall of the via, and the membrane layer.

Description

Membrane gate thin film transistor and method of fabricating the same

The present invention relates to a thin film transistor, and more particularly, to a field effect transistor type device having a membrane structure using a sacrificial layer etching process and a method for manufacturing the same.

A field effect transistor (or FET) is a semiconductor having three poles, a source, a drain, and a gate. Conventionally, in the case of a field effect transistor type device, the receptor and the target biological material are coupled to all portions of the front and rear surfaces of the electrodes. In this case, there is a problem in that the detection accuracy of the detection material becomes unstable depending on the area to be bound.

In addition, since the gate and the semiconductor substrate having the source electrode and the drain electrode are not physically separated, the detection material such as gas and humidity in contact with the gate affects the source electrode and the drain electrode, thereby limiting reliability.

On the other hand, the capacitive membrane module structure has a limitation in that it is necessary to directly measure the change in capacitance and to improve the sensitivity by changing the membrane module. In addition, a field effect transistor type device (MG-FET) having a membrane gate structure using wafer bonding is manufactured at a high temperature for strong bonding of different substrates. However, when a three-dimensional single integrated structure is applied to improve sensitivity, this manufacturing method may cause performance degradation of the underlying device. On the other hand, when the wafer bonding process is performed at a low temperature, there is a problem in that bonding characteristics such as source and drain contact are deteriorated.

An object of the present invention is to solve various problems including the above problems, and an object of the present invention is to provide a membrane gate thin film transistor having excellent detection accuracy and reliability, and a method for manufacturing the same. However, these problems are exemplary, and the scope of the present invention is not limited thereto.

A method of manufacturing a membrane gate thin film transistor according to an aspect of the present invention is provided.

The method of manufacturing the membrane gate thin film transistor includes: forming a semiconductor substrate; forming an etch stop layer on the semiconductor substrate; forming a sacrificial layer on the etch stop layer; forming a membrane layer on the sacrificial layer; forming an etching hole exposing the sacrificial layer in the membrane layer; removing the sacrificial layer through the etch hole; forming a sealing layer for sealing the etch hole to form a vacuum gap between the membrane layer and the semiconductor substrate; forming vias by patterning at least a portion of the membrane layer; and forming an electrode layer on the electrode of the semiconductor substrate exposed through the via, the inner wall of the via, and the membrane layer.

In the method of manufacturing the membrane gate thin film transistor, the forming of the sacrificial layer includes: forming a channel layer having an etch channel on the etch stop layer; and forming the sacrificial layer on the channel layer.

In the method of manufacturing the membrane gate thin film transistor, a concave portion may be formed in at least a portion of the sacrificial layer by the etch channel so that a portion of the membrane layer protrudes downwardly into the concave portion.

In the method of manufacturing the membrane gate thin film transistor, the sealing layer may be formed up to a portion of the membrane layer protruding downwardly into the etch channel through the etch hole.

The method of claim 2 , wherein the electrode layer may be formed on the membrane layer to partially protrude downward in the etch channel direction.

In the method of manufacturing the membrane gate thin film transistor, the vacuum gap may be surrounded by the sealing layer, the membrane layer, and the etch stop layer.

In the method of manufacturing the membrane gate thin film transistor, the etch stop layer, the sealing layer, and the membrane layer may be formed of the same material.

In the method of manufacturing the membrane gate thin film transistor, the etch stop layer, the sealing layer, and the membrane layer may include silicon nitride.

In the method of manufacturing the membrane gate thin film transistor, the forming of the semiconductor substrate includes: forming a silicon oxide layer on the silicon substrate; forming a semiconductor channel on the silicon oxide layer; and forming a source electrode and a drain electrode on the semiconductor channel.

In the method of manufacturing the membrane gate thin film transistor, the semiconductor channel may include indium gallium zinc oxide (IGZO).

Another aspect of the present invention provides a membrane gate thin film transistor.

The membrane gate thin film transistor may include a semiconductor substrate; an etch stop layer formed on the semiconductor substrate; a membrane layer formed on the etch stop layer; and an electrode layer formed on the membrane layer, wherein the membrane layer is spaced apart from the semiconductor substrate by a vacuum gap including a cavity, and the vacuum gap is formed on the etch stop layer, the membrane layer, and the membrane layer It may be sealed by the formed sealing layer.

The membrane gate thin film transistor according to the embodiments of the present invention made as described above has improved sensitivity, so that it is easy to detect a substance at a low concentration, and the detection accuracy and reliability are high at a low cost. Furthermore, according to the manufacturing method of the membrane gate thin film transistor according to the embodiments of the present invention, by economically manufacturing the vacuum gap using a semiconductor substrate, it is possible to manufacture with a high yield and can be applied to the memory field. Of course, the scope of the present invention is not limited by these effects.

1 is a schematic cross-sectional view showing a membrane gate thin film transistor and a method of manufacturing the same according to an embodiment of the present invention.
2 is an optical microscope (OM) image showing a sacrificial layer etching process according to the sacrificial layer etching process condition of the membrane gate thin film transistor according to an experimental example of the present invention.
3 is an image of a cross-sectional microstructure of a membrane gate thin film transistor according to an experimental example of the present invention analyzed with an electron microscope (SEM).
4 is an image of the microstructure according to the diameter of the membrane layer of the membrane gate thin film transistor according to the experimental example of the present invention analyzed by a focused ion beam electron microscope (FIB SEM).
5 is a schematic diagram for explaining an operating principle of a membrane gate thin film transistor according to an experimental example of the present invention.

Hereinafter, several preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Examples of the present invention are provided to more completely explain the present invention to those of ordinary skill in the art, and the following examples may be modified in various other forms, and the scope of the present invention is as follows It is not limited to an Example. Rather, these embodiments are provided so as to more fully and complete the present disclosure, and to fully convey the spirit of the present invention to those skilled in the art. In addition, in the drawings, the thickness or size of each layer is exaggerated for convenience and clarity of description.

The present invention provides a field effect transistor having a source and a drain for the amount of change in capacitance due to the bending of the membrane. Hereinafter, this will be described in detail with reference to the drawings.

1 is a schematic cross-sectional view showing a membrane gate thin film transistor and a method of manufacturing the same according to an embodiment of the present invention.

Referring to FIGS. 1A and 1B , the etch stop layer 110 may be formed on the semiconductor substrate 100 . For example, the semiconductor substrate 100 forms a silicon oxide layer 20 on the silicon substrate 10 . For example, silicon oxide may include _{SiO 2 .} Thereafter, a semiconductor channel 30 is formed on the silicon oxide layer 20 . Here, the semiconductor channel 30 may include indium gallium zinc oxide (IGZO). After the semiconductor channel 30 is deposited, a portion of the edge of the semiconductor channel 30 is removed to expose the silicon oxide layer 20 . A source electrode 42 and a drain electrode 44 are respectively formed on a portion of the exposed silicon oxide layer 20 and on both edge regions of the semiconductor channel 30 . The protective layer 50 is formed on the entire region including the source electrode 42 and the drain electrode 44 and the entire surface of the semiconductor channel 30 . The protective layer 50 may use the same material as the silicon oxide layer 20 , but in some cases, an oxide or nitride other than silicon oxide may be used.

Thereafter, the etch stop layer 110 may be entirely formed on the semiconductor substrate 100 on which the protective layer 50 is formed. The etch stop layer 110 may include silicon nitride, for example, Si ₃ N ₄ , and may be uniformly formed by a chemical vapor deposition (CVD) method. More specifically, as the CVD method, low vacuum CVD (LP CVD) or plasma enhanced CVD (PE CVD) may be used.

Referring to FIGS. 1C and 1D , a channel layer 120 having an etch channel 127 is formed on the etch stop layer 110 , and the channel layer 120 is patterned to a predetermined size and etched. A channel 127 may be formed. The etch channel 127 may be positioned inward by a predetermined distance from the edge of the etch stop layer 110 so that the layer to be formed thereafter protrudes downward. For example, the channel layer 120 may include amorphous silicon.

The etching channel 127 may be formed using photolithography and an etching process. For example, the etching may be performed using plasma dry etching having anisotropic etching characteristics, for example, reactive ion etching (RIE).

Thereafter, a sacrificial layer 125 may be formed on the channel layer 120 . The sacrificial layer 125 is formed to cover the etch channel 127 , and for example, the sacrificial layer 125 may include amorphous silicon. The sacrificial layer 125 is formed to cover the etch channel 127 , but may be formed to protrude downwardly into the etch channel 127 along the shape of the etch channel 127 .

Specifically, an amorphous silicon layer is thickly deposited to cover the channel layer 120 and the etch channel 127 by a chemical vapor deposition (CVD) method, and then patterned from the edge of the etch stop layer 110 to the inside by a predetermined distance. can do. The thickness of the amorphous silicon layer means the sum of the thickness of the channel layer 120 and the thickness of the sacrificial layer 125 .

Referring to FIG. 1E , the membrane layer 130 may be formed on the sacrificial layer 125 . For example, the membrane layer 130 may be entirely deposited on the sacrificial layer 125 and the etch stop layer 110 by a chemical vapor deposition (CVD) method. The membrane layer 130 may include silicon nitride, for example, Si ₃ N ₄ .

The membrane layer 130 is conformally formed on the sacrificial layer 125 so that this portion protrudes downwardly into the etch channel 127 along the shape of the etch channel 127 of the sacrificial layer 125 . can be formed.

Thereafter, an etching hole 135 exposing the sacrificial layer 125 may be formed in the membrane layer 130 . For example, the etching hole 135 may be formed using photolithography and etching techniques. The etching hole 135 may be formed to expose an edge portion of the sacrificial layer 125 in consideration of a subsequent sealing step.

Referring to FIG. 1F , an empty space 129 may be formed by removing the sacrificial layer 125 through the etching hole 135 . For example, the removal of the sacrificial layer 125 may be performed by isotropic etching, for example, by using a wet etching method to gradually remove the etchant from the etch hole 135 from the side of the sacrificial layer 125 . For example, when the sacrificial layer 125 is made of amorphous silicon, the etchant may include a KOH solution.

Referring to FIG. 1G , a vacuum gap 145 may be formed between the membrane layer 130 and the semiconductor substrate 100 by forming the sealing layer 140 sealing the etch hole 135 . . Since the step of forming the sealing layer 140 substantially uses a vacuum process, the inside of the vacuum gap 145 may be in a vacuum state of a predetermined pressure.

For example, the sealing layer 140 may include silicon nitride, such as Si ₃ N ₄ , and is uniformly formed by a chemical vapor deposition (CVD) method having excellent step coverage. can be formed. The sealing layer 140 may be formed from the bottom of the etch hole 135 until the sealing layer 140 is blocked.

In this case, the downwardly protruding portion of the membrane layer 130 may serve as a guide for stopping the growth of the sealing layer 140 in the vacuum gap 145 . For example, the sealing layer 140 may be formed up to the portion of the membrane layer 130 protruding downwardly into the etch channel 127 through the etch hole 135 .

Furthermore, the vacuum gap 145 may be sealed by being surrounded by the sealing layer 140 , the membrane layer 130 , and the etch stop layer 110 . The vacuum gap 145 , more specifically, a portion of the membrane layer 130 may be spaced apart from the semiconductor substrate 100 by the vacuum gap 145 including a cavity.

As another example, when a plasma enhanced CVD (PECVD) technique is used as a method of sealing the etch hole 135 , the sacrificial layer 125 is directly formed on the etch stop layer 110 without forming the etch channel 127 . By doing so, the vacuum gap 145 may be implemented. When the etch hole 135 is sealed using the PECVD technique, since conformal deposition in the lateral direction is easy, the step of forming the etch channel 127 on the etch stop layer 110 is omitted. can do. Accordingly, it may be easy to optimize the process according to the reduction in the number of process steps.

Referring to (h) and (i) of FIG. 1 , after sealing the etch hole 135 , patterning is performed on at least any part of the membrane layer 130 to form a via 137 . The electrode layer 150 is formed on the source electrode 42 and the drain electrode 44 of the semiconductor substrate 100 exposed through the via 137 , the inner wall of the via 137 , and the membrane layer 130 .

The electrode layer 150 may be formed of a conductive metal material. Since the electrode layer 150 is formed along the structure of the membrane layer 130 , it may be formed to partially protrude downward in the etch channel 127 direction. In some embodiments, some or all of the etch stop layer 110 , the sealing layer 140 , and the membrane layer 130 may be formed of the same material, for example, silicon nitride.

According to the above-described embodiment, a membrane structure can be easily manufactured by forming the sacrificial layer 125 on the semiconductor substrate 100, and furthermore, an expensive silicon-on-insulator (SOI) substrate is used. The membrane gate thin film transistor 1000 having the vacuum gap 145 can be manufactured at low cost without doing so.

The membrane gate thin film transistor 1000 according to the present invention is different from a conventional field effect transistor type device that detects a change in the amount of current, a semiconductor substrate ( 100) and a structure physically separated from each other to increase detection accuracy and reliability.

In addition, the present invention can be manufactured at low cost by manufacturing a field effect transistor type device (MG-FET) having a membrane structure without using a silicon on insulator (SOI) substrate. In addition, it is possible to manufacture with a high yield by using a conventional CMOS semiconductor process such as a sacrificial layer etching process.

In addition, it is possible to solve the source-drain contact problem that occurs when manufacturing a membrane-structured field-effect transistor type device (MG-FET) by bonding at low temperature, and attaching a layer that can detect a target detection material on the front side of the gate It has the advantage that it can be applied as a gas sensor or a biosensor by detecting a change in mass or a change in membrane stress.

On the other hand, the structure similar to the pressure sensor and capacitive micromachined ultrasonic transducer (CMUT) that measures the absolute pressure by changing the pressure of the vacuum gap during the process improves the sensitivity through amplification through the field effect transistor. It can also be applied as an ultrasonic sensor. It can also be applied to the memory field where the dynamic write/read function can be improved by using the membrane gate as a floating gate of the flash memory.

In particular, the present invention, which can be fabricated at a low temperature, such as a sacrificial layer etching process, is expected to dramatically improve sensitivity because it enables the application of a three-dimensional single integrated structure that requires fabrication at a low temperature.

Hereinafter, embodiments for helping understanding of the present invention will be described. However, the following experimental examples are only for helping understanding of the present invention, and the present invention is not limited only to the following examples.

의 온도에서 1시간동안 열처리를 수행하였다. 이후에 MA6 장비(상용장비)를 이용하여 IGZO 층을 패터닝하였다. 이 때, 습식식각으로 IGZO 층을 식각하였는데, 습식 조건은 물과 염산의 비율을 H₂O:HCl=200:10로 제어한 후 90초 동안 진행하였다. _{As an experimental example of the present invention, SiO 2} having a thickness of 100 nm was formed on a p-type Si wafer by using a thermal deposition method. Then, a 30 nm thick IGZO layer was formed on _{SiO 2 using a sputtering method, which was}

Heat treatment was performed at a temperature of Thereafter, the IGZO layer was patterned using MA6 equipment (commercial equipment). At this time, the IGZO layer was etched by wet etching, and the wet condition was _{carried out for 90 seconds after controlling the ratio of water and hydrochloric acid to H 2} O:HCl=200:10.

A source electrode and a drain electrode were formed by depositing 30 nm thick Mo on the patterned IGZO layer by a sputtering method, and patterning it using MA6 equipment. Thereafter, a buffer layer of 100 nm thick SiO ₂ was formed using a plasma chemical vapor deposition (PECVD) method.

에서 증착하였다. 식각방지층 상에 125㎚ 두께의 a-Si를 스퍼터링 방법으로 증착하고, 이를 MA6 장비로 패터닝하여 식각 채널을 형성하였다. 이후에 125㎚ 두께의 a-Si를 동일한 방법으로 희생층을 증착하였다. 두 번의 a-Si 증착 과정을 통해 희생층의 두께가 결정될 수 있다.After that, _{Si 3} N ₄ having a thickness of 100 nm as an etch stop layer _{on the SiO 2} buffer layer was deposited using a plasma chemical vapor deposition (PECVD) method.

was deposited in A-Si with a thickness of 125 nm was deposited on the etch stop layer by sputtering, and the etch channel was formed by patterning it with MA6 equipment. Thereafter, a sacrificial layer was deposited on a-Si with a thickness of 125 nm in the same manner. The thickness of the sacrificial layer may be determined through two a-Si deposition processes.

As a membrane layer on the sacrificial layer, Si ₃ N ₄ having a thickness of 300 nm was deposited using a plasma chemical vapor deposition (PECVD) method to form an etch hole. The sacrificial layer was removed using an etching hole.

The method of removing the sacrificial layer was rinsed with distilled water (DI water), distilled water and hydrofluoric acid (HF) were prepared at a ratio of 50:1, dipping was performed for 30 seconds, and then rinsed with distilled water again. Thereafter, the sacrificial layer was removed using a 45% KOH etchant, and rinsed with distilled water and isopropyl alcohol (IPA).

_{Thereafter, Si 3} N ₄ having a thickness of 400 nm was selectively deposited to seal the etch hole to implement a vacuum gap, and vias were formed near both ends of the membrane layer. Thereafter, a membrane gate thin film transistor sample was prepared by depositing Mo with a thickness of 100 nm on the entire upper surface of the membrane layer, the inner wall of the via, and the source and drain electrodes exposed to the outside by the via.

2 is an optical microscope (OM) image showing a sacrificial layer etching process according to the sacrificial layer etching process condition of the membrane gate thin film transistor according to an experimental example of the present invention.

Referring to FIG. 2 , when the etching rate is increased from 30 hours to 36 hours during the sacrificial layer etching process, it is confirmed that the area etched in the lateral direction (increase in the area of the yellow sector shape) increases. That is, it was confirmed that etching in the lateral direction could be performed by controlling the etching process time. In addition, it was possible to control the etching process time by controlling the etching rate by controlling the temperature of the etching solution.

3 is an image obtained by analyzing the cross-sectional microstructure of a membrane gate thin film transistor according to an experimental example of the present invention with an electron microscope (SEM), and FIG. It is an image analyzed by a focused ion beam electron microscope (FIB SEM).

3 and 4 , it was confirmed that the a-Si layer having a thickness of 250 nm was selectively removed through the sacrificial layer etching process, and a vacuum gap was stably formed. When the diameter of the membrane (the diameter of the membrane when viewed from the top (see Fig. 3 (a))) is 20 μm or more to less than 80 μm, it can be confirmed that the collapse of the membrane layer does not occur and is uniformly formed. (see FIGS. 3(c) and 4(a)).

In particular, according to (b) of FIG. 4 , when the diameter of the membrane was 20 μm, deflection of about 50 nm occurred at the center of the membrane layer by atmospheric pressure (external stimulus).

On the other hand, according to (c) of FIG. 4, when the diameter of the membrane is 80 μm or more, the central portion of the membrane layer is bent beyond the thickness (250 nm) of the sacrificial layer and a phenomenon (collapse) occurred (Fig. See (c) of 4). That is, when the membrane layer is spaced apart from the semiconductor substrate using the sacrificial layer, it is determined that the size (diameter and thickness) of the membrane affects stably forming a vacuum gap.

5 is a schematic diagram for explaining an operating principle of a membrane gate thin film transistor according to an experimental example of the present invention.

Referring to FIG. 5 , when a bioreceptor is formed on the front surface of the membrane serving as a gate and a target biomaterial specifically binds, a change in the amount of current of the channel due to a difference in capacitance according to the degree of bending of the membrane (electrical It is converted into a signal and amplified to detect a change in the amount of current).

Although the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

10: silicon substrate
20: silicon oxide layer
30: semiconductor channel
42: source electrode
44: drain electrode
50: protective layer
100: semiconductor substrate
110: etch stop layer
120: channel layer
125: sacrificial layer
127: etch channel
129: empty space
130: membrane layer
135: etching hole
137: via
140: sealing layer
145: vacuum gap
150: electrode layer
1000: membrane gate thin film transistor

Claims (11)

forming a semiconductor substrate;
forming an etch stop layer on the semiconductor substrate;
forming a sacrificial layer on the etch stop layer;
forming a membrane layer on the sacrificial layer;
forming an etching hole exposing the sacrificial layer in the membrane layer;
removing the sacrificial layer through the etch hole;
forming a sealing layer for sealing the etch hole to form a vacuum gap between the membrane layer and the semiconductor substrate;
forming vias by patterning at least a portion of the membrane layer; and
Forming an electrode layer on the electrode of the semiconductor substrate exposed through the via, the inner wall of the via, and the membrane layer;
The vacuum gap is surrounded by the sealing layer, the membrane layer, and the etch stop layer,
A method for manufacturing a membrane gate thin film transistor. The method of claim 1,
The step of forming the sacrificial layer,
forming a channel layer having an etch channel on the etch stop layer; and
Including; forming the sacrificial layer on the channel layer;
A method for manufacturing a membrane gate thin film transistor. 3. The method of claim 2,
A concave portion is formed in at least a portion of the sacrificial layer by the etching channel so that a portion of the membrane layer protrudes downwardly into the concave portion,
A method for manufacturing a membrane gate thin film transistor. 3. The method of claim 2,
The sealing layer is formed up to a portion of the membrane layer protruding downwardly into the etch channel through the etch hole,
A method for manufacturing a membrane gate thin film transistor. 3. The method of claim 2,
The electrode layer is formed on the membrane layer to partially protrude downward in the etch channel direction,
A method for manufacturing a membrane gate thin film transistor. delete The method of claim 1,
The etch stop layer, the sealing layer and the membrane layer are formed of the same material,
A method for manufacturing a membrane gate thin film transistor. The method of claim 1,
The etch stop layer, the sealing layer and the membrane layer comprising silicon nitride,
A method for manufacturing a membrane gate thin film transistor. The method of claim 1,
Forming the semiconductor substrate comprises:
forming a silicon oxide layer on a silicon substrate;
forming a semiconductor channel on the silicon oxide layer; and
Including; forming a source electrode and a drain electrode on the semiconductor channel;
A method for manufacturing a membrane gate thin film transistor. 10. The method of claim 9,
The semiconductor channel includes indium gallium zinc oxide (IGZO),
A method for manufacturing a membrane gate thin film transistor. semiconductor substrate;
an etch stop layer formed on the semiconductor substrate;
a membrane layer formed on the etch stop layer; and
and an electrode layer formed on the membrane layer;
The membrane layer is spaced apart on the semiconductor substrate by a vacuum gap including a cavity,
The vacuum gap is closed by the etch stop layer, the membrane layer, and a sealing layer formed on the membrane layer,
Membrane gate thin film transistor.

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