KR102287058B1 - Array Board And Method Manufacturing The Same - Google Patents

Abstract

The present invention, a substrate; a gate wiring formed on the substrate; a first gate electrode extending from the gate wiring; a gate insulating film formed on the gate wiring and the gate electrode; a data line formed on the gate insulating layer and perpendicular to the gate line; A source electrode part connected to the data line and formed at a position corresponding to a partial surface of the first gate electrode, a channel part adjacent to the source electrode part, and a position corresponding to a partial surface of the first gate electrode an active layer including a drain electrode spaced apart from the source electrode part by a channel part; Provided is a thin film transistor including a passivation layer formed on the active layer.

Description

Array substrate including thin film transistor and manufacturing method thereof

The present invention relates to an array substrate including a thin film transistor and a method for manufacturing the same.

A display device displays an image by applying a voltage, and representatively, there are a liquid crystal display (LCD) device and an organic light emitting diode (OLED) device.

The LCD device and the OLED device include an array substrate on which a plurality of thin film transistors for applying a voltage according to a data signal are formed on one substrate. let me explain

FIG. 1 is a plan view illustrating an array substrate formed in a display device, and FIG. 2 is a cross-sectional view taken along the cutting line I-II of FIG. 1 .

1 and 2 , the array substrate 10 includes a first gate electrode 11 formed to extend from a gate line G, a semiconductor layer 32, and a data line D to extend. A thin film including a formed source electrode 21 , a drain electrode 22 to which the voltage of the source electrode 21 is applied, and a second gate electrode 12 formed on the source and drain electrodes 21 and 22 . It includes a transistor Tr and a pixel electrode 40 .

A gate insulating film 15 is formed on the first gate electrode 11 , and an insulating layer 25 is formed on the source and drain electrodes 21 and 22 and the semiconductor layer 32 , and the first The gate electrode 11 and the second gate electrode 12 are connected to each other through the gate contact hole GCT to form a dual gate structure.

In this case, the drain electrode 22 is connected to the pixel electrode 40 through the drain contact hole DCT formed on the surface exposed to the outside of the second gate electrode 12 .

The semiconductor layer 32 is a key material for forming a thin film transistor (Tr) formed in LCD devices and OLED devices. Amorphous silicon is generally used for LCD devices, but in recent years, oxide semiconductors (Oxide) for high aperture ratios have been used. Semiconductor) has increased, and since the semiconductor layer 32 provided in the OLED device requires high electron mobility and stable voltage maintenance ability, LTPS (Low Temperture Poly-Silicon) or oxide semiconductor is used. It is common to use

At this time, an Etch Stop Layer (ESL, not shown) for preventing damage to the semiconductor layer 32 is further formed on the semiconductor layer 32 .

The thin film transistor Tr configured as described above has a structure capable of receiving a voltage from the source electrode 21 and applying a voltage to the drain electrode 22 by the voltage applied to the first gate electrode 11 . In the case of the structure, a case in which the second gate electrode 12 is electrically connected to the source electrode 21 or the drain electrode 22 may occur, which will be described with reference to FIG. 3 below.

3 is a cross-sectional photograph illustrating a connection failure of a thin film transistor formed in a conventional display device.

As shown in FIG. 3 , when the second gate electrode 12 is formed on the source and drain electrodes 21 and 22 to form a dual gate structure, the second gate is lost due to the loss of the insulating layer 25 . There may be a problem in that the electrode 12 is electrically connected to the source and drain electrodes 21 and 22 .

This is because, when the insulating layer 25 is stacked on top of the source and drain electrodes 21 and 22 made of a metal material, a problem occurs in that a portion of the insulating layer 25 is detached due to low adhesion.

Accordingly, when a dual gate structure is formed, a structure that improves adhesion between the insulating layer 25 and the source and drain electrodes 21 and 22 is required.

An object of the present invention is to solve a problem in which a protective film is not normally deposited and is detached from the upper portions of the source and drain electrodes formed in a thin film transistor.

The present invention, in order to solve the above problem, a substrate; a first gate electrode formed on the substrate; a gate insulating film formed on the first gate electrode; A source electrode unit formed at a position corresponding to a partial surface of the first gate electrode, a channel unit adjacent to the source electrode unit, and the channel unit at a position corresponding to a partial surface of the first gate electrode. an active layer including a drain electrode spaced apart from the electrode part; an etch stopper positioned above the channel part; Provided is a thin film transistor including a passivation layer formed on the active layer and the channel portion.

and a second gate electrode positioned on the passivation layer and connected to the first gate electrode through a gate contact hole formed in the passivation layer.

And, The active layer includes any one selected from Si-based, oxide semiconductor, graphene including carbon nanotubes, nitride-based and organic semiconductor.

On the other hand, the present invention, the substrate; a gate wiring formed on the substrate; a first gate electrode extending from the gate wiring; a gate insulating film formed on the gate wiring and the first gate electrode; a data line formed on the gate insulating layer and perpendicular to the gate line; A source electrode part connected to the data line and formed at a position corresponding to a partial surface of the first gate electrode, a channel part adjacent to the source electrode part, and a position corresponding to a partial surface of the first gate electrode an active layer including a drain electrode spaced apart from the source electrode part by a channel part; an etch stopper positioned above the channel part; a passivation layer formed on the active layer and the channel part; An array substrate including a pixel electrode connected to the drain electrode part through a drain contact hole formed in the passivation layer is provided.

The first gate electrode includes a second gate electrode formed on the passivation layer, and an insulating layer positioned on the second gate electrode to space the second gate electrode and the pixel electrode apart and including the drain electrode part. further formed.

In addition, the active layer includes any one selected from Si-based, oxide semiconductor, graphene including carbon nanotubes, nitride-based and organic semiconductor.

In addition, the source electrode part is positioned above the data line and electrically connected to the data line.

In addition, the source electrode part is positioned below the data line and electrically connected to the data line.

In addition, the present invention comprises the steps of forming a gate wiring and a first gate electrode on a substrate; stacking a gate insulating film on the gate wiring and the gate electrode; sequentially stacking an active layer and an etch stopper layer on the gate insulating layer; forming a photoresist pattern on the active layer and the etch stopper layer; exposing a portion of the active layer by partially etching the etch stopper layer exposed to the outside of the photoresist pattern; conducting the exposed active layer; stacking a passivation layer on the active layer and the etch stopper layer; forming a second gate electrode on the passivation layer; forming an insulating film on the gate electrode; The method of manufacturing an array substrate includes forming a pixel electrode disposed on the insulating layer and connected to the drain electrode.

In addition, the step of stacking the gate insulating layer further includes forming the data line.

In addition, forming the exposed active layer into a conductor further includes forming the data line.

The forming of the photoresist pattern may include: preparing a mask layer in which a light blocking portion, a transmitting portion, and a semi-transmissive portion are formed; The method further includes forming a first pattern portion and a second pattern portion having a lower height than that of the first pattern portion by exposing the photoresist to the mask layer.

According to the present invention, an array substrate including a thin film transistor and a method for manufacturing the same can solve a problem caused by poor adhesion of the protective film because the active layer constituting the thin film transistor serves not only as a channel but also as a source and a drain electrode.

FIG. 1 is a plan view illustrating an array substrate formed in a display device, and FIG. 2 is a cross-sectional view taken along the cutting line I-II of FIG. 1 .
3 is a cross-sectional photograph illustrating a connection failure of a thin film transistor formed in a conventional display device.
4 is a plan view showing a thin film transistor according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view of a portion of FIG. 4 taken along the cutting line I-II.
6A to 6H are plan views illustrating a process of forming a thin film transistor according to an embodiment of the present invention, and FIGS. 7A to 7H are cross-sectional views of a portion cut along the cutting line I-II of FIG. 4 according to the process sequence; am.

Hereinafter, an array substrate including a thin film transistor and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to the drawings.

4 is a plan view showing a thin film transistor according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view of a portion of FIG. 4 taken along the cutting line I-II.

As shown in FIG. 4 , the array substrate 101 according to the embodiment of the present invention includes a first gate electrode 111 formed to extend from a gate line G, an active layer 120 formed thereon; A pixel electrode (D) including a data line (D) connected to the active layer (120), a second gate electrode (112) formed on the active layer (120), and connected to one side of the drain electrode part (122) 140) is included.

The active layer 120 is divided into a channel part 131 showing semiconductor characteristics, a source electrode part 121 and a drain electrode part 122 showing conductor characteristics, and the active layer 120 is made of Si-based, oxide semiconductor, It may be formed of graphene including carbon nanotubes, nitride-based and organic semiconductors, and is preferably formed of IGZO of an oxide semiconductor.

In this case, the active layer 120 applies the source electrode unit 121 serving as the source electrode, the drain electrode unit 122 serving as the drain electrode, and the voltage of the source electrode unit 121 to the drain electrode according to the voltage application state. It includes a channel part 131 that moves to the part 122 , and the ESL 132 is formed to have the same size as the channel part 131 .

The active layer 120 of the thin film transistor according to the embodiment of the present invention is formed of IGZO, the higher the oxygen ratio, the lower the electrical conductivity, and the lower the oxygen ratio, the higher the electrical conductivity. The ratio of IGZO constituting the 131 is preferably 1:1:1:3 (indium, gallium, zinc, and oxygen from the left), and the source and drain electrodes 121 and 122 have a ratio of IGZO constituting them. The ratio of heavy oxygen should be less than 1:1:1:3, preferably 1:1:1:2.7 or less.

In this case, the source and drain electrode parts 121 and 122 are not directly connected to each other, and the channel part 131 should be positioned between them.

Meanwhile, the source electrode unit 121 extends in the direction in which the data line D is located and is formed on the data line D, but this is an example according to an embodiment of the present invention. When the data line D is formed earlier than the active layer 120 , the source electrode part 121 may be positioned on the data line D, and the data line D forms the active layer 120 . In the case where the data line D is formed after the process is performed, the data line D may be positioned on the source electrode part 121 , and the ESL 132 is formed on the active layer 120 without forming the source electrode part 121 . When the active layer 120 is divided into the channel part 131 and the data electrode part 122 by positioning and maintaining the channel part 131 , one side of the data line D is extended to form the active layer 120 . It can be connected to the channel part 131 of

However, when one side of the data line D is extended and connected to the channel part 131 of the active layer 120 , the data line D must be formed before the active layer 120 .

The configuration of the array substrate 101 as described above can be seen in more detail when cut along the cutting line I-II as shown in FIG. 5 .

A first gate electrode 111 is formed on the array substrate 101 , a gate insulating film 115 is formed on the first gate electrode 111 , and a source electrode part is formed on the gate insulating film 115 . 121 , the active layer 120 on which the drain electrode part 122 and the channel part 131 are formed, and the ESL 132 formed on the channel part 131 are formed.

In this case, as described above, since the source electrode part 121 and the drain electrode part 122 exhibit conductor characteristics and the channel part 131 shows semiconductor characteristics, the source electrode part 121 and the drain electrode part 122 ), even when the channel parts 131 are formed of the same material and are connected to each other, a malfunction due to the connection does not occur.

In addition, an insulating layer 125 is formed on the active layer 120 and the ESL 132 , and a second gate electrode 112 is formed on the insulating layer 125 .

In the insulating layer 125 , a gate contact hole (GCT of FIG. 4 ) capable of exposing the first gate electrode 111 and a drain contact hole (DCT of FIG. 4 ) capable of exposing the drain electrode part 122 are formed. and the second gate electrode 112 is connected to the first gate electrode 111 through the gate contact hole (GCT of FIG. 4 ) formed in the insulating layer 125 .

A passivation layer 135 is disposed on the second gate electrode 112 , and is spaced apart from the pixel electrode 140 formed on the passivation layer 135 by the passivation layer 135 .

At this time, a drain contact hole (DCT in FIG. 4 ) for exposing the drain electrode part 122 together with the insulating layer 125 is formed in the passivation layer 135 , through which the pixel electrode 140 is connected to the drain electrode part ( 122) can be connected.

The thin film transistor formed as described above has a source electrode part 121 and a drain electrode part 122 made of a conductive oxide semiconductor, thereby providing low adhesion between the source and drain electrodes made of metal and the insulating layer 125 . This can be solved, so that defects due to separation of the insulating layer 125 do not occur.

The first and second gate electrodes 111 and 112 are formed of a metal material and are characterized in that they are connected to each other through a gate contact hole (GCT in FIG. 4 ).

In this case, the first and second gate electrodes 111 and 112 are dual gates, and the current mobility of the active layer 120 can be increased, so that the voltage applied to the source electrode 121 is applied to the drain electrode 122 . Since it is easy to apply the current, it is possible to improve the current application characteristics.

The thin film transistor as described above necessarily requires the process of making the active layer 120 into a conductor. When the active layer 120, the source electrode part 121, and the drain electrode part 122 can be formed on the same layer, It can be changed without being limited by the shape of the thin film transistor.

A manufacturing method for manufacturing the thin film transistor as described above will be described with reference to FIGS. 6A to 6F and 7A to 7B below.

6A to 6H are plan views illustrating a process of forming a thin film transistor according to an embodiment of the present invention, and FIGS. 7A to 7H are cross-sectional views of a portion cut along the cutting line I-II of FIG. 4 according to the process sequence; am.

As shown in FIGS. 6A and 7A , a gate wiring G and a first gate electrode 111 are formed in order to manufacture the array substrate 101 according to the exemplary embodiment of the present invention.

At this time, in order to form the gate wiring G and the first gate electrode 111 in the form shown in FIGS. 6A and 7A , the gate wiring and the gate electrode are formed on the upper part of the array substrate 101 as shown in FIG. 7A . Depositing a gate wiring forming material 110a to form

In this case, the gate wiring forming material 110a is preferably formed of a metal having a high reflectance or light blocking rate so that light is not transmitted to the channel portion ( 131 in FIG. 5 ).

Thereafter, as shown in FIGS. 6A and 7B , after stacking a first photoresist (not shown), the transmitting portion O and the light blocking portion are formed at positions where the gate wiring G and the first gate electrode 111 are formed. A first photoresist (not shown) is exposed with the first mask M1 on which (C) is formed to form a first photoresist pattern 151 , and a gate wiring G and a first gate electrode 111 are formed. In order to do this, the gate wiring forming material (110a of FIG. 7A ) exposed to the outside of the first photoresist pattern 151 is removed.

At this time, the first gate electrode 111 is formed to have a plate shape, and the channel portion (131 in FIG. 5 ) formed by a subsequent process reacts with light to apply the voltage of the source electrode to the drain electrode. It is preferable to be formed so as not to.

Here, in the embodiment of the present invention, as shown in FIG. 6C , after laminating the gate insulating layer ( 115 in FIG. 7H ), the data line D is formed into the active layer ( 120 in FIG. 7H ) through a separate metal deposition process and etching process. ) will be described as an example.

Thereafter, as shown in FIGS. 6C and 7C , in order to form the active layer 120 and the ESL 132 , the gate insulating layer 115 is formed on the array substrate 101 and the data line D is formed on the upper portion of the gate insulating layer 115 . An active layer 120 made of an IGZO material formed to overlap, an ESL layer 135 and a second photoresist (not shown) are sequentially stacked, and a transmissive part O, a light blocking part C, and a transflective part H are The formed second mask layer M2 is positioned to expose the array substrate 101 .

Through this process, the second photoresist pattern 152 including the first and second pattern portions 152a and 152b is positioned on the array substrate 101 .

In this case, the first pattern part 152a is positioned to correspond to the light blocking part C, and is formed to be higher than the second pattern part 152b positioned to correspond to the transflective part H.

In addition, the active layer 120 formed on the gate insulating layer 115 exhibits the properties of a semiconductor at the time of being stacked, and it is exemplified that a part of the active layer 120 is formed into a conductor by a subsequent process.

Thereafter, as shown in FIGS. 6C and 7D , the ESL layer ( 135 in FIG. 7C ) and the active layer 120 exposed to the outside of the second photoresist pattern 152 are etched.

At this time, the ESL layer (135 in FIG. 7C ) and the active layer 120 exposed to the outside of the second photoresist pattern 152 are etched to expose the gate insulating layer 115 , and the first pattern portion ( FIG. 7C ) is etched. The ESL layer (135 in FIG. 7C) and the active layer 120 at positions corresponding to 152a in 7c) are not etched by the first pattern part (152a in FIG. 7C), and the second pattern part (152b in FIG. 7C) is not etched. The active layer 120 at a position corresponding to , is not etched by the second pattern part (152b in FIG. 7C) and the ESL layer (135 in FIG. 7C), so that it can have the same shape as in FIG. 6C.

In the embodiment of the present invention, since the active layer 120 is formed after the data line D is formed as an example, the first pattern portion ( The second photoresist pattern 152 having the same height as 152a of FIG. 7C is preferably formed.

Thereafter, as shown in FIGS. 6D and 7E , a plasma enhanced chemical vapor deposition (PECVD) process is performed on the active layer 120 exposed to the outside of the ESL 132 .

The PECVD process is used to change the surface properties of a material, particularly, the active layer 120 using plasma, and this process may include argon (Ar) gas.

In this case, the PECVD process is to increase the electrical conductivity by reducing the oxygen ratio of the IGZO forming the active layer 120, and the indium:gallium:zinc:oxygen ratio of the materials constituting the IGZO is 1:1:1: It is preferable to show a ratio of 2.7 or less, and the PECVE process can be replaced with equipment and processes that can reduce the ratio of oxygen constituting IGZO.

In the array substrate 101 on which the active layer 120 is formed, which has been subjected to the process of reducing the oxygen ratio as described above, the source electrode unit 121 connected to the data line D and the periphery of the source electrode unit 121 are formed. The channel portion 131 on which the ESL 132 is positioned and the drain electrode portion 122 spaced apart from the source electrode portion 121 by the channel portion 131 are shown.

In this case, the source electrode part 121 , the channel part 131 , and the drain electrode part 122 are defined within the region of the active layer 120 , and the source electrode part 121 exposed to the outside of the ESL 132 . ) and the drain electrode part 122 exhibit high electrical conductivity by reducing the ratio of oxygen by the PECVD process, and the channel part 131 is covered by the ESL 132 to maintain the oxygen ratio, so that the high electrical conductivity is achieved only above a certain voltage. Shows the semiconductor properties that indicate conductivity.

In addition, although it is shown that the channel part 131 and the drain electrode part 122 are divided into a shape like 'C', except for the source electrode part 121, the shape is not limited, and the source electrode part The 121 and the drain electrode part 122 are not directly connected, and any form in which the channel part 131 is positioned between them may be shown.

The active layer 120 configured as described above includes a thin film transistor having a general structure including source and drain electrodes and a channel part, despite the source electrode part 121 , the channel part 131 , and the drain electrode part 122 being connected to each other. can be driven in the same way.

Thereafter, as shown in FIGS. 6E and 7G , an insulating layer 125 and a second gate electrode are formed on the array substrate 101 on which the source and drain electrode parts 121 and 122 and the channel part 131 are formed. After laminating the forming material 110b and the third photoresist (not shown), the third photoresist pattern 153 is formed by exposing the third photoresist (not shown) using the third mask layer M3. do.

Thereafter, as shown in FIGS. 6E and 7H , the second gate electrode 112 is formed by etching the second gate electrode forming material ( 110b of FIG. 4G ) exposed to the outside of the third photoresist pattern 153 . .

In this case, the second gate electrode forming material 110b may be etched while connected to the first gate electrode 111 to form the second gate electrode 112 connected to the first gate electrode 111 . In this case, the second gate electrode 112 may be formed. A process of forming a gate contact hole GCT in a region where the insulating layer 125 and the first gate electrode 111 overlap may be added to expose the first gate electrode 111 .

In addition, after forming the second gate electrode 112 , a gate contact hole GCT is formed at a position where the second gate electrode 112 and the first gate electrode 111 overlap, and the first gate is formed thereon. A conductive material connecting the electrode 111 and the second gate electrode 112 may be deposited and etched.

Thereafter, an electric field is formed by forming a passivation layer (135 in FIG. 5 ) and a pixel electrode ( 140 in FIG. 5 ) connected to the drain electrode part 122 on the array substrate 101 on which the second gate electrode 112 is formed, or A thin film transistor capable of performing electron injection may be formed.

The thin film transistor having a conventional structure is formed of a source electrode and a drain electrode, and the protective film has a low tensile force, which causes a tearing phenomenon. However, in the thin film transistor formed as described above, since the source electrode and the drain electrode are not formed of metal, and thus the adhesion to the insulating layer 125 formed on the thin film transistor is excellent, the separation of the insulating layer 125 is difficult. This does not occur, and accordingly, there is an effect that a defect in which the second gate electrode 112 is connected to the source or drain electrode does not occur.

In the embodiment of the present invention, the active layer 120 and the ESL 132 are stacked on the data line D by forming the data line D after the gate insulating layer 115 is formed. As a preferred embodiment of the present invention, as described above, the thin film transistor according to the embodiment of the present invention may be formed by including the formation order of the data line D and the source electrode formed extending from the data line D. there is.

In addition, in the embodiment of the present invention, the dual gate structure in which the first and second gate electrodes are formed has been described as an example, but this is only one embodiment according to the embodiment of the present invention, and a bottom gate including a single gate And it is obvious that it can be applied to a dual gate (Top Gate) structure.

Although the above has been described with reference to the preferred embodiment of the present invention, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention described in the claims below. You will understand that it can be done.

110: array substrate 111: first gate electrode
112: second gate electrode 115: gate insulating film
120: active layer 121: source electrode part
122: drain electrode part 131: channel part
132: ESL 135: Shield
140: pixel electrode

Claims (13)

a substrate;
a first gate electrode formed on the substrate;
a gate insulating film formed on the first gate electrode;
a channel portion formed on the gate insulating film;
a source electrode and a drain electrode formed on the gate insulating layer to receive a signal from the outside;
an etch stopper positioned above the channel part;
an insulating layer formed on the channel portion, the source electrode, and the drain electrode;
a second gate electrode positioned on the insulating layer and connected to the first gate electrode through a gate contact hole formed in the insulating layer;
The first gate electrode and the second gate electrode are formed to have the same width to cover the entire channel portion and at least a portion of the source electrode and the drain electrode,
The channel part is made of an active material, and the source electrode and the drain electrode are made of a conductive active material continuously formed with the channel part on the same plane;
The active material is IGZO, the I:G:Z:O ratio of the channel part is 1:1:1:3, and the I:G:Z:O ratio of the source electrode and the drain electrode is 1:1, respectively. 1:1:2.7 or less,
The channel portion is a thin film transistor disposed between the source electrode and the drain electrode.
delete delete a substrate;
a gate wiring formed on the substrate;
a first gate electrode extending from the gate wiring;
a gate insulating film formed on the gate wiring and the first gate electrode;
a data line formed on the gate insulating layer and perpendicular to the gate line;
a channel portion formed on the gate insulating film;
a source electrode and a drain electrode formed on the gate insulating layer and connected to the data line to receive a signal from the outside;
an etch stopper positioned above the channel part;
an insulating layer formed on the channel portion, the source electrode, and the drain electrode;
a second gate electrode positioned on the insulating layer and connected to the first gate electrode through a gate contact hole formed in the insulating layer;
a protective film formed on the insulating layer;
a pixel electrode formed on the passivation layer and connected to the drain electrode part through a drain contact hole formed in the passivation layer;
The first gate electrode and the second gate electrode are formed to have the same width to cover the entire channel portion and at least a portion of the source electrode and the drain electrode,
The channel part is made of an active material, and the source electrode and the drain electrode are made of a conductive active material continuously formed with the channel part on the same plane;
The active material is IGZO, the I:G:Z:O ratio of the channel part is 1:1:1:3, and the I:G:Z:O ratio of the source electrode and the drain electrode is 1:1, respectively. 1:1:2.7 or less,
The channel portion is an array substrate disposed between the source electrode and the drain electrode.
delete delete 5. The method of claim 4,
and the source electrode is positioned above the data line and electrically connected to the data line.
5. The method of claim 4,
and the source electrode is positioned under the data line and electrically connected to the data line.
forming a gate wiring and a first gate electrode on a substrate;
stacking a gate insulating film on the gate wiring and the gate electrode;
sequentially stacking an active layer and an etch stopper layer on the gate insulating layer;
forming a photoresist pattern on the active layer and the etch stopper layer;
exposing a portion of the active layer by partially etching the etch stopper layer exposed to the outside of the photoresist pattern;
forming a channel portion, a source electrode, and a drain electrode continuously configured on the same plane by conducting the exposed active layer;
forming an insulating layer on the channel part, the source electrode, and the drain electrode;
forming a second gate electrode connected to the first gate electrode on the insulating layer;
stacking a passivation layer on the etch stopper layer, the source electrode, and the drain electrode;
forming a second gate electrode on the passivation layer;
forming an insulating film on the gate electrode;
and forming a pixel electrode disposed on the insulating layer and connected to the drain electrode,
the first gate electrode and the second gate electrode are formed to have the same width to cover the entire channel portion and at least a portion of the source electrode and the drain electrode;
The active layer material is IGZO, the I:G:Z:O ratio of the channel part is 1:1:1:3, and the I:G:Z:O ratio of the source electrode and the drain electrode is 1: A method of manufacturing an array substrate of 1:1:2.7 or less.
10. The method of claim 9,
Laminating the gate insulating film includes:
The method of manufacturing an array substrate further comprising the step of forming a data line.
10. The method of claim 9,
Conducting the exposed active layer may further include forming a data line.
10. The method of claim 9,
Forming the photoresist pattern comprises:
preparing a mask layer in which a light blocking part, a transmissive part, and a semi-transmissive part are formed;
forming a first pattern portion and a second pattern portion having a lower height than that of the first pattern portion by exposing a photoresist to the mask layer;
Method of manufacturing an array substrate further comprising
delete

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