KR102285394B1 - Organinc light emitting display device and manufacturing method for the same - Google Patents

Abstract

The present invention discloses an organic light emitting diode display and a method of manufacturing the same.
An organic light emitting diode display according to the present invention includes: a plurality of pixels formed in an area where a plurality of scan lines and a plurality of data lines intersect; a plurality of initialization voltage lines parallel to the plurality of scan lines and shared between two adjacent pixels of a row line to supply an initialization voltage to the two adjacent pixels; and a driving voltage line that supplies a driving voltage to each of the plurality of pixels and includes a first voltage line in a vertical direction and a second voltage line in a horizontal direction connected between the two adjacent pixels.

Description

Organic light emitting display device and manufacturing method thereof

The present invention relates to an organic light emitting diode display and a method for manufacturing the same.

BACKGROUND ART A display device is a device that displays an image, and an organic light emitting diode display (OLED) display has recently been attracting attention.

The organic light emitting diode display has a self-luminous property, and unlike a liquid crystal display device, it does not require a separate light source, so a thickness and weight can be reduced. In addition, the organic light emitting diode display exhibits high quality characteristics such as low power consumption, high luminance, and high response speed.

A panel of an organic light emitting diode display generally includes a plurality of pixels arranged in an NxM matrix, and a data signal Dm, a scan signal Sn, and a power supply voltage ELVDD are applied to each pixel. The power voltage ELVDD may be commonly supplied to all pixel circuits. A parasitic resistance component exists in the wiring for supplying the power supply voltage ELVDD to each pixel, and when the power supply voltage ELVDD is supplied through the wiring, a voltage drop occurs due to the parasitic resistance component.

An object of the present invention is to provide a display device capable of minimizing a leakage current while preventing a voltage drop of the power supply voltage ELVDD by forming a wire for supplying the power supply voltage ELVDD in a mesh structure.

An organic light emitting diode display according to an embodiment of the present invention includes: a plurality of pixels formed in a cross region of a plurality of scan lines and a plurality of data lines; a plurality of initialization voltage lines parallel to the plurality of scan lines and shared between two adjacent pixels of a row line to supply an initialization voltage to the two adjacent pixels; and a driving voltage line that supplies a driving voltage to each of the plurality of pixels and includes a first voltage line in a vertical direction and a second voltage line in a horizontal direction connected between the two adjacent pixels.

The driving voltage line may be arranged in a mesh structure in which the first voltage line and the second voltage line are connected. In addition, each of the first voltage lines of the two adjacent pixels may be formed to face each other while being spaced apart from each other. The driving voltage line may be formed on the same layer as the plurality of data lines.

The initialization voltage line may be disposed parallel to the second voltage line. In addition, the initialization voltage line may be formed on the same layer as the pixel electrode. The initialization voltage line may be electrically connected to the initialization thin film transistor of each of the two pixels through a via hole formed in common with respect to the two adjacent pixels.

An organic light emitting diode display according to an embodiment of the present invention includes: an active layer connected between two adjacent pixels in a row line; a first gate insulating film, a second gate insulating film, and an interlayer insulating film sequentially formed on the active layer; a contact hole formed in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer exposing a portion of a region connected between the two pixels in the active layer; a driving voltage line formed on the interlayer insulating film; a cover metal on the interlayer insulating layer and in contact with the contact hole; a protective film formed on the driving voltage line and the cover metal; a via hole exposing a portion of the cover metal and formed in the passivation layer; and an initialization voltage line connected to the active layer through the via hole.

The driving voltage line may include a first voltage line in a vertical direction and a second voltage line in a horizontal direction connected between the two adjacent pixels. The driving voltage line may be arranged in a mesh structure in which the first voltage line and the second voltage line are connected. The first voltage lines disposed in each of the two adjacent pixels may be spaced apart from each other to face each other. In addition, the driving voltage line may be formed on the same layer as the plurality of data lines.

The initialization voltage line may be disposed parallel to the second voltage line. The initialization voltage line may be formed on the same layer as the pixel electrode.

The active layer may be formed in a symmetrical structure between the two pixels based on a region connected between the two pixels. A portion of the active layer may be disposed in a direction perpendicular to the second voltage line and overlap the second voltage line.

A method of manufacturing an organic light emitting diode display according to an embodiment of the present invention includes: forming an active layer connected between two adjacent pixels in a row line on a substrate; sequentially forming a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer on the active layer; forming a contact hole in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer to expose a portion of a region connected between the two pixels in the active layer; forming a driving voltage line and a cover metal contacting the contact hole on the interlayer insulating layer; forming a protective layer on the driving voltage line and the cover metal; forming a via hole in the passivation layer to expose a portion of the cover metal; and forming an initialization voltage line connected to the active layer through the via hole.

The driving voltage line may include a first voltage line in a vertical direction and a second voltage line in a horizontal direction connected between the two pixels, and may have a mesh structure in which the first voltage line and the second voltage line are connected.

The initialization voltage line may be formed parallel to the second voltage line.

The active layer has a symmetrical structure between the two pixels based on a region connected between the two pixels, and in each pixel, a portion of the active layer is disposed in a direction perpendicular to the second voltage line, the second voltage line and It may be formed to overlap.

The display device according to the present invention has an effect of compensating for a voltage drop of a power voltage applied to each pixel due to an increase in the size of a panel of the display device.

In addition, the display device according to the present invention has an effect of improving black luminance by minimizing a parasitic capacitor.

1 is a block diagram schematically illustrating a display device according to an exemplary embodiment.
2 is an equivalent circuit diagram of one pixel of a display device according to an exemplary embodiment.
3 is a schematic circuit diagram of two adjacent pixels of a display device according to an exemplary embodiment.
4 is a diagram illustrating a network structure of a driving voltage line PL of a display device according to an exemplary embodiment.
5 to 10 are diagrams for explaining a method of forming a pixel circuit of two adjacent pixels according to an embodiment of the present invention.
11 to 13 are views for explaining a comparative example with respect to the embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings, various embodiments of the present invention will be described in detail so that those of ordinary skill in the art can easily implement them. The present invention may be embodied in many different forms and is not limited to the embodiments described herein.

In order to clearly explain the present invention, parts irrelevant to the description are omitted, and the same reference numerals are given to the same or similar elements throughout the specification.

In addition, since the size and thickness of each component shown in the drawings are arbitrarily indicated for convenience of description, the present invention is not necessarily limited to the illustrated bar.

In order to clearly express various layers and regions in the drawings, the thicknesses are enlarged. And in the drawings, for convenience of description, the thickness of some layers and regions are exaggerated. When a part, such as a layer, film, region, plate, etc., is "on" or "on" another part, it includes not only the case where the other part is "directly on" but also the case where there is another part in between.

In addition, throughout the specification, when a part "includes" a certain component, this means that other components may be further included, rather than excluding other components, unless otherwise stated. In addition, throughout the specification, "on" means to be located above or below the target part, and does not necessarily mean to be located above the direction of gravity.

1 is a block diagram schematically illustrating a display device according to an exemplary embodiment.

The display device 100 according to an exemplary embodiment includes a display unit 10 including a plurality of pixels, a scan driver 20 , a data driver 30 , and a controller 40 . The scan driver 20 , the data driver 30 , and the controller 40 may be respectively formed on separate semiconductor chips or may be integrated into one semiconductor chip. Also, the scan driver 20 may be formed on the same substrate as the display unit 10 .

The display unit 10 is positioned at the intersection of the plurality of scan lines SL0 to SLn, the plurality of data lines DL1 to DLm, and the plurality of light emission control lines EL1 to ELn, and is arranged in a substantially matrix form. contains pixels.

Each pixel is connected to two scan lines among the plurality of scan lines SL0 to SLn transmitted to the display unit 10 . In FIG. 1 , a pixel is connected to a scan line corresponding to a corresponding pixel line and a scan line of a previous pixel line, but the present invention is not limited thereto.

In addition, each pixel is connected to one data line among the plurality of data lines DL1 to DLm and to one light emission control line among the plurality of light emission control lines EL1 to ELn.

In addition, each pixel is connected to one of the plurality of initialization voltage lines VL supplying the initialization voltage and one of the plurality of driving voltage lines PL supplying the first power voltage ELVDD.

The plurality of scan lines SL0 to SLn are symmetrical to each other in an extending direction, that is, a row line (or a pixel line, a horizontal direction, or a horizontal direction). Two adjacent pixels having a symmetric structure share an initialization voltage line VL arranged in a row line. The driving voltage lines PL arranged in a column line (or vertical direction, vertical direction) of two adjacent pixels having a symmetric structure are spaced apart from each other by a predetermined distance to face in parallel, and the two driving voltage lines PL are symmetrical to the column line. They are connected to each other by driving voltage lines PL arranged in a row line to form a mesh structure.

The scan driver 20 generates and transmits two corresponding scan signals to each pixel through the plurality of scan lines SL0 to SLn. That is, the scan driver 20 transmits a first scan signal through a scan line corresponding to a row line including each pixel, and transmits a second scan signal through a scan line corresponding to a previous row line of the corresponding row line. For example, the scan driver 20 transmits the first scan signal Sn through the n-th scan line SLn to the pixel disposed on the m-th column line of the n-th row line, and the n-1 th scan line SLn. The second scan signal Sn-1 is transmitted through -1). Also, the scan driver 20 generates and transmits the emission control signals EM1 to EMn to each pixel through the plurality of emission control lines EL1 to ELn. In the present embodiment, it is illustrated that the scan signal and the emission control signal are generated by the same scan driver 20, but the present invention is not limited thereto. The display device 100 may further include a light emission control driver, and the emission control signal may be generated by the light emission control driver.

The data driver 30 transmits the data signals D1 to Dm to each pixel through the plurality of data lines DL1 to DLm.

The controller 40 converts the plurality of image signals R, G, and B transmitted from the outside into the plurality of image data signals DR, DG, and DB and transmits the converted image signals to the data driver 30 . In addition, the control unit 40 receives the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the clock signal MCLK to receive a control signal for controlling the driving of the scan driver 20 and the data driver 30 . Create and pass to each. That is, the controller 50 generates a scan driving control signal SCS and an emission driving control signal ECS for controlling the scan driver 20 , and a data driving control signal DCS for controlling the data driver 30 , respectively. transmit

Each of the plurality of pixels emits light having a predetermined luminance by the driving current Ioled supplied to the organic light emitting diode OLED according to the data signals D0 to Dm transmitted through the plurality of data lines DL1 to DLm. .

2 is an equivalent circuit diagram of one pixel of a display device according to an exemplary embodiment. 3 is a schematic circuit diagram of two adjacent pixels of a display device according to an exemplary embodiment.

The pixel 1 shown in FIGS. 2 and 3 is one of a plurality of pixels included in the n-th row line, and includes a scan line SLn corresponding to the n-th row line and an n-1 th row before the n-th row line. They are respectively connected to the scan line SLn-1 corresponding to the line.

One pixel 1 of the organic light emitting diode display according to an exemplary embodiment includes a pixel circuit 2 including a plurality of thin film transistors T1 to T6 and a storage capacitor (Cst). In addition, the pixel 1 includes an organic light emitting diode (OLED) that emits light by receiving a driving voltage through the pixel circuit 2 .

The thin film transistor includes a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, an initialization thin film transistor T4, a first emission control thin film transistor T5, and a second emission control thin film transistor T6. includes

The pixel 1 includes a first scan line SLn that transmits the first scan signal Sn to the switching thin film transistor T2 and the compensation thin film transistor T3 , and a second scan signal that is a previous scan signal to the initialization thin film transistor T4 . a second scan line SLn-1 transmitting the signal Sn-1, an emission control line ELn transmitting an emission control signal EMn to the operation control thin film transistor T5 and the emission control thin film transistor T6; The data line DLm intersecting the first scan line SLn and transmitting the data signal Dm, and the driving voltage line PL transmitting the first power voltage ELVDD and substantially parallel to the data line DLm , an initialization voltage line VL that transmits an initialization voltage VINT for initializing the driving thin film transistor T1 and is formed substantially parallel to the second scan line SLn-1.

The gate electrode G1 of the driving thin film transistor T1 is connected to the first electrode Cst1 of the storage capacitor Cst. The source electrode S1 of the driving thin film transistor T1 is connected to the driving voltage line PL via the first emission control thin film transistor T5. The drain electrode D1 of the driving thin film transistor T1 is electrically connected to the anode electrode of the organic light emitting diode OLED via the second emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2 and supplies the driving current Ioled to the organic light emitting diode OLED.

The gate electrode G2 of the switching thin film transistor T2 is connected to the first scan line SLn. The source electrode S2 of the switching thin film transistor T2 is connected to the data line DLm. The drain electrode D2 of the switching thin film transistor T2 is connected to the source electrode S1 of the driving thin film transistor T1 and connected to the driving voltage line PL via the first emission control thin film transistor T5. . The switching thin film transistor T2 is turned on according to the first scan signal Sn transmitted through the first scan line SLn and drives the data signal Dm transmitted through the data line DLm to the driving thin film transistor T1 . performing a switching operation of transferring to the source electrode S1 of

The gate electrode G3 of the compensation thin film transistor T3 is connected to the first scan line SLn. The source electrode S3 of the compensation thin film transistor T3 is connected to the drain electrode D1 of the driving thin film transistor T1 and the anode of the organic light emitting diode OLED via the second light emission control thin film transistor T6. anode) is connected to the electrode. The drain electrode D3 of the compensation thin film transistor T3 includes the first electrode Cst1 of the storage capacitor Cst, the drain electrode D4 of the initialization thin film transistor T4, and the gate electrode G1 of the driving thin film transistor T1. ) is connected with The compensation thin film transistor T3 is turned on according to the first scan signal Sn transmitted through the first scan line SLn to connect the gate electrode G1 and the drain electrode D1 of the driving thin film transistor T1 to each other. Thus, the driving thin film transistor T1 is diode-connected.

The gate electrode G4 of the initialization thin film transistor T4 is connected to the second scan line SLn-1. The source electrode S4 of the initialization thin film transistor T4 is connected to the initialization voltage line VL. The drain electrode D4 of the initialization thin film transistor T4 includes the first electrode Cst1 of the storage capacitor Cst, the drain electrode D3 of the compensation thin film transistor T3, and the gate electrode G1 of the driving thin film transistor T1. ) is connected with The initialization thin film transistor T4 is turned on according to the second scan signal Sn-1 received through the second scan line SLn-1 to apply the initialization voltage VINT to the gate electrode G1 of the driving thin film transistor T1. ) to initialize the voltage of the gate electrode G1 of the driving thin film transistor T1 is performed.

The gate electrode G5 of the first emission control thin film transistor T5 is connected to the emission control line ELn. The source electrode S5 of the first emission control thin film transistor T5 is connected to the driving voltage line 26 . The drain electrode D5 of the first emission control thin film transistor T5 is connected to the source electrode S1 of the driving thin film transistor T1 and the drain electrode D2 of the switching thin film transistor T2 .

The gate electrode G6 of the second emission control thin film transistor T6 is connected to the emission control line ELn. The source electrode S6 of the second emission control thin film transistor T6 is connected to the drain electrode D1 of the driving thin film transistor T1 and the source electrode S3 of the compensation thin film transistor T3 . The drain electrode D6 of the second emission control thin film transistor T6 is electrically connected to the anode electrode of the organic light emitting diode OLED. The second light emission control thin film transistor T5 and the second light emission control thin film transistor T6 are simultaneously turned on according to the light emission control signal EMn received through the light emission control line 34 to increase the first power voltage ELVDD. The driving current Ioled flows through the organic light emitting diode OLED.

The second electrode Cst2 of the storage capacitor Cst is connected to the driving voltage line PL. The first electrode Cst1 of the storage capacitor Cst is the gate electrode G1 of the driving thin film transistor T1, the drain electrode D3 of the compensation thin film transistor T3, and the drain electrode of the initialization thin film transistor T4 ( D4) are connected together.

A cathode electrode of the organic light emitting diode OLED is connected to the second power voltage ELVSS. The organic light emitting diode OLED receives the driving current Ioled from the driving thin film transistor T1 and emits light to display an image. The first power voltage ELVDD may be a predetermined high level voltage, and the second power voltage ELVSS may be a voltage lower than the first power voltage ELVDD or a ground voltage.

Referring to FIG. 3 , an initialization voltage line VL supplying an initialization voltage VINT, a first scan line SLn supplying a first scan signal Sn, and a first scan line SLn supplying a second scan signal Sn-1 The two scan lines SLn-1 and the emission control line ELn for supplying the emission control signal EMn are formed in parallel in the horizontal direction. In addition, the data lines DLm-1 and DLm and the driving voltage line PL are formed in parallel in a vertical direction perpendicular to the horizontal direction.

The two adjacent pixels 1 share the initialization voltage line VL, and the data lines DLm-1 and DLm and the driving voltage line PL are formed to face each other at a predetermined distance apart from each other. The driving voltage lines PL facing each other are connected by the connecting wirings 118 formed in the horizontal direction to form a mesh structure, so that power can be supplied in the horizontal and vertical directions. Accordingly, the area of the wiring supplying power is further expanded, so that the voltage drop phenomenon caused by the resistance of the wiring itself can be solved.

According to an embodiment of the present invention, the two adjacent pixels 1 share the initialization voltage line VL, so that the two adjacent pixels 1 may have a symmetrical structure. Accordingly, the data line DLm-1 in the vertical direction and the driving voltage line PL in the vertical direction of the left pixel 1 are arranged on the left outer side of the left pixel 1, and the vertical direction of the right pixel 1 is disposed. The data line DLm and the vertical driving voltage line PL may be disposed outside the right side of the right pixel 1 . Therefore, since no other signal wiring of the same layer is disposed between the two driving voltage lines PL in the vertical direction of the left pixel and the right pixel 1 , it is formed on the same layer as the vertical driving voltage line PL at the same time. It is possible to connect two driving voltage lines PL in the vertical direction with the connection wiring 118 .

4 is a diagram illustrating a network structure of a driving voltage line PL of a display device according to an exemplary embodiment.

Referring to FIG. 4 , the driving voltage line PL of the display device according to the exemplary embodiment includes a vertical driving voltage line PLV extending in a vertical direction for each column line and two pixels (eg, a row line) adjacent to each other. For example, it is formed in a mesh structure including a horizontal driving voltage line PLH connecting between PX1 and PX2. The horizontal driving voltage line PLH is formed by a connection line 118 connecting the two vertical driving voltage lines PLV. The connection wiring 118 may be integrally formed as a wiring extending from the vertical driving voltage line PLV, or may be formed as separate wirings.

The horizontal driving voltage line PLH is arranged according to the arrangement of elements of the pixel circuit. Each vertical driving voltage line PLV of two pixels (eg, the first pixel PX1 and the second pixel PX2 ) sharing the horizontal driving voltage line PLH is spaced apart from each other and disposed to face each other. On the other hand, the vertical driving voltage lines PLV of two adjacent pixels that do not share the horizontal driving voltage line PLH (eg, the second pixel PX2 and the third pixel PX3 ) are disposed to face each other close to each other. do. The horizontal driving voltage line PLH is not formed between two adjacent pixels that do not share the horizontal driving voltage line PLH (eg, the second pixel PX2 and the third pixel PX3 ).

5 to 10 are diagrams for explaining a method of forming a pixel circuit of two adjacent pixels according to an embodiment of the present invention. 9 is a cross-sectional view taken along line A-A' of FIG. 8 .

5 and 9 , active layers 112 - 1 and 112 - 2 of the first pixel PX1 and the second pixel PX2, respectively, are formed on the substrate 101 . The first active layer 112-1 of the first pixel PX1 and the second active layer 112-2 of the second pixel PX2 are connected to each other. The first active layer 112 - 1 and the second active layer 112 - 2 are formed in a symmetrical structure with respect to a region connected between the first pixel PX1 and the second pixel PX2 . The active region connected between the first pixel PX1 and the second pixel PX2 is later connected to the initialization voltage line VL.

The first active layer 112-1 and the second active layer 112-2 are formed of an amorphous silicon layer, a polycrystalline silicon layer, or a GIZO layer [(In2O3)a(Ga2O3)b(ZnO)c layer. ] (a, b, and c are real numbers satisfying the conditions of a≥0, b≥0, and c>0, respectively). According to an embodiment of the present invention, since the first active layer 112-1 and the second active layer 112-2 are connected to each other, the initialization voltage VINT applied from the initialization voltage line VL is applied to the first It may be transmitted to the pixel PX1 and the second pixel PX2 .

A thin film transistor of a pixel circuit is formed along the first active layer 112-1 and the second active layer 112-2. A driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, an initialization thin film transistor T4, and a second thin film transistor T1, Active layers A1, A2, A3, A4, A5, and A6 of the first light emission control thin film transistor T5 and the second light emission control thin film transistor T6 are formed. The active layer of each thin film transistor includes a channel region not doped with impurities, and a source region and a drain region formed by doping both sides of the channel region with impurities. Here, the impurity varies depending on the type of the thin film transistor, and may be an N-type impurity or a P-type impurity.

The first active layer 112-1 and the second active layer 112-2 are bent in various shapes. In particular, the active layer A1 of the driving thin film transistor T1 has a plurality of curved portions in a zigzag shape, an 'S' shape, or a 'R' shape. Accordingly, the channel region can be formed to be long, so that the driving range of the gate voltage is widened. Therefore, since the driving range of the gate voltage is wide, it is possible to more precisely control the gradation of light emitted from the organic light emitting diode (OLED) by changing the size of the gate voltage, and as a result, the resolution of the organic light emitting diode display is increased and display quality is increased. can improve

6 and 9 , a first gate insulating layer 102 is formed on the substrate 101 on which the first active layer 112-1 and the second active layer 112-2 are formed. The first gate insulating layer 102 may be formed of an organic insulating material, an inorganic insulating material, or a multilayer structure in which an organic insulating material and an inorganic insulating material are alternated.

Then, a first gate line GL1 is formed on the first gate insulating layer 102 . The first gate line GL1 may include a first scan line SLn, a second scan line SLn-1, an emission control line ELn, and first capacitor electrodes 114 - 1 and 114 - 2 . The material of the first gate line GL1 may include a low-resistance metal material such as aluminum (Al) or copper (Cu).

The first capacitor electrodes 114 - 1 and 114 - 2 also serve as the gate electrode G1 of the driving thin film transistor T1 at the same time. The first capacitor electrodes 114-1 and 114-2 are separated from the first scan line SLn, the second scan line SLn-1, and the emission control line ELn, and are formed as floating electrodes. T1) overlaps the channel region of the active layer A1. The first capacitor electrodes 114 - 1 and 114 - 2 are separated from adjacent pixels and formed in a rectangular shape. The first scan line SLn serves as the gate electrode G2 of the switching thin film transistor T2 and the gate electrode G3 of the compensation thin film transistor T3 . The second scan line SLn-1 serves as the gate electrode G4 of the initialization thin film transistor T4. The emission control line ELn serves as the gate electrode G5 of the first emission control thin film transistor T5 and the gate electrode G6 of the second emission control thin film transistor T6 .

7 and 9 , a second gate insulating layer 103 is formed on the substrate 101 on which the first gate line GL1 is formed. The second gate insulating layer 103 also functions as a dielectric of the storage capacitor Cst. The second gate insulating layer 103 may be formed of an organic insulating material, an inorganic insulating material, or a multilayer structure in which an organic insulating material and an inorganic insulating material are alternated.

Then, a second gate wiring GL2 is formed on the second gate insulating layer 103 . The second gate line GL2 may include second capacitor electrodes 116 - 1 and 116 - 2 . The material of the second gate line GL2 also preferably includes a low-resistance metal material such as aluminum (Al) or copper (Cu), similar to the material of the first gate line GL1 .

The second capacitor electrodes 116 - 1 and 116 - 2 overlap the first capacitor electrodes 114 - 1 and 114 - 2 to form a storage capacitor Cst. The second capacitor electrodes 116 - 1 and 116 - 2 are separated between adjacent pixels having a symmetric structure sharing the initialization voltage VINT and are connected between adjacent pixels based on the data line. The second capacitor electrodes 116 - 1 and 116 - 2 have a storage opening 115 . The storage opening 115 may have a shape of a single closed curve. Here, a single closed curve means a closed figure with the same starting point and the same ending point when a point is drawn on a straight line or curve, such as a polygon or a circle. The second capacitor electrodes 116-1 and 116-2 having the storage opening 115 may have a donut shape. Due to the shape of the second capacitor electrodes 116-1 and 116-2, the first capacitor electrodes 114-1 and 114-2 and the second capacitor electrodes 116-1 and 116- are used during the manufacturing process of the display device. 2) Even if an overlay deviation occurs between the two, the storage capacitor Cst may always maintain a constant capacitance. Overlay deviation means that when two or more layers overlapping each other are formed, when each layer is shifted in the up, down, left, and right directions, the overlapping area is different from the initially designed overlapping area. difference in the area. Overlay deviation is caused by a misalignment between a substrate and a mask or a misalignment between a substrate and an exposure machine when a conductive layer is formed on the entire substrate and patterned by a photo lithography process. may occur due to There is a high probability that such an overlay deviation may occur within the error range of the process equipment in a system in which a panel is enlarged and a large number of panels are produced at the same time. In the embodiment of the present invention, even when the first capacitor electrodes 114-1 and 114-2 are shifted up, down, left, or right from the designed positions, the second capacitor electrodes 116-1 and 116-2 are always The first capacitor electrodes 114-1 and 114-2 overlap the entirety of the first capacitor electrodes 114-1 and 114-2, and the storage opening 115 of the second capacitor electrodes 116-1 and 116-2 always overlaps the first capacitor electrodes 114-1 and 114-2. Since it overlaps with 2), the capacitance can be kept constant.

8 and 9 , an interlayer insulating layer 104 is formed on the substrate 101 on which the second gate line GL2 is formed. Like the first gate insulating layer 102 and the second gate insulating layer 103 , the interlayer insulating layer 104 may be formed in a multilayer structure in which an organic insulating material or an inorganic insulating material, or an organic insulating material and an inorganic insulating material are alternated. .

The second gate insulating layer 103 and the interlayer insulating layer 104 pass through the opening 115 of the second capacitor electrodes 116-1 and 116-2 to expose the first capacitor electrodes 114-1 and 114-2. is provided with a first contact hole Cnt1. In addition, a third contact hole Cnt3 is provided on the interlayer insulating layer 104 to expose the second capacitor electrodes 116 - 1 and 116 - 2 . In addition, the first gate insulating layer 102 and the second gate insulating layer 103 are exposed to expose the drain region of the active layer A3 of the compensation thin film transistor T3 and the drain region of the active layer A4 of the initialization thin film transistor T4. ) and the interlayer insulating layer 104 are provided with a second contact hole Cnt2. In addition, a fourth contact hole Cnt4 is formed in the first gate insulating layer 102 , the second gate insulating layer 103 , and the interlayer insulating layer 104 to expose the source region of the active layer A2 of the switching thin film transistor T2 . provided A fifth contact hole Cnt5 is formed in the first gate insulating layer 102 , the second gate insulating layer 103 , and the interlayer insulating layer 104 to expose the active layer A5 of the first emission control thin film transistor T5 . provided A sixth contact hole Cnt6 is formed in the first gate insulating layer 102 , the second gate insulating layer 103 , and the interlayer insulating layer 104 to expose the active layer A6 of the second emission control thin film transistor T6 . provided In addition, the first gate insulating layer 102 to expose a region where the first active layer 112-1 of the first pixel PX1 and the second active layer 112-2 of the second pixel PX2 are connected to each other; A seventh contact hole Cnt7 is provided in the second gate insulating layer 103 and the interlayer insulating layer 104 .

Next, the data lines DLm-1 and DLm, the driving voltage line PL in the vertical direction, the connection line 118, the first contact hole Cnt1 and the second contact hole Cnt2 are formed on the interlayer insulating layer 104 on the upper portion. A connecting wire 120 connecting the , a first cover metal CM1 formed to cover the sixth contact hole Cnt6, and a second cover metal CM2 formed to cover the seventh contact hole Cnt7 are formed. do.

The data lines DLm-1 and DLm are vertically disposed outside the pixel, one for each pixel. The data lines DLm-1 and DLm are connected to the switching thin film transistor T2 through the fourth contact hole Cnt4.

The driving voltage line PL includes a vertical driving voltage line PL and a horizontal connection line 118 . The vertical driving voltage lines PL are disposed in the vertical direction at the outer edge of the pixel adjacent to the data lines DLm-1 and DLm, one for each pixel. The two vertical driving voltage lines PL face each other with the first pixel PX1 and the second pixel PX2 interposed therebetween. The connection wiring 118 crosses the first pixel PX1 and the second pixel PX2 in the horizontal direction, and connects the driving voltage line PL of the first pixel PX1 and the second pixel PX2 in the vertical direction to each other. By connecting it, it serves as a driving voltage line PL in the horizontal direction. Accordingly, a mesh structure of the driving voltage line PL is implemented. The driving voltage line PL is connected to the first capacitor electrodes 114 - 1 and 114 - 2 through the third contact hole Cnt3 .

The connection line 120 connects the first capacitor electrodes 114 - 1 and 114 - 2 to the compensation thin film transistor T3 and the initialization thin film transistor T4 .

The data lines DLm-1 and DLm, the driving voltage line PL including the connection wiring 118, the connection wiring 120, the first cover metal CM1, and the second cover metal CM2 are on the same layer. It may be formed of a material.

Next, the data lines DLm-1 and DLm, the driving voltage line PL including the connection wiring 118, the connection wiring 120, the first cover metal CM1, and the second cover metal CM2 are formed. A passivation layer 105 is formed on the substrate 101 . A first via hole VH1 and a second via hole VH2 exposing a portion of each of the first cover metal CM1 and the second cover metal CM2 are formed in the passivation layer 105 , respectively. The first via hole VH1 and the second via hole VH2 may be formed of the same material.

By forming the second via hole VH2 in common with respect to the two adjacent pixels PX1 and PX2 , the aperture ratio of the pixel may be improved compared to the case where the second via hole VH2 is formed for each pixel.

Referring to FIG. 10 , the pixel electrodes PE1 and PE2 and the initialization voltage line VL are formed on the passivation layer 105 . The pixel electrodes PE1 and PE2 are respectively connected to the second emission control thin film transistor T6 through the first via hole VH1. In addition, the initialization voltage line VL is connected to the initialization thin film of the first pixel PX1 and the second pixel PX2 through the second via hole VH2 formed in common for the first pixel PX1 and the second pixel PX2 . It is connected to the transistor T4 to simultaneously transfer the initialization voltage VINT to the first pixel PX1 and the second pixel PX2 . The initialization voltage line VL may be formed on the same layer as the pixel electrodes PE1 and PE2 and made of the same material.

Although not shown, a pixel defining layer is formed on the edges of the pixel electrodes PE1 and PE2 and on the passivation layer 105 , and the pixel defining layer has a pixel opening exposing the pixel electrodes PE1 and PE2 . The pixel defining layer may be made of an organic material such as polyacrylates resin and polyimides, or an inorganic material such as silica. In addition, the organic layers OE1 and OE2 and the opposite electrode (not shown) covering the organic layers OE1 and OE2 are formed on the pixel electrodes PE1 and PE2 exposed through the pixel opening. Accordingly, the pixel electrodes PE1 and PE2, the organic layers OE1 and OE2 disposed on the pixel electrodes PE1 and PE2, and the opposite electrode (not shown) covering the organic layers OE1 and OE2 and formed on the entire surface of the substrate ) of the first pixel PX1 and the second pixel PX2 each including an organic light emitting diode OLED is formed.

When the display device has a top emission type structure, the pixel electrodes PE1 and PE2 may be provided as reflective electrodes, and the opposite electrodes may be provided as light transmitting electrodes. In this case, the counter electrode may include a transflective film formed as a thin film of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or the like, or light such as ITO, IZO, ZnO, etc. permeable metal oxides. When the display device has a bottom emission type structure, the counter electrode may have a reflective function by depositing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or the like. When the pixel electrodes PE1 and PE2 are used as anode electrodes, a layer made of a metal oxide such as ITO, IZO, or ZnO having a high work function (absolute value) is included. When the pixel electrodes PE1 and PE2 are used as cathode electrodes, highly conductive metals with low work functions (absolute values) such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, etc. use When the pixel electrodes PE1 and PE2 are used as an anode electrode, the opposite electrode is a cathode electrode, and when the pixel electrodes PE1 and PE2 are used as a cathode, the opposite electrode is an anode electrode.

The organic layers OE1 and OE2 of the first pixel PX1 and the second pixel PX2 include an organic emissive layer (EML), a hole transport layer (HTL), and a hole injection layer (hole injection). Layer: HIL), an electron transport layer (ETL), and any one or more of functional layers such as an electron injection layer (EIL) may be formed by stacking a single or complex structure. The organic layers OE1 and OE2 may be formed of a low molecular weight or high molecular weight organic material. When the organic layers OE1 and OE2 emit red, green, and blue light, respectively, the light emitting layer is to be patterned into a red light emitting layer, a green light emitting layer and a blue light emitting layer according to the red sub-pixel, the green sub-pixel, and the blue sub-pixel, respectively. can On the other hand, when the organic layers OE1 and OE2 emit white light, the light emitting layer has a multilayer structure in which a red light emitting layer, a green light emitting layer and a blue light emitting layer are stacked to emit white light, or a red light emitting material, a green light emitting material and It may have a single layer structure including a blue light emitting material.

11 to 13 are views for explaining a comparative example with respect to the embodiment of the present invention. 12 is a cross-sectional view taken along line B-B' of FIG. 11 .

11 to 13 , the active layer 212 - 1 of the first pixel PX1 and the active layer 212 - 2 of the second pixel PX2 are formed on the substrate 101 to be separated from each other. . The first gate insulating layer 102 , the first gate wiring GL1 , the second gate insulating layer 103 , the second gate wiring GL2 , and the interlayer insulating layer 104 are formed on the active layers 212 - 1 and 212 - 2 . ) are formed in turn. The first gate line GL1 may include a first scan line SLn, a second scan line SLn-1, an emission control line ELn, and first capacitor electrodes 214 - 1 and 214 - 2 . The second gate line GL2 may include second capacitor electrodes 216 - 1 and 216 - 2 . The second capacitor electrode 216 - 1 of the first pixel PX1 and the second capacitor electrode 216 - 2 of the second pixel PX2 are connected to each other.

A data line DL and a driving voltage line PL are respectively formed on the interlayer insulating layer 104 . The second capacitor electrode 216 - 1 of the first pixel PX1 and the second capacitor electrode 216 - 2 of the second pixel PX2 are respectively connected to the driving voltage line PL through a contact hole, The capacitor electrodes 216 - 1 and 216 - 2 also serve to implement a mesh structure of the driving voltage line PL. In addition, a first cover metal CM1 and a second cover metal CM2 are formed on the interlayer insulating layer 104 .

A passivation layer 105 is formed on the substrate 101 on which the data lines DLm-1 and DLm, the driving voltage line PL, the first cover metal CM1, and the second cover metal CM2 are formed. In the passivation layer 105 , a first via hole VH1 and a second via hole VH2 exposing a portion of each of the first cover metal CM1 and the second cover metal CM2 are formed in the first pixel PX1 and the second pixel. (PX2), respectively.

Then, the pixel electrodes PE1 and PE2 and the initialization voltage line VL are formed on the passivation layer 105 . Each of the pixel electrodes PE1 and PE2 is connected to the second emission control thin film transistor T6 of each of the pixels PX1 and PX2 through the first via hole VH1. And, the initialization voltage line VL is connected to the initialization thin film transistor T4 of each of the pixels PX1 and PX2 through the second via hole VH2 formed in each of the first and second pixels PX1 and PX2, The initialization voltage VINT is transmitted to the first pixel PX1 and the second pixel PX2, respectively.

9, the driving voltage line PL having a mesh structure including the vertical driving voltage line PLV and the horizontal driving voltage line PLH is the same as the data lines DLm-1 and DLm. The layer is formed of the same material. Accordingly, the second connection line 118 constituting the horizontal driving voltage line PLH is disposed between the connection wiring 118 and the lower active layers 112-1 and 112-2 disposed in a direction substantially orthogonal to the connection wiring 118 . A first gate insulating film 102 , a second gate insulating film 103 , and an interlayer insulating film 104 are disposed.

On the other hand, in the case of the comparative example of FIG. 12 , the driving voltage line PL having a mesh structure is formed as the second capacitor electrodes 216 - 1 and 216 - 2 which are the second gate wirings GL2 . Accordingly, the first gate insulating layer 102 and the second gate insulating layer ( 103) is placed.

9 and 12, the capacitance of the parasitic capacitor C1 generated between the driving voltage line PL and the active layers 112-1 and 112-2 in the embodiment of the present invention is, in the comparative example, the driving voltage line ( PL) and the parasitic capacitor C2 generated between the active layers 212-1 and 112-2.

The parasitic capacitor generated between the driving voltage line PL of the mesh structure and the active layer causes an increase in leakage current flowing to the pixel electrode of the organic light emitting diode OLED through the second light emission control thin film transistor T6, The black luminance of the display device is increased.

In the embodiment of the present invention, by forming the horizontal driving voltage line PLH on the same layer as the vertical driving voltage line PLV formed on the same layer as the data lines DLm-1 and DLm, the driving voltage line ( A thick insulating layer may be formed between the PL) and the active layers 112-1 and 112-2. That is, in the embodiment of the present invention, by maximizing the gap between the driving voltage line PL and the active layer, which are two signal lines, unnecessary parasitic capacitors can be reduced, thereby preventing black luminance increase, and thus screen distortion. can reduce

In addition, in the embodiment of the present invention, since the driving voltage line PL is formed in a mesh structure, the first power voltage ELVDD having a predetermined size can be supplied to the pixel, thereby reducing the voltage drop.

In the above-described embodiment, an active matrix (AM) type organic light emitting diode display having a 6Tr-1Cap structure including six thin film transistors (TFTs) and one capacitor in one pixel is provided. Although illustrated, the present invention is not limited thereto. Accordingly, the display device may include a plurality of thin film transistors and one or more capacitors in one pixel, and may be formed to have various structures by further forming separate wires or omitting existing wires.

In the present specification, the present invention has been described with reference to limited embodiments, but various embodiments are possible within the scope of the present invention. In addition, although not described, it will be said that equivalent means are also combined with the present invention as it is. Therefore, the true scope of protection of the present invention should be defined by the following claims.

Claims (30)

A scan line extending in the first direction:
a first data line extending in a second direction different from the first direction;
a first driving voltage line extending in the second direction;
an initialization voltage line extending in the first direction;
a first thin film transistor including a first gate electrode and a first active layer having a curved lower portion of the first gate electrode and electrically connected to the first driving voltage line;
a second thin film transistor connected to the first data line and the first thin film transistor and including a gate electrode connected to the scan line;
a third thin film transistor connected to the first gate electrode of the first thin film transistor and the initialization voltage line;
a first light emitting device electrically connected to the first thin film transistor;
a first insulating film covering the first gate electrode of the first thin film transistor; and
a first capacitor electrically connected to the first gate electrode of the first thin film transistor; and
and the first capacitor includes a first capacitor electrode including a part of the first gate electrode of the first thin film transistor and a second capacitor electrode overlapping the first capacitor electrode.
A portion of the first insulating film is provided between the first capacitor electrode and the second capacitor electrode,
One end of the first active layer extends to the second thin film transistor, and the other end of the first active layer extends to the third thin film transistor. According to claim 1,
and a fourth thin film transistor connected to the first driving voltage line and the first thin film transistor. 3. The method of claim 2,
and one end of the first active layer extends to the fourth thin film transistor. 3. The method of claim 2,
and a second insulating film on the second capacitor electrode. 5. The method of claim 4,
The first light emitting device includes a first pixel electrode provided on the second insulating layer and electrically connected to the first thin film transistor. 5. The method of claim 4,
and the initialization voltage line is provided on the second insulating layer. 7. The method of claim 6,
and one end of the first active layer extends to the fourth thin film transistor. 8. The method of claim 7,
and a cover metal connected to the initialization voltage line and the third thin film transistor. According to claim 1,
a second data line extending in the second direction;
a second driving voltage line extending in the second direction;
a fifth thin film transistor including a second gate electrode and a second active layer having a curved lower portion of the second gate electrode and electrically connected to the second driving voltage line;
a sixth thin film transistor connected to the second data line and the fifth thin film transistor and including a gate electrode connected to the scan line;
a seventh thin film transistor connected to the second gate electrode of the fifth thin film transistor and the initialization voltage line;
a second light emitting device electrically connected to the fifth thin film transistor; and
a second capacitor electrically connected to the second gate electrode of the fifth thin film transistor; and
and the second capacitor includes a third capacitor electrode including a part of the second gate electrode of the fifth thin film transistor and a fourth capacitor electrode overlapping the third capacitor electrode.
A portion of the first insulating layer is provided between the third capacitor electrode and the fourth capacitor electrode,
One end of the second active layer extends to the sixth thin film transistor, and the other end of the second active layer extends to the seventh thin film transistor,
and the second active layer and the first active layer are symmetrical. 10. The method of claim 9,
and an eighth thin film transistor connected to the second driving voltage line and the fifth thin film transistor. 11. The method of claim 10,
and one end of the second active layer extends to the eighth thin film transistor. 10. The method of claim 9,
and a second insulating layer on the first capacitor and the second capacitor. 13. The method of claim 12,
The second light emitting device includes a second pixel electrode provided on the second insulating layer and electrically connected to the fifth thin film transistor. 14. The method of claim 13,
and the initialization voltage line is provided on the second insulating layer. 15. The method of claim 14,
The first active layer extends to the second active layer and is connected to the second active layer. Board;
a plurality of scan lines on the substrate;
a plurality of data lines;
a first thin film transistor including a gate electrode connected to a first one of the plurality of scan lines and connected to a first one of the plurality of data lines;
a plurality of driving voltage lines;
a second thin film transistor including a first gate electrode and a first active layer and electrically connected to a first driving voltage line among the plurality of driving voltage lines;
a plurality of initialization voltage lines;
a third thin film transistor including a second gate electrode and connected to a first initialization voltage line among the plurality of initialization voltage lines and the first gate electrode of the second thin film transistor;
a first light emitting device electrically connected to the second thin film transistor;
a first insulating film covering the first gate electrode of the second thin film transistor; and
a first capacitor connected to the first gate electrode and including a first capacitor electrode and a second capacitor electrode on the first capacitor electrode;
the first capacitor electrode includes a part of the first gate electrode of the second thin film transistor, and a part of the first insulating layer is positioned between the first capacitor electrode and the second capacitor electrode;
The first active layer is connected to the active layer of the third thin film transistor,
and the first active layer under the first gate electrode is curved. 17. The method of claim 16,
and a fourth thin film transistor including a third gate electrode and electrically connected to the first driving voltage line and the second thin film transistor. 18. The method of claim 17,
and the first active layer is connected to the active layer of the fourth thin film transistor. 18. The method of claim 17,
and a second insulating film on the first capacitor. 20. The method of claim 19.
and the first light emitting device includes a first pixel electrode provided on the second insulating layer. 21. The method of claim 20,
and the initialization voltage line is provided on the second insulating layer. 22. The method of claim 21,
and the first active layer is connected to the active layer of the fourth thin film transistor. 23. The method of claim 22,
and a cover metal connected to the first initialization voltage line and the third thin film transistor. 17. The method of claim 16,
a fourth thin film transistor including a gate electrode connected to the first scan line and connected to a second data line among the plurality of data lines;
a fifth thin film transistor including a third gate electrode and a second active layer and electrically connected to a second driving voltage line among the plurality of driving voltage lines;
a sixth thin film transistor including a fourth gate electrode and connected to the first initialization voltage line and the third gate electrode of the fifth thin film transistor;
a second light emitting device electrically connected to the fifth thin film transistor; and
a second capacitor connected to the third gate electrode and including a third capacitor electrode and a fourth capacitor electrode on the third capacitor electrode;
the third capacitor electrode includes a part of a third gate electrode of the fifth thin film transistor, and a part of the first insulating layer is positioned between the third capacitor electrode and the fourth capacitor electrode;
the second active layer is connected to the active layer of the sixth thin film transistor, the second active layer under the third gate electrode is curved;
and the second active layer is symmetrical to the first active layer. 25. The method of claim 24,
and a seventh thin film transistor including a fifth gate electrode and electrically connected to the second driving voltage line and the fifth thin film transistor. 26. The method of claim 25,
and the second active layer is connected to the active layer of the seventh thin film transistor. 25. The method of claim 24,
and a second insulating layer on the first capacitor and the second capacitor. 28. The method of claim 27,
The second light emitting device includes a second pixel electrode provided on the second insulating layer. 29. The method of claim 28,
and the first initialization voltage line is provided on the second insulating layer. 30. The method of claim 29,
and the first active layer is connected to the second active layer.

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