KR102282619B1 - Negative charge pump and operating method of the negative charge pump based on switch capacitor circuit having fast start-up and recovery time - Google Patents

Abstract

The present invention relates to a negative charge pump and an operating method thereof, wherein the negative charge pump comprises: a storage capacitor that stores a negative power supply; a charging/discharging circuit connected to the storage capacitor and periodically charges the inner two capacitors with a smaller capacity than that of the storage capacitor according to a state of a plurality of clock signals and discharges a charging power of the two capacitors to the storage capacitor; and a switch capacitor circuit connected to the storage capacitor and charging the storage capacitor to a negative voltage according to an enable signal inputted independently of the charging/discharging circuit. Therefore, the present invention is capable of having an effect for which a stable negative voltage can quickly be provided.

Description

NEGATIVE CHARGE PUMP AND OPERATING METHOD OF THE NEGATIVE CHARGE PUMP BASED ON SWITCH CAPACITOR CIRCUIT HAVING FAST START-UP AND RECOVERY TIME

The present invention relates to a negative charge pump and an operating method thereof, and more particularly, to a switched capacitor circuit-based negative charge pump having fast start-up and return times, and an operating method thereof.

A negative charge pump (NCP) is widely used in the design of integrated circuits using negative power.

For example, an RF switch in which a body or gate control signal switches between 0V and a negative voltage or between a negative voltage and a positive voltage has a negative charge pump therein.

As another example, in order to reduce dark current leakage, the CMOS image sensor uses a negative charge pump provided therein. As another example, a negative charge pump is used for body biasing of a transistor. In addition, the negative charge pump may be simply configured in various integrated circuits (eg, a communication chipset or a communication circuit) that require a negative voltage (negative voltage).

The negative charge pump has a capacitor to store the negative voltage. The negative voltage storage capacitor has a large capacitance in order to supply a stable negative voltage to the inside of the integrated circuit.

A negative charge pump with a simple structure using a capacitor supplies a small amount of a negative voltage current (around several mA) to a circuit requiring a negative voltage, which is advantageous for the miniaturization of an integrated circuit compared to other negative voltage generating circuits.

On the other hand, the current supplied through the storage capacitor is small, which causes various side effects in various operating environments of the integrated circuit. In particular, the integrated circuit at the start-up time (first power supply time) when the storage capacitor does not have enough negative voltage storage or at the storage capacitor current over-discharge time point (for example, the over-discharge time due to switching of the RF switch). It may not be possible to use the negative voltage of the negative charge pump.

This causes the problem of destabilizing the integrated circuit using the negative voltage of the negative charge pump, causing side effects and slowing the speed of the integrated circuit. As an example of a typical side effect of an integrated circuit, a dark current leakage in a pixel of an image sensor or low Inter Modulaton Distortion (IMD) performance of an RF switch before stabilization of a negative charge pump is provided.

Therefore, there is a need for a negative charge pump capable of rapidly providing a stable negative voltage at the time of startup or recovery.

Publication 10-2020-0107284, September 16, 2020

An object of the present invention is to provide a negative charge pump capable of rapidly providing a stable negative voltage by reducing the negative voltage stabilization time at the time of startup or recovery, and an operating method thereof. There is this.

Another object of the present invention is to provide a negative charge pump having a switch capacitor circuit having a simple structure and control, and having a fast start-up time and a return time of an integrated circuit independently of the existing charge/discharge circuit, and a method of operating the same. there is.

In addition, the present invention provides a negative charge pump capable of resolving or reducing known side effects of the known negative charge pump by providing the integrated circuit with fast start-up time and return time, thereby enabling rapid stabilization of the integrated circuit, and a method for operating the same. It is intended to

The technical problems to be achieved in the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those of ordinary skill in the art to which the present invention belongs from the following description. will be able

The negative charge pump according to an aspect of the present invention is connected to a storage capacitor for storing negative power, the storage capacitor, and periodically charges internal two capacitors having a smaller capacity than the storage capacitor according to the state of a plurality of clock signals, and A charging/discharging circuit for discharging the charging power to the storage capacitor, and a switching capacitor circuit connected to the storage capacitor and charging the storage capacitor to a negative voltage according to an input enable signal.

In the above-described negative charge pump, the switch capacitor circuit is connected to a first node connected to a charge/discharge circuit of a delay and storage capacitor for delayed output of an enable signal, and a first operating power source, so that the storage capacitor and the second circuit are connected according to the enable signal. 1 The first switch element for connecting or opening the operating power source and the second node on the other side of the first node of the storage capacitor and the second operating power source to connect or open the storage capacitor and the second operating power source according to the delay signal from the delay and a third switch element.

In the negative charge pump described above, the switch capacitor circuit is connected to the second node of the storage capacitor and the first operating power supply, and a second switch element for connecting or opening the storage capacitor and the first operating power according to the delay signal from the delay. include more

In the above-described negative charge pump, the first switch element and the third switch element are of the same type of transistor, the second switch element is a transistor of a different type from that of the first switch element, and the first operating power supply and the second operating power supply are Power supplies with different voltage levels.

The negative charge pump further comprises a clock generator for generating a plurality of clock signals from an input basic clock signal and outputting them to a charge/discharge circuit, wherein the enable signal is generated in an integrated circuit including the negative charge pump It is a reset signal or a recovery signal.

In addition, according to the state of the plurality of clock signals according to an aspect of the present invention, a negative comprising a charge/discharge circuit for periodically charging two capacitors having a smaller capacity than the storage capacitor and discharging the charging power of the two capacitors to the storage capacitor The method of operating the charge pump includes charging a storage capacitor to a negative voltage according to an input enable signal independently of charging and discharging of the charge/discharge circuit.

In the above-described operating method of the negative charge pump, delay outputting an enable signal through a delay and supplying VDD power to a second node of a storage capacitor through a third switch element according to a first signal value of the delayed enable signal and connecting the first node of the storage capacitor to the VSS power supply through the first switch element according to the first signal value of the enable signal.

In the above-described operating method of the negative charge pump, the step of fixing the voltage of the first node of the storage capacitor by opening the first switch element as the enable signal is changed to the second signal value, and the delayed enable signal is applied to the second The method further includes the step of opening the second node of the storage capacitor from the VDD power supply of the third switch element as the signal value is changed and connecting the storage capacitor to the VSS power supply through the second switch element.

In the above-described operating method of the negative charge pump, the first switch element and the third switch element are PMOS type transistors, the second switch element is an NMOS type transistor, and the enable signal is an integrated circuit including a negative charge pump. It is a reset signal or a recovery signal generated within.

Further, according to an aspect of the present invention, the integrated circuit includes the negative charge pump and the control circuit for outputting a basic clock signal and an enable signal to the negative charge pump.

The negative charge pump and its operating method according to the present invention as described above have the effect of reducing the negative voltage stabilization time at the start-up time or the recovery time to provide a stable negative voltage quickly.

In addition, the negative charge pump and its operating method according to the present invention as described above include a switch capacitor circuit having a simple structure and control, and thus have an effect of having a fast start-up time and a return time of an integrated circuit independently of the existing charge/discharge circuit. there is.

In addition, the negative charge pump and its operating method according to the present invention as described above enable fast stabilization of the integrated circuit by providing the integrated circuit with fast start-up time and return time, thereby eliminating known side effects of the known negative charge pump or has the effect of reducing it.

The effects obtainable in the present invention are not limited to the above-mentioned effects, and other effects not mentioned may be clearly understood by those of ordinary skill in the art to which the present invention belongs from the following description. will be.

1 is a diagram illustrating an example of an integrated circuit including a negative charge pump according to the present invention.
2 is a diagram illustrating an exemplary configuration of a negative charge pump according to the present invention.
3 is a diagram illustrating a detailed hardware block diagram of a charge/discharge circuit, a switch capacitor circuit, and a storage capacitor of a negative charge pump.
4 is a diagram illustrating an example of an output of a clock signal and a charging/discharging operation in the first capacitor according to the clock signal.
5 is a diagram illustrating an example of a storage capacitor charging operation of a switch capacitor circuit according to an input enable signal.
6 is a diagram illustrating a graph in the case of charging the storage capacitor through the charge/discharge circuit and a graph in the case of charging the storage capacitor through the switch capacitor circuit.

The above-described objects, features, and advantages will become more clear through the detailed description described below in detail with reference to the accompanying drawings, and accordingly, those of ordinary skill in the art to which the present invention pertains can understand the technical spirit of the present invention. can be easily implemented. In addition, in the description of the present invention, when it is determined that a detailed description of a known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating an example of an integrated circuit 10 including a negative charge pump 100 according to the present invention.

Referring to FIG. 1 , an integrated circuit 10 includes at least a control circuit 200 , a negative charge pump 100 , and a negative power supply device 300 . The integrated circuit 10 that embeds the negative charge pump 100 in a chip package is configured to perform a designed function using a negative voltage (or negative voltage) generated by the negative charge pump 100 . The control circuit 200 , the negative charge pump 100 , and the negative power supply device 300 may be configured with a hardware circuit and logic.

The integrated circuit 10 may be, for example, an image sensor chipset such as CMOS, an RF switch chipset, a chipset including a transistor, or a chipset that requires a negative voltage (eg, a communication chipset using a negative voltage, etc.) there is.

The integrated circuit 10 provides operating power (VDD of 1.2V, 1.8V, 3.3V, etc. (see ⓒ of FIG. 1)), 0V through pins, balls, pads, etc. of the chip package. Alternatively, it is connected to VSS of GND (refer to ⓑ of FIG. 1 ) to drive the internal control circuit 200 , the negative charge pump 100 , and further the negative power using device 300 according to the operating power.

Looking at the main configuration of the integrated circuit 10 related to the present invention, the control circuit 200 controls at least the negative charge pump 100 . The control circuit 200 generates and outputs a basic clock signal usable from the negative charge pump 100 (using PLL, DLL, etc.) and indicates this when the negative power output from the negative charge pump 100 needs rapid stabilization. or an enable (EN) signal indicating

The control circuit 200 generates and outputs a basic clock signal usable to the negative charge pump 100 from a clock signal from an oscillator external to the integrated circuit 10 . In addition, when the first power supply is started (start-up), when an external reset input is received, the control circuit 200 excessively uses negative power by the negative power using device 300 (negative power using device 300). state change, switching, etc.) occurs, an enable signal for requesting charging of the negative power source may be generated through the switch capacitor circuit 150 and output to the negative charge pump 100 .

As such, the control circuit 200 may output a reset signal generated according to the start of power supply or reception of an external reset signal or a recovery signal (or recovery signal) according to excessive use of negative power as an enable signal.

The negative charge pump 100 (Negative Charge Pump: NCP) may generate negative power (“-VDD” in FIG. 1 ) using VDD and VSS power and output it to the negative power using device 300 . The negative charge pump 100 receives the basic clock signal CLK and the enable signal EN from the control circuit 200 , and receives a power (−) specified according to the basic clock signal and the enable signal input from the control circuit 200 . VDD) is generated through charging, and the generated negative power is output to the negative power using device 300 .

The negative charge pump 100 will be described in detail with reference to FIGS. 2 to 6 .

The negative power supply device 300 is a device that uses the negative power of the negative charge pump 100 . The negative power-using device 300 may be various according to its purpose or function, and may be, for example, an RF switch, an image pixel switch, a transistor, a communication circuit, and the like.

The negative power using device 300 performs a specified function using the negative power supplied from the negative charge pump 100 and outputs a signal corresponding thereto (refer to ⓐ in FIG. 1 ).

2 is a diagram illustrating an exemplary configuration of a negative charge pump 100 according to the present invention, and FIG. 3 is a charge/discharge circuit 130, a switch capacitor circuit 150, and a storage capacitor 170 of the negative charge pump 100. ) is a diagram showing a detailed hardware block diagram.

2 and 3 , the negative charge pump 100 includes a clock generator 110 , a charge/discharge circuit 130 , a switch capacitor circuit 150 , and a storage capacitor 170 .

2 and 3, looking at the negative charge pump 100 in detail, the clock generator 110 receives the basic clock signal CLK from the control circuit 200 and generates a plurality of clock signals from the basic clock signal, A plurality of clock signals (see CLK1 , CLK2 , CLK3 , and CLK4 in FIG. 2 ) are output to the charge/discharge circuit 130 .

The clock generator 110 may generate and output nonoverlapping clock signals. For example, the clock generator 110 outputs a basic clock signal as a CLK1 signal and outputs an inverting signal of the basic clock signal as a CLK4 signal. The clock generator 110 may generate a CLK2 signal from a basic clock signal using a delay 151 or an inverter, and may generate a CLK3 signal by inverting the CLK2 signal. Alternatively, the clock generator 110 multiplies the basic clock signal to output the CLK1 signal, and inverts the CLK1 signal to output the CLK4 signal. The clock generator 110 may generate a CLK2 signal from a CLK1 signal using a delay 151 or an inverter, and invert the CLK2 signal to generate a CLK3 signal.

The clock generator 110 configures the CLK1 signal and the CLK3 signal having the same signal pattern to non-overlap each other, and configures the CLK2 signal and the CLK4 signal to non-overlapping each other with the same signal pattern.

The charging/discharging circuit 130 periodically charges the connected storage capacitor 170 to a negative voltage according to a plurality of input clock signals. The charging/discharging circuit 130 includes two capacitors and a plurality of switch elements 131 therein to control the plurality of switch elements 131 according to a change in state of a plurality of clock signals input from the clock generator 110 . Two internal capacitors may be periodically charged and the charging power of the charged capacitor may be discharged to the storage capacitor 170 .

3 shows a specific circuit configuration of the charging/discharging circuit 130, as in the example of FIG. 3, the charging/discharging circuit 130 includes eight switch elements 131 (M1, M2, M3, M4, M5, M6, M7, M8) and two capacitors 133, 135 (C1, C2), and the switch element 131 can close or open between the source and drain according to the gate control of each individual clock signal. . According to a design example, the charge/discharge circuit 130 may be configured by further including an additional switch element and an additional capacitor or omitting some switch elements and some capacitors.

One capacitor (C1, hereinafter referred to as a 'first capacitor') is charged with the VDD power supply according to the clock state constituted by the clock signals and the opening and connection of the switch element 131 accordingly, and a negative power supply (-VDD). , and may be discharged to the storage capacitor 170 .

The other capacitor (C2, hereinafter referred to as a 'second capacitor') is charged with the VDD power supply according to the clock state constituted by the clock signals and the opening and connection of the switch element 131 accordingly, and the negative power supply (-VDD). ) and may be discharged to the storage capacitor 170 .

The first capacitor 133 and the second capacitor 135 may be periodically charged according to the frequency of the clock signal (eg, 10 MHz, 20 MHz, etc.) and periodically discharged to the storage capacitor 170 .

The first capacitor 133 and the second capacitor 135 are charged and discharged in different clock states (complementary clock states). For example, while the first capacitor 133 is being charged, the second capacitor 135 is converted to negative power and discharged to the storage capacitor 170 , and the first capacitor 133 is converted to negative power to convert the storage capacitor ( While discharging to 170 , the second capacitor 135 may be charged.

The first capacitor 133 and the second capacitor 135 may have a smaller capacity than the storage capacitor 170 , and may charge (supply) negative power to the storage capacitor 170 by repetition by clock signals. The capacity of the first capacitor 133 and the second capacitor 135 may be as small as 100 times (eg, 1 pF) compared to the storage capacitor 170 (eg, 100 pF). When the negative power to the storage capacitor 170 is present at a certain voltage level (eg, -0.2 V, etc.) or higher due to start-up or external overdischarge, charging and It is possible to charge the storage capacitor 170 with negative power of a stable power level through repeated discharging.

As can be seen from the example of FIG. 4 , the upper node (or terminal) of the first capacitor 133 is connected through the switch element 131 M1 in a state '1' when the CLK1 signal is low and CLK3 is low. It is connected to VDD and the lower node (or terminal) of the first capacitor 133 is connected to VSS through the switch element 131 M5. In the state '1', the first capacitor 133 is charged with the VDD power supply.

In a state '2' where CLK1 is changed to high and CLK3 is low, VDD power is stored in the first capacitor 133, and in a state '3' when CLK3 is changed to high, the upper node of the first capacitor 133 is connected to VSS and the lower node is converted to '-VDD' by the relative potential difference across the first capacitor 133 .

The negative power converted in the state '3' is stored in the storage capacitor 170 according to the capacity ratio of the storage capacitor 170 and the first capacitor 133 . As such, in the state '3', the first capacitor 133 discharges the negative power charged by the storage capacitor 170 .

The second capacitor 135 performs a complementary operation with the first capacitor 133 . During the charging operation of the first capacitor 133 in the state '1', the second capacitor 135 is connected to the storage capacitor 170 . During the discharging operation of the first capacitor 133 in the state '3' after discharging the negative power, the second capacitor 135 performs a charging operation.

6 is a diagram illustrating a graph in the case of charging the storage capacitor through the charge/discharge circuit and a graph in the case of charging the storage capacitor through the switch capacitor circuit.

② of FIG. 6 shows a simulation graph reaching a stable negative voltage level through the charging/discharging circuit 130 (only) including the first capacitor 133 and the second capacitor 135 after the start-up or overdischarge occurs. and ① of FIG. 6 shows a simulation graph of reaching a stable negative voltage level using the switch capacitor circuit 150 at the start-up time or after the occurrence of overdischarge.

The simulation graphs of ① and ② may vary depending on the sizes of the first capacitor 133 , the second capacitor 135 , and the storage capacitor 170 .

As can be seen from the ② graph of FIG. 6 , when there is no negative power to the storage capacitor 170 or a certain voltage level (eg, -0.1 V, etc.) is reached after startup or overdischarge, the first capacitor The charging operation for the storage capacitor 170 by the 133 and the second capacitor 135 has a stable negative voltage level (designed negative voltage level, for example, -1.0 V, -1.2 V, -1.8 V, etc.) It takes a lot of time to reach

In general, the first capacitor 133 and the second capacitor 135 are 100 times smaller than that of the storage capacitor 170 , so that the charging of the first capacitor 133 and the second capacitor 135 for at least 50 clocks or more is reduced. A stable negative power may be charged to the storage capacitor 170 by discharging.

As can be seen from the graph ② of FIG. 6 , it takes about 10 us or more to reach a stable state up to the specified negative voltage (for example, -1.0 V) as a result of the simulation, for example, following several tens or more repetitions. do.

In this way, the charging/discharging circuit 130 including two capacitors for charging the storage capacitor 170 according to an input clock signal is a general normal that is maintained below a certain level of power to the storage capacitor 170 . It operates stably in the mode, but when power is present in the storage capacitor 170 above a certain power level (eg, starting power supply, etc.) or overdischarge occurs, a lot of settling time is required for stabilization. Due to this, various side effects (eg, IMD, dark current generation, etc.) may occur depending on the designed integrated circuit 10 .

The negative charge pump 100 further includes a storage capacitor 170 and a switch capacitor circuit 150 together with the charge/discharge circuit 130 and the clock generator 110 . The storage capacitor 170 stores the negative power output to the negative power using device 300 . The storage capacitor 170 may store negative power supplied through the connected charging/discharging circuit 130 or the connected switch capacitor circuit 150 and output it to the external negative power using device 300 .

The storage capacitor 170 has a larger capacity than the first capacitor 133 and the second capacitor 135, and the capacity may be changed in design according to an external load (the number or consumption of the negative power-using devices 300, etc.). . For example, the storage capacitor 170 may have a storage capacity of 100 pF, 200 pF, or 400 pF.

The switch capacitor circuit 150 connected to the storage capacitor 170 and capable of charging the storage capacitor 170 to a negative voltage below a predetermined voltage level is an enable input from the control circuit 200 independently of the charge/discharge circuit 130 . According to the (EN) signal, the storage capacitor 170 is charged to a negative voltage.

When the enable signal is a low signal value (active low), the switch capacitor circuit 150 charges the storage capacitor 170 to a negative voltage equal to or less than a specified voltage level within a short time, and the enable signal is high. ) signal value, the charging/discharging circuit 130 may periodically charge a small amount of negative power to the storage capacitor 170 according to the cycle of the clock signal.

Alternatively, the switch capacitor circuit 150 charges the storage capacitor 170 to a negative voltage equal to or less than a specified voltage level within a short time when the enable signal is a high signal value, and the enable signal is low. When the signal value is (low), the charging/discharging circuit 130 may periodically charge a small amount of negative power to the storage capacitor 170 according to the cycle of the clock signal.

The switch capacitor circuit 150 of FIG. 3 shows an example of rapidly charging the storage capacitor 170 to a negative voltage by the switch capacitor circuit 150 when the enable signal is a low signal value. The switch capacitor circuit 150 operating as active high may be configured by, for example, changing the MOS types of the first switch element 153 , the second switch element 155 , and the second switch element 155 .

3 , the switch capacitor circuit 150 includes a delay 151 , a first switch element 153 , a second switch element 155 , and a third switch element 157 .

Looking at the switch capacitor circuit 150 in detail, the delay 151 delays and outputs the enable signal from the control circuit 200 . The delay 151 includes a circuit for delaying or amplifying an enable signal input therein, and delays the enable signal for more than a predetermined time (eg, around several nanoseconds) (ⓓ in FIG. 5 ) ) can be printed out.

The first switch element 153 (see M9 of FIG. 3 ) is a node connected to the charge/discharge circuit 130 of the storage capacitor 170 ( 'N1' in FIGS. 2 and 3, hereinafter referred to as a 'first node') A source and a drain are connected to a specific operating power source (0V or VSS in FIG. 3, hereinafter referred to as a 'first operating power supply'), and an enable signal not delayed by the delay 151 is connected to the gate and is applied to the enable signal. Accordingly, the storage capacitor 170 and the first operating power are connected or opened. The first switch element 153 may be a PMOS type transistor that connects a source and a drain when the enable signal is a low signal.

The second switch element 155 (refer to M10 of FIG. 3 ) includes a node on the opposite side to the first node of the storage capacitor 170 ( 'N2' in FIGS. 2 and 3, hereinafter referred to as a 'second node') and A source and a drain are connected to the first operating power source, and an enable signal delayed through a delay 151 is connected to a gate, and the storage capacitor 170 according to an enable signal (hereinafter also referred to as a 'delay signal') from the delay 151. ) and the first operating power supply or open.

The second switch element 155 is a transistor of a different type from that of the first switch element 153 or the third switch element 157, and may be, for example, an NMOS type transistor that connects the source and the drain when the delay signal is a high signal. there is.

The third switch element 157 (refer to M11 of FIG. 3 ) includes a second node opposite to the first node side of the storage capacitor 170 and a specific operating power (VDD in FIG. 3 , hereinafter referred to as ‘second operating power supply’). '), the source and the drain are connected, and the storage capacitor 170 and the second operating power are connected or opened according to the delay signal from the delay 151 . The third switch element 157 may be a PMOS type transistor that connects the source and the drain when the delay signal is a low signal.

The second operating power may have a different voltage level than that of the first operating power. For example, the first operating power may be 0V or VSS power, and the second operating power may be 1.2V, 1.8V, or 3.3V VDD power. The third switch element 157 is a transistor of the same type as the first switch element 153 .

5 is a delay 151 according to an enable signal of a switch capacitor circuit 150 including a delay 151 , a first switch element 153 , a second switch element 155 , and a third switch element 157 . and a charging sequence according to an on/off connection or open operation of the switch elements 153 , 155 , and 157 . As an active-low enable signal is applied from the control circuit 200 , the delay 151 is turned on. The enable signal EN is output with a delay (refer to EN_D in FIG. 5).

In the state '1' according to the combination of the enable signal and the delay signal, the control of the first switch element 153, the second switch element 155, and the third switch element 157 by the enable signal and the delay signal ( open or closed), the second node of the storage capacitor 170 is connected to a first operating power supply and the first node is connected to any negative power supply (VB, VB being a voltage lower than VDD (second operating power supply)) . The second node of the storage capacitor 170 is connected to the first operating power supply through the first switch element 153 and the second switch element 155 gated on in the state '1', and the first node is an arbitrary negative power supply. connected to (VB).

In the state '2' after the delay signal is changed to the low signal after a predetermined time, the first switch element 153, the second switch element 155, and the third switch element 157 are formed by the enable signal and the delay signal. As a control (open or closed), the second node of the storage capacitor 170 is connected to VDD (second operating power supply) and the first node of the storage capacitor 170 is connected to an arbitrary negative power supply (VB).

In state '2', the third switch element 157 is gated on by the low signal value of the delay signal to connect the VDD power supply to the second node of the storage capacitor 170, and is controlled by the low signal value of the enable signal. One switch element 153 is gated on to connect the VSS power supply to the first node of the storage capacitor 170 . In the state '2', the voltage VB of the first node depends on the size of the first switch element 153 and is lower than VDD.

As the control circuit 200 changes the enable signal (eg, from a low signal to a high signal), in a state '3' where the enable signal is a high signal and the delay signal is low, the source depends on the enable signal. The first switch element 153 connecting the and drain opens the source and drain to freeze the voltage VB of the first node of the storage capacitor 170 .

After the lapse of a predetermined time by the internal circuit of the delay 151, in a state '4' in which the delay signal is also changed to a high signal, the first switch element 153 and the second switch element by the enable signal and the delay signal Under the control (open or closed) of 155 and the third switch element 157 , the second node of the storage capacitor 170 is connected to VSS (first operating power) and the first node of the storage capacitor 170 is stored It is converted into negative power by the relative potential difference between both ends of the capacitor 170 .

As the delay signal is changed to a high signal, the third switch element 157 opens the VDD power supply and the second node, and the second switch element 155 connects the VSS power supply to the second node. The voltage of the first node, which had an arbitrary VB voltage, is switched to the negative power supply of VB - VDD as the second node is switched (switched) to the VSS power supply. Thereafter, the charging/discharging circuit 130 may operate to charge the storage capacitor 170 to a voltage (-VDD voltage) less than or equal to the previously charged VB-VDD voltage.

It operates according to the enable signal and is configured by utilizing the delay signal of the enable signal, and the storage capacitor 170 can be directly negatively charged by the switch capacitor circuit 150 in a very short time compared to the use of the charge/discharge circuit 130 . The power supply can be stabilized.

As can be seen from FIG. 6 , the storage capacitor is stored in a very short time (under several tens of nanoseconds in the simulation test) by the enable (EN) signal applied according to the reset signal or the recovery signal generated in the integrated circuit 10 . It can be seen that the negative power of 170 is stabilized to a negative voltage level capable of normal operation.

The present invention described above, for those of ordinary skill in the art to which the present invention pertains, various substitutions, modifications and changes are possible within the scope without departing from the technical spirit of the present invention. It is not limited by the drawing.

10: integrated circuit
100: negative charge pump
110: clock generator
130: charge and discharge circuit
131: switch element
133: first capacitor
135: second capacitor
150: switch capacitor circuit
151: delay
153: first switch element
155: second switch element
157: third switch element
170: storage capacitor
200: control circuit
300: a negative power supply device

Claims (10)

A negative charge pump comprising:
storage capacitor to store negative power;
A charging/discharging circuit connected to a first node of the storage capacitor and periodically charging two internal capacitors having a smaller capacity than the storage capacitor according to states of a plurality of clock signals and discharging the charging power of the two capacitors to the storage capacitor ; and
a switch capacitor circuit connected to the second node on the other side of the first node of the storage capacitor and charging the storage capacitor to a negative voltage independently of charging and discharging of the charging/discharging circuit according to an input enable signal;
The switch capacitor circuit including a delay outputting the enable signal with a delay and a plurality of switch elements is a first operating power source or a second operating power source according to a state change according to a combination of the enable signal and the delay signal from the delay. Directly charging the storage capacitor to a negative voltage by changing the connection of the storage capacitor to the first operating power or the second operating power through the plurality of switch elements connected to
wherein the enable signal is a reset signal or a recovery signal generated within an integrated circuit including the negative charge pump;
negative charge pump. According to claim 1,
The switch capacitor circuit comprises:
It is connected to the first node connected to the charge/discharge circuit of the storage capacitor and the first operating power to connect or open the storage capacitor and the first operating power according to the enable signal, and to select one of the plurality of switch elements. One first switch element; and
A third switch that is connected to the second node of the storage capacitor and the second operating power to connect or open the storage capacitor and the second operating power according to a delay signal from the delay, and is one of the plurality of switch elements element; including,
negative charge pump. storage capacitor to store negative power;
a charging/discharging circuit connected to the storage capacitor and periodically charging internal two capacitors having a smaller capacity than the storage capacitors according to states of a plurality of clock signals and discharging charging power of the two capacitors to the storage capacitors; and
a switch capacitor circuit connected to the storage capacitor and charging the storage capacitor to a negative voltage according to an input enable signal;
The switch capacitor circuit comprises:
a delay delay outputting the enable signal;
a first switch element connected to a first node connected to the charge/discharge circuit of the storage capacitor and a first operating power to connect or open the storage capacitor and the first operating power according to the enable signal;
a second switch element connected to a second node at the other side of the first node of the storage capacitor and the first operating power to connect or open the storage capacitor and the first operating power according to a delay signal from the delay; and
A third switch element connected to the second node of the storage capacitor and a second operating power supply to connect or open the storage capacitor and the second operating power source according to the delay signal from the delay;
negative charge pump. 4. The method of claim 3,
The first switch element and the third switch element are transistors of the same type,
The second switch element is a transistor of a different type than the first switch element,
The first operating power and the second operating power are power having different voltage levels from each other,
negative charge pump. According to claim 1,
A clock generator for generating a plurality of clock signals from the input basic clock signal and outputting them to the charging/discharging circuit;
negative charge pump. A method of operating a negative charge pump comprising: a charging/discharging circuit for periodically charging two capacitors having a smaller capacity than a storage capacitor according to the state of a plurality of clock signals and discharging the charging power of the two capacitors to the storage capacitor,
Independent of charging and discharging of the charging and discharging circuit, charging the storage capacitor to a negative voltage according to an input enable signal;
Independently of the charging and discharging of the charging and discharging circuit, the step of charging the storage capacitor to a negative voltage,
delay outputting the enable signal through a delay;
The VDD power supply is connected to the second node of the storage capacitor through a third switch element according to the first signal value of the delayed enable signal, and the storage is performed through the first switch element according to the first signal value of the enable signal. connecting the first node of the capacitor to the VSS supply;
fixing a voltage of a first node of the storage capacitor by opening a first switch element as the enable signal is changed to a second signal value; and
When the delayed enable signal is changed to a second signal value, opening a second node of the storage capacitor from the VDD power supply of a third switch element and connecting to the VSS power supply through the second switch element;
How a negative charge pump works. delete delete 7. The method of claim 6,
The first switch element and the third switch element are PMOS type transistors,
The second switch element is an NMOS type transistor,
wherein the enable signal is a reset signal or a recovery signal generated within an integrated circuit including the negative charge pump;
How a negative charge pump works. The negative charge pump of claim 1 ; and
a control circuit outputting a basic clock signal and an enable signal to the negative charge pump;
integrated circuit.

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