KR102266166B1 - Memory controller and storage device including the same - Google Patents

Abstract

The present invention relates to a memory controller and a storage device including the same, wherein the memory controller according to an embodiment of the present invention stores data to be written into the nonvolatile memory 200 and data to be read from the nonvolatile memory 200 into a buffer memory. In the memory controller 100 for executing a buffering operation for temporarily storing data in 300 , a plurality of buffer write requests, which are requests for temporarily storing data in the buffer memory 300 , and the buffer memory 300 ) A buffer request queue (queue, 10) that stores a number of buffer read requests, which are requests to read data stored in the , and a plurality of buffer write requests and buffer read requests stored in the buffer request queue 10, respectively. The buffer traffic monitoring unit 20 for calculating the total amount of request data in real time by summing the lengths of the data contained in the buffer, and the buffer for controlling the execution of the buffering operation by setting the execution ratio based on the total amount of request data calculated in real time and a management unit 30 .

Description

MEMORY CONTROLLER AND STORAGE DEVICE INCLUDING THE SAME

The present invention relates to a memory controller and a storage device including the same, and more particularly, to a memory controller for predicting whether a performance bottleneck occurs by monitoring traffic of a buffer memory and managing the buffer memory accordingly, and to a storage device including the same will be.

The semiconductor memory is divided into a volatile memory and a non-volatile memory according to a storage mechanism of information. Volatile memory includes DRAM and SRAM, which reads and writes fast, but information is lost when the power supply is cut off. On the other hand, the nonvolatile memory is used to store data to be preserved regardless of whether the power is supplied or not because the memory information can be preserved even when the power is cut off. Examples of such non-volatile memory include EPROM, EEPROM, FRAM, PRAM, MRAM, and flash memory. In particular, as disclosed in the patent documents of the following prior art documents, the flash memory is a computer, a smartphone, a digital camera, It is widely used as audio and video data storage media of information devices such as voice recorders and camcorders.

A flash storage device configured with such a flash memory uses a buffer memory as a write buffer and a prefetch buffer to increase processing performance of a write command received from a host. However, when a high bandwidth memory (HBM) such as a flash memory is used as a storage media, a performance bottleneck may occur in the buffer memory. Since the host data traffic to the buffer memory generated in the process of processing the host's write command is very large compared to the storage media, if the bandwidth of the buffer memory is not overwhelmingly higher than that of the storage media, the buffer memory will become a performance bottleneck. do. In addition to write buffering, various traffics such as software code execution or metadata access exist in the buffer memory. In the case of read prefetch, if a read command to the corresponding logical block address (LBA) does not occur, the buffer memory is Because bandwidth is wasted, it is likely to become a performance bottleneck.

Accordingly, there is an urgent need for a method for managing a buffer memory performance bottleneck in a conventional flash storage device.

US 1994-0022295 A

SUMMARY OF THE INVENTION The present invention is to solve the problems of the prior art described above, and an aspect of the present invention is to check the traffic to the buffer memory in real time to determine the possibility of a performance bottleneck, and to limit write buffering and read prefetch execution in response thereto Accordingly, an object of the present invention is to provide a memory controller capable of managing the buffer memory.

In the memory controller according to an embodiment of the present invention, the memory controller performs a buffering operation of temporarily storing data to be written into a nonvolatile memory and data to be read from the nonvolatile memory in a buffer memory, wherein the data is stored in the buffer memory A buffer request queue for storing a plurality of buffer write requests, which is a request to temporarily store the data, and a plurality of buffer read requests, which is a request to read the data stored in the buffer memory. ; a buffer traffic monitoring unit calculating a total amount of request data in real time by summing the lengths of the data included in each of the plurality of buffer write requests and the buffer read requests stored in the buffer request queue; and a buffer management unit configured to control execution of the buffering operation by setting an execution rate based on the total amount of the request data calculated in real time.

Further, in the memory controller according to an embodiment of the present invention, the memory controller executes the buffering operation according to a preset initial execution ratio, and when the total amount of the request data calculated in real time exceeds a preset upper limit, the buffer The management unit may set the execution ratio by downwardly adjusting the initial execution ratio.

In addition, in the memory controller according to an embodiment of the present invention, the buffer management unit repeatedly adjusts downwards the execution ratio until the total amount of the request data calculated in real time is equal to or greater than a predetermined lower limit and less than or equal to the upper limit. can be set.

In addition, in the memory controller according to an embodiment of the present invention, the buffer manager may increase the execution ratio when the total amount of the request data calculated in real time is less than the lower limit.

In addition, in the memory controller according to the embodiment of the present invention, the buffer management unit, even if the total amount of the request data calculated in real time is less than the lower limit value, if the set execution ratio is the same as the initial execution ratio, the execution ratio can keep

Also, in the memory controller according to an embodiment of the present invention, the buffer management unit may adjust the execution ratio by applying a preset execution ratio variation for each section according to the degree of exceeding the upper limit value and the degree of less than the lower limit value.

In addition, in the memory controller according to an embodiment of the present invention, the buffer manager includes: write buffering for temporarily storing the data to be written in response to a write command from a host in the buffer memory during the buffering operation; In anticipation of a second read command to be continuously generated after processing of the first read command is completed, read prefetches for temporarily storing the data to be read may be distinguished from each other in the buffer memory, and the execution of each operation may be controlled.

In addition, in the memory controller according to an embodiment of the present invention, the buffer manager sets a first execution ratio to control execution of the write buffering operation, and a second execution ratio equal to or different from the first execution ratio Execution of the read prefetch operation may be controlled by setting an execution rate.

In addition, in the memory controller according to an embodiment of the present invention, the buffer management unit randomly selects a part from among a plurality of the write commands according to the first execution ratio, and executes the buffering operation on only the selected part and randomly selects a part of the plurality of first read commands according to the second execution ratio, and executes the read prefetch operation on only the selected part.

Meanwhile, a storage device according to an embodiment of the present invention includes a non-volatile memory; buffer memory; and the memory controller according to any one of claims 1 to 9.

The features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Prior to this, the terms or words used in the present specification and claims should not be construed as conventional and dictionary meanings, and the inventor may properly define the concept of the term to describe his invention in the best way. It should be interpreted as meaning and concept consistent with the technical idea of the present invention based on the principle that there is.

According to the present invention, the occurrence of a performance bottleneck is predicted by inspecting the traffic of the buffer memory in real time, and accordingly, in response to a write command from the host, data is directly transferred from the host to the storage medium without going through the write buffer, and the host read command In response, by omitting read prefetch after read completion, buffers can be managed efficiently, especially when high-bandwidth memory is used as a storage medium.

1 is a block diagram schematically illustrating a memory controller according to an embodiment of the present invention.
2 to 3 are block diagrams for explaining the operation of the memory controller shown in FIG. 1 .
4 to 5 are flowcharts illustrating a method of operating a memory controller according to an exemplary embodiment of the present invention.
6 is a block diagram schematically illustrating a storage device according to an embodiment of the present invention.
7 is a block diagram illustrating an example in which a storage device according to an embodiment of the present invention is applied to an SSD.

The objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings and preferred embodiments. In the present specification, in adding reference numbers to the components of each drawing, it should be noted that only the same components are given the same number as possible even though they are indicated on different drawings. Also, terms such as “first” and “second” are used to distinguish one component from another, and the component is not limited by the terms. Hereinafter, in describing the present invention, detailed descriptions of related known technologies that may unnecessarily obscure the gist of the present invention will be omitted.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically illustrating a memory controller according to an embodiment of the present invention, and FIGS. 2 to 3 are block diagrams for explaining an operation of the memory controller shown in FIG. 1 .

1 to 3 , the memory controller according to an embodiment of the present invention stores data to be written to the nonvolatile memory 200 and data to be read from the nonvolatile memory 200 to the buffer memory 300 . In the memory controller 100 for executing a buffering operation for temporarily storing, a plurality of buffer write requests, which are requests for temporarily storing data in the buffer memory 300 , and data stored in the buffer memory 300 . A buffer request queue (queue, 10) that stores a plurality of buffer read requests that are read requests, a plurality of buffer write requests and buffer read requests stored in the buffer request queue 10. The buffer traffic monitoring unit 20 for calculating the total amount of request data in real time by summing the lengths, and the buffer management unit 30 for controlling the execution of the buffering operation by setting the execution ratio based on the total amount of request data calculated in real time includes

The present invention relates to a memory controller for controlling a non-volatile memory. The nonvolatile memory is controlled by the memory controller according to the present invention and is a storage medium capable of retaining information data even when power is cut off, and is controlled by the memory controller to perform operations such as reading and programming. Examples of the non-volatile memory include EPROM, EEPROM, FRAM, PRAM, MRAM, and flash memory. In the case of a storage device employing a non-volatile memory as a medium, the buffer memory can be used as a write buffer or a prefetch buffer to increase the processing performance of the host's write and read commands. Since the amount of read and write data traffic that occurs to the buffer memory in the process of processing the host's command is much higher than that of the storage device, the buffer memory may become a performance bottleneck. As a solution to this, the buffer memory is used. A manageable invention has been devised.

Specifically, the memory controller 100 according to the present invention includes a buffer request queue 10 , a buffer traffic monitoring unit 20 , and a buffer management unit 30 .

The buffer request queue 10 is composed of a queue for storing at least one or more buffer write requests and/or buffer read requests to the buffer memory 300 . The memory controller 100 according to an embodiment of the present invention receives and processes a write command or a read command from the host 400 , and by using the buffer memory 300 , the command processing performance is improved. can do it In order to improve the response speed to the host write command, write buffering of temporarily storing write data to be written to the non-volatile memory 200 in the buffer memory 300 may be performed, and the pattern of the host read command may be identified. Thus, a prefetch operation of pre-reading data of a logical block address (LBA), which is expected to be requested by a future read command, from the non-volatile memory 200 to the buffer memory 300 can be performed. have. In addition to write buffering and read prefetching, a plurality of buffer write and read requests to the buffer memory 300 occur simultaneously for software code execution or meta-data storage, etc. It is stored in the buffer request queue (10).

The buffer write request includes master information, write address information (ADDR1), and data to be written. The address information (ADDR1) contains information including the start address of the buffer area to be accessed and the length of the data. do. The buffer read request includes master information and read address information (ADDR2) that have delivered the request, and the address information (ADDR2) contains information including the start address of the buffer area where the read data to be read is located and the length of the data. are included

The request stored in the buffer request queue 10 may be fetched by the buffer memory controller 15 to perform buffer write and/or read operations. In the case of a buffer write request, a buffer write operation may be performed by generating a signal for buffer writing using write address information in the request and transferring the signal to the buffer memory 300 , and transferring the write data to the buffer memory 300 . The result of performing the write operation may be transmitted to the module that generated the request according to master information in the request. In the case of a buffer read request, a signal for buffer reading is generated using the read address information in the request and delivered to the buffer memory 300 , and read data is received from the buffer memory 300 to receive the target according to the master information in the request. The module can return read data.

The buffer memory 300 is used to temporarily store data in order to improve storage performance. Specifically, referring to FIG. 2 , when receiving a write command from the host 400 , the memory controller 100 may perform write buffering and buffer flush. First, upon receiving a write command from the host 400 , a buffer space is allocated to a buffer memory 300 , and a buffer write request to temporarily store host data in the allocated buffer space is transmitted to the buffer request queue 10 . do. When the buffer memory controller 15 successfully returns a buffer write operation result after processing the buffer write request, it transmits a write completion for the host write command to the host 400 . This process is called write buffering. Next, in order to flush the buffered data to the nonvolatile memory 200 , a program request for the corresponding data is transmitted to the memory channel controller 60 . After receiving data from the buffer memory controller 15 through the buffer read request, the memory channel controller 60 performs a program operation on the nonvolatile memory and returns a program completion. When the program is completed, the location where the data is stored is recorded in the mapping table, and the allocated buffer space is released. The above process is called buffer flush. Meanwhile, referring to FIG. 3 , when a read command from the host 400 is input, first, whether requested data exists in the buffer memory 300 is searched. When data exists in the buffer memory 300 , a buffer read request is transmitted to the buffer request queue 10 , and when the buffer memory controller 15 processes the request and returns data, the data is transmitted to the host 400 . and send the completion. On the other hand, if there is no data in the buffer memory 300, a read request is transmitted to the memory channel controller 60 by referring to the mapping table to obtain a physical address on the nonvolatile memory 200 where the data is located, Accordingly, data and completion of the nonvolatile memory 200 are transferred to the host 400 . In general, since the buffer memory 300 has a faster access speed than the non-volatile memory 200 , when data to be read from the host is predicted and data is read from the non-volatile memory 200 to the buffer memory 300 in advance, the host read performance can be improved For example, after reading the host data having a logical block address (LBA) contiguous with the first read command of the host that has been previously processed is read from the non-volatile memory 200, it is temporarily stored in the buffer memory 300 through a buffer write request. Thereafter, when a second read command from the host having the corresponding logical block address arrives in the future, data may be transferred from the buffer memory 300 to the host 400 . This operation is defined as read prefetch.

In addition to the above-described use of the buffer memory 300 , various buffer write and read requests such as software code execution or meta data access may occur. Also, in the case of read prefetch, if a read request for a corresponding logical block address does not occur, the bandwidth of the buffer memory 300 is wasted. Accordingly, a performance bottleneck may occur in the buffer memory 300 .

The buffer traffic monitoring unit 20 monitors the state of the buffer request queue 10 in real time, and determines whether a performance bottleneck of the buffer memory 300 occurs. When a performance bottleneck occurs in the buffer memory 300 , a large amount of requests that are not fetched into the queue 10 because the speed at which requests are input into the buffer request queue 10 is faster than the speed at which they are fetched from the queue 10 . will exist Since the length of data requested to be written or read may be different for each buffer request, data length information in the request may be used to precisely determine a performance bottleneck. As an embodiment, data waiting to be processed without being fetched (hereinafter referred to as 'request data') by summing the lengths of data included in each of a plurality of write requests and/or read requests stored in the buffer request queue 10 . can calculate the total amount of In this case, if the total amount of request data exceeds a preset upper limit, it may be determined that the buffer memory 300 is a performance bottleneck. Conversely, if the total amount of request data is less than a preset lower limit, it may be determined that the buffer memory bandwidth is not sufficiently utilized. If the total amount of request data is less than or equal to the upper limit and equal to or greater than the lower limit, it may indicate that the bandwidth of the buffer memory 300 is fully utilized and there is no performance bottleneck problem of the buffer memory 300 . Accordingly, the buffer management unit 30 can efficiently manage the bandwidth of the buffer based on the total amount of request data generated by the buffer traffic monitoring unit 20 .

The buffer management unit 30 sets an execution ratio based on the total amount of request data calculated by the buffer traffic monitoring unit 20 in real time, and according to the execution ratio, data to be written to the nonvolatile memory 200 and the nonvolatile memory The buffer memory 300 is managed in a manner that controls execution of a buffering operation for temporarily storing data to be read from 200 in the buffer memory 300 . Since the buffering operation includes write buffering and read prefetching, the buffer memory 300 may be managed in a manner that adjusts the write buffering execution and/or the read prefetch execution ratio. In this case, it is possible to distinguish between write buffering and read prefetching to control the execution of each operation.

The memory controller 100 may execute a buffering operation according to a preset initial execution ratio. When the total amount of request data for the buffer exceeds a preset upper limit value, the initial execution ratio is lowered to set the execution ratio, and the execution ratio Accordingly, the buffering operation (eg, write buffering execution and/or read prefetch execution) may be omitted. For example, if the initial buffering ratio is 100% and the total amount of request data exceeds the preset upper limit, the write buffering ratio is lowered to 70% and then write buffering is executed only for 70% of the host write commands, For the remaining 30%, write buffering may be omitted and write data may be directly transferred to the nonvolatile memory 200 . In this case, even though the write buffering ratio is limited, if the total amount of request data calculated in real time after that exceeds the preset upper limit, the write buffering ratio may be lowered again by a predetermined value. That is, the downward adjustment of the write buffering may be repeated until the total amount of request data calculated in real time becomes less than or equal to a preset upper limit. On the other hand, when the total amount of request data is less than a preset lower limit, the write buffering ratio may be increased by a predetermined value. Such dynamic change of the write buffering execution rate is stopped when the total amount of request data is within a desired range, for example, within a range below a preset upper limit and higher than or equal to a lower limit. Although the total amount of request data is not in the above preferred range, when a saturation condition, for example, an initial execution ratio is reached, the execution ratio for write buffering may be maintained as it is. In one embodiment, even if the total amount of request data is less than the predetermined lower limit, if the write buffering ratio is already saturated to 100% as in the initial case, the ratio adjustment may not occur. Since the execution rate of the read prefetch execution limit is adjusted in the same principle as the write buffering execution restriction described above, a detailed description thereof will be omitted.

Meanwhile, since the execution ratio of the write buffering and the execution ratio of the read prefetch may be the same or different, when the execution of the write buffering operation is controlled by setting the first execution ratio, the second execution ratio equal to or different from the first execution ratio You can control the execution of read prefetch operations by setting the execution rate. In addition, the upward and downward degrees of the write buffering and/or read prefetch execution ratio may be set differently according to the calculated total amount of request data. In an embodiment, the execution ratio may be adjusted by applying a preset execution ratio variation for each section according to the degree of exceeding the upper limit and the degree of less than the lower limit. As an example, as shown in <Table 1> below, it is possible to determine the amount of variation in the execution ratio for each of the write buffering and read prefetching.

Total amount of request data Write Buffering Ratio Variation Read Prefetch Rate Variation 50 KB or less +20 +40 50 to 100 KB +10 +20 100 to 200 KB 0 0 200 to 250 KB -10 -30 250 KB or more -20 -60

In the above embodiment, the amount of change in the write buffering and read prefetch execution ratio according to the total amount of request data is preset, and the total amount of requests calculated in real time by the buffer traffic monitoring unit 20 is applied to write buffering, and/or read prefetching Adjust the patch ratio. For example, at a certain point in time, when the write buffering execution ratio is 90% and the read prefetch execution ratio is 70%, if the calculated total amount of request data exceeds 200 KB and is less than 250 KB, the execution ratio variation for each is applied Thus, the write buffering and read prefetch ratios can be changed to 80% (= 90-10 %) and 40% (= 70-30%), respectively. On the other hand, write buffering and/or read prefetching are executed according to the execution ratio. , it is necessary to select a host write command and/or a read command whose execution is omitted. Accordingly, the buffer manager 30 may randomly select a portion according to the execution ratio of each of the plurality of host write commands and read commands, and execute the buffering operation and the read prefetch operation only on the selected portion. In an embodiment, a host command may be selected randomly according to a random number. For example, when a host write command is input, if the host write buffering execution rate is 70%, a random number between 1 and 100 is generated to If the value is 70 or less, write buffering is enabled, otherwise, write buffering can be omitted. The host may apply the same method to the read command, and in this case, the execution ratios of the write command and the read command may be the same or different.

Meanwhile, the buffer manager 30 may monitor the buffer area of the buffer memory 300 to limit write buffering and/or read prefetch execution independently of whether or not a performance bottleneck occurs. In this case, the buffer manager 30 may calculate a size of a buffer area in which write data is temporarily stored or read data is prefetched, and limit the execution based on the calculated size of the buffer area. In this case, a threshold value regarding the size of the buffer area may be preset, the calculated size is compared with the threshold value, and when the threshold value is exceeded, the execution may be restricted.

The above-described buffer traffic monitoring unit 20 and/or buffer management unit 30 may be implemented in hardware or software. That is, it may be implemented in the form of a digital or analog circuit located inside the memory controller 100 , or implemented as a separate chip or module and connected to the memory controller 100 , and an internal memory such as SRAM, a floppy disk, a compact disk, or a USB It may be implemented in a manner of storing and executing software in an external memory, such as, or may be implemented in a form programmable by a user. Furthermore, it may be integrated into the buffer memory controller 15 or other built-in modules.

The memory controller 100 according to the present invention may further include a host interface 40 as a means for providing an interface with the host 400 . The host interface 40 may be connected to the host 400 through one or more channels or ports. For example, the host interface 40 may be connected to the host 400 through any one or both of a parallel AT attachment bus (PATA), a serial AT attachment (SATA) bus, and a peripheral component interconnect express (PCIe) bus. have. Alternatively, it may be connected to the outside through SCSI, USB, or the like.

In addition, the memory controller 100 according to the present invention may further include a memory channel controller 60 as a means for providing an interface with the nonvolatile memory 200 . Here, the non-volatile memory 200 may be implemented as a flash memory, PRAM, MRAM, ReRAM, FRAM, or the like, and a plurality of memory channel controllers 60 may be used to support the plurality of non-volatile memories 200 . In this case, one or more nonvolatile memories 200 may be connected to one memory channel controller 60 , and the nonvolatile memories 200 connected to one memory channel controller 60 may share the same data bus. can

Meanwhile, the memory controller 100 according to the present invention may further include a processor 50 to process a request from the host 400 . The processor 50 may be implemented as a micro control unit (MCU), a central processing unit (CPU), or the like. The processor 50 is a component for processing the write command and the read command transmitted from the host 400 , and may control the function of the memory controller 100 by driving software necessary for processing the command. Such a processor 50 may run software such as a flash translation layer (FTL). The flash translation layer may control the execution of the memory channel controller 60 and may perform garbage collection (GC). Here, software driven by the processor 50 may be stored in the buffer memory 300 .

Hereinafter, a memory controller according to the present invention will be described in more detail by taking an embodiment in which a read command and a write command are respectively received from the host.

4 to 5 are flowcharts illustrating a method of operating a memory controller according to an embodiment of the present invention. FIG. 4 illustrates an operation method for a host write command and FIG. 5 illustrates an operation method for a host read command, respectively.

Referring to FIG. 4 , when the memory controller receives a host write command, it is first checked whether the buffer of the buffer memory is in a full state. In the full state, write buffering cannot be executed, so the data corresponding to the write command is transferred to the non-volatile memory and a mapping (LBA-to-physical) that converts the logical block address (LBA) of the data into a physical address address), after performing the update, a processing completion signal (completion) is transmitted to the host. If the buffer is not in the full state, a random number between 1 and 100 is generated, and compared with the write buffering execution ratio, if the value is greater than the execution ratio, the write buffering is omitted. That is, it is processed in the same way as when the buffer is full. On the other hand, if the random number is less than the write buffering execution rate, a buffer area is allocated in the buffer memory, the data is transferred to the buffer memory, and temporarily stored in the write buffer, and the logical block address (LBA, Logical Block Address) of the write data is stored. It inserts into the write buffer LBA list and performs a series of write buffering that delivers a processing completion signal to the host. At this time, if there is an LBA of the corresponding write data in the read prefetch buffer LBA list, it is deleted. Next, after executing a buffer flush that transfers the data stored in the write buffer to the non-volatile memory, and updating the LBA-to-physical address that translates the LBA into a physical address, the LBA in the write buffer LBA list delete

Referring to FIG. 5 , when a read command is received from the host, it is searched for whether data corresponding to the read command exists in the write buffer of the buffer memory, and if the data exists, the data is transmitted to the host, and the write buffer If there is no data in the buffer memory, the prefetch buffer of the buffer memory is searched and the data is present in the prefetch buffer, and the data is delivered to the host. When the corresponding data does not exist in the buffer memory, the data is transferred from the nonvolatile memory to the host. When data is transferred to the host in this way, read prefetch is performed according to the read prefetch execution ratio. A random number between 1 and 100 is generated and if it is greater than the execution ratio, the read prefetch execution is omitted. perform the patch.

The memory controller according to the present invention can be applied to a storage device, which will be described below.

5 is a block diagram schematically illustrating a storage device according to an embodiment of the present invention, and FIG. 6 is a block diagram illustrating an example in which the storage device according to an embodiment of the present invention is applied to an SSD.

As shown in FIG. 5 , a storage device 1000 according to an embodiment of the present invention includes a non-volatile memory 200 , a buffer memory 300 ; and a memory controller 100 for controlling the nonvolatile memory 200 and managing the buffer memory 300 .

Here, the storage device 1000 may include a memory card or a removable removable storage device. The storage device 1000 is used in connection with the host 2000 , and data is exchanged with the host 2000 through the host 2000 interface. In this case, the storage device 1000 may receive power from the host 2000 to perform an internal operation.

The non-volatile memory 200 may be a flash memory or the like, and the memory controller 100 controls the non-volatile memory 200 as described above, determines the performance bottleneck of the buffer memory 300 and functionalizes it to manage it. The buffer memory 300 is used to buffer data to be transmitted from the host 2000 to the non-volatile memory 200 or from the non-volatile memory 200 to the host 2000, each of which is described above. Thus, detailed description will be omitted.

Also, referring to FIG. 6 , the storage device 1000 according to the present invention may be a solid state drive (SSD).

Since the SSD is connected to the host 2000 , the host 2000 may write data to or read data stored in the SSD. The SSD may exchange signals with the host 2000 through the host 2000 interface and receive power through the power connector. The SSD may include a plurality of non-volatile memories 200 and an SSD controller, where the non-volatile memory 200 may be implemented as PRAM, MRAM, ReRAM, FRAM, etc. in addition to flash memory, and a plurality of non-volatile memories 200 may be connected to the SSD controller through a plurality of channels. In this case, one or more nonvolatile memories 200 may be connected to one channel, and the nonvolatile memories 200 connected to one channel may be connected to the same data bus.

Meanwhile, the memory controller 100 according to the present invention is provided as an SSD controller and transmits and receives signals to and from the host 2000 through the host 2000 interface. Here, a command, address, data, etc. may be transmitted through a signal, and data is written to or read from the nonvolatile memory 200 according to a command of the host 2000 .

Although the present invention has been described in detail through specific examples, this is intended to describe the present invention in detail, and the present invention is not limited thereto, and by those of ordinary skill in the art within the technical spirit of the present invention. It is clear that the modification or improvement is possible.

All simple modifications and variations of the present invention belong to the scope of the present invention, and the specific scope of protection of the present invention will be made clear by the appended claims.

10: request queue 15: buffer memory controller
20: buffer traffic monitoring unit 30: buffer management unit
40: host interface 50: processor
60: memory channel controller 100: memory controller
200: non-volatile memory 300: buffer memory
400, 2000: host 1000: storage device

Claims (10)

Write buffering for temporarily storing data to be written into the non-volatile memory in response to a write command from the host, and read from the non-volatile memory in anticipation of a subsequent read command that will occur continuously after processing of the read command from the host is completed A memory controller for executing a buffering operation including a read prefetch for temporarily storing data to be used in the buffer memory,
In response to each of a plurality of write commands and read commands of the host, a plurality of buffer write requests, which are requests for temporarily storing the data in the buffer memory, and a plurality of buffer write requests for reading the data stored in the buffer memory is a buffer request queue that stores a number of buffer read requests that are requests;
a buffer traffic monitoring unit stored in the buffer request queue and calculating a total amount of request data in real time by summing the lengths of the data included in each of the plurality of unexecuted buffer write requests and the unexecuted buffer read requests; and
A buffer configured to set an execution ratio based on the total amount of the request data calculated in real time, and limit the execution of the buffering operation for a part randomly selected among write commands and read commands of the plurality of hosts according to the execution ratio management; including;
For some of the write commands in which the execution of the buffering operation is restricted, the write buffering is omitted and the data to be written is transferred to the non-volatile memory;
For some of the read commands in which the execution of the buffering operation is restricted, the read prefetch is omitted,
The buffer management unit,
The memory controller performs the buffering operation according to a preset initial execution ratio, but sets the execution ratio by lowering the initial execution ratio when the total amount of the request data calculated in real time exceeds a preset upper limit.
delete The method according to claim 1,
The buffer management unit,
The memory controller for setting the execution ratio by repeatedly adjusting downward until the total amount of the request data calculated in real time is equal to or greater than a predetermined lower limit and less than or equal to the upper limit.
4. The method according to claim 3,
The buffer management unit,
If the total amount of the request data calculated in real time is less than the lower limit, the memory controller increases the execution ratio.
5. The method according to claim 4,
The buffer management unit,
Even if the total amount of the request data calculated in real time is less than the lower limit value, the memory controller maintains the execution ratio when the set execution ratio is the same as the initial execution ratio.
5. The method according to claim 4,
The buffer management unit,
The memory controller adjusts the execution ratio by applying a preset execution ratio variation for each section according to the degree of exceeding the upper limit value and the degree of being less than the lower limit value.
The method according to claim 1,
The buffer management unit,
A memory controller that distinguishes the write buffering from the read prefetch, and controls execution of an operation for each.
8. The method of claim 7,
The buffer management unit,
setting a first execution rate to control execution of the write buffering operation;
The memory controller controls execution of the read prefetch operation by setting a second execution ratio that is the same as or different from the first execution ratio.
9. The method of claim 8,
The buffer management unit,
Among a plurality of the write commands, a part is randomly selected according to the first execution ratio, and the buffering operation is performed only on the selected part,
A memory controller that randomly selects a part of the plurality of read commands according to the second execution ratio, and executes the read prefetch operation on only the selected part.
non-volatile memory;
buffer memory; and
A storage device comprising a; the memory controller according to any one of claims 1 and 3 to 9.

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