KR102088945B1 - Memory controller and storage device including the same - Google Patents

Abstract

The present invention relates to a memory controller and a storage device including the same. According to an embodiment of the present invention, a memory controller 100 includes: a memory channel controller 10 that executes erase/program, read, and erase/program suspend operations for a flash memory 200, a flash conversion layer 20 that controls the execution of the memory channel controller 10 by receiving a write/read command, temporarily stores data by allocating a buffer space in a buffer memory corresponding to the write command of the write/read command, and releases the buffer space allocated when the program operation for the data is executed, a host interface 30 that receives the write/read command from a host 300 and transmits the write/read command to the flash conversion layer 20, and a suspend changing unit 40 that dynamically changes an erase/program suspend limit, which represents the maximum possible number of times for the erase/program suspend operation, based on an allocable size of the buffer space.

Description

MEMORY CONTROLLER AND STORAGE DEVICE INCLUDING THE SAME TECHNICAL FIELD

The present invention relates to a memory controller and a storage device including the same, and more particularly, to a memory control technology for dynamically changing and controlling the number of erasing / program supends possible.

Semiconductor memories are classified into volatile memory and non-volatile memory according to information storage mechanisms. Volatile memory includes DRAM, SRAM, etc., which reads and writes quickly, but when the power supply is cut off, memory information is lost. On the other hand, the non-volatile memory is used to store data to be preserved regardless of whether or not power is supplied because the storage information can be stored even when the power is cut off. Examples of the non-volatile memory include EPROM, EEPROM, FRAM, PRAM, MRAM, and Flash memory. In particular, as disclosed in the patent documents of the following prior art documents, flash memory includes computers, smartphones, digital cameras, It is widely used as an audio and video data storage medium for information devices such as voice recorders and camcorders.

There are a number of outstanding host commands in a flash storage device composed of such flash memory, and these host command processing operations and buffer flush or garbage collection, GC) causes multiple outstanding flash commands. Due to the queuing effect due to multiple commands, the host read / write latency is not constant and has a specific distribution. It is desirable that the latency is narrow. This is because the host can easily predict the latency. That is, the higher the latency consistency (the narrower the distribution width), the better the quality of service (QoS) of the storage device. Conventionally, write buffering is used to improve the write QoS. In order to improve read QoS, erase / program suspend was used. However, if the number of erase / program suspend possible is set too small, the read QoS decreases, and if the number is set too large, the write QoS decreases. In particular, if the number of times the suspend is possible is too large, erase or program throughput decreases, and thus buffer flush or GC performance deteriorates. In this case, when the buffer flush is late and the buffer becomes full, or when the GC is late and the free block is exhausted, the write command processing is delayed.

Accordingly, a method for solving the problems of the prior art for improving the QoS of the flash storage device is urgently required.

KR 1994-0022295 A

The present invention is to solve the above-mentioned problems of the prior art, one aspect of the present invention is to provide a memory controller capable of dynamically changing the number of times the program can be erased or suspended.

A memory controller according to an embodiment of the present invention includes a memory channel controller that performs erase / program, read, and erase / program suspend operations for a flash memory; A write / read command is received to control execution of the memory channel controller, but in response to a write command among the write / read commands, buffer space is allocated to a buffer memory to temporarily store data, and the program operation for the data is performed. A flash translation layer that, when executed, releases the allocated buffer space; A host interface that receives the write / read command from a host and transmits it to the flash conversion layer; And a suspension changing unit dynamically changing the erase / program suspend limit, which is the maximum number of erasing / program suspends, based on the size of the allocable buffer space.

In addition, in the memory controller according to an embodiment of the present invention, the suspension changing unit may change the erase / program suspend limit by referring to the reference table in which the erase / program suspend limit is recorded for each size of a predetermined buffer space.

In addition, in the memory controller according to an embodiment of the present invention, it may further include a; memory unit for storing the reference table.

In addition, in the memory controller according to the embodiment of the present invention, the flash conversion layer calculates the size of the allocable buffer space, and the suspend change unit refers to the reference table to calculate the calculated size of the buffer space. It is possible to change the erase / program suspend limit to correspond to.

In addition, in the memory controller according to an embodiment of the present invention, the suspend change unit calculates the size of the allocable buffer space, and refers to the reference table to erase the data so as to correspond to the calculated size of the buffer space. You can change the program suspend limit.

In addition, in the memory controller according to an embodiment of the present invention, the memory channel controller counts the number of erase / program suspensions, and during the erase / program operation according to the write command of the write / read command, a read command is generated. When input, the erase / program suspend count may be less than the erase / program suspend limit, suspend the erase / program operation and execute the read operation.

In addition, the storage device according to an embodiment of the present invention includes a flash memory; And a memory controller that controls the flash memory.

Features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings.

Prior to this, the terms or words used in the specification and claims should not be interpreted in a conventional and lexical sense, and the inventor can appropriately define the concept of terms in order to best describe his or her invention. Based on the principle that it should be interpreted as meanings and concepts consistent with the technical spirit of the present invention.

According to the present invention, by dynamically changing the number of times the number of suspends can be erased / programmed, the write QoS and read QoS can be kept constant even if the host workload characteristics change.

1 is a block diagram schematically illustrating a memory controller according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating the operation of the memory controller shown in FIG. 1.
3 is a flowchart illustrating a method of operating a memory controller according to the present invention.
4 is a block diagram schematically illustrating a storage device according to an embodiment of the present invention.
5 is a block diagram illustrating an example in which a storage device according to an embodiment of the present invention is applied to an SSD.

The objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and preferred embodiments that are associated with the accompanying drawings. It should be noted that in this specification, when adding reference numerals to components of each drawing, the same components have the same number as possible, even if they are displayed on different drawings. Further, terms such as “first” and “second” are used to distinguish one component from other components, and the component is not limited by the terms. Hereinafter, in describing the present invention, detailed descriptions of related well-known technologies that may unnecessarily obscure the subject matter of the present invention are omitted.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically illustrating a memory controller according to an embodiment of the present invention.

As shown in FIG. 1, the memory controller 100 according to an embodiment of the present invention is a memory channel controller that executes erase / program, read, and erase / program suspend operations for the flash memory 200 (10) Controls the execution of the memory channel controller 10 by receiving a write / read command, but allocates buffer space to the buffer memory in response to the write command among the write / read commands to temporarily store the data. When the program operation is executed, the flash conversion layer 20 that releases the allocated buffer space, the host interface 30 that receives a write / read command from the host 300 and transmits it to the flash conversion layer 20, and allocable Based on the size of the buffer space, the erase / program suspend limit, which is the maximum possible number of erase / program suspends, is dynamically adjusted. And a suspend changing section 40 to change.

The present invention relates to a memory controller for controlling flash memory in a storage device. In order to improve the quality of service (QoS) of the storage device, erase / program suspend is used, but if the number of erase / program suspends is set too small, read QoS deteriorates and the number is too large. When set, a problem occurs in that the write QoS decreases, and the present invention has been devised as a solution to this.

Specifically, the memory controller 100 according to the present invention includes a memory channel controller 10, a flash translation layer 20, a host interface 30, and a suspend changer 40.

The memory channel controller 10 may perform erase, program, read, erase suspend, and program suspend operations for the flash memory 200 connected through the channel. Run it. The execution of this operation is performed in response to a flash erase command, a flash program command, and a flash read command of the flash conversion layer 20.

The memory channel controller 10 fetches a command from a queue, executes the corresponding command when the target flash memory 200 of the command is in an idle state, and executes the completion information. The result is attached and transmitted to the flash translation layer 20. On the other hand, if the target flash memory 200 is in a busy state, that is, when executing the previous command, wait for the flash memory 200 to become idle before executing a new command, or already being executed. Suspend the command, execute the new command first, and then resume the suspended command. At this time, whether to suspend the running command depends on the priority of the command. The flash read command may be set to have a higher priority than the flash erase or program command. Meanwhile, the flash erase or program resumed after being suspended may be suspended again. However, the maximum possible number of such erase / program suspension may be limited, and if the maximum possible number of times is exceeded, the corresponding erase or program operation is executed without being suspended even if a command having a high priority is input. Hereinafter, the maximum possible number of erase / program suspends is defined as a suspend limit of erase / program suspends. Here, the erase / program suspend limit may be divided into an erase suspend limit and a program suspend limit.

The flash conversion layer 20 receives the write / read command and controls the execution of the memory channel controller 10. Here, the write / read command is a command input from the host 300, and may be classified into a host write command and a host read command.

In response to the host write command, the flash conversion layer 20 may perform write buffering and buffer flush. First, when a host write command is received, the buffer space is allocated to the buffer memory, the host data is temporarily stored in the allocated buffer space, and then write completion is transmitted to the host 300. do. This process is called write buffering. Next, in order to flush the buffered data to the flash memory 200, a flash program command is transmitted to the memory channel controller 10, and upon receiving the flash program completion, the location where the data is stored is mapped table (mapping table). ) And free the allocated buffer space. The above process is called buffer flush. The write buffering can be quickly completed to the host 300, thereby improving write latency. Since the buffer flush is performed in the background, it does not affect the performance experienced by the host 300 in the normal case, but if the buffer flush is too late, the space available for allocation to the buffer memory is exhausted. The latency for can be lengthened.

On the other hand, when the host read command is input, first, it is searched whether the requested data exists in the buffer space. When data exists in the buffer, data is transferred from the buffer to the host 300 and completion is transmitted. On the other hand, when the buffer data does not exist, the flash read command is transmitted to the memory channel controller 10 by obtaining a physical address on the flash memory 200 where the data is located by referring to the mapping table, and accordingly, the host 300 ) To transfer data and completion of the flash memory 200.

Further, the flash conversion layer 20 performs garbage collection (Grbage Collection, GC). The page of the flash memory 200 must be written only when it is in a free state, and since overwrite is not allowed, a block of the flash memory 200 must be erased first to program new data. . At this time, the erased and programmable block is called a free block. In order to flush write buffered data, there must be a free block, and the operation of generating such a free block is called garbage collection.

The host interface 30 provides an interface with the host 300. The host interface 30 may be connected to the host 300 through at least one channel or ports. For example, the host interface 30 may be connected to the host 300 through any one or both of a parallel AT attachment bus (PATA bus), a serial AT attachment (SATA bus), and a peripheral component interconnect express (PCIe bus). have. Alternatively, it may be connected to the outside through SCSI, USB, or the like.

The host interface 30 receives a write / read command from the host 300 and transmits it to the flash conversion layer 20, and receives a completion corresponding to the transmitted write / read command from the flash conversion layer 20. To the host 300.

The suspend change unit 40 dynamically changes the erase / program suspend limit based on the size of the allocable buffer space. The size of the allocable buffer space can be defined as the free write buffer size, which is initially set to the maximum value of the operable buffer memory. The size of the buffer space decreases during write buffering and increases again when buffer flushing is complete.

The suspension change unit 40 may be implemented in hardware or software. That is, it may be implemented in the form of a digital or analog circuit located inside the memory controller 100, or may be implemented as a separate chip or module and connected to the memory controller 100, and may have built-in memory such as SRAM or floppy disk, compact disk, USB It may be implemented by storing and executing software in an external memory. It may also be implemented in a form that can be programmed by the user. Furthermore, it can be integrated with the flash translation layer 20 or the host interface 30. That is, the flash conversion layer 20 or the host interface 30 may perform all or part of the functions of the suspend change unit 40 in addition to the original functions described above.

When the erase suspend limit and / or program suspend limit is changed by the suspend changing unit 40, the memory channel controller 10 does not infinitely erase or suspend the program when a command having a higher priority than the command being executed is input. , Suspend operation is executed only when the number of suspends executed so far is smaller than the suspend limit value. At this time, since the suspend limit is changed based on the write / read latency obtained from the actual operation execution, the write QoS and read QoS can be kept constant even if the host workload characteristics are changed.

Hereinafter, an embodiment of determining an erase / program suspend limit will be described.

FIG. 2 is a block diagram illustrating the operation of the memory controller shown in FIG. 1, and FIG. 3 is a flowchart illustrating a method of operating the memory controller according to the present invention.

Referring to FIGS. 2 to 3, when the suspend change unit 40 determines the erase / program suspend limit, the reference table may be referred to. The reference table is a table in which erase / program suspend limits are recorded for each size of the buffer space, and is provided by presetting the erase suspend limit and program suspend limit optimized according to the size value of the allocable buffer space. An example of such a reference table is shown in [Table 1] below. Here, p-limit means a program suspend limit, and e-limit means a clear suspend limit.

Free write buffer size (MB) Suspend limit p-limit e-limit Less than 10 0 0 10 to 20 4 10 20 to 30 8 20 … 180 ~ 190 72 110 190 ~ 200 ∞ ∞

The reference table is only an example, and the size of a specific buffer space and the corresponding suspension limit may be determined through experiments. The reference table may be stored in the memory unit 50. Here, the memory unit 50 may be provided as a separate memory such as SRAM, or may utilize an existing buffer memory. When the size of the buffer space allocable during the write / read command is calculated, the suspension change unit 40 may change the erase / program suspend limit to correspond to the calculated size of the buffer space by referring to the reference table. Here, the size calculation of the allocable buffer space may be performed in the flash conversion layer 20 or may be performed in the suspension change unit 40.

The erase / program suspend limit determined by the suspension changing unit 40 may be separately stored, for example, may be stored in the memory channel controller 10.

The memory channel controller 10 performs an operation on the flash memory 200 by using the erase / program suspend limit. Here, the memory channel controller 10 counts the number of times the corresponding command is suspended for a specific erase or program command, that is, the number of times each of the erase suspension and the program suspension is suspended. At this time, if a high-priority read command is input during the erase or program operation execution corresponding to the write command, after comparing the counted suspend count and the suspend limit, the suspend operation is executed only when the count count is less than the suspend limit. Execute read operation.

The memory controller according to the present invention can be applied to a storage device, which will be described below.

4 is a block diagram schematically showing a storage device according to an embodiment of the present invention, and FIG. 5 is a block diagram showing an example of applying a storage device according to an embodiment of the present invention to an SSD.

As illustrated in FIG. 4, the storage device 1000 according to an embodiment of the present invention may include a flash memory 1100 and a memory controller 1200 that controls the flash memory 1100.

Here, the storage device 1000 may include a memory card or a removable removable storage device. The storage device is used in connection with the host 2000, and exchanges data with the host 2000 through the host 2000 interface. At this time, the storage device 1000 may receive power from the host 2000 and perform an internal operation.

As described above, the flash memory 1100 has read / erase / program suspend operations controlled based on the erase / program suspend limit dynamically changed according to the memory controller 1200. The operation control related to this has been described above, and a detailed description thereof will be omitted.

In addition, referring to FIG. 5, the storage device 1000 according to the present invention may be a solid state drive (SSD).

Since the SSD is connected to the host 2000, the host 2000 can write data to the SSD or read data stored in the SSD. The SSD may exchange signals with the host 2000 through a host interface and receive power through a power connector. The SSD may include a plurality of flash memories 1100 and an SSD controller, wherein the plurality of flash memories 1100 may be connected to the SSD controller through a plurality of channels. In this case, one or more flash memories 1100 may be connected to one channel, and the flash memory 1100 connected to one channel may be connected to the same data bus.

Meanwhile, the memory controller 1200 according to the present invention is provided as an SSD controller, and exchanges signals with the host 2000 through the host 2000 interface. Here, commands, addresses, data, and the like may be transmitted through a signal, and data may be written to or read from the flash memory 1100 according to a command of the host 2000.

Although the present invention has been described in detail through specific embodiments, the present invention is specifically for describing the present invention, and the present invention is not limited to this, and by those skilled in the art within the technical spirit of the present invention. It is clear that the modification and improvement are possible.

All simple modifications or changes of the present invention belong to the scope of the present invention, and the specific protection scope of the present invention will be clarified by the appended claims.

10: memory channel controller 20: flash translation layer
30: host interface 40: suspension change unit
50: memory unit 100, 1200: memory controller
200, 1100: Flash memory 300, 2000: Host
1000: storage device

Claims (7)

A memory channel controller that performs erase / program, read, and erase / program suspend operations for flash memory;
A write / read command is received to control execution of the memory channel controller, but in response to a write command among the write / read commands, buffer space is allocated to a buffer memory to temporarily store data, and the program operation for the data is performed. A flash translation layer that, when executed, releases the allocated buffer space;
A host interface that receives the write / read command from a host and transmits it to the flash conversion layer; And
And a suspension changing unit dynamically changing the erase / program suspend limit, which is the maximum possible number of erase / program suspend operations, based on the size of the allocable buffer space.
The method according to claim 1,
The suspend change section,
A memory controller that changes the erase / program suspend limit by referring to the reference table in which the erase / program suspend limit is recorded for each size of the preset buffer space.
The method according to claim 2,
A memory controller further comprising a memory unit for storing the reference table.
The method according to claim 2,
The flash conversion layer calculates the size of the allocated buffer space,
The suspend change unit, referring to the reference table, changes the erase / program suspend limit to correspond to the calculated size of the buffer space.
The method according to claim 2,
The suspend change section,
A memory controller that calculates the size of the allocable buffer space and changes the erase / program suspend limit to correspond to the calculated size of the buffer space with reference to the reference table.
The method according to claim 2,
The memory channel controller,
Count the number of times of the erase / program suspend operation,
A memory controller executing the read operation when the number of times of the erase / program suspend operation is less than the erase / program suspend limit when a read command is input during the erase / program operation according to the write command among the write / read commands .
Flash memory; And
According to any one of claims 1 to 6, Memory device for controlling the flash memory; Storage device comprising a.

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