KR102263163B1 - Semiconductor memory device including plurality of memory cells and operating method thereof - Google Patents

Abstract

The method of operating a semiconductor memory device according to an embodiment of the present invention includes performing program operations on the plurality of pages, respectively, and applying at least one program pulse to a plurality of word lines to include in the plurality of pages. The method may include further increasing threshold voltages of memory cells, setting a reference test voltage, and detecting a defective page by performing respective reads on a plurality of pages using the reference test voltage.

Description

A semiconductor memory device including a plurality of memory cells and an operating method thereof

The present invention relates to an electronic device, and more particularly, to a semiconductor memory device including a plurality of memory cells and an operating method thereof.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si, silicon), germanium (Ge, Germanium), gallium arsenide (GaAs, gallium arsenide), indium phosphide (InP), etc. to be. A semiconductor memory device is largely divided into a volatile memory device and a nonvolatile memory device.

A volatile memory device is a memory device in which stored data is destroyed when power supply is cut off. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). The nonvolatile memory device is a memory device that retains stored data even when power supply is cut off. Nonvolatile memory devices include ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), Flash memory, PRAM (Phase-change RAM), MRAM (Magnetic RAM) , RRAM (Resistive RAM), FRAM (Ferroelectric RAM), and the like. Flash memory is largely divided into a NOR type and a NAND type.

SUMMARY An embodiment of the present invention is to provide a semiconductor memory device having improved reliability.

A semiconductor memory device according to an embodiment of the present invention includes a plurality of pages connected to a plurality of word lines. The method of operating the semiconductor memory device may include performing program operations on the plurality of pages, respectively, in each of the program operations, by performing a program on a selected page to change threshold voltages of memory cells included in the selected page increasing, applying a verification voltage to the word line of the selected page to verify whether the result of the program is a pass, and executing the program until the result of the program is the pass; comprising repeating the steps; further increasing threshold voltages of memory cells included in the plurality of pages by applying at least one program pulse to the plurality of word lines; setting a voltage higher than the reference voltage by a predetermined voltage as a reference test voltage; and detecting a defective page among the plurality of pages by performing reads on the plurality of pages, respectively, using the reference test voltage. includes

In an embodiment, the plurality of pages may be stacked over a substrate, and each of the plurality of pages may be connected to a corresponding word line at a predetermined height from the substrate.

In an embodiment, the detecting of the defective page may include: detecting first and second page data by performing reads on first and second pages among the plurality of pages; generating a first comparison page by performing an OR operation on the data bits of the first page data and the data bits of the second page data; and generating a first error value according to the number of fail bits of the first comparison page.

In an embodiment, the detecting of the defective page may include: detecting third page data by reading a third page among the plurality of pages; generating a second comparison page by performing an OR operation on the data bits of the second page data and the data bits of the third page data; and generating a second error value according to the number of fail bits of the second comparison page.

In an embodiment, the detecting of the defective page may further include detecting the third page as the defective page by comparing the second error value with the first error value.

In an embodiment, the detecting of the defective page may further include detecting the third page as the defective page when the second error value is greater than an integer multiple of the first error value.

In an embodiment, the detecting of the defective page may further include detecting the third page as the defective page when the second error value is greater than the first error value by a predetermined value. .

In an embodiment, the detecting of the defective page may include: detecting first page data by reading a first page among the plurality of pages; generating a first error value according to the number of fail bits in the first page data; detecting second page data by reading a second page among the plurality of pages; and generating a second error value according to the number of fail bits in the second page data.

In an embodiment, the detecting of the defective page may further include detecting the third page as the defective page by comparing the second error value with the first error value.

In an embodiment, the detecting of the defective page may include: generating page data by reading any one of the plurality of pages; and detecting the corresponding page as the defective page when the number of fail bits of the page data is greater than a reference value.

In an embodiment, the area corresponding to the defective page may be defined as a bad area.

According to another embodiment of the present invention, a method of operating a semiconductor memory device includes: performing a program operation according to an incremental step pulse program (ISPP) method using a determined verification voltage on each of a plurality of pages; further providing at least one program pulse to the plurality of pages through a plurality of word lines; and detecting a defective page among the plurality of pages by performing reads on the plurality of pages, respectively, using a reference test voltage that is higher than the verification voltage by a predetermined voltage.

In an embodiment, the memory cells included in the plurality of pages may be stacked over a substrate, and each of the plurality of pages may be connected to a corresponding word line at a predetermined height from the substrate.

In an embodiment, the program operation may be performed so that the threshold voltages of the memory cells included in the plurality of pages rise higher than the verification voltage.

Another aspect of the present invention relates to a semiconductor memory device. A semiconductor memory device according to an embodiment of the present invention includes: a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of pages connected to a plurality of word lines; and respectively performing program operations on the plurality of pages, performing a program on a page selected in each of the program operations, and applying a verification voltage to a word line of the selected page to determine whether the result of the program is a pass and a peripheral circuit configured to verify the program and repeat the program and the verification until the result of the program is the pass. The peripheral circuit applies at least one program pulse to the plurality of word lines to further increase threshold voltages of memory cells included in the plurality of pages, and thereafter, a reference test voltage higher than the verification voltage by a predetermined voltage. and to detect a defective page among the plurality of pages by performing reads on the plurality of pages, respectively.

In an embodiment, the plurality of pages may be stacked over a substrate, and each of the plurality of pages may be connected to a corresponding word line at a predetermined height from the substrate.

In an embodiment, the peripheral circuit detects first and second page data by performing reads on first and second pages among the plurality of pages, and includes data bits of the first page data and the second page data. and a detector configured to generate a first comparison page by performing an OR operation on data bits of the second page data, and to generate a first error value according to the number of fail bits of the first comparison page.

In an embodiment, the peripheral circuit detects third page data by reading a third page among the plurality of pages, and the data bits of the second page data and the data bits of the third page data A second comparison page may be generated by performing an OR operation on the values, and the detector may generate a second error value according to the number of fail bits of the second comparison page.

In an embodiment, the peripheral circuit may further include a control logic configured to detect the third page as the defective page by comparing the second error value with the first error value.

In an embodiment, the area corresponding to the defective page may be defined as a bad area.

According to an embodiment of the present invention, a semiconductor memory device having improved reliability is provided.

1 is a graph showing voltage distributions of memory cells included in each of a plurality of pages.
2 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
3 is a block diagram illustrating an embodiment of the memory cell array of FIG. 1 .
FIG. 4 is a circuit diagram showing any one of the memory blocks of FIG. 3 .
5 is a circuit diagram illustrating another embodiment of any one of the memory blocks of FIG. 3 .
6 is a block diagram conceptually illustrating pages included in the memory block of FIG. 4 .
7 is a flowchart illustrating a test operation of a semiconductor memory device according to an embodiment of the present invention.
8 is a flowchart illustrating program operations on pages of one cell string group of a selected memory block.
9 is a timing diagram illustrating program pulses applied during the program operation in step S110 of FIG. 8 and additional program pulses applied in step S120 of FIG. 8 .
10 is a graph illustrating changes in voltage distributions of pages of a selected memory block in steps S110 and S120 of FIG. 7 .
11 is a graph illustrating another example of a change in voltage distributions of pages of a selected memory block in steps S110 and S120 of FIG. 7 .
12 is a flowchart illustrating a method of determining whether a defective page exists among pages of one cell string group of a selected memory block.
13 is a flowchart illustrating another embodiment of a method of determining whether a defective page exists among pages of one cell string group of a selected memory block.
14 is a block diagram illustrating one embodiment of the page buffers of FIG. 2 .
15 is a diagram illustrating an embodiment for generating the first and second comparison pages of FIG. 13 .
16 is a flowchart illustrating another embodiment of a method of determining whether a defective page exists among pages of one cell string group of a selected memory block.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only parts necessary for understanding the operation according to the present invention are described, and descriptions of other parts will be omitted so as not to obscure the gist of the present invention. Also, the present invention is not limited to the embodiments described herein and may be embodied in other forms. However, the embodiments described herein are provided to explain in detail enough to easily implement the technical idea of the present invention to those of ordinary skill in the art to which the present invention pertains.

Throughout the specification, when a part is "connected" with another part, this includes not only the case of being "directly connected" but also the case of being "indirectly connected" with another element interposed therebetween. . Throughout the specification, when a part "includes" a certain element, it means that other elements may be further included, rather than excluding other elements, unless otherwise stated.

1 is a graph showing voltage distributions of memory cells included in each of a plurality of pages. In FIG. 1 , a horizontal axis indicates a threshold voltage, and a vertical axis indicates the number of memory cells.

It is assumed that a high voltage program pulse is applied to each of the plurality of pages when the memory cells of the plurality of pages have the erase distribution E. Threshold voltages of the corresponding memory cells will increase.

Most pages may have similar voltage distributions VD1. On the other hand, a specific page may have a voltage distribution VD2 in a relatively low voltage range. Corresponding memory cells may be defined as slow cells. Slow cells will have low threshold voltages despite application of the same program pulse. It will be appreciated that slow cells may appear due to various causes. For example, due to a defect in a word line, the corresponding word line may not normally transmit a program pulse. For example, a bridge between a corresponding word line and an adjacent word line may be generated. Such a defect may be any one of a process defect and a growing defect.

Slow cells degrade the reliability of the semiconductor memory device. During programming, the slow cells may not have desired threshold voltages despite continuous application of the program pulse. Due to these slow cells, the speed of the semiconductor memory device may be lowered and the reliability of the semiconductor memory device may be lowered.

2 is a block diagram illustrating a semiconductor memory device 50 according to an embodiment of the present invention.

Referring to FIG. 2 , the semiconductor memory device 50 includes a memory cell array 100 and a peripheral circuit 110 .

The memory cell array 100 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 120 through row lines RL and to the read and write circuit 140 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells are nonvolatile memory cells. The plurality of memory blocks BLK1 to BLKz will be described in more detail with reference to FIGS. 3 to 6 .

The peripheral circuit 110 includes an address decoder 120 , a voltage generator 130 , a read and write circuit 140 , a data input/output circuit 150 , a control logic 160 , and a detector 170 .

The address decoder 120 is connected to the memory cell array 110 through row lines RL. The address decoder 120 is configured to operate in response to the control of the control logic 160 .

A program operation and a read operation of the semiconductor memory device 50 are performed in units of pages. The erase operation of the semiconductor memory device 50 is performed in units of memory blocks.

The address decoder 120 receives an address ADDR. In a program operation or read operation, the address ADDR may include a block address and a row address. In an erase operation, the address ADDR will include the block address.

The address decoder 120 is configured to decode a block address among the received addresses ADDR. The address decoder 120 selects one of the memory blocks BLK1 to BLKz according to the decoded block address.

The address decoder 120 is configured to decode a row address among the received addresses ADDR. The address decoder 120 selects one word line of the selected memory block by applying voltages provided from the voltage generator 130 to the row lines RL according to the decoded row address.

In an embodiment, the address decoder 120 may include an address buffer, a block decoder, and a row decoder.

The voltage generator 130 is configured to generate a plurality of voltages using an external power voltage supplied to the semiconductor memory device 50 . The voltage generator 130 operates in response to the control of the control logic 160 .

As an embodiment, the voltage generator 130 may generate an internal power supply voltage by regulating the external power supply voltage. The internal power voltage generated by the voltage generator 130 is used as an operating voltage of the semiconductor memory device 50 .

As an embodiment, the voltage generator 130 may generate a plurality of voltages using an external power voltage or an internal power voltage. For example, the voltage generator 130 may include a plurality of pumping capacitors receiving an internal power supply voltage, and in response to control of the control logic 160 , selectively activating the plurality of pumping capacitors to generate a plurality of voltages. . The generated voltages may be applied to the word lines by the address decoder 120 .

The read and write circuit 140 includes first to mth page buffers PB1 to PBm. The first to m-th page buffers PB1 to PBm are respectively connected to the memory cell array 110 through the first to m-th bit lines BL1 to BLm. The first to mth page buffers PB1 to PBm operate in response to the control of the control logic 160 .

The first to mth page buffers PB1 to PBm may communicate data DATA with the data input/output circuit 150 through data lines DL. During reading, the first to mth page buffers PB1 to PBm read data from memory cells connected to the selected word line through the bit lines BL1 to BLm. The read data DATA may be output to the data input/output circuit 150 through the data lines DL or may be output to the detector 170 . During programming, the first to mth page buffers PB1 to PBm receive the data DATA to be programmed from the data input/output circuit 150 or the control logic 160 . The first to mth page buffers PB1 to PBm may program data to be programmed into memory cells connected to the selected word line through the bit lines BL1 to BLm.

The data input/output circuit 150 is connected to the first to mth page buffers PB1 to PBm through data lines DL. The data input/output circuit 150 operates in response to the control of the control logic 160 . The data input/output circuit 150 communicates data DATA with the outside.

The control logic 160 is connected to the address decoder 120 , the voltage generator 130 , the read and write circuit 140 , the data input/output circuit 150 , and the detector 170 . The control logic 160 receives the command CMD. The control logic 160 is configured to control the address decoder 120 , the voltage generator 130 , the read and write circuit 140 , the data input/output circuit 150 , and the detector 170 in response to the command CMD.

According to an embodiment of the present invention, the control logic 160 controls the peripheral circuit 110 to perform a test operation. In an embodiment, the control logic 160 may control the test operation in response to the command CMD. The test operation includes program operations on pages of the selected memory block and a plurality of reads for detecting a defective page using a reference test voltage. The test operation may be sequentially performed on each of the first to z-th memory blocks BLK1 to BLKz.

The control logic 160 may set a voltage higher than the verification voltage used in each program operation by a predetermined voltage as the reference test voltage. Control logic 160 will control voltage generator 130 to generate a reference test voltage. Thereafter, the control logic 160 may detect a defective page by controlling the peripheral circuit 110 to perform respective reads on pages of the selected memory block according to the reference test voltage. This is explained in more detail with reference to FIG. 7 .

The detector 170 determines the number of fail bits among data received from the first to mth page buffers PB1 to PBm and outputs the determined number of fail bits as an error value ER to the control logic 160 . do. For example, a fail bit may be defined as a data bit having a logical value “1” and a pass bit may be defined as a data bit having a logical value “0”. The control logic 160 may detect a defective page with reference to the received error value ER.

The control logic 160 may define an area corresponding to a defective page as a bad area. In an embodiment, the control logic 160 may define a memory block including a defective page as a bad area. The bad area will be replaced with a redundancy memory block among the plurality of memory blocks BLK1 to BLKz. In an embodiment, the control logic 160 may define a defective page as a bad area. In this case, the bad area will be replaced with a redundancy page among pages included in the corresponding memory block.

In an embodiment, the control logic 160 may store information on a defective page in an internal register (not shown). In an embodiment, the control logic 160 may store information on the defective page in a predetermined block among the plurality of memory blocks BLK1 to BLKz. Information on the defective page may be externally provided according to the command CMD.

3 is a block diagram illustrating an embodiment of the memory cell array 110 of FIG. 1 .

Referring to FIG. 3 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block has a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. The plurality of memory cells are arranged along the +X direction, the +Y direction, and the +Z direction. The structure of each memory block will be described in more detail with reference to FIGS. 4 and 5 .

FIG. 4 is a circuit diagram illustrating one of the memory blocks BLK1 to BLKz of FIG. 3 .

Referring to FIG. 4 , the first memory block BLK1 includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a 'U' shape. In the first memory block BLK1 , m cell strings are arranged in the row direction (ie, the +X direction). In the first memory block BLK1 , two cell strings are arranged in a column direction. However, this is for convenience of description and it will be understood that two or more cell strings may be arranged in the column direction (ie, +Y).

Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes at least one source select transistor SST, at least one source-side dummy memory cell SDC, a plurality of memory cells NMC1 to NMCn, and a pipe transistor. PT, at least one drain-side dummy memory cell DDC, and at least one drain select transistor DST.

Each of the selection transistors SST and DST, the dummy memory cells SDC and DDC, and the memory cells NMC1 to NMCn may have a similar structure. In an embodiment, each of the selection transistors SST and DST, the dummy memory cells SDC and DDC, and the memory cells NMC1 to NMCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer.

In each cell string, the memory cells NMC1 to NMCp, the source-side dummy memory cell SDC, and the source select transistor SST intersect the substrate (not shown) under the memory block BLK1, that is, the +Z direction. are sequentially stacked. In each cell string, the memory cells NMCp+1 to NMCn, the drain-side dummy memory cell DDC, and the drain select transistor DST are sequentially stacked in the +Z direction.

Two holes penetrating structures disposed between the bit lines BL1 to BLm and a substrate (not shown) under the memory block BLK1 in a direction opposite to the +Z direction are provided, and a channel is provided inside each of the provided holes. A film may be formed. These two holes may be understood to correspond to one cell string. A channel layer of each of the two holes may be connected by a channel layer of the pipe transistor PT. A channel layer of each of the two holes may serve as channel layers of the selection transistors SST and DST, the dummy memory cells SDC and DDC, and the memory cells NMC1 to NMCn included in one cell string.

As is well known, the width of each hole decreases as it approaches the substrate due to process characteristics. For example, the structures of the memory block BLK1 are etched from the top toward the substrate to form holes, and accordingly, the width of each hole decreases as it approaches the substrate. When the channel layer is formed inside the hole, the channel layer corresponding to each of the memory cells NMC1 to NMCn of the cell string may have a diameter corresponding to the width of the hole. Accordingly, the memory cells NMC1 to NMCn for each word line have different channel layers, and thus the memory cells NMC1 to NMCn may have different characteristics. In addition, it will be understood that characteristics of the memory cells NMC1 to NMCn may be different due to various causes. For example, it will be understood that characteristics of the memory cells NMC1 to NMCn for each word line may be different according to a difference in a distance between the common source line CSL and the memory cells. For example, a voltage transferred to the memory cell through the common source line CSL may be different according to a distance between the common source line CSL and the corresponding memory cell.

The source select transistor SST of each cell string is connected between the common source line CSL and the source-side dummy memory cell SDC. In an embodiment, the common source line CSL may be commonly connected to the memory blocks BLK1 to BLKz (refer to FIG. 3 ).

In an embodiment, the source select transistors of the cell strings arranged in the same row (+X direction) are connected to the source select line extending in the row direction. Source select transistors of cell strings arranged in different rows are connected to different source select lines. The source select transistors of the cell strings CS11 to CS1m arranged in the first row are connected to the first source select line SSL1 . The source select transistors of the cell strings CS21 to CS2m arranged in the second row are connected to the second source select line SSL2 .

The source-side dummy memory cell SDC of each cell string is connected between the source select transistor SST and the memory cells NMC1 to NMCp. In an embodiment, gates of the source-side dummy memory cells having the same height may be connected to one source-side dummy word line SDWL.

The first to nth memory cells NMC1 to NMCn of each cell string are connected between the source-side dummy memory cell SDC and the drain-side dummy memory cell DDC.

The first to nth memory cells NMC1 to NMCn may be divided into first to pth memory cells NMC1 to NMCp and p+1 to nth memory cells NMCp+1 to NMCn. The first to p-th memory cells NMC1 to NMCp and the p+1 to n-th memory cells NMCp+1 to NMCn are connected through the pipe transistor PT.

The first to p-th memory cells NMC1 to NMCp are connected in series between the source-side dummy memory cell SDC and the pipe transistor PT. The p+1th to nth memory cells NMCp+1 to NMCn are connected in series between the pipe transistor PT and the drain-side dummy memory cell DDC. Gates of the first to nth memory cells NMC1 to NMCn are respectively connected to the first to nth word lines NWL1 to NWLn.

The gate of the pipe transistor PT of each cell string is connected to the pipeline PL.

The drain-side dummy memory cell DDC of each cell string is connected between the drain select transistor DST and the memory cells NMCp+1 to NMCn. In an embodiment, gates of the drain-side dummy memory cells having the same height may be connected to one drain-side dummy word line DDWL.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the drain-side dummy memory cell DDC. The drain select transistors of the cell strings arranged in the same row are connected to a drain select line extending in the row direction. Drain select transistors of cell strings arranged in different rows are connected to different drain select lines. Drain select transistors of the cell strings CS11 to CS1m arranged in the first row are connected to the first drain select line DSL1. Drain select transistors of the cell strings CS21 to CS2m arranged in the second row are connected to the second drain select line DSL2.

Cell strings arranged in the column (+Y direction) direction are connected to bit lines extending in the column direction. The cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the m-th column are connected to the m-th bit line BLm. That is, the cell strings CS1x and CS2x of the x-th column are connected to the x-th bit line BLx (x is an integer greater than or equal to 1 and less than or equal to m).

Data may be stored in the first to nth memory cells NMC1 to NMCn through the first to mth bit lines BL1 to BLm. Data stored in the first to n-th memory cells NMC1 to NMCn may be read through the first to m-th bit lines BL1 to BLm. Data is not stored in the dummy memory cells SDC and DDC.

Unlike FIG. 4 , even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. Even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction are respectively connected to the even bit lines, and among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction, The odd-numbered cell strings may be respectively connected to odd bit lines.

FIG. 5 is a circuit diagram illustrating another embodiment BLK1' of any one of the memory blocks BLK1 to BLKz of FIG. 3 .

Referring to FIG. 5 , the first memory block BLK1' includes a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each cell string includes at least one source select transistor SST, at least one source-side dummy memory cell SDC, first to n-th memory cells NMC1 to NMCn, and at least one drain-side dummy memory cell DDC. ), and at least one drain select transistor DST.

Each of the selection transistors SST and DST, the dummy memory cells SDC and DDC, and the memory cells NMC1 to NMCn may have a similar structure. In an embodiment, each of the selection transistors SST and DST, the dummy memory cells SDC and DDC, and the memory cells NMC1 to NMCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer.

In each cell string, the source select transistor SST, the source-side dummy memory cell SDC, the first to n-th memory cells NMC1 to NMCn, the drain-side dummy memory cell DDC, and the drain select transistor DST are The memory blocks BLK1' are sequentially stacked in a direction crossing the lower substrate (not shown), that is, in the +Z direction.

A hole may be provided through the structures disposed between the bit lines BL1 to BLm and a substrate (not shown) under the memory block BLK1 in a direction opposite to the +Z direction, and a channel layer may be formed in the formed hole. have. Such a hole may be understood to correspond to one cell string. The channel layer formed in the hole may serve as channel layers of the selection transistors SST and DST, the dummy memory cells SDC and DDC, and the memory cells NMC1 to NMCn included in one cell string.

In this case, the width of each of the holes decreases as they are adjacent to the substrate due to process characteristics. For example, when the structures of the memory block BLK1 are etched from the top toward the substrate to form holes, the width of each hole may decrease as it approaches the substrate. When the channel layer is formed inside the hole, the channel layer corresponding to each of the memory cells NMC1 to NMCn of the cell string may have a diameter corresponding to the width of the hole. Accordingly, characteristics of the memory cells NMC1 to NMCn included in the cell string may be different.

Meanwhile, the source select transistor SST of each cell string is connected between the common source line CSL and the source-side dummy memory cell SDC. The source of the source select transistor SST is commonly connected to the common source line CSL.

In an embodiment, the source select transistors of the cell strings arranged in the same row (+X direction) are connected to the same source select line. Source select transistors of cell strings arranged in different rows are connected to different source select lines. Source select transistors of the cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. Source select transistors of the cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2.

The source-side dummy memory cell SDC of each cell string is connected between the source select transistor SST and the memory cells NMC1 to NMCn. In an embodiment, source-side dummy memory cells having the same height may be connected to the same source-side dummy word line SDWL.

In each cell string, the first to nth memory cells NMC1 to NMCn are connected in series between the source-side dummy memory cell SDC and the drain-side dummy memory cell DDC. In the cell strings CS11' to CS1m' and CS21' to CS2m', memory cells of the same height are connected to the same word line. The first to nth memory cells NMC1 to NMCn are respectively connected to the first to nth word lines NWL1 to NWLn.

The drain-side dummy memory cell DDC of each cell string is connected between the memory cells NMC1 to NMCn and the drain select transistor DST. In an embodiment, drain-side dummy memory cells having the same height may be connected to the same source-side dummy word line DDWL.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the drain-side dummy memory cell DDC. Drain select transistors of the cell strings CS11' to CS1m' arranged in the first row are connected to the first drain select line DSL1. Drain select transistors of the cell strings CS21' to CS2m' arranged in the second row are connected to the second drain select line DSL2.

As a result, except that the pipe transistor PT is excluded from each cell string, the memory block BLK1 ′ of FIG. 5 has an equivalent circuit similar to that of the memory block BLK1 of FIG. 4 .

Hereinafter, for convenience of description, an embodiment of the present invention will be described with reference to the memory block BLK1 of FIG. 4 .

6 is a block diagram conceptually illustrating pages included in the memory block BLK1 of FIG. 4 . In FIG. 6 , it is assumed that each cell string includes six memory cells for convenience of description.

4 and 6 , the memory block BLK1 includes a plurality of pages P1_1 to P1_6 and P2_1 to P2_6 . Among the cell strings (eg, CS11 to CS1m) arranged in the same row (eg, the first row), memory cells connected to the same word line (eg, NWL1 ) constitute one page. Since m cell strings are arranged in the row direction (ie, the +X direction) in the memory block BLK1 , one page includes m memory cells.

Cell strings arranged in the same row are included in one cell string group CG. Since each cell string includes 6 memory cells, 6 pages are included in one cell string group CG. The first to sixth pages P1_1 to P1_6 of the first row constitute a first cell string group, and the first to sixth pages P2_1 to P2_6 of the second row constitute a second cell string group. do.

7 is a flowchart illustrating a test operation of the semiconductor memory device 50 according to an embodiment of the present invention.

2, 6, and 7 , in step S110 , the peripheral circuit 110 performs program operations on the pages P1_1 to P1_6 and P2_1 to P2_6 of the selected memory block using a verification voltage, respectively. . Each of the program operations may be performed according to an Incremental Step Pulse Program (ISPP) method. When the program operations are completed, the memory cells of the pages P1_1 to P1_6 and P2_1 to P2_6 may have threshold voltages higher than the verify voltage.

Before program operations, threshold voltages of memory cells of the selected memory block may be distributed in a relatively wide voltage range. This may be due to different characteristics of the memory cells NMC1 to NMCn for each word line. It is assumed that an erase operation is performed on the memory cells of the selected memory block before the program operations. The erase operation is performed in units of memory blocks. The erase operation lowers the threshold voltages of the memory cells by transmitting an erase pulse in common to the channel layers of the cell strings, and a common application of the erase verification voltage (refer to Vev of FIG. 10 ) to the word lines to reduce the threshold voltages of the memory cells. and determining whether the voltages are lower than the erase verification voltage Vev. By repeatedly performing these operations, the threshold voltages of the memory cells are lower than the erase verification voltage Vev. The above operations may be repeatedly performed until the threshold voltages of all memory cells in the memory block become lower than the erase verification voltage Vev. Due to the different characteristics of the memory cells NMC1 to NMCn for each word line, voltage distributions of the pages P1_1 to P1_6 and P2_1 to P2_6 may have different voltage ranges. For example, the memory cells of the word line adjacent to the substrate are less affected by the erase pulse because the length (diameter) of their channel layers is short, and thus may have a relatively high voltage distribution (see E4 of FIG. 10 ). ). For example, the memory cells of the word line adjacent to the common source line CSL are greatly affected by the erase pulse because the length (diameter) of the channel layers thereof is long, and thus may have a relatively low voltage distribution ( See E1 in FIG. 10).

A program operation for each page is performed according to the ISPP method. Program operations are performed in units of pages. The program is repeatedly performed until the memory cells of each page become higher than the verify voltage. After the program operation, the voltage distribution of each page is higher than the verification voltage and falls within a narrow voltage range.

In step S120 , the peripheral circuit 110 applies at least one program pulse to the pages. The high voltage program pulse generated by the voltage generator 130 may be applied to the word lines NWL1 to NWLn through the address decoder 120 . Accordingly, the threshold voltages of the memory cells will increase. The voltage distribution of each page will rise. The voltage distribution of the page containing the slow cells will rise slightly.

As a result, a page containing slow cells will have a different voltage distribution than other pages.

In step S130, a voltage higher than the verification voltage by a predetermined voltage is set as the reference test voltage. Control logic 160 will set voltage generator 130 to generate a reference test voltage.

In operation S140 , reads using the reference test voltage are performed on the pages PG1_1 to PG1_6 and PG2_1 to PG2_6 to detect a defective page among the pages PG1_1 to PG1_6 and PG2_1 to PG2_6. The reference test voltage generated by the voltage generator 130 is applied to each page through the address decoder 120 to perform each read. It may be determined whether a defective page exists among the pages PG1_1 to PG1_6 and PG2_1 to PG2_6 based on the read page data. As reads are sequentially performed on the first to sixth pages PG1_1 to PG1_6 of the first cell string group, it may be determined whether a defective page exists among the first to sixth pages PG1_1 to PG1_6. . Thereafter, as reads are sequentially performed on the first to sixth pages PG2_1 to PG2_6 of the second cell string group, it can be determined whether a defective page exists among the first to sixth pages PG2_1 to PG2_6. have.

In step S150, an area corresponding to a defective page is processed as a bad area. In an embodiment, the control logic 160 may define a memory block including a defective page as a bad area. The bad area will be replaced with a redundancy memory block among the plurality of memory blocks BLK1 to BLKz. In an embodiment, the control logic 160 may define a defective page as a bad area. In this case, the bad area will be replaced with a redundancy page among pages included in the corresponding memory block.

According to an embodiment of the present invention, after program operations according to the ISPP method are performed on the pages P1_1 to P1_6 and P2_1 to P2_6 of the selected memory block, at least one of the pages P1_1 to P1_6 and P2_1 to P2_6 A program pulse of n is applied. Accordingly, the page including the slow cells will have a voltage distribution distinguishable from other pages. Thereafter, reads are performed on the pages P1_1 to P1_6 and P2_1 to P2_6 to detect a defective page. Accordingly, the detection of the defective page can be efficiently performed. Accordingly, the semiconductor memory device 50 having improved reliability is provided.

8 is a flowchart illustrating program operations on pages of one cell string group (CG, see FIG. 6 ) of a selected memory block. The embodiment of FIG. 8 will be described with reference to program operations on pages P1_1 to P1_6 of the first cell string group of the selected memory block. Program operations for the pages P2_1 to P2_6 of the second cell string group are also described as in FIG. 8 .

4 and 8 , in step S111 , a program for the kth page among pages P1_1 to P1_6 is performed. In this case, k may be an integer greater than or equal to 1 and less than or equal to 6.

In an embodiment, a turn-off voltage (eg, a ground voltage) is applied to the source selection lines SSL1 and SSL2 of the selected memory block so that the cell strings CS11 to CS1m and CS21 to CS2m are connected to the common source line CSL. ) will be electrically isolated from A turn-off voltage may be applied to an unselected drain select line among the drain select lines DSL1 and DSL2 . The drain select transistors connected to the unselected drain select line are turned off, and the corresponding cell strings are electrically isolated from the bit lines BL1 to BLm. A turn-on voltage (eg, a power supply voltage) may be applied to a selected drain select line among the drain select lines DSL1 and DSL2 . Accordingly, cell strings connected to the selected drain select line are determined as the selected cell strings. The selected cell strings are cell strings including the kth page.

A high-voltage program voltage is applied to the k-th word line connected to the k-th page. Each of the memory cells of the k-th page is programmed or prohibited according to data transmitted through a corresponding bit line. When a program allowable voltage (eg, a ground voltage) is applied to the bit line, the corresponding drain select transistor is turned on according to the power supply voltage of the selected drain select line and receives the program allowable voltage from the bit line of the corresponding cell string. The program allowable voltage is transferred to the memory cell of the kth page. The threshold voltage of the memory cell of the k-th page increases due to a difference between the program allowable voltage and the program voltage of the k-th word line. When a program prohibition voltage (eg, a power supply voltage) is applied to the bit line, the corresponding drain select transistor is turned off despite the power supply voltage being applied to the selected drain select line, and the corresponding cell string is electrically isolated from the bit line. That is, the cell string is floated separately from the bit line and the common source line. When the program voltage is applied to the k-th word line, the voltage of the channel layer of the corresponding cell string is boosted. Since the difference between the boosted voltage of the channel layer and the program voltage is not high, the threshold voltage of the memory cell of the kth page does not increase.

The control logic 160 may control the page buffers PB1 to PBm to bias the bit lines BL1 to BLm with a program allowable voltage. Accordingly, the threshold voltages of the k-th page memory cells will increase during programming.

In step S112 , threshold voltages of the kth page memory cells are verified using the verification voltage.

In an embodiment, a turn-on voltage may be applied to the source select line and the drain select line corresponding to the selected cell strings. A turn-off voltage is applied to the source select line and the drain select line corresponding to the unselected cell strings. The selected cell strings may be electrically connected to the bit lines BL1 to BLm and the common source line CSL. The unselected cell strings may be electrically separated from the bit lines BL1 to BLm and the common source line CSL.

A verification voltage is applied to the k-th word line. A high-voltage pass voltage is applied to the remaining word lines. Memory cells connected to the remaining word lines will be turned on regardless of their threshold voltages. The memory cells of the kth page are turned on or off according to their threshold voltages. The page buffers PB1 to PBm may verify threshold voltages of memory cells of the kth page by sensing voltages or currents of the bit lines BL1 to BLm. When the threshold voltages of the memory cells are lower than or equal to the verification voltage, the logic value “1” may be read. When the threshold voltages of the memory cells are higher than the verify voltage, a logic value “0” may be read. The read page data is stored in the page buffers PB1 to PBm. The page buffers PB1 to PBm transmit page data to the detector 170 .

In step S113, it is determined whether the program result is a pass. The detector 170 may detect the number of data bits having a logical value of “1” among the page data. The control logic 160 may determine the result of the program as fail when a data bit having a logic value of “1” exists among the page data. If not, the control logic 160 may determine the result of the program as a pass. When the result of the program is fail, step S111 is re-performed. In step S111 , the page buffer storing the data bit of the logical value “1” among the page buffers PB1 to PBm will bias the corresponding bit line to the program allowable voltage. Among the page buffers PB1 to PBm, a page buffer storing a data bit having a logical value of “0” will bias a corresponding bit line with a program inhibit voltage. That is, a memory cell having a threshold voltage lower than or equal to the verification voltage may be programmed, and a memory cell having a threshold voltage higher than the verification voltage may be inhibited from being programmed.

The program operation for the k-th page may include steps S111 to S113. As steps S111 to S113 are repeatedly performed until the program result is a pass, the threshold voltages of the memory cells of the kth page may be higher than the verification voltage but within a narrow voltage range.

In step S114 , it is determined whether the kth page is the last page among the pages P1_1 to P1_6 , and if not, step S115 is performed. That is, the program operation will be performed on the next page.

9 is a timing diagram illustrating program pulses Vpgm1 to VpgmQ applied during the program operation in step S110 of FIG. 8 and an additional program pulse Vadt applied in step S120 of FIG. 8 .

During the program operation, the program pulse is repeatedly applied to the word line of the selected page. First, the first program pulse Vpgm1 will be applied. During the verification, the verification voltage Vvrf is applied to the word line of the selected page. When the result of the program is fail, the second program pulse Vpgm2 higher than the first program pulse Vpgm1 by the first step voltage Vstep1 is applied. During the verification, the verification voltage Vvrf is applied. Until the result of the program is a pass, a plurality of incremental step pulses Vpgm1 to VpgmQ may be applied. Each of the plurality of program pulses Vpgm1 to VpgmQ is higher than the previous program pulse by the first step voltage Vstep1. That is, the program operation may be performed in an incremental step pulse program (ISPP) method.

It will be understood that the number of times the program pulses Vpgm1 to VpgmQ are applied may be different for each page. For example, a fairly large number of program pulses Vpgm1 to VpgmQ may be applied during a program operation on a page including slow cells. The number of times the program pulses Vpgm1 to VpgmQ are applied may be different between pages including normal cells.

After program operations on the pages P1_1 to P1_6 and P2_1 to P2_6 of the selected memory block are completed, an additional program pulse Vadt is applied. The additional program pulse Vadt may be higher than the highest program pulse VpgmQ among program pulses applied in program operations for the pages P1_1 to P1_6 and P2_1 to P2_6 by the second step voltage Vstep2. . As an embodiment, the second step voltage Vstep2 may be higher than the first step voltage Vstep1 . As an embodiment, the second step voltage Vstep2 may be the same as the first step voltage Vstep1 .

10 is a graph showing changes in voltage distributions of pages P1_1 to P1_6 and P2_1 to P2_6 of a selected memory block in steps S110 and S120 of FIG. 7 .

Referring to FIG. 10 , before operation S110 is performed, pages P1_1 to P1_6 and P2_1 to P2_6 have a plurality of erase distributions E1 to E4 . Each word line may have different erase distributions E1 to E4 according to characteristics of the memory cells NMC1 to NMCn. For convenience of explanation, only four erase distributions E1 to E4 are shown in FIG. 10 . Some of the pages P1_1 to P1_6 and P2_1 to P2_6 may have a first erase distribution E1 . Other pages of the pages P1_1 to P1_6 and P2_1 to P2_6 may have the second erase distribution E2 . Still other partial pages among the pages P1_1 to P1_6 and P2_1 to P2_6 may have a third erase distribution E3 . Some of the pages P1_1 to P1_6 and P2_1 to P2_6 may have a fourth erase distribution E4 . The erase distributions E1 to E4 may have lower voltage ranges than the erase verification voltage Vev.

When step S110 is performed, the pages P1_1 to P1_6 and P2_1 to P2_6 have first voltage distributions D1. The first voltage distributions D1 may be higher than the verification voltage Vvrf but fall within a narrow voltage range.

When step S120 is performed, the threshold voltages of the pages P1_1 to P1_6 and P2_1 to P2_6 may increase to have the second voltage distributions D2 or the third voltage distribution D3 . Most pages will have similar voltage distributions D2. On the other hand, the page including the slow cells will have a third voltage distribution D3. For example, due to a defect in a word line, the corresponding word line may not normally transmit a program pulse. The memory cells of that word line will form a wide voltage range.

The reference test voltage Vtst1 may be set near a left tail of the second voltage distributions D2 as shown in FIG. 10 . The reference test voltage Vtst1 may be higher than the verification voltage Vvrf by the first voltage difference dV1 . As an embodiment, the first voltage difference dV1 may be the same as the second step voltage Vstep2 (refer to FIG. 9 ).

Thereafter, as described in step S140 of FIG. 7 , readings of pages of the selected memory block may be performed using the reference test voltage Vtst1. In each of those reads, a data bit having a logical value of “1” among the page data (or comparison data, see FIGS. 13 and 15) is defined as a fail bit, and a data bit having a logical value of “0” is defined as a pass bit. will be. Accordingly, memory cells whose threshold voltage does not rise as much as desired may be detected in step S120 .

11 is a graph illustrating another example of a change in voltage distributions of pages P1_1 to P1_6 and P2_1 to P2_6 of a selected memory block in steps S110 and S120 of FIG. 7 .

Referring to FIG. 11 , when step S110 is performed, pages P1_1 to P1_6 and P2_1 to P2_6 have first voltage distributions D1 .

When step S120 is performed, the threshold voltages of the pages P1_1 to P1_6 and P2_1 to P2_6 increase.

A specific page may have a relatively high voltage distribution D4. Corresponding memory cells are fast cells, and the fast cells have high threshold voltages despite application of the same program pulse. The fourth voltage distribution D4 has a higher voltage range compared to the voltage distributions D2 of normal pages. It will be appreciated that fast cells may appear due to a variety of causes. For example, the corresponding memory cells may be sensitively affected by a program pulse due to an error during processing of the semiconductor memory device.

Fast cells degrade the reliability of the semiconductor memory device. During programming, fast cells may have excessively elevated threshold voltages even when a small number of program pulses are applied. Excessively raised threshold voltages reduce the read margin.

The reference test voltage Vtst2 may be set to detect a page including fast cells as a defective page. The reference test voltage Vtst2 may be higher than the verification voltage Vvrf by the second voltage difference dV2. The second voltage difference dV2 is higher than the first voltage difference dV1 .

Thereafter, as described in step S140 of FIG. 7 , readings of pages of the selected memory block may be performed using the reference test voltage Vtst2. In each of those reads, a data bit having a logical value of “0” among the page data (or comparison data, see FIGS. 13 and 15) is defined as a fail bit, and a data bit having a logical value of “1” is defined as a pass bit. will be. Accordingly, memory cells with excessively increased threshold voltages may be detected in step S120 .

Hereinafter, an embodiment of the present invention will be described with a focus on a method of detecting a defective page corresponding to the third voltage distribution D3 of FIG. 10 to avoid overlapping description.

12 is a flowchart illustrating a method of determining whether a defective page exists among pages of one cell string group CG (refer to FIG. 6 ) of a selected memory block. The exemplary embodiment of FIG. 12 will be described with reference to a method of detecting a defective page among the pages P1_1 to P1_6 of the first cell string group. Detecting a defective page among the pages P2_1 to P2_6 of the second cell string group will be described as in FIG. 12 .

6 and 12 , in step S141 , an x-th page (x is a natural number less than or equal to 6) among pages P1_1 to P1_6 is read to generate x-th page data. The reference test voltage is applied to the corresponding word line to read the data of the memory cells of the x-th page. The read x-th page data is stored in the first to n-th page buffers PB1 to PBm (refer to FIG. 2 ).

In step S142, it is determined whether the number of fail bits in the x-th page data is greater than a reference value. Among the data bits of the x-th page data, the number of data bits having a logical value "1" (ie, fail bit) may be determined. The x-th page data is provided to the detector 170 from the first to m-th page buffers PB1 to PBm, and the detector 170 determines the number of fail bits included in the x-th page data. The determination result will be transmitted to the control logic 160 (refer to FIG. 2) as an error value (ER, see FIG. 2).

As another embodiment, when a defective page corresponding to the fourth voltage distribution D4 of FIG. 11 is detected, the number of data bits having a logical value of “0” (that is, a fail bit) among data bits of the x-th page data is determined. will be The detector 170 receives the x-th page data from the first to n-th page buffers PB1 to PBm, and determines the number of data bits having a logical value of “0” among the x-th page data.

In step S143, when the error value ER is greater than the reference value, the x-th page may be determined as a defective page. In this case, the reference value may be predetermined. When the error value ER is less than or equal to the reference value, it may mean that the threshold voltages of the memory cells of the xth page normally rise during programming. When the error value ER is greater than the reference value, it may mean that the threshold voltages of the memory cells of the xth page do not rise smoothly during programming. When the threshold voltages of the corresponding memory cells are not smoothly increased, it may be understood that the program pulse is not normally transmitted to the corresponding memory cells due to, for example, a defect in the x-th word line WLx.

As another embodiment, when a defective page corresponding to the fourth voltage distribution D4 of FIG. 11 is detected, the reference value may be set as a different value. In this case, when the error value ER is less than or equal to the reference value, it may mean that the threshold voltages of the memory cells of the xth page normally rise during programming. When the error value E is greater than the reference value, it may mean that the threshold voltages of the memory cells of the x-th page are excessively increased during programming. Excessive increase in threshold voltages of the corresponding memory cells may be understood as that the corresponding memory cells are sensitively affected by a program pulse due to an error during a process of the semiconductor memory device.

Thereafter, the memory block including the defective page may be treated as a bad area. For example, the bad area may be replaced with a redundancy memory block among the plurality of memory blocks BLK1 to BLKz. When data corresponding to the bad area is received from the outside, the data may be addressed to the redundancy memory block.

13 is a flowchart illustrating another embodiment of a method of determining whether a defective page exists among pages of one cell string group CG (refer to FIG. 6 ) of a selected memory block. The embodiment of FIG. 13 will be described with reference to a method of detecting a defective page among the pages P1_1 to P1_6 of the first cell string group. Detecting a defective page among the pages P2_1 to P2_6 of the second cell string group will be described as in FIG. 13 .

Referring to FIGS. 4 and 13 , in step S200 , reads are performed on the xth and x+1th pages (x is a natural number less than or equal to 6) among the pages P1_1 to P1_6 so that the xth and xth pages are read. Generates x+1 page data.

In step S201, an OR operation is performed on the data bits of the x-th page data and the data bits of the x+1-th page data to generate a first comparison page. Each of the data bits of the first comparison page has a logical value of “1” when at least one of the corresponding data bit of the x-th page data and the corresponding data bit of the x+1-th page data is a logical value “1” (ie, a fail bit). " will have

As another embodiment, when a defective page corresponding to the fourth voltage distribution D4 of FIG. 11 is detected, an OR operation is performed on the data bits of the x-th page data and the data bits of the x+1-th page data. can be performed. Each of the calculated data bits will have a logical value "0" when at least one of the corresponding data bit of the x-th page data and the corresponding data bit of the x+1-th page data is the logical value "0" (ie, the fail bit). .

In step S202, the number of fail bits of the first comparison page is determined, and a first error value is generated according to the determined number of fail bits. The detector 170 will receive the first comparison page, and determine the number of fail bits included in the first comparison page. The determined number of fail bits is transmitted to the control logic 160 as a first error value (refer to ER of FIG. 2 ).

In step S203, reading of the next page (that is, the x+2th page) is performed to generate x+2th page data.

In step S204, an OR operation is performed on the data bits of the x+1th page data and the data bits of the x+2th page data to generate a second comparison page. Each of the data bits of the second comparison page has a logical value "when at least one of the corresponding data bit of the x+1th page data and the corresponding data bit of the x+2th page data is a logical value "1" (ie, a fail bit). will have 1".

As another embodiment, when a defective page corresponding to the fourth voltage distribution D4 of FIG. 11 is detected, the data bits of the x+1th page data and the data bits of the x+2th page data are logically multiplied. The operation will be performed. Among the calculated data bits, a data bit having a logical value of “0” may be a fail bit.

In step S205, the number of fail bits of the second comparison page is determined, and a second error value is generated according to the determined number of fail bits. The detector 170 receives the second comparison page, and sends the number of fail bits in the second comparison page to the control logic 160 as a second error value (see ER in FIG. 2 ).

In step S206, the second error value is compared with the first error value to detect whether the x+2th page is a defective page.

As an embodiment, the control logic 160 may calculate an average value by dividing each received error value by two. The calculated average value may be understood as indicating an average value of the number of fail bits of the corresponding two page data. The first average value corresponding to the first error value may mean an average value of the number of fail bits included in the xth page data and the x+1th page data. The second average value corresponding to the second error value may mean an average value of the number of fail bits included in the x+1th page data and the x+2th page data. Thereafter, the control logic 160 may detect whether the x+2 th page is a defective page by comparing the second average value with the first average value. As an embodiment, when the second average value is greater than an integer multiple (eg, 4 times) of the first average value, the x+2 th page may be determined as a defective page. As a result, when the second error value is greater than an integer multiple (eg, 4 times) than the first error value, the x+2th page will be determined as a defective page. As another embodiment, when the second error value is greater than the first error value by a predetermined value, the x+2th page may be determined as a defective page.

Accordingly, a defective page may be detected based on a change rate with respect to the number of fail bits of consecutively arranged pages in one memory block. More specifically, the current page will be determined to be a defective page when the current page (eg, the X+2th page) contains excessively more fail bits than the previous page (eg, the X+1th page). . When the current page contains slightly more fail bits than the previous page, the current page may not be determined as a defective page. The fact that the current page includes slightly more fail bits than the previous page may mean that it is due to the characteristics of memory cells for each word line, not a defect in the word line. When the current page includes excessively more fail bits than the previous page, it may mean that memory cells are not normally programmed due to a defect in a word line. According to an embodiment of the present invention, by determining a current page as a defective page based on a change rate with respect to the number of fail bits of consecutively arranged pages, an unintentional generation of a bad area can be suppressed.

It is assumed that a defective page is detected according to the embodiment of FIG. 12 . The number of fail bits included in each page is compared with a reference value, and the corresponding page is selected as a defective page according to the comparison result. Since generation of comparison data and operations on two error values (a first error value and a second error value) are not performed, a defective page may be detected at a high speed. On the other hand, even when the corresponding page includes slightly more fail bits than the reference value, the corresponding page may be determined as a defective page. For example, the first page may be determined as a defective page even if it is determined that the first page includes slightly more fail bits than the reference value. Even if it is determined that the sixth page includes slightly fewer fail bits than the reference value, the sixth page may not be determined as a defective page. Such a decision can create a bad area by defining a normal page as a defective page.

14 is a block diagram illustrating one embodiment of the page buffers PB1 to PBm of FIG. 2 .

Referring to FIG. 14 , the first page buffer PB1 includes a sensing transistor ST, a precharge circuit 210 , a latch circuit 220 , and a switching circuit 230 .

The sensing transistor ST is connected between the first bit line BL1 and the sense node SO. The sensing transistor ST is turned on in response to the sensing signal SES from the control logic 160 (refer to FIG. 2 ).

The precharge circuit 210 is connected to the sense node SO, and is connected to the first bit line BL1 through the sensing transistor ST. The precharge circuit 210 precharges the first bit line BL1 through the sensing transistor ST in response to the control of the control logic 160 .

The latch circuit 220 is connected to the sense node SO. The latch circuit 220 includes a plurality of latch units LAT1 to LAT3. Each of the first to third latch units LAT1 to LAT3 may store one data bit. Data read from the memory cell through the first bit line BL1 is stored in the first latch unit LAT1. The first to third latches LAT1 to LAT3 may exchange data in response to the control of the control logic 160 .

The first to third latch units LAT1 to LAT3 are respectively connected to the switching circuit 230 through the first to third nodes AN to CN. The first to third latch units LAT1 to LAT3 are connected to the data input/output circuit 150 and the detector 170 through the switching circuit 230 .

The latch circuit 220 may further include additional transistors (not shown) in addition to the plurality of latch units LAT1 to LAT3 . It will be understood that an OR operation or an OR operation may be performed on the data bits stored in the first to third latches LAT1 to LAT3 by using these transistors. The first and second comparison pages of FIG. 13 may be generated in the page buffers PB1 to PBm using these transistors.

15 is a diagram illustrating an embodiment for generating first and second comparison pages of FIG. 13 .

2 and 15 , in step S300 , the x-th page is read and the x-th page data is stored in the first latches (LATs1, see LAT1 of FIG. 14 ) of the page buffers PB1 to PBm. is read In step S301 , the x-th page data is transmitted from the first latches LATs1 to the second latches LATs2 (refer to LAT2 of FIG. 14 ) of the page buffers PB1 to PBm. For example, data stored in the first latch LAT1 in each page buffer may be transmitted to the second latch LAT2 through the sense node SO.

In step S302 , the x+1th page is read to read the x+1th page data into the first latches LATs1 .

In step S303 , an OR operation is performed on the x+1th page data stored in the first latches LATs1 and the xth page data stored in the second latches LATs2 . In step S304 , the first comparison page according to the OR operation is stored in third latches LATs3 (refer to LAT3 of FIG. 14 ) of the page buffers PB1 to PBm.

In step S305 , the first comparison page is output to the detector 170 from the third latches LATs3 . Detector 170 will detect the number of fail bits in the first comparison page.

In step S306 , the x+1th page data remaining in the first latches LATs1 is transmitted to the second latches LATs2 . Thereafter, in step S307 , the x+2th page is read, and the x+2th page data is read into the first latches LATs1 .

In operation S308 , an OR operation is performed on the x+2th page data stored in the first latches LATs1 and the x+1th page data stored in the second latches LATs2 . In step S309 , the second comparison page according to the OR operation may be stored in the third latches LATs3 .

In step S310 , the second comparison page is output to the detector 170 from the third latches LATs3 . Detector 170 will detect the number of fail bits in the second comparison page.

According to the embodiment of FIG. 15 , comparison is performed using a plurality of latches LATs1 , LATs2 , and LATs3 in the page buffers PB1 to PBm without a separate configuration in the semiconductor memory device 50 for storing the comparison page. A page can be created. Accordingly, the area of the semiconductor memory device 50 is saved.

16 is a flowchart illustrating another embodiment of a method of determining whether a defective page exists among pages of one cell string group CG (refer to FIG. 6 ) of a selected memory block. The embodiment of FIG. 16 will be described with reference to a method of detecting a defective page among the pages P1_1 to P1_6 of the first cell string group. Detecting a defective page among the pages P2_1 to P2_6 of the second cell string group will be described as in FIG. 16 .

Referring to FIGS. 2 and 16 , in step S400 , an x-th page among pages P1_1 to P1_6 is read to generate x-th page data. The x-th page data may be provided to the detector 170 from the page buffers PB1 to PBm.

In step S401, the number of fail bits in the x-th page data is detected as a first error value. The detector 170 detects the number of fail bits in the x-th page data, and transmits the detected number of fail bits to the control logic 160 as a first error value (refer to ER of FIG. 2 ).

In step S402 , an x+1th page is read among the pages P1_1 to P1_6 to generate x+1th page data. The x+1th page data may be provided to the detector 170 from the page buffers PB1 to PBm.

In step S403, the number of fail bits in the x+1th page data is detected as a second error value. The detector 170 may transmit the number of fail bits in the x+1th page data to the control logic 160 as a second error value (refer to ER of FIG. 2 ).

In step S404, the second error value is compared with the first error value to determine whether the x+1th page is a defective page. As an embodiment, when the second error value is greater than an integer multiple (eg, 4 times) of the first error value, the control logic 160 may determine the x+1th page as a defective page. As an embodiment, when the second error value is greater than the first error value by a predetermined value, the control logic 160 may determine the x+1th page as a defective page.

Accordingly, a defective page may be detected based on a change rate with respect to the number of fail bits of consecutively arranged pages in one memory block.

According to an embodiment of the present invention, after program operations according to the ISPP method are performed on pages of a selected memory block, at least one program pulse is applied to the pages. Accordingly, the page including the slow cells will have a voltage distribution distinguishable from other pages. Accordingly, the detection of the defective page using the reference test voltage may be efficiently performed. Accordingly, a semiconductor memory device having improved reliability is provided.

In the detailed description of the present invention, although specific embodiments have been described, various changes are possible without departing from the scope and technical spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the claims and equivalents of the claims as well as the claims to be described later.

100: memory cell array
110: peripheral circuit
120: address decoder
130: voltage generator
140: read and write circuit
150: data input/output circuit
160: control logic
170: detector
P1_1 to P1_6, P2_1 to P2_6: first to twelfth pages

Claims (20)

A method of operating a semiconductor memory device including a plurality of pages connected to a plurality of word lines, the method comprising:
performing program operations on the plurality of pages, each of the program operations performing a program on a selected page to increase threshold voltages of memory cells included in the selected page; applying a verification voltage to a word line to verify whether the result of the program is a pass, and repeating the steps of executing and verifying the program until the result of the program is the pass ;
further increasing threshold voltages of memory cells included in the plurality of pages by applying at least one program pulse to the plurality of word lines;
setting a voltage higher than the verification voltage by a predetermined voltage as a reference test voltage; and
and detecting a defective page among the plurality of pages by performing reads on the plurality of pages, respectively, using the reference test voltage. ◈Claim 2 was abandoned when paying the registration fee.◈ The method of claim 1,
The plurality of pages are stacked over a substrate,
Each of the plurality of pages is connected to a corresponding word line at a predetermined height from the substrate. ◈Claim 3 was abandoned when paying the registration fee.◈ The method of claim 1,
The step of detecting the defective page comprises:
detecting first and second page data by reading first and second pages among the plurality of pages;
generating a first comparison page by performing an OR operation on the data bits of the first page data and the data bits of the second page data; and
and generating a first error value according to the number of fail bits of the first comparison page. ◈Claim 4 was abandoned when paying the registration fee.◈ 4. The method of claim 3,
The step of detecting the defective page comprises:
detecting third page data by reading a third page among the plurality of pages;
generating a second comparison page by performing an OR operation on the data bits of the second page data and the data bits of the third page data; and
and generating a second error value according to the number of fail bits of the second comparison page. ◈Claim 5 was abandoned when paying the registration fee.◈ 5. The method of claim 4,
The step of detecting the defective page comprises:
and detecting the third page as the defective page by comparing the second error value with the first error value. ◈Claim 6 was abandoned when paying the registration fee.◈ 5. The method of claim 4,
The step of detecting the defective page comprises:
and detecting the third page as the defective page when the second error value is greater than an integer multiple of the first error value. ◈Claim 7 was abandoned when paying the registration fee.◈ 5. The method of claim 4,
The step of detecting the defective page comprises:
and detecting the third page as the defective page when the second error value is greater than the first error value by a predetermined value. ◈Claim 8 was abandoned when paying the registration fee.◈ The method of claim 1,
The step of detecting the defective page comprises:
detecting first page data by reading a first page among the plurality of pages;
generating a first error value according to the number of fail bits in the first page data;
detecting second page data by reading a second page among the plurality of pages; and
and generating a second error value according to the number of fail bits in the second page data. ◈Claim 9 was abandoned at the time of payment of the registration fee.◈ 9. The method of claim 8,
The step of detecting the defective page comprises:
and detecting the second page as the defective page by comparing the second error value with the first error value. ◈Claim 10 was abandoned when paying the registration fee.◈ The method of claim 1,
The step of detecting the defective page comprises:
generating page data by reading any one of the plurality of pages; and
and detecting a corresponding page as the defective page when the number of fail bits of the page data is greater than a reference value. ◈Claim 11 was abandoned when paying the registration fee.◈ The method of claim 1,
An operation method in which an area corresponding to the defective page is defined as a bad area. A method of operating a semiconductor memory device including a plurality of pages connected to a plurality of word lines, the method comprising:
performing a program operation on each of the plurality of pages according to an incremental step pulse program (ISPP) method using a determined verification voltage;
further providing at least one program pulse to the plurality of pages through the plurality of word lines; and
and detecting a defective page from among the plurality of pages by performing reads on the plurality of pages, respectively, using a reference test voltage that is higher than the verification voltage by a predetermined voltage. ◈Claim 13 was abandoned when paying the registration fee.◈ 13. The method of claim 12,
Memory cells included in the plurality of pages are stacked over a substrate,
Each of the plurality of pages is connected to a corresponding word line at a predetermined height from the substrate. ◈Claim 14 was abandoned at the time of payment of the registration fee.◈ 13. The method of claim 12,
The program operation is performed so that threshold voltages of memory cells included in the plurality of pages rise higher than the verification voltage. a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of pages connected to a plurality of word lines; and
Each program operation is performed on the plurality of pages, a program is performed on a page selected in each of the program operations, and a verification voltage is applied to a word line of the selected page to determine whether the result of the program is a pass a peripheral circuit configured to verify and repeat the program and the verification until the result of the program is the pass;
The peripheral circuit applies at least one program pulse to the plurality of word lines to further increase threshold voltages of memory cells included in the plurality of pages, and thereafter, a reference test voltage higher than the verification voltage by a predetermined voltage. The semiconductor memory device is configured to detect a defective page from among the plurality of pages by performing reads on each of the plurality of pages by using . ◈Claim 16 was abandoned at the time of payment of the registration fee.◈ 16. The method of claim 15,
The plurality of pages are stacked over a substrate,
Each of the plurality of pages is connected to a corresponding word line at a predetermined height from the substrate. ◈Claim 17 was abandoned when paying the registration fee.◈ 16. The method of claim 15,
The peripheral circuit detects first and second page data by performing reads on first and second pages among the plurality of pages, and includes data bits of the first page data and the second page data. A first comparison page is generated by performing an OR operation on the data bits,
and a detector configured to generate a first error value according to the number of fail bits of the first comparison page. ◈Claim 18 was abandoned when paying the registration fee.◈ 18. The method of claim 17,
The peripheral circuit detects third page data by reading a third page among the plurality of pages, and ORs the data bits of the second page data and the data bits of the third page data A second comparison page is generated by performing an operation,
The detector generates a second error value according to the number of fail bits of the second comparison page. ◈Claim 19 was abandoned when paying the registration fee.◈ 19. The method of claim 18,
The peripheral circuit further includes a control logic configured to detect the third page as the defective page by comparing the second error value with the first error value. ◈Claim 20 was abandoned at the time of payment of the registration fee.◈ 16. The method of claim 15,
The region corresponding to the defective page is defined as a bad region.

Images