KR102254255B1 - Device including single wire interface and data processing system having the same - Google Patents

Abstract

The master device capable of communicating with the slave device generates an oversampling clock signal from a single pad and a clock signal that exchanges a command frame including an address and a data frame including data with the slave device through a single wire, The synchronization process of selecting one of the clock phases of the oversampling clock signal, and each bit value included in the data frame transmitted from the slave device is present at the same position as the clock phase selected in the synchronization process. And a processing circuit that performs a sampling process of sampling using a clock phase.

Description

A device including a single wire interface and a data processing system including the device {DEVICE INCLUDING SINGLE WIRE INTERFACE AND DATA PROCESSING SYSTEM HAVING THE SAME}

An embodiment according to the concept of the present invention relates to an integrated circuit, and more particularly, to a master device and a slave device capable of communicating with each other using a single wire interface, and a data processing system including the same.

In telecommunication or computer science, serial communication refers to a process of transmitting data in units of one bit at a time through a communication channel or a computer bus. The serial communication contrasts with parallel communication, which transmits several bits at the same time over a link with several parallel channels. Serial communication is used in all long-haul communications and in most computer networks.

Many communication systems are designed to connect two integrated circuits on the same printed circuit board (PCB). An integrated circuit becomes more expensive the more pins it contains. To reduce the number of pins in the package, many integrated circuits use a serial bus to transfer data when communication speed is not critical. Examples of such low-cost serial buses include serial peripheral interface (SPI) and inter-integrated circuit (I2C).

The SPI bus is a synchronous serial communication interface used in short distance communication, mainly embedded systems. SPI can use 3 pins or 4 pins. Since the SPI uses 3 pins or 4 pins, the number of pins is large, and since there are output drivers and input buffers connected to each of the pins, the price of a chip may increase.

I2C is a multi-master, multi-slave, single-ended, serial computer bus invented by Philips Semiconductor (now NXP Semiconductors). I2C is used to connect low-speed peripherals in motherboards, embedded systems, or mobile phones. I2C has two bidirectional open-drain lines, a serial data line (SDA) pulled up by resistors and a serial clock line (SCL). use. I2C uses a serial clock to transmit serial data to synchronize between two connected devices, so power consumption is large, and operation speed may be slow because the output capacitor is charged using a resistor.

The technical problem to be achieved by the present invention is to reduce the number of pins (or pads) for data transmission between chips to one, thereby reducing the number of pins, and increasing the price competitiveness of the chip as the number of pins decreases. An apparatus capable of supporting a new communication protocol capable of reducing power consumption as the number of is reduced, and a data processing system including the same are provided.

According to an embodiment of the present invention, a master device capable of communicating with a slave device transmits a command frame including an address and a data frame including data through a single wire from one pad to and from the slave device, and a clock signal. A synchronization process of generating an oversampling clock signal and selecting one of the clock phases of the oversampling clock signal, and each bit value included in the data frame transmitted from the slave device are selected during the synchronization process. And a processing circuit that performs a sampling process of sampling by using a clock phase existing at the same position as the clock phase.

Each of the command frame and the data frame includes a start bit value and a stop bit value, and the processing circuit performs the synchronization process on the start bit value.

The processing circuit includes a synchronization detection circuit including at least two flip-flops, and a data processing circuit. The synchronization detection circuit generates clock phase selection signals related to the selected clock phase for each period of the oversampling clock signal using the at least two flip-flops, and the data processing circuit includes the oversampling clock signal Each of the bit values included in the data frame is sampled by using a clock phase associated with the clock phase selection signals at each period of.

According to an embodiment, the oversampling clock signal may be a 4x oversampling clock signal. According to an embodiment, the oversampling clock signal may be a 2x oversampling clock signal.

The single wire does not include a clock line for transmitting the clock signal to the slave device.

The frequency of the clock signal used in the master device is the same as the frequency of the clock signal used in the slave device.

The master device further includes a pull-up resistor for controlling a connection between a voltage supply line and the one pad in response to a pull-up resistance control signal, and an output driver connected to the one pad.

The master device further includes a control circuit for activating the pull-up resistance control signal when a stop bit value included in the command frame is transmitted to the one pad through the output driver.

The master device further includes a frame generator for generating the command frame including a parity bit.

According to an embodiment of the present invention, a slave device capable of communicating with a master device transmits a command frame including an address and a data frame including data through a single wire from one pad to and from the master device and a clock signal. Generating an oversampling clock signal, selecting one of the clock phases of the oversampling clock signal, and sampling each bit value included in the data frame transmitted from the master device using the selected clock phase Includes a processing circuit. The single wire does not include a clock line for transmitting the clock signal.

The slave device further includes a pull-up resistor for controlling a connection between a voltage supply line and the one pad in response to a pull-up resistance control signal, and an output driver connected to the one pad.

According to an embodiment of the present invention, a data processing system includes a master device including one first pad, a slave device including a second pad and a processing circuit connected to the one second pad, and the one A single wire connected between the first pad and the second pad of, and the processing circuit generates an oversampling clock signal from a clock signal, and one of the clock phases of the oversampling clock signal Then, each bit value included in the frame transmitted from the master device is sampled using the selected clock phase.

Since the master device or the slave device according to an embodiment of the present invention includes only one pad connected to a single wire interface, the number of pads is reduced to one.

As the number of pads decreases to one, the number of output drivers driving output data to the pads and the number of input buffers processing input data inputted through the pads can also be reduced, thus reducing the overall die or chip size. There is an effect.

As the number of pads decreases to one, the power consumed by the master device or the slave device is also reduced.

In order to more fully understand the drawings cited in the detailed description of the present invention, a detailed description of each drawing is provided.
1 is a block diagram of a data processing system according to an embodiment of the present invention.
2 is an embodiment of a command frame format for burst operation according to the protocol of the present invention.
3 is an embodiment of a command frame format for random operation according to the protocol of the present invention.
4 is an embodiment of a data frame format according to the protocol of the present invention.
5 is a start field of the frame shown in FIG. 2, 3, or 4 and a description thereof.
6 is a stop field of the frame shown in FIG. 2, 3, or 4 and a description thereof.
7 is a mode field of the frame shown in FIG. 2, 3, or 4 and a description thereof.
8 is a direction field of the frame shown in FIG. 2 or 3 and a description thereof.
9 is a random field of the frame shown in FIG. 2 or 3 and a description thereof.
10 is an address field of the frame shown in FIG. 2 or 3 and a description thereof.
11 is a burst field of the frame shown in FIG. 2 and a description thereof.
12 is a burst length field of the frame shown in FIG. 2 and a description thereof.
13 is a timing diagram of signals for explaining a synchronization process and a sampling process performed using a 4x oversampling clock signal according to an embodiment of the present invention.
14 is a block diagram illustrating an embodiment of a second processing circuit included in the slave device illustrated in FIG. 1.
15 is a block diagram illustrating an embodiment of a synchronization circuit included in the synchronization detection circuit shown in FIG. 14.
FIG. 16 is a state diagram of a finite-state machine (FSM) included in the synchronization detection circuit shown in FIG. 14 and performing a synchronization process using 4x oversampling.
FIG. 17 is a state diagram illustrating a phase count operation of an FSM included in the synchronization detection circuit shown in FIG. 14 and performing a synchronization process using 4x oversampling.
18 is a block diagram illustrating an embodiment of a second processing circuit included in the slave device illustrated in FIG. 1.
FIG. 19 shows an embodiment of a clock generator that generates a 2x oversampling clock signal included in the processing circuit shown in FIG. 18.
FIG. 20 shows an embodiment of a clock generator that generates a 2x oversampling clock signal included in the processing circuit shown in FIG. 18.
21 is a block diagram illustrating an embodiment of a synchronization circuit included in the synchronization detection circuit shown in FIG. 18.
22 is a timing diagram of signals for explaining a synchronization process and a sampling process performed using a 2x oversampling clock signal according to an embodiment of the present invention.
FIG. 23 is a state diagram of an FSM included in the synchronization detection circuit shown in FIG. 18 and performing a synchronization process using 2x oversampling.
FIG. 24 is a diagram illustrating a phase count operation of an FSM included in the synchronization detection circuit shown in FIG. 18 and performing a synchronization process using 2x oversampling.
25 is a timing diagram of signals for explaining a process of controlling a dynamic pull-up resistance included in an apparatus for performing 4x oversampling.
26 is a timing diagram of signals for explaining a process of controlling a dynamic pull-up resistance included in an apparatus for performing 2x oversampling.
27 shows a command frame format and a data frame format according to the protocol of the present invention including a parity bit.
28 is a block diagram of a data processing system including a slave device including a parity enable register and a parity status register.
29 is an embodiment of a frame format according to the protocol of the present invention for explaining a parity enable process.
30 is an embodiment of a frame format according to the protocol of the present invention for explaining a parity disable process.
FIG. 31 is a timing diagram illustrating a process in which the master device shown in FIG. 1 controls the power mode of the slave device shown in FIG. 1.
32 shows a clock gating circuit according to an embodiment of the present invention.
33 shows a timing diagram of the clock gating circuit shown in FIG. 32;
34 is a block diagram of a data processing system according to an embodiment of the present invention.
35 is a block diagram of a data processing system according to an embodiment of the present invention.

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in the present specification are exemplified only for the purpose of describing the embodiments according to the concept of the present invention, and the embodiments according to the concept of the present invention are It may be implemented in various forms and is not limited to the embodiments described herein.

Since the embodiments according to the concept of the present invention can apply various changes and have various forms, the embodiments will be illustrated in the drawings and described in detail herein. However, this is not intended to limit the embodiments according to the concept of the present invention to specific disclosed forms, and includes all changes, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first or second may be used to describe various constituent elements, but the constituent elements should not be limited by the terms. The terms are only for the purpose of distinguishing one component from other components, for example, without departing from the scope of the rights according to the concept of the present invention, the first component may be named as the second component and similarly the second component. The constituent element may also be referred to as a first constituent element.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it is directly connected to or may be connected to the other component, but other components may exist in the middle. It should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle. Other expressions describing the relationship between components, such as "between" and "directly between" or "adjacent to" and "directly adjacent to" should be interpreted as well.

The terms used in the present specification are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as "comprise" or "have" are intended to designate the presence of features, numbers, steps, actions, components, parts, or combinations thereof described herein, but one or more other features. It is to be understood that the presence or addition of elements or numbers, steps, actions, components, parts, or combinations thereof, does not preclude in advance the possibility of the presence or addition.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be construed as having a meaning consistent with the meaning of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in the present specification. Does not.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a data processing system according to an embodiment of the present invention. Referring to FIG. 1, the data processing system 100 includes a master device 200 and a slave device capable of sending and receiving a transmission frame (SPEEDY) defined in an embodiment of the present invention through a single wire 110. 300).

The data processing system 100 may further include a clock source 130 that supplies a clock signal TCLK to the master device 200 and the slave device 300. The single wire 110 does not include a clock line for transmitting the clock signal TCLK. That is, the clock signal TCLK output from the clock source 130 may be transmitted to the slave device 300 through the clock line 111 independent from the single wire 110. The clock source 130 may be implemented as a temperature compensated crystal oscillator (TCXO) or a crystal oscillator, but is not limited thereto.

The clock signal TCLK supplied to the master device 200 is referred to as a "master clock signal", and the clock signal TCLK supplied to the slave device 300 is referred to as a "slave clock signal". That is, the clock source 130 of the master clock signal and the clock source 130 of the slave clock signal may be the same. However, as shown in FIG. 35, the clock source 370 of the master clock signal MCLK and the clock source 370-1 of the slave clock signal TCLK may be different from each other, but each processing circuit 220 and 320 The frequency of the clock signal TCLK supplied to the device must be the same.

For example, the data processing system 100 may be a personal computer (PC) or a mobile computing device. The mobile computing device includes a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, and a digital video camera. ), PMP (portable multimedia player), PND (personal navigation device or portable navigation device), handheld game console, mobile internet device (MID), wearable computer, Internet of Things ( It may be implemented as an internet of things (IoT)) device, an internet of everything (IoE) device, a drone, or an e-book.

The single wire 110 may mean a digital bitstream, that is, a bidirectional serial bus capable of transmitting a sequence of bits.

A protocol defined according to an embodiment of the present invention, that is, a single wire 110 capable of sending and receiving a command frame for transmitting an address and a data frame for transmitting data, is one of the master device 200. It may be connected between the first pad 214 and one second pad 314 of the slave device 300. Here, the frame may include a sequence of bits or symbols as a digital data transmission unit. For example, the single wire 110 may be implemented as an electrical transmission line, for example, a microstrip that may be manufactured using a printed circuit board (PCB) technology, but is not limited thereto.

The master device 200 according to an embodiment of the present invention reduces the number of pads compared to a conventional master device using an inter-integrated circuit (I2C) bus interfacing method or a serial peripheral interface (SPI) bus interfacing method. I can. In addition, the slave device 300 according to an embodiment of the present invention can reduce the number of pads compared to a conventional slave device using the I2C bus interfacing method or the SPI bus interfacing method. Here, the pad may mean a contact pad or a pin, but is not limited thereto.

Unlike the I2C bus interfacing method and the SPI bus interfacing method, the single wire 110 according to an embodiment of the present invention does not include a clock line for transmitting the clock signal TCLK.

When the device 200 or 300 according to an embodiment of the present invention is a die, as the number of pads implemented on the die 200 or 300 decreases, the size of the die 200 or 300 decreases, The power consumed by the die 200 or 300 is also reduced, and the cost of manufacturing the die 200 or 300 is also reduced.

That is, since the die 200 or 300 can be implemented in a smaller silicon area, there is an effect of increasing the price competitiveness of the die 200 or 300. For example, the device 200 or 300 may be implemented as an integrated circuit (IC), a system on chip (SoC), or a package.

The master device 200 may refer to a controller circuit or a processor capable of controlling the slave device 300. For example, the master device 200 is implemented as a baseband modem processor chip, a chip capable of performing the functions of a modem and an application processor (AP) together, an AP, or a mobile AP. It may be, but is not limited thereto.

The slave device 300 includes a radio frequency integrated circuit (RFIC), a connectivity chip, a sensor, a fingerprint recognition chip, a power management IC, and a power supply module. module), a digital display interface chip, a display driver IC, or a touch screen controller, but is not limited thereto.

For example, the RFIC may include at least one connection chip. For example, the connection chip is a chip for mobile communication, a chip for wireless local area network (WLAN) communication, a chip for Bluetooth communication, a chip for global navigation satellite system (GNSS) communication, and a frequency modulation (FM) audio signal/video. A chip for processing a signal, a chip for near field communication (NFC), and/or a chip for Wi-Fi communication may be included, but the present invention is not limited thereto.

The master device 200 includes a first frame generator 210, a first output driver 212, a first pad 214, a first input buffer 216, a first processing circuit 220, and a first control circuit ( 270), and a first pull-up resistor 271.

The first frame generator 210 may generate a command frame for transmitting an address under control of the first control circuit 270. Command frames according to an embodiment of the present invention may be classified into a burst command frame and a random command frame.

2 is an embodiment of a command frame format for burst operation according to the protocol of the present invention. 2, a command frame format (CFFB) for a burst operation includes a plurality of fields (START, MODE, DIR(R/W), RANDOM, ADDRESS, BURST, BURST LENGTH, and STOP). Can include. Functions and descriptions of each field (START, MODE, DIR(R/W), RANDOM, ADDRESS, BURST, BURST LENGTH, and STOP) will be described in detail with reference to FIGS. 5 to 12. The number of bits included in each field (START, MODE, DIR(R/W), RANDOM, ADDRESS, BURST, BURST LENGTH, and STOP) is exemplary, and the technical idea of the present invention is based on each field (START, MODE, It is not limited to the number of bits included in DIR (R/W), RANDOM, ADDRESS, BURST, BURST LENGTH, and STOP). Here, a bit may have any one of two values (eg, 1 (or logic 1) or 0 (or logic 0)). Hereinafter, the value of a bit is referred to as a bit value.

3 is an embodiment of a command frame format for random operation according to the protocol of the present invention. Referring to FIG. 3, a command frame format (CFFR) for random operation may include a plurality of fields (START, MODE, DIR (R/W), RANDOM, ADDRESS, and STOP). Functions and descriptions of each field (START, MODE, DIR(R/W), RANDOM, ADDRESS, and STOP) will be described in detail with reference to FIGS. 5 to 12. The number of bits included in each field (START, MODE, DIR (R/W), RANDOM, ADDRESS, and STOP) is exemplary, and the technical idea of the present invention is based on each field (START, MODE, DIR (R/W) ), RANDOM, ADDRESS, and STOP).

In order to write the first data DATA1 to the slave device 300, the first frame generator 210 may generate a first output frame ODATA1 including the first data DATA1.

4 is an embodiment of a data frame format according to the protocol of the present invention. Referring to FIG. 4, the data frame format DFF may include a plurality of fields (START, MODE, DATA, and STOP). The function and description of each field (START, MODE, DATA, and STOP) will be described in detail with reference to FIGS. 5 to 12. The number of bits included in each field (START, MODE, DATA, and STOP) is exemplary, and the technical idea of the present invention is not limited to the number of bits included in each field (START, MODE, DATA, and STOP). .

For example, the data field DATA may be implemented as 8-bit, 16-bit, 22-bit, or 32-bit, but the number of bits included in the data field DATA may be variously changed according to implementation examples. have.

In response to the first output enable signal OEN1, the first output driver 212 first converts each bit (or each bit value) included in the first output frame ODATA1, for example, a command frame or a data frame. You can drive with the pad 214. The first pad 214 may output the first output frame ODATA1 as a transmission frame SPEEDY through a single wire 110.

The first input buffer 216 buffers the transmission frame SPEEDY output from the slave device 300 and input through the first pad 214, and removes each bit included in the buffered first frame IDATA1. It can be transmitted to the first processing circuit 220. For example, the buffered first frame IDATA1 may be read data read from the slave device 300.

When processing the buffered first frame IDATA1, the first processing circuit 220 generates an oversampling clock signal from the clock signal TCLK, and one of the clock phases of the generated oversampling clock signal. (E.g., in the synchronization process), and for each period of the oversampling clock signal, each bit value included in the buffered first frame IDATA1 is calculated using a clock phase present at the same position as the selected clock phase. Can be sampled.

For example, each sampled bit value may be stored in a memory device (not shown) that can be accessed by the master device 200, but is not limited thereto. The memory device may be implemented inside or outside the master device 200, and the memory device may be implemented as a volatile memory device such as DRAM or a nonvolatile memory device such as a flash-based memory device.

The first control circuit 270 includes a first output enable signal OEN1 that controls enable of the first output driver 212 and a first pull-up resistor that controls the first pull-up resistor 271. An enable signal PEN1 may be generated. The enable/disable timing of the first output enable signal OEN1 and the first pull-up resistor enable signal PEN1 will be described in detail with reference to the timing diagram exemplarily shown in FIGS. 25 and/or 26. Will be.

The first control circuit 270 may include a register 272 that stores control values capable of controlling an activation period of the first pull-up resistance enable signal PEN1. Although the register 272 is shown inside the first control circuit 270 in FIG. 1, the register 272 may be implemented outside the first control circuit 270. The first control circuit 270 may control an activation period of the first pull-up resistance enable signal PEN1 using control values stored in the register 272.

The first pull-up resistor 271 is in response to the first pull-up resistor enable signal PEN1, a first voltage line (or a first voltage node) supplying a first operating voltage VDD1 and a first voltage line. One may be connected or disconnected between the pads 214. For example, when the first pull-up resistor enable signal PEN1 is activated, the first pull-up resistor 271 may be connected between the first voltage line and the first pad 214. However, when the first pull-up resistor enable signal PEN1 is deactivated, the first pull-up resistor 271 may separate the first voltage line from the first pad 214. In this specification, activation may be defined as a transition from a low level (or logic 0) to a high level (or logic 1), and deactivation may be defined as a transition from the high level to the low level, but the opposite is true according to embodiments. May be.

The slave device 300 includes a second frame generator 310, a second output driver 312, a second pad 314, a second input buffer 316, a second processing circuit 320, and a second control circuit ( 370), and a second pull-up resistor 371.

The second frame generator 310 may generate an error bit, a status bit, or a data frame for transmitting data under control of the second control circuit 370.

In order for the slave device 300 to transmit the second data DATA2 to the master device 200, the second frame generator 310 generates a second output frame ODATA2 including the second data DATA2. I can. For example, the second data DATA2 may be read data from the viewpoint of the master device 200, but is not limited thereto.

For example, the second data DATA2 may be data read from a memory device (not shown) of the slave device 300 according to a command frame output from the master device 200. The memory device may be a volatile memory or a nonvolatile memory, and the memory device may be implemented inside or outside the slave device 300, and the memory device may be fixed to the slave device 300. It can be removed from the slave device 300 (removable).

The format of the second output frame ODATA2 may be the same as or similar to the data frame format DFF illustrated in FIG. 4.

The second output driver 312 drives each bit (or each bit value) included in the second output frame ODATA2 to the second pad 314 in response to the second output enable signal OEN2. I can. The second pad 314 may output the second output frame ODATA2 as a transmission frame SPEEDY through a single wire 110.

The second input buffer 316 buffers the transmission frame SPEEDY output from the master device 200 and input through the second pad 314, and removes each bit included in the buffered second frame IDATA2. It can be transmitted to the second processing circuit 320.

The second processing circuit 320 generates an oversampling clock signal from the slave clock signal TCLK, selects one clock phase from among the clock phases of the generated oversampling clock signal, and performs each period of the oversampling clock signal. , Each bit value included in the buffered second frame IDATA2 may be sampled by using the clock phase existing at the same position as the selected clock phase.

When the data sampled by the second processing circuit 320 is data included in the command frame (for example, a write command or a read command), the second processing circuit 320 controls a write operation related to the write command. Signals or read control signals for a read operation related to the read command may be generated.

The second control circuit 370 is a second output enable signal OEN2 that controls enable of the second output driver 312 and a second pull-up resistor that controls the second pull-up resistor 371. An enable signal PEN2 may be generated. The enable/disable timing of the second output enable signal OEN2 and the second pull-up resistor enable signal PEN2 will be described in detail with reference to FIGS. 25 and/or 26.

The second control circuit 370 may include a register 372 that stores control values capable of controlling an activation period of the second pull-up resistance enable signal PEN2. Although the register 372 is shown inside the second control circuit 370 in FIG. 1, the register 372 may be implemented outside the second control circuit 370. The second control circuit 370 may control an activation period of the second pull-up resistor enable signal PEN2 using control values stored in the register 372.

The second pull-up resistor 371 is between the second voltage line and the second pad 314 supplying the second operating voltage VDD2 in response to the second pull-up resistor enable signal PEN2. Can be connected or disconnected. For example, when the second pull-up resistor enable signal PEN2 is activated, the second pull-up resistor 371 may be connected between the second voltage line and the second pad 314. However, when the second pull-up resistor enable signal PEN2 is deactivated, the second pull-up resistor 371 may separate the second voltage line from the second pad 314. For example, the level of the first operating voltage VDD1 and the level of the second operating voltage VDD2 may be the same or different from each other.

The clock source 130 may supply a clock signal TCLK to the master device 200 and the slave device 300. For example, each of the first processing circuit 220 and the second processing circuit 320 may generate an oversampling clock signal using a clock signal TCLK having the same frequency. That is, since the first processing circuit 220 and the second processing circuit 320 each use the clock signal TCLK having the same frequency as the source clock signal, the first processing circuit 220 and the second processing circuit 320 The frequency offset between) may be removed.

5 is a start field of the frame shown in FIG. 2, 3, or 4 and a description thereof. Referring to FIG. 5, the start bit of the start field STRAT is 1-bit, and when the start bit value of the start field START of the transmission frame SPEEDY transitions from "1" to "0", data, For example, it indicates that transmission of a transmission frame (SPEEDY) is started. Here, “1” means a high level or logic “1”, and “0” means a low level or logic “0”.

6 is a stop field of the frame shown in FIG. 2, 3, or 4 and a description thereof. 6, when the stop bit of the stop field (STOP) is 1-bit and the stop bit value of the stop field (STOP) of a transmission frame (SPEEDY) is 1, data, for example, transmission of a transmission frame (SPEEDY) Indicates that this is to be stopped. Further, when the stop bit value of the stop field STOP of the transmission frame SPEEDY maintains "1", it indicates that transmission of data, for example, the transmission frame SPEEDY is stopped. For example, the bit value of the bit immediately preceding the stop bit of the stop field STOP may be "0" or "1".

Although, the case where the oversampling clock signal is 4xCLK is illustrated in FIGS. 5 and 6, this is only exemplary.

7 is a mode field of the frame shown in FIG. 2, 3, or 4 and a description thereof. Referring to FIG. 7, the mode bit of the mode field (MODE) is 1-bit, and the mode bit indicates whether the transmission frame SPEEDY is a command frame for a command phase or a data frame for a data phase. can do. For example, the mode bit value of the mode field (MODE) of the command frame format (CFFB or CFFR) shown in FIG. 2 or 3 may be set to “0”, and the data frame format (DFF) shown in FIG. The mode bit value of the mode field MODE may be set to "1".

8 is a direction field of the frame shown in FIG. 2 or 3 and a description thereof. Referring to FIG. 8, the indication bit of the direction field DIR(R/W) is 1-bit. For example, the value of the indication bit of the direction field (DIR(R/W)) for read operation (READ) may be set to “0”, and the direction field (DIR(R/W)) for write operation (WRITE) The indication bit value of may be set to "1".

For example, if the frame generated by the master device 200 is a command frame and the indication bit value of the direction field (DIR(R/W)) is set to "0", the slave device 300 Conversion can be done. Here, "direction change" may mean an operation change performed by the slave device 300 to transmit a data frame including read data to the master device 200. That is, the slave device 300 may change from a reception mode for receiving a command frame to a transmission mode for transmitting a data frame. As shown in FIGS. 25 and 26, the direction change may be determined according to the levels of each of the output enable signals OEN1 and OEN2.

However, if the frame generated by the master device 200 is a command frame and the indication bit value of the direction field (DIR(R/W)) is set to "1", the slave device 300 Do not perform conversion. That is, the slave device 300 may maintain the receiving mode as it is in order to receive the data frame.

9 is a random field of the frame shown in FIG. 2 or 3 and a description thereof. Referring to FIG. 9, the indication bits of the random field RANDOM are 1-bit, and the indication bits of the random field RANDOM are address bits of the address field ADDRESS (eg, ADDRESS[8:0] in FIG. 10). ) May indicate whether it is a random address or a burst address. The indication bit value of the random field (RANDOM) of the command frame format (CFFB) shown in FIG. 2 may be set to “0”, and the indication of the random field (RANDOM) of the command frame format (CFFR) shown in FIG. 3 The bit value can be set to "1".

10 is an address field of the frame shown in FIG. 2 or 3 and a description thereof. Referring to FIG. 10, address bits of the address field ADDRESS may be 9-bits. For example, when the address bits are 9-bits, the address spaces can support 512 destinations. Although the number of address bits in the address field ADDRESS is shown as 9 in FIG. 10, the number of address bits in the address field ADDRESS may be variously changed according to exemplary embodiments.

11 is a burst field of the frame shown in FIG. 2 and a description thereof. Referring to FIG. 11, indication bits of the burst field BURST are 2-bits, and "00" and "01". Each of "10" and "11" may represent a burst type. For example, "00" represents a fixed-address burst as a FIXED burst type, "01" represents an increasing-address burst as an INCREMENT burst type, and "10" represents an EXTENSION burst. A special command extended as a type is indicated, and "11" indicates infinite data as a stream (STREAM) type, and the master device 200 may use a write command having a large amount of data.

12 is a burst length field of the frame shown in FIG. 2 and a description thereof. Referring to FIG. 12, indication bits ([4:0]) of the burst length BURST LENGTH are 5-bits, and may indicate the number of data transmissions.

13 is a timing diagram of signals for explaining a synchronization process and a sampling process performed using a 4x oversampling clock signal according to an embodiment of the present invention, and FIG. 14 is a second diagram included in the slave device shown in FIG. It is a block diagram showing an embodiment of a processing circuit.

Referring to FIGS. 1 to 14, except for the enable signal generator 327-1 and the mask circuit 327-2, the structure and operation of the second processing circuit 320 of the slave device 300 is a master device ( It is assumed that the structure and operation of the first processing circuit 220 of 200) are the same or similar. 13 and 14 show a 4x oversampling process.

The enable signal generator 327-1 may generate the enable signal EN by using the transmission frame SPEEDY. The mask circuit 327-2 may control transmission of the clock signal TCLK using the enable signal EN. For example, the mask circuit 327-2 may be implemented as an AND gate, but is not limited thereto. That is, when the slave device 300 is in the sleep state, the enable signal generator 327-1 can generate the enable signal EN having a low level, so the mask circuit 327-2 is a clock signal. Transmission of (TCLK) can be blocked. The structure and operation of the enable signal generator 327-1 will be described in detail with reference to FIG. 32.

Although, in FIG. 14, an enable signal generator 327-1 and a mask circuit 327-2 capable of controlling transmission of the clock signal TCLK for low power operation are shown, the enable signal generator 327-2 is shown. The signal generator 327-1 and the mask circuit 327-2 may be replaced with a frequency control circuit capable of generating a clock signal TCLK' having a frequency lower than that of the clock signal TCLK. For example, when the slave device 300 is in a sleep state, the frequency control circuit may generate a clock signal TCLK' having a frequency lower than the frequency of the clock signal TCLK by using the transmission frame SPEEDY. have.

Since the transmission frame SPEEDY transmitted from the transmission device 200 or 300 through the single wire 110 is asynchronous signals that do not include the clock signal TCLK, the reception device 300 or 200 is a transmission frame A processing circuit 320 or 220 capable of performing a synchronization process and an oversampling process for (SPEEDY) may be included. For example, the processing circuit 320 or 220 may newly perform a synchronization process for each transmission frame (SPEEDY; for example, a command frame or a data frame).

The phase difference between the phase of the master oversampling clock signal (M_4xCLK) used in the master device 200 and the slave oversampling clock signal (S_4xCLK) used in the slave device 300 (in some cases, the worst phase difference). When) occurs, each of (a) and (b) of FIG. 13 shows how to detect synchronization between two over-sampling clock signals (M_4xCLK and S_4xCLK) and sample data at some point, that is, transmission frame (SPEEDY). Indicates whether each bit value contained in can be safely sampled.

Each processing circuit 220 or 320 must satisfy the following conditions in order to accurately sample data, for example, each bit value included in the transmission frame SPEEDY.

First, each oversampling clock signal M_4xCLK and S_4xCLK is generated based on a clock signal TCLK having the same frequency, and the frequencies of each oversampling clock signal M_4xCLK and S_4xCLK must be the same. That is, if the frequencies of each of the oversampling clock signals M_4xCLK and S_4xCLK are the same, the frequency offset problem does not occur.

Second, in order to accurately sample data, for example, each bit value included in a transmission frame (SPEEDY) from a phase offset and jitter, each processing circuit 220 or 320 is positioned at the center of each bit value ( center), you can safely sample the value of each bit. For example, as shown in each of (a) and (b) of Fig. 13, when each bit value is sampled at each rising edge (rising edge or positive edge) of each sampling area (SR), each bit value is safely sampled. Can be.

Third, each processing circuit 220 or 320 clearly identifies the start of the transmission frame (SPEEDY) by using the start bit value of the start field (STRAT) of the transmission frame (SPEEDY), and synchronizes the transmission frame (SPEEDY). The process can be carried out.

For example, when a write operation for the slave device 300 is performed, the second processing circuit 320 includes a start field (STRAT) included in each of the frames (eg, a command frame and a data frame) output from the master device 200. The start of each of the frames may be clearly identified by using the start bit value of, and a synchronization process may be performed for each of the frames.

For example, during a read operation for the slave device 300, the second processing circuit 320 uses the start bit value of the start field STRAT included in the command frame output from the master device 200 to determine the command frame. It is possible to clearly identify the start of and perform a synchronization process for the command frame. After that, the first processing circuit 220 clearly identifies the start of the data frame by using the start bit value of the start field STRAT included in the data frame output from the slave device 300, and Synchronization process can be performed. That is, each processing circuit 220 or 320 may clearly identify the start of each frame and perform a synchronization process.

Each processing circuit 220 or 320, through a synchronization process, one of the four clock phases (P1 to P4) of the slave 4x oversampling clock signal (S_4xCLK) (e.g., Select the second clock phase (P2) in case 1 (CASE1) or the third clock phase (P3) in case 2 (CASE2) in Fig. 13(b), and the period of the slave 4x oversampling clock signal (S_4xCLK) Each time, a transmission frame (SPEEDY) using the selected clock phase (e.g., the second clock phase (P2) in case 1 (CASE1) or the clock phase existing at the same position as the third clock phase (P3) in 2 (CASE2)) is used. Each bit value contained in) can be safely and accurately sampled.

Each processing circuit 220 or 320 may newly perform a synchronization process for each transmission frame SPEEDY. Accordingly, each processing circuit 220 or 320 may newly select one clock phase for each transmission frame SPEEDY from among the four clock phases P1 to P4 of the slave 4x oversampling clock signal S_4xCLK.

Depending on the embodiment, each processing circuit 220 or 320 may change a data phase for a robust synchronization process. Examples of changing the data phase are as follows.

Depending on the embodiment, the master device 200 is each data synchronized to each rising edge of the master clock signal (TCLK or TCLK' in the normal state (NORMAL)) (that is, each bit value included in the transmission frame (SPEEDY)) Is transmitted to the slave device 300, the second processing circuit 320 uses each rising edge of the slave clock signal (TCLK or TCLK' in the normal state) to use the respective data (that is, the transmission frame (SPEEDY)). Each bit value included in) may be sampled. For sampling, a slave 4x oversampling clock signal (S_4xCLK) may be used.

Depending on the embodiment, the frequency of the master clock signal TCLK and the frequency of the slave clock signal TCLK are the same, and the distance between the master device 200 and the slave device 300 (e.g., the wiring length of the PCB) is short, , When the transmission speed of the transmission frame (SPEEDY) transmitted from the master device 200 to the slave device 300 is low, the master device 200 is synchronized with each rising edge of the master clock signal (TCLK). , When each bit value included in the transmission frame (SPEEDY) is transmitted to the slave device 300, the second processing circuit 320 uses each falling edge or negative edge of the slave clock signal TCLK. Thus, each of the data (that is, each bit value included in the transmission frame SPEEDY) can be sampled. For sampling, a slave 4x oversampling clock signal S_4xCLK may be used.

For example, each processing circuit 220 or 320 may include a programmable memory (eg, 329 of FIG. 14) that stores information capable of changing a data phase. For example, the programmable memory may be implemented as a register that can be programmed by each control circuit 270 or 370, but is not limited thereto.

13A and 14, the second processing circuit 320A according to the embodiment of the second processing circuit 320 includes a clock generator 322A, a synchronization detection circuit 324A, and second data. Processing circuitry 328 may be included. The second processing circuit 320A may further include a register 329. For example, the register 329 may include first information capable of controlling the data phase and second information capable of controlling the synchronization on/off of the synchronization detection circuit 324A. As described above, the first information may be information for selecting an edge of a clock signal for sampling or a slave 4x oversampling clock signal (S_4xCLK), and the second information is to control on/off of the synchronization process. It can be information that can be done. Each of the pieces of information may include one or more digital signals.

When the synchronization detection circuit 324A is turned on, the synchronization detection circuit 324A performs a synchronization process, and when the synchronization detection circuit 324A is off, the synchronization detection circuit 324A performs a synchronization process. I never do that. For example, when the synchronization detection circuit 324A is turned off, the transmission frame SPEEDY may be transmitted to the second data processing circuit 328 as it is.

The clock generator 322A may generate a slave 4x oversampling clock signal S_4xCLK using the slave clock signal TCLK' output from the mask circuit 327-2. 13A and 13B, the slave 4x oversampling clock signal S_4xCLK may include four clock phases P1 to P4 per period. According to an embodiment, the second processing circuit 320A may further include an enable signal generator 327-1 and a mask circuit 327-2. Operations of the enable signal generator 327-1 and the mask circuit 327-2 will be described in detail with reference to FIGS. 31 to 33.

Synchronization detection circuit 324A, in order to sample each bit value included in the transmission frame SPEEDY, any one of the four clock phases (P1 to P4) of the slave 4x oversampling clock signal (S_4xCLK). Can be selected for each cycle. In addition, the synchronization detection circuit 324A may transmit the valid indication signal VALID, the data DDATA, and the phase count PCNT to the second data processing circuit 328. For example, the data DDATA may be the same as the transmission frame SPEEDY.

The synchronization detection circuit 324A may include a synchronization circuit 324-1 and a finite-state machine (FSM) 324-2. The synchronization detection circuit 324A may further include a register 324-3. The register 324-3 may store error information or timeout information.

15 is a block diagram illustrating an embodiment of a synchronization circuit included in the synchronization detection circuit shown in FIG. 14.

13A to 15, the synchronization circuit 324-1 may include a plurality of flip-flops 326-1 and 326-2 for stable sampling. The first flip-flop 326-1 may sample each bit value included in the transmission frame SPEEDY in response to the slave 4x oversampling clock signal S_4xCLK. The second flip-flop 326-2 samples each bit value output from the first flip-flop 326-1 in response to the slave 4x oversampling clock signal S_4xCLK, and each sampled bit value (SD0=DDATA) can be output. The plurality of flip-flops 326-1 and 326-2 may constitute a sampling circuit.

FIG. 16 is a state diagram of a finite-state machine (FSM) included in the synchronization detection circuit shown in FIG. 14 and performing a synchronization process using 4x oversampling, FIG. 17 is a state diagram illustrating a phase count operation of an FSM included in the synchronization detection circuit shown in FIG. 14 and performing a synchronization process using 4x oversampling.

13A to 17, the FSM 324-2 includes data sampled by the synchronization circuit 324-1 (SD0=DDATA), a reception enable signal RxEN, and a frame end. Using the signal (EndFrame), it is possible to generate a valid indication signal (VALID) and a phase count (PCNT).

For example, as shown in FIG. 14, when the slave device 300 is in the reception mode, the reception enable signal RxEN is activated to "1", and when the slave device 300 is in the transmission mode, the reception enable signal RxEN ) Is assumed to be deactivated to "0". In addition, when the transmission of the transmission frame (SPEEDY) is not finished, the frame end signal (EndFrame) is deactivated to "0", and when the transmission of the transmission frame (SPEEDY) is finished, the frame end signal (EndFrame) is set to "1". It is assumed to be active. The phase count (PCNT) is, for each period of the slave 4x oversampling clock signal (S_4xCLK), in response to the rising edge of each clock phase (P1-P4), down-counting in the order of 4, 3, 2, 1 ). However, according to the embodiment, the phase count (PCNT) is in the order of 1, 2, 3, and 4 in response to the rising edge of each clock phase (P1-P4) for each period of the slave 4x oversampling clock signal (S_4xCLK). It can also be up-counted.

For example, the synchronization circuit 324-1 samples the start bit value of the start field START by using the rising edge of the first clock phase P1 of the slave 4x oversampling clock signal S_4xCLK, and the sampled Outputs the bit value (SD0=0). Since the sampled bit value SD0 is "0", the rising edge of the first clock phase P1 is included in the synchronization detection area SDR.

That is, the synchronization circuit 324-1 may perform a synchronization operation in the synchronization detection area SDR. In FIGS. 13A and 13B, THRESHOLD may mean a value capable of detecting “0”.

The FSM 324-2 in the idle state (IDLE) proceeds in synchronization in response to the bit value (SD0=0) sampled in the first clock phase (P1) and the activated receive enable signal (RxEN=1). It can transition to the state (SYNC). At this time, the FSM 324-2 may count the rising edge of the first clock phase P1 and output “4” as the phase count PCNT.

In the synchronization progress state (SYNC), when the receive enable signal (RxEN) activated by an error or glitch transitions to "0" or the sampled bit value (SD0) transitions to "1", the FSM 324 -2) may transition from the synchronization progress state (SYNC) to the idle state (IDLE) and generate an error signal (ERROR). The bit value corresponding to the error signal ERROR may be stored in the register 324-3.

In the synchronization progress state (SYNC), the synchronization circuit 324-1 uses the rising edge of the second clock phase (P2) of the slave 4x oversampling clock signal (S_4xCLK), the start bit value of the start field (START). May be sampled, and a sampled bit value (SD0=0) may be output. That is, in the synchronization progress state (SYNC), the FSM 324-2, the bit value sampled at the rising edge of the second clock phase (P2) (SD0 = 0) and the activated receive enable signal (RxEN = 1) In response to, it is possible to transition to the synchronization complete state (SYNC_DONE). That is, when the bit value sampled at the rising edge of the first clock phase (P1) (SD0=0) and the bit value sampled at the rising edge of the second clock phase (P2) are “0” , The FSM 324-2 may transition from a synchronization progress state (SYNC) to a synchronization completion state (SYNC_DONE). At this time, the FSM 324-2 may count the rising edge of the second clock phase P2 and output "3" as the phase count PCNT. For example, when "3" is output as the phase count PCNT, the FSM 324-2 may generate an activated valid indication signal VALID.

The FSM 324-2 can count the rising edge of the third clock phase (P3) and output "2" as the phase count (PCNT), and count the rising edge of the fourth clock phase (P4) and count the phase. "1" can be output as (PCNT). For example, the FSM 324-2, for each period of the slave 4x oversampling clock signal S_4xCLK, is a phase count (PCNT) indicating which clock phase is the current clock phase among the four clock phases P1-P4. ) Can be created.

In addition, the FSM 324-2 indicates that the second clock phase P2 is a clock phase for sampling each bit value included in the transmission frame SPEEDY for each period of the slave 4x oversampling clock signal S_4xCLK. It is possible to generate an activated valid indication signal VALID.

The second data processing circuit 328 receives a slave 4x oversampling clock signal (S_4xCLK), a valid indication signal (VALID), data (DDATA), and a phase count (PCNT), and receives the slave 4x oversampling clock signal (S_4xCLK). Each bit value (eg, D7 and D6) included in the data DDATA may be sampled using the rising edge of the second clock phase P2 for each period of. For example, the valid indication signal VALID may have an activated pulse shape whenever the phase count PCNT is “3”, but is not limited thereto.

When the reception enable signal (RxEN) is not "1" (!RxEN) or when the reception of the transmission frame (SPEEDY) is completed, the status of the FSM 324-2 is set to idle (IDLE) from the synchronization completion status (SYNC_DONE). ). In addition, when the reception enable signal (RxEN) is not "1" (!RxEN), when the reception of the transmission frame (SPEEDY) is completed, or when an error occurs, the FSM 324-2 is in a phase count state. You can transition from (PHASE COUNT) to IDLE.

The second data processing circuit 328 converts each bit value included in the data (DDATA=SPEEDY) output from the synchronization circuit 324-1 for each second clock phase (P2) of the slave 4x oversampling clock signal (S_4xCLK). It is possible to sample and generate control signals for a write operation or a read operation according to the sampling result.

In the case of (a) of FIG. 13, 1 (CASE1) is when the phase of the slave 4x oversampling clock signal (S_4xCLK) is the fastest (e.g., the phase of the master 4x oversampling clock signal (M_4xCLK) and the slave 4x oversampling clock signal (When the difference in phase of S_4xCLK is the smallest), this is a timing diagram for explaining a process of selecting any one clock phase (eg, P2) from among a plurality of clock phases P1-P4.

The synchronization circuit 234-1 selects a second clock phase P2 from among four clock phases P1-P4 for each period of the slave 4x oversampling clock signal S_4xCLK, and activates corresponding to the selection result. The valid indication signal VALID may be output to the second data processing circuit 328.

In the case of (b) of FIG. 13, 2 (CASE2) is when the phase of the slave 4x oversampling clock signal (S_4xCLK) is the slowest (e.g., the phase of the master 4x oversampling clock signal (M_4xCLK) and the slave 4x oversampling clock signal (When the phase difference of S_4xCLK is the largest), a timing diagram for explaining a process of selecting any one clock phase (eg, P3) from among a plurality of clock phases P1-P4.

The synchronization circuit 324-1 samples the start bit value of the start field START by using the rising edge of the first clock phase P1 of the slave 4x oversampling clock signal S_4xCLK, and the sampled bit value. Assume that (SD0=1) is output. At this time, since the sampled bit value SD0 is not "0", the rising edge of the first clock phase P1 is not included in the synchronization detection area SDR. The FSM 324-2 may count the rising edge of the first clock phase P1 and may not output the phase count PCNT, but is not limited thereto. That is, when the sampled bit value SD0 is "0", the phase count PCNT may be output, but the output timing of the phase count PCNT may be variously changed according to exemplary embodiments.

The synchronization circuit 324-1 samples the start bit value of the start field START by using the rising edge of the second clock phase P2 of the slave 4x oversampling clock signal S_4xCLK, and the sampled bit value. (SD0=0) can be output. At this time, since the sampled bit value SD0 is "0", the rising edge of the second clock phase P2 is included in the synchronization detection area SDR.

The FSM 324-2 in the idle state (IDLE) is in response to the bit value (SD0=0) sampled in the second clock phase (P2) and the activated receive enable signal (RxEN=1), and the synchronization is in progress. Transition to (SYNC) is possible. At this time, the FSM 324-2 may count the rising edge of the second clock phase P2 and output "4" as the phase count PCNT.

In the synchronization progress state (SYNC), if the receive enable signal (RxEN) activated by an error or glitch transitions to "0" or the sampled bit value (SD0) transitions to "1", FSM (324-2) May transition from the synchronization progress state (SYNC) to the idle state (IDLE) and generate an error signal (ERROR). The bit value corresponding to the error signal ERROR may be stored in the register 324-3.

In the synchronization progress state (SYNC), the synchronization circuit 324-1 uses the rising edge of the third clock phase (P3) of the slave 4x oversampling clock signal (S_4xCLK), the start bit value of the start field (START). May be sampled, and a sampled bit value (SD0=0) may be output. That is, in the synchronization progress state (SYNC), the FSM 324-2, the bit value sampled at the rising edge of the third clock phase (P3) (SD0 = 0) and the activated receive enable signal (RxEN = 1) In response to, it is possible to transition to the synchronization complete state (SYNC_DONE). That is, when the bit value sampled at the rising edge of the second clock phase (P2) (SD0=0) and the bit value sampled at the rising edge of the third clock phase (P3) are “0” , The FSM 324-2 may transition from a synchronization progress state (SYNC) to a synchronization completion state (SYNC_DONE). In this case, the FSM 324-2 may count the rising edge of the third clock phase P3 and output “3” as the phase count PCNT. For example, when "3" is output as the phase count PCNT, the FSM 324-2 may generate an activated valid indication signal VALID.

The FSM 324-2 may count the rising edge of the fourth clock phase P4 and output "2" as the phase count PCNT. For example, the FSM 324-2, for each period of the slave 4x oversampling clock signal S_4xCLK, is a phase count (PCNT) indicating which clock phase is the current clock phase among the four clock phases P1-P4. ) Can be created.

In addition, the FSM 324-2 indicates that the third clock phase P3 is a clock phase for sampling each bit value included in the transmission frame SPEEDY for each period of the slave 4x oversampling clock signal S_4xCLK. It is possible to generate an activated valid indication signal VALID.

The second data processing circuit 328 receives a slave 4x oversampling clock signal (S_4xCLK), a valid indication signal (VALID), data (DDATA), and a phase count (PCNT), and receives the slave 4x oversampling clock signal (S_4xCLK). Each bit value (eg, D7 and D6) included in the data DDATA may be sampled by using the rising edge of the third clock phase P3 for each period of. For example, the valid indication signal VALID may have an activated pulse shape whenever the phase count PCNT is “3”, but is not limited thereto.

When the reception enable signal (RxEN) is not "1" (!RxEN) or when the reception of the transmission frame (SPEEDY) is completed, the status of the FSM 324-2 is set to idle (IDLE) from the synchronization completion status (SYNC_DONE). ). In addition, when the reception enable signal (RxEN) is not "1" (!RxEN), when the reception of the transmission frame (SPEEDY) is completed, or when an error occurs, the FSM 324-2 is in a phase count state. You can transition from (PHASE COUNT) to IDLE.

The second data processing circuit 328 converts each bit value included in the data (DDATA=SPEEDY) output from the synchronization circuit 324-1 for each third clock phase P3 of the slave 4x oversampling clock signal S_4xCLK. It is possible to sample and generate control signals for a write operation or a read operation according to the sampling result.

The synchronization circuit 234-1 selects the third clock phase P3 from the four clock phases P1-P4 for each period of the 4x oversampling clock signal S_4xCLK, and a valid indication corresponding to the selection result The signal VALID may be output to the second data processing circuit 328.

The second data processing circuit 328 is a third of the four clock phases P1-P4 based on the valid indication signal VALID and the phase count PCNT for each period of the 4x oversampling clock signal S_4xCLK. Sampling of each bit value included in the frame may be performed using the clock phase P3.

18 is a block diagram illustrating an embodiment of a second processing circuit included in the slave device illustrated in FIG. 1.

The second processing circuit 320B of FIG. 18 according to the embodiment of the second processing circuit 320 of FIG. 1 includes a clock generator 322B, a synchronization detection circuit 324B, and a second data processing circuit 328. can do. The second processing circuit 320A may further include a register 329. For example, the register 329 may include first information for controlling the data phase and second information for controlling the on/off of the synchronization detection circuit 324B. As described above, the first information may be information capable of selecting a sampling edge, and the second information may be information capable of controlling on/off of a synchronization process.

The clock generator 322B may generate a slave 2x oversampling clock signal S_2xCLK using the slave clock signal TCLK' output from the mask circuit 327-2. According to an embodiment, the second processing circuit 320B may further include an enable signal generator 327-1 and a mask circuit 327-2. Operations of the enable signal generator 327-1 and the mask circuit 327-2 will be described in detail with reference to FIGS. 31 to 33.

19 illustrates an embodiment of a clock generator that generates a slave 2x oversampling clock signal included in the second processing circuit illustrated in FIG. 18. Referring to FIG. 19, the clock generator 322B may include a delay circuit 331 and an exclusive OR (XOR) circuit 333. The delay circuit 331 may delay the slave clock signal TCLK'. For example, the delay circuit 331 may be implemented as a delay buffer, but is not limited thereto. The XOR circuit 333 performs an XOR operation on the slave clock signal TCLK' and the delay clock signal dCLK output from the delay circuit 331, and generates a slave 2x oversampling clock signal S_2xCLK.

FIG. 20 shows an embodiment of a clock generator that generates a slave 2x oversampling clock signal included in the second processing circuit illustrated in FIG. 18. Referring to FIG. 20, the clock generator 322B may include a flip-flop 341, an inverter 343, and an exclusive NOR (XNOR) circuit 345.

The output signal of the inverter 343 is supplied (or fed back) as an input signal of the flip-flop 341, and the output signal S_2xCLK of the XNOR circuit 345 is supplied as a clock signal of the flip-flop 341. The inverter 343 inverts the output signal of the flip-flop 341. The XNOR circuit 345 performs an XNOR operation on the output signal of the inverter 343 and the slave clock signal TCLK', and generates a slave 2x oversampling clock signal S_2xCLK.

The synchronization detection circuit 324B may select any one of the two clock phases of the slave 2x oversampling clock signal S_2xCLK in order to sample each bit value included in the transmission frame SPEEDY. The synchronization detection circuit 324B may transmit the valid indication signal VALID, the data DDATA, and the phase count PCNT to the second data processing circuit 328.

The synchronization detection circuit 324B may include a synchronization circuit 324-1B and an FSM 324-2B. The synchronization detection circuit 324B may further include a register 324-3B. The register 324-3B may store error information or timeout information.

21 is a block diagram illustrating an embodiment of a synchronization circuit included in the synchronization detection circuit shown in FIG. 18. The synchronization circuit 324-1B may include a delay circuit 351 and two synchronization devices 353 and 355.

The delay circuit 351 may delay the transmission frame SPEEDY. For example, the delay circuit 351 may be implemented as a delay buffer, but is not limited thereto.

The first synchronous device 353 may include a first flip-flop 353-1 and a second flip-flop 353-2. The first flip-flop 353-1 may latch (or sample) the transmission frame SPEEDY in response to the slave 2x oversampling clock signal S_2xCLK. The second flip-flop 353-2 may latch the output signal of the first flip-flop 353-1 and output data SD0 in response to the slave 2x oversampling clock signal S_2xCLK.

The second synchronous device 355 may include a third flip-flop 355-1 and a fourth flip-flop 355-2. The third flip-flop 355-1 may latch (or sample) the output signal dSPEEDY of the delay circuit 351 in response to the slave 2x oversampling clock signal S_2xCLK. The fourth flip-flop 355-2 may latch the output signal of the third flip-flop 355-1 and output data SD1 in response to the slave 2x oversampling clock signal S_2xCLK.

22 is a timing diagram of signals for explaining a synchronization process performed using a slave 2x oversampling clock signal according to an embodiment of the present invention. 18 to 22, it is assumed that the clock generator 322B can periodically generate a slave 2x oversampling clock signal S_2xCLK having a 55% duty cycle and a 45% duty cycle, but is limited thereto. no.

FIG. 23 is a state diagram of an FSM included in the synchronization detection circuit shown in FIG. 18 and performing a synchronization process using slave 2x oversampling, and FIG. 24 is a slave 2x oversampling included in the synchronization detection circuit shown in FIG. It is a state diagram for explaining the phase count operation of the FSM performing the synchronization process by using.

18 to 24, the FSM 324-2B includes data sampled by the synchronization circuit 324-1B (DDATA=SD0 and SD1), a reception enable signal RxEN, and a frame end signal ( EndFrame) can be used to generate a valid indication signal (VALID) and a phase count (PCNT).

For example, when the slave device 300 is in the receive mode, the receive enable signal RxEN is activated to "1", and when the slave device 300 is in the transmit mode, the receive enable signal RxEN is deactivated to "0". Is assumed to be. In addition, when the reception of the transmission frame (SPEEDY) is not finished, the frame end signal (EndFrame) is deactivated to "0", and when the reception of the transmission frame (SPEEDY) is finished, the frame end signal (EndFrame) is set to "1". It is assumed to be active. It is assumed that the phase count (PCNT) is down-counted in the order of 2 and 1 for each period of the 2x oversampling clock signal S_2xCLK, but according to the embodiment, the phase count (PCNT) is for each period of the 2x oversampling clock signal S_2xCLK It can also be up-counted in the order of 1 or 2.

For example, the synchronization circuit 324-1B samples the start bit value of the start field START using the second clock phase of the slave 2x oversampling clock signal S_2xCLK, and samples the sampled bit values (SD0=0). And SD1=0).

The FSM 324-2B in the idle state (IDLE) responds to the activated receive enable signal (RxEN=1) and the bit values sampled at the rising edge of the second clock phase (SD0=0 and SD1=0). , Can transition to the synchronization complete state (SYNC_DONE).

However, the FSM 324-2B in the idle state (IDLE) is based on the activated receive enable signal (RxEN=1) and the bit values sampled at the rising edge of the second clock phase (SD0=0 and SD1=1). In response, it may transition to a synchronization progress state (SYNC).

In the synchronization progress state (SYNC), when the receive enable signal (RxEN) activated by an error or glitch transitions to inactive or the sampled bit value (SD0) transitions to "1", the FSM 324-2B It is possible to transition from the synchronization progress state (SYNC) to the idle state (IDLE) and generate an error signal (ERROR). Bits corresponding to the error signal ERROR may be stored in the register 324-3B.

However, in the synchronization progress state (SYNC), when the activated receive enable signal RxEN is maintained and each of the sampled bit values (SD0 and SD1) is "0", the FSM 324-2B is in the synchronization progress state ( SYNC) can transition to the synchronization complete state (SYNC_DONE).

The FSM 324-2b is an activated valid indication indicating that the second clock phase is a clock phase for sampling each bit value included in the transmission frame SPEEDY, for each period of the slave 2x oversampling clock signal S_2xCLK. A signal (VALID) can be generated.

The second data processing circuit 328 receives a slave 2x oversampling clock signal (S_2xCLK), a valid indication signal (VALID), data (DDATA), and a phase count (PCNT), and each bit included in the data (DDATA). The value may be sampled using the second clock phase of the slave 2x oversampling clock signal S_2xCLK. The second data processing circuit 328 samples each bit value included in the data DDATA output from the synchronization circuit 324-1B using the second clock phase of the slave 2x oversampling clock signal S_2xCLK, Depending on the sampling result, control signals for write operation or read operation can be generated.

25 is a timing diagram of signals for explaining a process of controlling a dynamic pull-up resistance included in an apparatus for performing 4x oversampling.

When the transmission frame (SPEEDY) is transmitted through a single wire 110, each pull-up resistor 271 and 371 connects each pad 214 and 314 and each voltage line for power consumption and fast transition. Can be separated. That is, each pull-up resistor 271 and 371 is disabled. However, while the stop bit of the stop field STOP is transmitted through the single wire 110, the pull-up resistor 271 or 371 may be dynamically controlled.

When the master device 200 and the slave device 300 simultaneously drive the single wire 110, the energy loss of each of the master device 200 and the slave device 300 is large, and each of the pads 214 and 314 is It can be damaged. In addition, if both the master device 200 and the slave device 300 do not drive the single wire 110, a large short current may flow through the single wire 110, and thus energy loss is large. The master device 200 and the slave device 300 may be in an unstable state. Therefore, enabling or disabling of the pull-up resistor 271 or 371 for direction change must be controlled.

When the last data output from the master device 200, for example, the bit value of the last bit among the bits included in the field immediately before the stop field (STOP) is "0", the first output is enabled in the first period (I) Since the control signal OEN1 is in an active state, the first output driver 212 can strongly drive the stop bit ODATA1 with the first pad 214. Accordingly, a rising time of the stop bit included in the transmission frame SPEEDY may be reduced.

When the first period I starts, the first pull-up resistance control signal PEN1 is activated. Therefore, since the first pull-up resistor 271 is enabled, the first operating voltage VDD1 is supplied to the single wire 110 through the first pull-up resistor 271 and the first pad 214. I can. For example, the resistance value of the enabled first pull-up resistor 271 may be 45 kΩ, but is not limited thereto.

When the fourth period (IV) starts, the second output enable control signal OEN2 is activated, so the second output driver 312 transmits the bit value to the single wire 110 through the second pad 314. I can.

As shown in FIG. 25, the first period (I) is a first transmission period (TxDATA) in which a transmission frame (SPEEDY) output from the master device 200 is transmitted to the slave device 300 through a single wire 110. Can mean ).

In the second period (II) and the third period (III), when all of the output enable signals OEN1 and OEN2 are deactivated, the single wire 110 is controlled by the first pull-up resistor 271. It may mean a pull-up period (PULL-UP) being pulled up to one operating voltage (VDD1).

The fourth period IV may mean a second transmission period RxDATA in which the transmission frame SPEEDY output from the slave device 300 is transmitted to the master device 200 through a single wire 110.

As shown in FIG. 25, the activation period of the first pull-up resistance control signal PEN1 may be variably controlled for stable direction change. For example, the first control circuit 270 may control an activation period of the first pull-up resistance control signal PEN1. Information capable of controlling the activation period may be set or programmed in the register 272. The direction change timing may be controlled by activation timing and deactivation timing of each of the output enable control signals OEN1 and OEN2.

The first transmission period TxDATA is determined by a deactivation point of the first output enable control signal OEN1, and during the first transmission period TxDATA, the first output driver 212 passes through the first pad 214. The single wire 110 can be driven in the first direction. The second transmission period (RxDATA) is determined by the activation time of the second output enable control signal OEN2, and the second output driver 312 connects the single wire 110 to the second through the second pad 314. It can be driven in any direction. For example, the first direction and the second direction may be opposite to each other.

26 is a timing diagram of signals for explaining a process of controlling a dynamic pull-up resistance included in an apparatus for performing 2x oversampling.

When the first period i starts, the first pull-up resistance control signal PEN1 is activated. Therefore, since the first pull-up resistor 271 is enabled, the first operating voltage VDD1 is supplied to the single wire 110 through the first pull-up resistor 271 and the first pad 214. I can.

In the first period i, the first output driver 212 drives the stop bit "1" with the single wire 110 through the first pad 214. When the second period (ii) starts, the first output enable signal OEN1 is deactivated.

In the third period (①), the second output enable signal OEN2 is activated, and when the fourth period (②) starts, the start bit of the second output frame ODATA2 transitions from "1" to "0". do.

As shown in FIG. 26, the activation period of the first pull-up resistance control signal PEN1 may be variably controlled for stable direction change. For example, the first control circuit 270 may control an activation period of the first pull-up resistance control signal PEN1. Information capable of controlling the activation period may be set or programmed in the register 272.

In FIGS. 25 and 26, a range in which the first pull-up resistance control signal PEN1 is varied is indicated by hatching.

The error detection methods are as follows.

First, referring to FIGS. 14 and 16, in order to prevent the second processing circuit 320 from becoming a malfunction due to an error or glitch in the synchronization progress state (SYNC), the data SD0 is "1". Is detected as "or the receive enable signal (RxEN) is detected as "0", the FSM 324-2 sets (or programs) an error signal (ERROR) in the error status register 324-3 and in the idle state ( IDLE). In addition, when synchronization fails, the FSM 324-2 checks whether the bit value of the stop field STOP is "1", and sets an error signal ERROR in the error status register 324-3 (or Program) and transition to the idle state (IDLE).

Second, the second controller 370 has a maximum response time ( Or you can limit the maximum timeout time). The maximum response time may be stored in a register 372 that can be accessed by the second controller 370, and the maximum response time is set (or programmed) in the register 372 by the second controller 370. Can be.

When the slave device 300 fails to respond within the maximum response time (or the maximum timeout time), the second controller 370 may release the control right for the second enable control signal OEN2. That is, the second controller 370 may generate the deactivated second enable control signal OEN2. Since the control right for the second enable control signal OEN2 is released by the second controller 370, the master device 200 cannot determine the state of the slave device 300. Accordingly, the master device 200 may transmit a command frame for obtaining information set in the register 372 to the slave device 300.

Third, the master device 200 may add a parity bit to a command frame or a data frame to detect an error. A method of adding a parity bit will be described with reference to FIG. 27.

27 shows a command frame format and a data frame format according to the protocol of the present invention including a parity bit. A parity bit or a check bit is a bit added to the end of a string of a binary code and indicates whether the number of values "1" included in the string is odd or even. Parity bits are used as the simplest form of error detecting code. Parity bits are classified into even parity bits and odd parity bits.

The even parity bit determines the parity bit so that the number of "1s" is an even number among all bits included in the string, and the odd parity bit is the parity so that the number of "1" is odd among all the bits included in the string. It is to determine the beat.

According to an embodiment, the master device 200 may add an even parity bit or an odd parity bit to a frame (eg, a command frame or a data frame). For example, the first frame generator 210 of the master device 200 may add an even parity bit or an odd parity bit to a frame (eg, a command frame or a data frame) under the control of the first control circuit 270. I can.

The second processing circuit 320 of the slave device 300 may detect an error of the frame by using a parity bit included in the frame transmitted from the master device 200 and store the detection result in a register. For example, when an error is detected in the received frame, the slave device 300 may transmit a detection result to the master device 200, and the master device 200 may transmit the frame to the slave device 300 in response to the detection result. You can send it again.

Although, in (a) to (d) of FIG. 27, an embodiment in which a parity bit field (PARITY) including a parity bit is added immediately before the stop field (STOP) of each frame format (FR1 to FR4) is shown. , According to an embodiment, the parity bit field PARITY may be added at various positions in each frame format FR1 to FR4. For example, the parity bit may be 1-bit, but is not limited thereto.

FIG. 27A shows a data frame format FR1 including a parity bit field PARITY, and FIG. 27B shows a burst command frame format FR2 including a parity bit field PARITY. , FIG. 27(c) shows a random command frame format (FR3) including a parity bit field (PARITY), and FIG. 27(d) is a command frame (special command) format including a parity bit field (PARITY). (FR4).

Referring to FIG. 27D, when all bits included in the address field ADDRESS are "1", the slave device 300 stops the current operation (eg, write operation or read operation) or resets ( reset). Therefore, the slave device 300 may not perform an erroneous command.

Although, in (d) of FIG. 27, an embodiment in which the bits included in the address field ADDRESS are all "1" is shown, the bits included in the address field ADDRESS are previously When set to specific defined bits (or specific pattern), the slave device 300 may stop or reset the current operation in response to the predefined specific bits.

In addition, when the master device 200 transmits an abnormal frame (eg, a frame that does not match the frame format shown in FIGS. 2, 3, and 4) to the slave device 300, the slave device 300 In response to, the current operation can be stopped or reset.

28 is a block diagram of a data processing system including a slave device including a parity enable register and a parity status register. 1 and 28, the slave device 300 includes a parity enable register 381 and a parity state in addition to the components 310, 312, 314, 316, 320, 370, and 371 shown in FIG. 1. A register 383 may be further included.

29 is an embodiment of a frame format according to the protocol of the present invention for explaining a parity enable process. In this case, the parity enable register 381 and the parity status register 383 are assumed to be the same register, but are not limited thereto.

Referring to FIGS. 28 and 29A, the master device 200 uses a single wire 110 to write a write frame for writing a bit for enable in the parity enable register 381, that is, a write command frame. Through this, it can be output to the slave device 300. For example, the parity enable register 381 may be determined by bits included in the address field ADDRESS.

Referring to FIGS. 28 and 29B, the master device 200 converts a data frame into a single wire 110 in order to write bits 22'b0000000000000000000001 for enable in the parity enable register 381. Through the output may be output to the slave device 300. Accordingly, bits (22'b0000000000000000000001) for enable may be stored in the parity enable register 381.

28 and 29(c), the master device 200 includes a command frame for reading the bits 22'b0000000000000000000001 stored in the parity status register 383, for example, a parity field. The read command frame may be output to the slave device 300 through a single wire 110. The slave device 300 reads the bits 22'b0000000000000000000001 stored in the parity status register 383 in response to the read command frame, and a data frame including the read bits 22'b0000000000000000000001, for example , A read data frame including a parity field (PARITY) may be transmitted to the master device 200.

30 is an embodiment of a frame format according to the protocol of the present invention for explaining a parity disable process. In this case, the parity enable register 381 and the parity status register 383 are assumed to be the same register, but are not limited thereto.

Referring to FIGS. 28 and 30A, the master device 200 uses a single wire 110 to write a write frame for writing a bit for disable in the parity enable register 381, that is, a write command frame. Through this, it can be output to the slave device 300. For example, the parity enable register 381 may be determined by bits included in the address field ADDRESS.

Referring to FIGS. 28 and 30B, the master device 200 converts a data frame to a single wire 110 in order to write bits 22'b0000000000000000000000 for disable in the parity enable register 381. Through the output may be output to the slave device 300. Accordingly, bits 22'b0000000000000000000001 for disable may be stored in the parity enable register 381.

28 and 30(c), the master device 200 includes a command frame for reading the bits 22'b0000000000000000000001 stored in the parity status register 383, for example, a parity field. The read command frame may be output to the slave device 300 through a single wire 110. The slave device 300 reads the bits 22'b0000000000000000000001 stored in the parity status register 383 in response to the read command frame, and a data frame including the read bits 22'b0000000000000000000001, for example , A read data frame including a parity field (PARITY) may be transmitted to the master device 200.

FIG. 31 is a timing diagram illustrating a process in which the master device shown in FIG. 1 controls the power mode of the slave device shown in FIG. 1.

1, 14, 18, and 31, when the data processing system 100 is booted, the slave device 300 may operate in a sleep state (SLEEP) for low power operation. . As exemplarily shown in FIG. 31, when the slave device 300 operates in the sleep state (SLEEP), the mask circuit 327-2 is a clock signal in response to the enable signal EN having a low level. Transmission of (TCLK) can be blocked.

The enable signal generator 327-1 may control activation or deactivation of the enable signal EN based on a signal input through the second pad 314, for example, a signal included in the transmission frame SPEEDY. I can. For example, the enable signal generator 327-1 may detect a rising edge of a signal input through the second pad 314 and generate an enable signal EN having a high level according to the detection result. . The mask circuit 327-2 may output the clock signal TCLK as an output clock signal TCLK' in response to the enable signal EN having a high level. Accordingly, since the slave device 300 may change from the sleep state (SLEEP) to the normal state (NORMAL), the slave device 300 may wake up.

For example, the master device 200 may transmit a wake-up signal WUS to the slave device 300 to change the slave device 300 in the sleep state (SLEEP) to a wake-up state (or wake-up mode). .

The master device 200 may transmit a command (e.g., a command for a sleep state (CSM)) to the slave device 300 to change the slave device 300 in the normal state (NORMAL) to the sleep state (SLEEP). have. The command for the sleep state (CSM) may be transmitted from the master device 200 to the slave device 300 as a transmission frame (SPEEDY). For example, the enable signal generator 327-1 may generate an enable signal EN having a low level by using a command for a sleep state (SPEEDY=CSM). Accordingly, the mask circuit 327-2 may block the clock signal TCLK from being supplied to the clock generator 322A or 322B. As the supply of the clock signal TCLK is cut off, power consumed by the slave device 300 may be reduced.

As described above, the master device 200 transmits a signal capable of operating the slave device 300 in a sleep state (SLEEP) or a normal state (NORMAL), for example, a transmission frame (SPEEDY) through a single wire 110. It can be transmitted to the device 300. For example, the sleep state (SLEEP) may include an idle state, and the normal state (NORMAL) may include a wake-up state.

32 shows a clock gating circuit according to an embodiment of the present invention, and FIG. 33 shows a timing diagram of the clock gating circuit shown in FIG. 32. 1, 14, 18, 31, 32, and 33, the master device 200 is a power on reset (POR) to control the state of the slave device 300 to a sleep state (SLEEP). ) Signal or write a sleep command (SLEEP_CMD) for a sleep state in the sleep register 327-3. According to an embodiment, the command for the sleep state SLEEP_CMD may be transmitted to the enable signal generator 327-1 through the transmission frame SPEEDY.

For example, when the POR signal transitions to the high level, each flip-flop 327-3, 327-6, and 327-7 may latch the output signal Q having the high level. Accordingly, since the inverter 327-4 outputs an output signal having a low level (ie, the enable signal EN), the mask circuit 327-2 may block transmission of the clock signal TCLK.

When the slave device 300 is in a normal state (NORMAL), that is, when the enable signal EN is at a high level, the mask circuit 327-2 converts the clock signal TCLK to the output clock signal TCLK'. Can be printed.

In order to change the state of the slave device 300 from the normal state (NORMAL) to the sleep state (SLEEP), the master device 200 may transmit a sleep command SLEEP_CMD to the slave device 300. For example, the sleep command SLEEP_CMD may be transmitted as a transmission frame SPEEDY. In the sleep state (SLEEP), the enable signal generator 327-1 may generate an enable signal EN having a low level, and the mask circuit 327-2 may block transmission of the clock signal TCLK. .

In order to change the state of the slave device 300 from the sleep state (SLEEP) to the normal state (NORMAL), the master device 200 may transmit a normal state command CMD to the slave device 300. For example, the steady state command CMD may be transmitted in a transmission frame SPEEDY. When the transmission frame SPEEDY becomes "1", the enable signal generator 327-1 generates an enable signal EN having a high level, and the mask circuit 327-2 generates a clock signal TCLK. Can be output as an output clock signal TCLK'. At the first time point T1, the state of the slave device 300 may be changed from the normal state (NORMAL) to the sleep state (SLEEP), and at the second time point T2, the state of the slave device 300 is a sleep state ( SLEEP) can be changed to a normal state (NORMAL).

34 is a block diagram of a data processing system according to an embodiment of the present invention. 1 and 34, the master device 200-1 may mean a processor capable of controlling each of the slave devices 300-1 to 300-8. Single wires independent of each other may be connected between the master device 200-1 and each of the slave devices 300-1 to 300-8. As described above, the master device 200-1 may be implemented as a baseband modem processor chip, a chip capable of performing both a modem function and an AP function, an AP, or a mobile AP, but is not limited thereto.

The slave devices are RFIC (300-1), PMIC (300-2), power supply module (300-3), second RFIC (300-4), sensor (300-5), fingerprint identification chip (300-6), A touch screen controller 300-7 and a digital display interface or display driver IC (DDI) chip 300-8 may be included. The RFIC 300-1 may include at least one connection chip. For example, the connection chip is a chip for mobile communication, a chip for WLAN communication, a chip for Bluetooth communication, a chip for GNSS communication, a chip for processing FM audio/video, NFC, and/or for Wi-Fi communication. It may include a chip, but is not limited thereto.

35 is a block diagram of a data processing system according to an embodiment of the present invention. 1 and 35, the data processing system 100-2 may include a master device 200A, a slave device 300, a first clock source 370 and a second clock source 370-1. I can. Assume that the first clock source 370 generates a first clock signal MCLK having a first frequency, and the second clock source 370-1 generates a second clock signal TCLK having a second frequency. do.

The phase locked loop (PLL) 280 of the master device 200A may receive the first clock signal MCLK and generate a second clock signal TCLK having a second frequency. That is, the PLL 280 generates a second clock signal TCLK having the same frequency as the second clock signal TCLK supplied to the second processing circuit 320 of the slave device 300, and the second clock signal (TCLK) may be supplied to the first processing circuit 220.

The present invention has been described with reference to the embodiments shown in the drawings, but these are only exemplary, and those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical idea of the attached registration claims.

100, 100-1, 100-2: data processing system
110: single wire
200, 200A: master device
210: first frame generator
212: first output driver
214: first pad
216: first input buffer
220: first processing circuit
270: first control circuit
271: first pull-up resistance
300: slave device
310: second frame generator
312: second output driver
314: second pad
316: second input buffer
320: second processing circuit

Claims (20)

In a master device capable of communicating with a slave device,
A single pad for transmitting and receiving a command frame including an address and a data frame including data to and from the slave device through a single wire; And
A synchronization process of generating an oversampling clock signal from a clock signal, selecting one of the clock phases of the oversampling clock signal, and synchronizing each bit value included in the data frame transmitted from the slave device. A master device comprising a processing circuit that performs a sampling process for sampling by using a clock phase present at the same position as the clock phase selected in the process. The method of claim 1,
Each of the command frame and the data frame includes a start bit value and a stop bit value,
The processing circuit is a master device that performs the synchronization process on the start bit value. The method of claim 1, wherein the processing circuit,
A synchronization detection circuit including at least two flip-flops; And
Including data processing circuitry,
The synchronization detection circuit, using the at least two flip-flops, generates clock phase selection signals related to the selected clock phase for each period of the oversampling clock signal,
The data processing circuit, for each period of the oversampling clock signal, samples each bit value included in the data frame by using a clock phase associated with the clock phase selection signals. The method of claim 3,
The oversampling clock signal is a 4x oversampling clock signal. The method of claim 3,
The oversampling clock signal is a 2x oversampling clock signal. The method of claim 1,
The single wire does not include a clock line for transmitting the clock signal to the slave device. The method of claim 1,
The frequency of the clock signal used in the master device is the same as the frequency of the clock signal used in the slave device. The method of claim 1, wherein the master device,
A pull-up resistor for controlling a connection between a voltage supply line and the one pad in response to a pull-up resistor control signal; And
Master device further comprising an output driver connected to the one pad. The method of claim 8, wherein the master device,
And a control circuit for activating the pull-up resistance control signal when a stop bit value included in the command frame is transmitted to the one pad through the output driver. The method of claim 1, wherein the master device,
The master device further comprises a frame generator for generating the command frame including a parity bit. In the slave device that can communicate with the master device,
A single pad for transmitting and receiving a command frame including an address and a data frame including data to and from the master device through a single wire; And
Generate an oversampling clock signal from a clock signal, select one of the clock phases of the oversampling clock signal, and use the selected clock phase for each bit value included in the data frame transmitted from the master device. A slave device including a processing circuit for sampling and sampling. The method of claim 11, wherein the processing circuit,
A synchronization detection circuit including at least two flip-flops; And
Including data processing circuitry,
The synchronization detection circuit, using the at least two flip-flops, generates clock phase selection signals related to the one clock phase for each period of the oversampling clock signal,
The data processing circuit, for each period of the oversampling clock signal, samples each bit value included in the data frame by using the one clock phase related to the clock phase selection signals. The method of claim 12,
The oversampling clock signal is a 4x oversampling clock signal. The method of claim 12,
The oversampling clock signal is a 2x oversampling clock signal. The method of claim 11,
The single wire is a slave device that does not include a clock line for transmitting the clock signal. The method of claim 11,
The frequency of the clock signal used in the slave device is the same as the frequency of the clock signal used in the master device. The method of claim 11, wherein the slave device,
A pull-up resistor for controlling a connection between a voltage supply line and the one pad in response to a pull-up resistor control signal; And
The slave device further comprising an output driver connected to the one pad. The method of claim 17, wherein the slave device,
And a control circuit for activating the pull-up resistance control signal when a stop bit value included in the command frame is transmitted to the one pad through the output driver. A master device including one first pad;
A slave device including one second pad and a processing circuit connected to the one second pad; And
Including a single wire connected between the one first pad and the one second pad,
The processing circuit generates an oversampling clock signal from a clock signal, selects one of the clock phases of the oversampling clock signal, and selects each bit value included in the frame transmitted from the master device. A data processing system that samples by using. The method of claim 19, wherein the slave device,
A pull-up resistor for controlling a connection between a voltage supply line and the one pad in response to a pull-up resistor control signal; And
A data processing system further comprising an output driver connected to the one pad.

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