KR102245004B1 - Method of fabricating array substrate for liquid crystal display device - Google Patents

Abstract

In order to provide an array substrate for a liquid crystal display device capable of preventing display image defects such as spot defects, the present invention includes a pixel electrode, wherein the pixel electrode is a first pixel disposed on both outermost sides of the pixel electrode. A method of manufacturing an array substrate for a liquid crystal display in a fringe field switching mode comprising an electrode finger and a second pixel electrode finger disposed between the first pixel electrode finger and a pixel electrode connector connecting the first and second pixel electrodes. And forming a common electrode on a substrate, forming a gate insulating layer on the common electrode and on the entire surface of the substrate, forming a data line on the gate insulating layer, and protecting the data wiring and the entire surface of the substrate. Forming a layer, stacking a transparent conductive layer on the protective layer, depositing a photoresist layer on the transparent conductive layer, and exposing the photoresist layer to light with an exposure mask, on the top of the common electrode. Forming first and second photoresist patterns spaced apart from the data line by a predetermined distance, etching and removing the transparent conductive layer outside the first and second photoresist patterns, and the first and second photos Forming the first and second pixel electrode fingers respectively corresponding to the first and second photoresist patterns by stripping and removing the resist pattern, wherein the exposure mask includes the first and second photoresist Each of the first and second blocking regions corresponding to the pattern is provided, and the width of the first blocking region is larger than the width of the second blocking region, so that the first and second pixel electrode fingers have the same width. A method of manufacturing an array substrate for a liquid crystal display device is provided.

Description

Method of fabricating array substrate for liquid crystal display device {Method of fabricating array substrate for liquid crystal display device}

The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device capable of preventing display defects.

In general, a fringe field switching mode liquid crystal display has a configuration including an array substrate, a color filter substrate having a color filter layer corresponding thereto, and a liquid crystal layer between the two substrates. In particular, an insulating layer is interposed on the array substrate. A pixel electrode and a common electrode are provided, and a plurality of bar-shaped openings are provided in one of the pixel electrode and the common electrode, thereby driving by a fringe field expressed by the pixel electrode and the common electrode around each opening. It is characterized by being.

Due to these structural features, the fringe field switching mode liquid crystal display device has an improved aperture ratio and transmittance compared to a horizontal electric field type liquid crystal display device.

1 is a plan view of a pixel area in an array substrate for a conventional fringe field switching mode liquid crystal display device, and FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1.

As shown in the drawing, a gate electrode 14a and a common electrode 15 are formed on the array substrate 10 in a pixel region defined by crossing the gate wiring 14 and the data wiring 16.

In addition, a gate insulating film 11 is formed on the entire surface of the gate electrode 14a and the common electrode 15, and a semiconductor layer (not shown) is formed on the gate electrode 14a and the gate insulating film 11.

In addition, a source electrode 16a and a drain electrode 16b spaced apart from each other in correspondence with the gate electrode 14a are formed on the semiconductor layer (not shown), and connected to the source electrode 16a on the gate insulating layer 111 Data wiring 16 is formed.

At this time, the gate electrode 14a, the gate insulating layer 11, the semiconductor layer (not shown), and the source and drain electrodes 16a and 16b sequentially stacked form a thin film transistor T.

In addition, a protective layer 12 having a drain contact hole (DCH) exposing a part of the drain electrode 16b is formed on the source and drain electrodes 16a and 16b, and on the protective layer 12 A pixel electrode 13 is formed independently for each pixel region and in contact with the drain electrode 16b through the drain contact hole DCH.

Specifically, the common electrode 15 is formed in each pixel region and is supplied with a reference voltage (hereinafter, a common voltage) for driving the liquid crystal through a common line (not shown) connected to the common electrode 15.

In addition, the pixel electrode 13 includes a plurality of pixel electrode fingers 13a and 13b defining a plurality of first openings OP1 and a pixel electrode connector 13c connecting the pixel electrode fingers 13a and 13b. It is distinguished.

In addition, second openings OP2 are provided on both sides of the pixel electrode 13 to separate it from neighboring pixel electrodes.

In addition, the plurality of pixel electrode fingers 13a and 13b are disposed between the first pixel electrode fingers 13a and 13a disposed on both outermost sides of the plurality of pixel electrode fingers 13a and 13b. The second pixel electrode fingers 13b are divided.

Accordingly, a parabolic fringe field is formed on the pixel electrode fingers 13a and 13b and the common electrode 15.

3A to 3D are views for explaining a process of forming a pixel electrode in an array substrate for a conventional fringe field switching mode liquid crystal display device.

First, a common wiring (not shown) and a common electrode 15 are formed on the array substrate 10, and then a gate insulating layer 11 is formed on the common wiring (not shown) and the common electrode 15.

Next, a data line 16, a source electrode 16a, and a drain electrode 16b are formed on the gate insulating layer 11.

Next, a protective layer 12 including a drain contact hole DCH exposing a portion of the drain electrode 16b is formed on the data line 16, the source electrode 16a, and the drain electrode 16b.

In this case, the protective layer 12 may be made of an organic insulating material, such as photoacrylic, or an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiNx).

Next, as shown in FIG. 3A, a transparent conductive layer 23 is deposited on the protective layer 12 through a deposition method such as sputtering, and the transparent conductive layer 23 is Indium Tin Oxide (ITO). ), Tin Oxide (TO), Indium Zinc Oxide (IZO), Indium Tin Zinc Oxide (ITZO), and the like.

Next, as shown in FIG. 3B, a photoresist layer 33 is formed by applying a photoresist on the transparent conductive layer 23, and the transmissive regions 41a and 41b are blocked on the photoresist layer 33. An exposure mask 40 having regions 43a and 43b is positioned.

Next, as shown in Fig. 3C, after exposing the photoresist layer 33 to light, the photoresist layer (33 in Fig. 3B) is developed to form the photoresist patterns 34a and 34b.

At this time, the photoresist patterns 34a and 34b are formed corresponding to the portion where the pixel electrode 13 is to be formed. In particular, the first photoresist pattern 34a is formed on the portion where the first pixel electrode fingers 13a are to be formed. And, the second photoresist pattern 34b is formed to correspond to the portion where the second pixel electrode finger 13b is to be formed.

Next, as shown in FIG. 3D, etching is performed to remove the transparent conductive layer 23 exposed to the outside of the first and second photoresist patterns 34a and 34b, and thereafter, the first and second photoresists As the patterns 34a and 34b are removed by a strip, the pixel electrode 13 having the first opening OP1, the first and second pixel electrode fingers 13a and 13b, and the pixel electrode connection portion 13c Is formed.

On the other hand, in recent years, the resolution of liquid crystal displays is rapidly progressing, and resolution is defined as the number of pixels displayed per unit area (PPI: pixel per inch), and the high resolution display device is usually 300 PPI (pixel per inch). ) Or higher, and recently, a liquid crystal display device having an ultra-high resolution of 500 PPI or higher is also required.

In addition, in order to realize the high resolution of the liquid crystal display, the number of pixel areas per unit area of the display area displaying an image must be increased, which means that the size of one pixel area is reduced.

Therefore, in order to implement a high PPI liquid crystal display, the widths of the first opening OP1 and the pixel electrode fingers 13a and 13b are formed to be small, for example, 2 to 3 μm. The width of the photoresist patterns 34a and 34b is also formed small.

In addition, in order to prevent display defects of the liquid crystal display device in the fringe field switching mode, the first openings OP1 and the pixel electrode fingers 13a and 13b must have the same width, and accordingly, the first and second openings The photoresist patterns 34a and 34b must have the same width.

In this case, the exposure mask 40 includes a first blocking region 43a corresponding to the first photoresist pattern 34a, a second blocking region 43b corresponding to the second photoresist pattern 34b, and It is disposed outside the first blocking area 43a and is disposed between the first transmission area 41a corresponding to the second opening OP2 and between the blocking areas 43a and 43b and corresponding to the first opening OP1. It is divided into a second transmission area 41b.

In addition, when exposure to the photoresist layer 33 is in progress, two blocking regions 43a and 43b are disposed on both sides of the second transmission region 41b, whereas one blocking region is provided on only one side of the first transmission region 41a. The region 43a is disposed so that light may be transmitted from the first transmission region 41a to the photoresist layer 33 corresponding to the first blocking region 43a.

That is, when the first and second blocking regions 43a and 43b have the same width, the photoresist layer 33 corresponding to the first transmission region 41a is a photoresist corresponding to the second transmission region 41b. The exposure amount may be relatively larger than that of the layer 33.

Accordingly, when developing, the first photoresist pattern 34a may be formed to have a relatively smaller width compared to the second photoresist pattern 34b, and then etching is performed to form the first and second photoresist patterns. (34a, 34b) After removing the transparent conductive layer 23 exposed to the outside and removing the first and second photoresist patterns 34a and 34b by stripping, the width of the first pixel electrode finger 13a P1 may be formed to be relatively smaller than the width P2 of the second pixel electrode finger 13b.

Accordingly, in the conventional fringe field switching mode liquid crystal display, as the widths of the pixel electrode fingers included in one pixel electrode are formed to be different, a problem of display image defects such as spot defects occurs.

The present invention has been devised to solve this problem, and a method of manufacturing an array substrate for a liquid crystal display device capable of preventing display image defects caused by the formation of different widths of pixel electrode fingers included in one pixel electrode Its purpose is to provide.

In order to achieve the above object, the pixel electrode includes a pixel electrode, wherein the pixel electrode includes a first pixel electrode finger disposed on both outermost sides of the pixel electrode and a second pixel electrode disposed between the first pixel electrode finger. A method of manufacturing an array substrate for a liquid crystal display device comprising a finger and a pixel electrode connector connecting the first and second pixel electrodes, the method comprising: forming a common electrode on a substrate and a gate on the upper side of the common electrode and on the front surface of the substrate. Forming an insulating film, forming a data wire on the gate insulating film, forming a protective layer on the data wire and on the entire surface of the substrate, laminating a transparent conductive layer on the protective layer, and the transparent conduction Stacking a photoresist layer on top of the layer and exposing the photoresist layer to light with an exposure mask to form first and second photoresist patterns spaced apart from the data line on the common electrode by a predetermined distance, and the Etching and removing the transparent conductive layer outside the first and second photoresist patterns, and stripping and removing the first and second photoresist patterns, respectively, corresponding to the first and second photoresist patterns. Forming first and second pixel electrode fingers, wherein the exposure mask has first and second blocking regions corresponding to the first and second photoresist patterns, respectively, and A method of manufacturing an array substrate for a liquid crystal display device in which the first and second pixel electrode fingers have the same width by forming the width larger than the width of the second blocking region is provided.

In addition, the width of the first blocking region is characterized in that 105% to 110% of the width of the second blocking region.

In addition, the number of the second pixel electrode fingers may be at least one.

In addition, the common electrode is characterized in that it includes a plurality of common electrode fingers and a common electrode connecting portion connecting the plurality of common electrode fingers.

In addition, the plurality of common electrode fingers are arranged in parallel with the first and second pixel electrode fingers, but are arranged so as not to overlap.

In addition, the transparent conductive layer is Indium Tin Oxide (ITO), Tin Oxide (TO), Indium Zinc Oxide (IZO), Indium Tin Zinc Oxide (ITZO) It is characterized by consisting of, etc.

In addition, the forming of the common electrode includes forming a common wiring connected to the common electrode, a gate electrode and a gate wiring connected to the gate electrode, and forming the data wiring includes: Forming a source electrode connected to a data line and a drain electrode connected to the pixel electrode, wherein the forming of the protective layer includes forming a drain contact hole exposing a portion of the drain electrode The forming of the first and second pixel electrode fingers further includes connecting the pixel electrode and the drain electrode through the drain contact hole.

The array substrate for a liquid crystal display device manufactured according to an exemplary embodiment of the present invention has an effect of preventing display image defects such as spot defects by forming the same widths of pixel electrode fingers included in one pixel electrode.

1 is a plan view of a pixel area in an array substrate for a conventional fringe field switching mode liquid crystal display device.
FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1.
3A to 3D are views for explaining a process of forming a pixel electrode in an array substrate for a conventional fringe field switching mode liquid crystal display device.
4 is a plan view of a pixel area in an array substrate for a fringe field switching mode liquid crystal display device according to an exemplary embodiment of the present invention.
5 is a cross-sectional view taken along line V-V of FIG. 4.
6A to 6D are views for explaining a process of forming a pixel electrode in an array substrate for a fringe field switching mode liquid crystal display device according to an exemplary embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a plan view of a pixel area in an array substrate for a fringe field switching mode liquid crystal display device according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along line V-V of FIG. 4.

As shown in the drawing, a gate electrode 114a and a common electrode 115 are formed on the array substrate 100 in a pixel region defined by crossing the gate wiring 114 and the data wiring 116.

In addition, a gate insulating layer 111 is formed on the entire surface of the gate electrode 114a and the common electrode 115, and a semiconductor layer (not shown) is formed on the gate electrode 114a and the gate insulating layer 111.

In addition, a source electrode 116a and a drain electrode 116b spaced apart from each other in correspondence with the gate electrode 114a are formed on the semiconductor layer (not shown), and are connected to the source electrode 116a on the gate insulating layer 111. The data wiring 116 is formed.

In this case, the gate electrode 114a, the gate insulating layer 111, the semiconductor layer (not shown), and the source and drain electrodes 116a and 116b sequentially stacked form a thin film transistor T.

In addition, a protective layer 112 having a drain contact hole (DCH) exposing a part of the drain electrode 116b is formed on the source and drain electrodes 116a and 116b, and on the protective layer 112 A pixel electrode 113 that is independent for each pixel region and contacts the drain electrode 116b through the drain contact hole DCH is formed.

Specifically, the common electrode 115 is formed in each pixel region and is supplied with a reference voltage (hereinafter, a common voltage) for driving the liquid crystal through a common wiring (not shown) connected to the common electrode 115.

In addition, although the common electrode 115 is formed in a plate shape in the drawing, when the common electrode 115 is formed by being divided into a plurality of common electrode fingers defining a plurality of openings and a common electrode connecting portion connecting the common electrode fingers, a horizontal electric field type A liquid crystal display can be implemented.

In this case, it is preferable that the plurality of common electrode fingers are disposed in parallel with the pixel electrode fingers 13a and 13b to be described later, but are formed so as not to overlap.

Accordingly, the aperture ratio can be improved and the capacity of the storage capacitor can be stably maintained.

The pixel electrode 113 is divided into a plurality of pixel electrode fingers 113a and 113b defining a plurality of first openings OP1 and a pixel electrode connector 113c connecting the pixel electrode fingers 113a and 113b. .

In addition, second openings OP2 are provided on both sides of the pixel electrode 113 to separate it from neighboring pixel electrodes.

In addition, the plurality of pixel electrode fingers 113a and 113b are disposed between the first pixel electrode fingers 113a and 113a disposed on both outermost sides of the plurality of pixel electrode fingers 113a and 113b. The second pixel electrode fingers 113b are divided.

Accordingly, a parabolic fringe field is formed on the pixel electrode fingers 113a and 113b and the common electrode 115, and the liquid crystal molecules are driven by the fringe field to secure a viewing angle of the liquid crystal display. In addition, the aperture ratio is improved.

Meanwhile, in the drawing, the first and second pixel electrode fingers 113a and 113b are shown as four, each of two, but if there are at least one second pixel electrode finger 113b between the first pixel electrode fingers 113a, the present invention Can achieve the effect of.

6A to 6D are views for explaining a process of forming a pixel electrode in an array substrate for a fringe field switching mode liquid crystal display device according to an exemplary embodiment of the present invention.

First, a common wiring (not shown) and a common electrode 115 are formed on the array substrate 100, and then a gate insulating layer 111 is formed on the common wiring (not shown) and the common electrode 115.

Next, a data line 116, a source electrode 116a, and a drain electrode 116b are formed on the gate insulating layer 111.

Next, a protective layer 112 including a drain contact hole DCH exposing a portion of the drain electrode 116b is formed on the data line 116, the source electrode 116a and the drain electrode 116b.

In this case, the protective layer 12 may be made of an organic insulating material, such as photoacrylic, or an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiNx).

Next, as shown in FIG. 6A, a transparent conductive layer 123 is deposited on the protective layer 112 through a deposition method such as sputtering, and the transparent conductive layer 123 is Indium Tin Oxide (ITO). ), Tin Oxide (TO), Indium Zinc Oxide (IZO), Indium Tin Zinc Oxide (ITZO), and the like.

Next, as shown in FIG. 6B, a photoresist layer 133 is formed by applying a photoresist on the transparent conductive layer 123, and the transmissive regions 141a and 141b are blocked on the photoresist layer 133. An exposure mask 140 having regions 143a and 143b is positioned.

Next, as shown in Fig. 6C, after exposure is performed on the photoresist layer 133, the photoresist layer (133 in Fig. 6B) is developed to form the photoresist patterns 134a and 134b.

At this time, the photoresist patterns 134a and 134b are formed corresponding to the portion where the pixel electrode 113 is to be formed. In particular, the first photoresist pattern 134a is formed on the portion where the first pixel electrode finger 113a is to be formed. And, the second photoresist pattern 134b is formed to correspond to the portion where the second pixel electrode finger 113b is to be formed.

Next, as shown in FIG. 6D, etching is performed to remove the transparent conductive layer 123 exposed to the outside of the first and second photoresist patterns 134a and 134b, and thereafter, the first and second photoresists As the patterns 134a and 134b are removed by a strip, the pixel electrode 113 having the second opening OP2, the first and second pixel electrode fingers 113a and 113b, and the pixel electrode connection portion 113c Is formed.

Meanwhile, the exposure mask 140 includes a first blocking region 143a corresponding to the first photoresist pattern 134a, a second blocking region 143b corresponding to the second photoresist pattern 134b, and The first transmission area 141a is disposed outside the blocking area 143a and corresponding to the second opening OP2, and the first transmission area 141a is disposed between the blocking areas 143a and 143b and corresponds to the first opening OP1. It is divided into two transmission areas 141b.

In addition, when exposure is performed on the photoresist layer 133, two blocking regions 143a and 143b are disposed on both sides of the second transmission region 141b, whereas one blocking region is provided on only one side of the first transmission region 141a. The region 143a is disposed so that light may be transmitted from the first transmission region 141a to the photoresist layer 133 corresponding to the first blocking region 143a.

That is, when the widths of the first and second blocking regions 143a and 143b are the same, the photoresist layer 133 corresponding to the first transmission region 141a is a photoresist corresponding to the second transmission region 141b. The exposure amount may be relatively larger than that of the layer 133.

Accordingly, when developing, the first photoresist pattern 134a may have a relatively smaller width compared to the second photoresist pattern 134b, and then etching is performed to form the first and second photoresist patterns. (134a, 134b) After removing the transparent conductive layer 123 exposed to the outside and removing the first and second photoresist patterns 134a and 134b by stripping, the width of the first pixel electrode finger 113a (P1 of FIG. 4) may be formed to be relatively smaller than the width of the second pixel electrode finger 113b (P2 of FIG. 4).

Table 1 below shows experimental results in order to prove that the width of each pixel electrode finger is formed differently when the width of the blocking region of the exposure mask is formed to be the same.

7 is a graph showing the results of Table 1 in an easy-to-understand manner.

Finger 1 Finger 2 Finger 3 Finger 4 Pixel 1 1.770 1.990 1.940 1.810 Pixel 2 1.860 1.990 1.950 1.860 Pixel 3 1.850 1.980 2.020 1.850 Pixel 4 1.590 1.850 1.760 1.550 Pixel 5 1.720 1.940 1.940 1.810 Pixel 6 1.740 1.870 1.870 1.740 Pixel 7 1.880 2.100 2.010 1.880 Pixel 8 2.080 2.130 2.080 1.910 Pixel 9 1.670 1.800 1.850 1.710 Pixel 10 1.680 1.850 1.850 1.680 Pixel 11 1.930 2.150 2.110 1.890 Pixel 12 1.610 1.740 1.830 1.700 Average 1.782 1.949 1.934 1.783

First, Pixels 1 to 12 of FIGS. 7 and 1 are arbitrary pixel electrodes of an array substrate, and Fingers 1 to 4 represent each of the pixel electrode fingers of Pixels 1 to 12 in sequence. In addition, the unit of each result value is µm.

The average values of the widths of Fingers 1 and 2, respectively, placed on the outermost side of the pixel electrode, are 1.782 μm and 1.783 μm, respectively, and the average values of the widths of Fingers 3 and 4, respectively, disposed between Fingers 1 and 2 are 1.949 μm and 1.934 μm to be.

Therefore, it can be found experimentally that the average value of the widths of Fingers 1 and 2 is formed to be about 0.16㎛ smaller than the average value of the widths of Fingers 3 and 4

In the array substrate 100 according to the exemplary embodiment of the present invention, the width of the first blocking area 143a of the exposure mask 140 is larger than that of the second blocking area 143b.

For example, when the widths of the blocking areas 143a and 143b of the exposure mask 140 are the same, the average value of the widths of Fingers 1 and 2 is formed to be about 0.16㎛ less than the average value of the widths of Fingers 3 and 4 Based on the experimental values shown in Fig. 7 and Table 1, the width of the first blocking area 143a of the exposure mask 140 is preferably formed to be 0.1 to 0.2 μm larger than the width of the second blocking area 143b. .

In addition, in terms of this percentage, it is preferable that the width of the first blocking region 143a of the exposure mask 140 is greater than 5% to 10% of the width of the second blocking region 143b.

Accordingly, the exposure amount of the photoresist layer 133 corresponding to the first transmission region 141a may be the same as the exposure amount of the photoresist layer 133 corresponding to the second transmission region 141b, and subsequent development may be performed. Thus, the first photoresist pattern 134a may have the same width as the second photoresist pattern 134b.

Further, subsequent etching is performed to remove the transparent conductive layer 123 exposed to the outside of the first and second photoresist patterns 134a and 134b, and strip the first and second photoresist patterns 134a and 134b. After removal, the width P1 of the first pixel electrode finger 113a may be formed equal to the width P2 of the second pixel electrode finger 113b.

Accordingly, in the liquid crystal display according to an exemplary embodiment of the present invention, since the pixel electrode fingers included in one pixel electrode can have the same width, display image defects such as spot defects can be prevented.

The present invention is not limited to the above-described embodiments, and various changes and modifications are possible without departing from the spirit of the present invention.

100: array substrate
111: gate insulating film
112: protective layer
113a, 113b: first and second pixel electrode fingers
115: common electrode
116: data wiring

Claims (7)

Including a pixel electrode, wherein the pixel electrode comprises a first pixel electrode finger disposed on both outermost sides of the pixel electrode, a second pixel electrode finger disposed between the first pixel electrode finger, and the first and second pixel electrodes In a method of manufacturing an array substrate for a liquid crystal display device comprising a pixel electrode connection portion connecting
Forming a plate-shaped common electrode on the substrate;
Forming a gate insulating layer over the common electrode and over the entire surface of the substrate;
Forming a data line on the gate insulating layer;
Forming a protective layer over the data line and over the entire substrate;
Stacking a transparent conductive layer on the protective layer;
Laminating a photoresist layer on the transparent conductive layer;
Exposing the photoresist layer to light with an exposure mask to form first and second photoresist patterns spaced apart from the data line on the common electrode by a predetermined distance;
Etching and removing the transparent conductive layer outside the first and second photoresist patterns; And
Forming the first and second pixel electrode fingers corresponding to the first and second photoresist patterns, respectively, by stripping and removing the first and second photoresist patterns,
The exposure mask includes first and second blocking regions respectively corresponding to the first and second photoresist patterns, and the first blocking region has a width greater than the width of the second blocking region, thereby forming the first And the second pixel electrode fingers have the same width,
The first pixel electrode finger positioned adjacent to the data line is not positioned to overlap the plate-shaped common electrode, and the remaining first and second pixel electrode fingers are positioned to overlap the common electrode. Method of manufacturing an array substrate.
The method of claim 1,
A method of manufacturing an array substrate for a liquid crystal display, wherein the width of the first blocking region is 105% to 110% of the width of the second blocking region.
The method of claim 1,
A method of manufacturing an array substrate for a liquid crystal display, wherein the second pixel electrode finger is at least one.
delete delete The method of claim 1,
The transparent conductive layer is made of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc. A method of manufacturing an array substrate for a liquid crystal display device.
The method of claim 1,
The forming of the common electrode includes forming a common wire connected to the common electrode, a gate electrode and a gate wire connected to the gate electrode,
The forming of the data line includes forming a source electrode connected to the data line and a drain electrode connected to the pixel electrode,
The forming of the protective layer includes forming a drain contact hole exposing a portion of the drain electrode,
The forming of the first and second pixel electrode fingers further comprises connecting the pixel electrode and the drain electrode through the drain contact hole.

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