KR102230234B1 - Image Mask Processing Circuit Using Switch-Capacitor and Method Thereof - Google Patents

Abstract

The present invention relates to an image mask processing circuit using a switch-capacitor and a method thereof, which perform image mask processing on hardware using the capacitor characteristics. The power consumption can be reduced and processing speed can be improved since it is possible to process in hardware using a switch-capacitor structure in an analog pre-processing process without converting pixel values into digital codes within an image sensor. In addition, since it is easy to operate desired data in an image using the capacitor characteristics, the mask processing can be easily implemented in the hardware.

Description

Image Mask Processing Circuit Using Switch-Capacitor and Method Thereof}

The present invention relates to an image mask processing circuit and method using a switch-capacitor, and more particularly, to an image mask processing circuit and method using a switch-capacitor for performing image mask processing on hardware using capacitor characteristics.

Convolutional Neural Networks (CNN) are a type of deep learning and are mainly used to recognize images. In CNN, a convolution operation, that is, mask processing is required for an image or data, which is generally processed through software.

1 is a diagram showing a conventional image mask process.

Referring to Fig. 1, the conventional image mask processing is generally processed through software. In other words, the process of masking the input image, which is a mask processing process, and then creating the sum of the values obtained by multiplying each pixel and the mask, is processed through software. Therefore, since the process is complicated and the power consumption is large in software processing, the signal processing speed is lowered and the area is also increased.

Korean Patent Publication 10-2008-0069887

An object of the present invention is to provide an image mask processing circuit and method using a switch-capacitor that performs image mask processing within an image sensor itself without using an image signal processor (ISP).

The image mask processing circuit using the switch-capacitor of the present invention for solving the above problem is a first column for storing data information for a first column in a capacitor and outputting data information for the first column stored in the capacitor. A data storage unit and a second column data storage unit for storing data information on a second column adjacent to the first column in a capacitor, and outputting data information on the second column stored in the capacitor, wherein the first Mask processing is performed using data information respectively stored in the column data storage unit and the capacitor of the second column data storage unit.

The capacitor of the first column data storage unit and the capacitor of the second column data storage unit may be formed to be symmetrical to each other.

The first column data storage unit includes: a first column input terminal for applying a reset signal or signal signal for the first column, a first switch for providing the reset signal or signal signal to a capacitor, and data for the reset signal It may include a first reset signal storage unit for storing the signal and a first signal signal storage unit for storing data on the signal signal.

The first reset signal storage unit is connected to the first switch and is connected to a first capacitor to store the reset signal, a second capacitor connected in parallel with the first capacitor, and connected to the second capacitor by a switching operation. A third switch connected to a second switch providing the reset signal to the second capacitor and a reference voltage input terminal, and providing a reference voltage to the first capacitor and the second capacitor through a switching operation may be included. .

The first signal signal storage unit is connected to the first switch, a third capacitor for storing the signal signal, a fourth capacitor connected in parallel with the third capacitor, and connected to the fourth capacitor, by a switching operation. A fifth switch connected to a fourth switch providing the signal signal to the fourth capacitor and a reference voltage input terminal, and providing a reference voltage to the third capacitor and the fourth capacitor through a switching operation may be included. .

The second column data storage unit may include a second column input terminal for applying a reset signal or signal signal for the second column, a sixth switch for providing the reset signal or signal signal to a capacitor, and data for the reset signal It may include a second reset signal storage unit for storing the signal and a second signal signal storage unit for storing data on the signal signal.

The second reset signal storage unit is connected to the sixth switch and connected to a fifth capacitor to store the reset signal, a sixth capacitor connected in parallel with the fifth capacitor, and the sixth capacitor, by a switching operation. An eighth switch connected to a seventh switch providing the reset signal to the sixth capacitor and a reference voltage input terminal, and providing a reference voltage to the fifth capacitor and the sixth capacitor through a switching operation may be included. .

The second signal signal storage unit is connected to the sixth switch, a seventh capacitor for storing the signal signal, an eighth capacitor connected in parallel with the seventh capacitor, and the eighth capacitor, by a switching operation. A tenth switch connected to a ninth switch providing the signal signal to the eighth capacitor and a reference voltage input terminal, and providing a reference voltage to the seventh capacitor and the eighth capacitor through a switching operation may be included. .

It may further include an eleventh switch connecting the first column data storage unit and the second column data storage unit.

The image mask processing method using a switch-capacitor of the present invention for solving the above problem includes storing data information of a first column corresponding to an n-th row and a second column adjacent to the first column in a capacitor. (n is a natural number greater than or equal to 1), storing data information of the first column and the second column corresponding to the n+1th row adjacent to the nth row in a capacitor, and the nth row and the n+1th row And performing mask processing by summing the data information output from the rows.

The storing of the data information of the column corresponding to the n-th row in the capacitor includes applying a first reset signal to the n-th row, storing the applied first reset signal in the capacitor, and the n-th row It may include applying a first signal signal to a row and storing the applied first signal signal in the capacitor.

Storing the data information of the column corresponding to the n+1th row in the capacitor may include applying a second reset signal to the n+1th row and storing the applied second reset signal in the capacitor. And applying a second signal signal to the n+1th row and storing the applied second signal signal in the capacitor.

According to the present invention, the conventional mask processing method has a processing method using software, but the mask processing method according to the present invention performs a basic Correlated Double Sampling (CDS) and at the same time, within the image sensor itself without software processing. Since the convolution operation is performed, power consumption can be reduced and processing speed can be improved.

In addition, since only desired data can be extracted from an image using capacitor characteristics, mask processing can be easily implemented on hardware.

The technical effects of the present invention are not limited to those mentioned above, and other technical effects that are not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a diagram showing a conventional image mask process.
2 is a diagram showing an image sensor according to the present invention.
3 is a diagram showing an embodiment of a mask for explaining image mask processing according to the present invention.
4 is a circuit diagram showing an image mask processing circuit according to the present invention.
5 is an output waveform diagram for explaining the operation of the image mask processing circuit of the present invention.
6 to 9 are circuit diagrams for explaining a method of operating the image mask processing circuit of the present invention.

Since the present invention can apply various transformations and have various embodiments, specific embodiments will be illustrated in the drawings and will be described in detail in the detailed description. However, this is not intended to limit the present invention to a specific embodiment, it should be understood to include all conversions, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the present invention, when it is determined that a detailed description of a related known technology may obscure the subject matter of the present invention, a detailed description thereof will be omitted.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, and in the description with reference to the accompanying drawings, the same or corresponding components are assigned the same reference numbers, and redundant descriptions thereof will be omitted. It should be.

Example

2 is a diagram showing an image sensor according to the present invention.

3 is a diagram showing an embodiment of a mask for explaining image mask processing according to the present invention.

2 and 3, the image sensor according to the present invention has a column parallel structure using a row driver. Accordingly, pixel data is output one row at a time, and two data of a reset signal Vrst and a signal signal Vsig are outputted from one pixel using a 4-tr pixel. With these reset signal (Vrst) and signal signal (Vsig) data, it is possible to detect the difference value (ΔPixel) between the two data by using the switch-capacitor structure of the image mask processing circuit of the present invention. Offsets that are not available can be removed.

For example, as shown in FIG. 3, a 2×2 mask structure may be provided. That is, it may have an Nth row and an N+1th row in a vertical direction, and a C1 and C2th pixel structure in a horizontal direction.

In this mask structure, data for a pixel is output one row at a time, and data for a reset signal Vrst and a signal signal Vsig may be respectively output to each pixel. In addition, such data is converted into a masked value according to a capacitance value stored in a capacitor of the image mask processing circuit, and a convolution operation is simply performed.

4 is a circuit diagram showing an image mask processing circuit according to the present invention.

3 and 4, the image mask processing circuit according to the present invention includes a first column data storage unit 100 and a second column data storage unit 200.

The first column data storage unit 100 stores data information on the first column in a capacitor and outputs data information on the first column stored in the capacitor. Here, the first column may be the nth (n is a natural number greater than or equal to 1) and the n+1th C1 pixel (a,c) in FIG. 3.

In addition, the first column data storage unit 100 includes a first column input terminal C1, a first switch SW1, a first reset signal storage unit 110, and a first signal signal storage unit 120. I can.

The first column input terminal C1 may be connected to the first switch SW1. In addition, a reset signal or a signal signal for a pixel may be applied to the first reset signal storage unit 110 and the first signal signal storage unit 120 by a switching operation of the first switch SW1.

The first reset signal storage unit 110 is connected to the first switch SW1 and stores data on the reset signal input from the first column input terminal C1.

In addition, the first reset signal storage unit 110 may include two capacitors and two switches. That is, the first reset signal storage unit 110 is connected to the first switch SW1, a first capacitor Cbr storing a reset signal, and a second capacitor Car connected in parallel with the first capacitor Cbr. , Connected to the second capacitor (Car), connected to the second switch (SW2) and the reference voltage input terminal (Vref) providing a reset signal to the second capacitor (Car) by a switching operation, A third switch SW3 providing a reference voltage to the first capacitor Cbr and the second capacitor Car may be included.

As an example, a reset signal input from the first column input terminal C1 and a reference voltage input from the reference voltage input terminal Vref by the switching operation of the first switch SW1 and the third switch SW3 are the first Reset signal and reference voltage stored in the capacitor Cbr or input from the first column input terminal C1 by the switching operation of the first switch SW1, the second switch SW2, and the third switch SW3 The reference voltage input from the input terminal Vref may be stored in the first capacitor Cbr and the second capacitor Car, respectively. The data information stored in the first reset signal storage unit 110 may be reset signal information corresponding to the C1 pixels (a,c) in the nth and n+1th rows.

The first signal signal storage unit 120 is connected to the first switch SW1 and stores data on a signal signal input from the first column input terminal C1.

In addition, the first signal signal storage unit 120 may include two capacitors and two switches. That is, the first signal signal storage unit 120 is connected to the first switch (SW1), the third capacitor (Cbs) for storing the signal signal, the fourth capacitor (Cas) connected in parallel with the third capacitor (Cbs) , Connected to the fourth capacitor Cas, connected to the fourth switch SW4 and the reference voltage input terminal Vref for providing a signal signal to the fourth capacitor Cas by a switching operation, and controlled by a switching operation. A fifth switch SW5 providing a reference voltage to the third capacitor Cbs and the fourth capacitor Cas may be included.

As an example, a signal signal input from the first column input terminal C1 and a reference voltage input from the reference voltage input terminal Vref by the switching operation of the first switch SW1 and the fifth switch SW5 are third. A signal signal and a reference voltage stored in the capacitor Cbs or input from the first column input terminal C1 by the switching operation of the first switch SW1, the fourth switch SW4, and the fifth switch SW5. The reference voltage input from the input terminal Vref may be stored in the third capacitor Cbs and the fourth capacitor Cas, respectively. The data information stored in the first signal signal storage unit 120 may be signal signal information corresponding to the C1 pixels (a,c) in the nth and n+1th rows.

The second column data storage unit 200 stores data information on the second column in a capacitor and outputs data information on the second column stored in the capacitor. Here, the second column may be the C2 pixel (b, d) corresponding to the nth and n+1th in FIG. 3.

In addition, the second column data storage unit 200 includes a second column input terminal C2, a sixth switch SW6, a second reset signal storage unit 210, and a second signal signal storage unit 220. I can.

The second column input terminal C2 may be connected to the sixth switch SW6. In addition, a reset signal or a signal signal for a pixel may be applied to the second reset signal storage unit 210 and the second signal signal storage unit 220 by the switching operation of the sixth switch SW6.

The second reset signal storage unit 210 is connected to the sixth switch SW6 and stores data on the reset signal input from the second column input terminal C2.

In addition, the second reset signal storage unit 210 may include two capacitors and two switches. That is, the second reset signal storage unit 210 is connected to the sixth switch SW6, the fifth capacitor Cdr storing the reset signal, and the sixth capacitor Ccr connected in parallel with the fifth capacitor Cdr. , Connected to the sixth capacitor Ccr, connected to the seventh switch SW7 and the reference voltage input terminal Vref for providing a reset signal to the sixth capacitor Ccr by a switching operation, and controlled by a switching operation. It may include an eighth switch SW8 providing a reference voltage to the fifth capacitor Cdr and the sixth capacitor Ccr.

As an example, the reset signal input from the second column input terminal C2 and the reference voltage input from the reference voltage input terminal Vref by the switching operation of the sixth switch SW6 and the eighth switch SW8 are the sixth. Reset signal and reference voltage stored in the capacitor Ccr or input from the second column input terminal C2 by the switching operation of the sixth switch SW6, the seventh switch SW7, and the eighth switch SW8 The reference voltage input from the input terminal Vref may be stored in the fifth capacitor Cdr and the sixth capacitor Ccr, respectively. The data information stored in the second reset signal storage unit 210 may be reset signal information corresponding to the C2 pixels (b,d) in the nth and n+1th rows.

The second signal signal storage unit 220 is connected to the sixth switch SW6 and stores data on a signal signal input from the second column input terminal C2.

In addition, the second signal signal storage unit 220 may include two capacitors and two switches. That is, the second signal signal storage unit 220 is connected to the sixth switch SW6, the seventh capacitor Cds for storing a signal signal, and the eighth capacitor Ccs connected in parallel with the seventh capacitor Cds. , Connected to the eighth capacitor Ccs, connected to the ninth switch SW9 and the reference voltage input terminal Vref for providing a signal signal to the eighth capacitor Ccs by a switching operation, and controlled by a switching operation. A tenth switch SW10 that provides a reference voltage to the seventh capacitor Cds and the eighth capacitor Ccs may be included.

As an example, a signal signal input from the second column input terminal C2 and a reference voltage input from the reference voltage input terminal Vref by the switching operation of the sixth switch SW6 and the tenth switch SW10 are the seventh. Signal signal and reference voltage stored in the capacitor Cds or input from the second column input terminal C2 by the switching operation of the sixth switch SW6, the ninth switch SW9, and the tenth switch SW10 The reference voltage input from the input terminal Vref may be stored in the seventh capacitor Cds and the eighth capacitor Ccs, respectively. The data information stored in the first signal signal storage unit 120 may be signal signal information corresponding to the C1 pixels (b, d) in the nth and n+1th rows.

In addition, an eleventh switch (SW11) for calculating and final outputting data information stored in the first column data storage unit 100 and the data information stored in the second column data storage unit 200 by the switching operation may be further included. I can.

As described above, in the image mask processing circuit according to the present invention, the configuration of the first column data storage unit 100 for storing and outputting data information on the first column and the data information on the second column are stored in the capacitor. By forming and connecting the configurations of the second column data storage unit 200 to be stored and output symmetrically to each other, the reset signal or signal signal information of the C1 and C2 pixels corresponding to the nth or n+1th row can be simultaneously processed. have.

In addition, since each terminal for applying reset information and signal information to a pixel is connected to a capacitor, and data necessary for an image can be calculated using the characteristics of the reset information and signal information stored in the capacitor, the pixel data information within the image sensor It can be processed in hardware using switches and capacitors in the analog preprocessing process without converting the digital code.

Operation mode

5 is an output waveform diagram for explaining the operation of the image mask processing circuit of the present invention.

6 to 9 are circuit diagrams for explaining a method of operating the image mask processing circuit of the present invention.

The image mask processing method of the present invention will be described in detail below with reference to FIGS. 3 to 9.

First, looking at the output waveform diagram of FIG. 5, operation modes are divided into a total of four modes, and a switch to which a clock (CLK) signal is applied and a shape of a signal are defined according to each mode. That is, in mode 1, a reset signal is applied to the nth row, and in mode 2, a signal signal is applied to the nth row. In addition, in mode 3, a reset signal is applied to the n+1th row, and in mode 4, a signal signal is applied to the n+1th row.

Here, the switching operation according to the applied clock signal is based on the first switch SW1 and the sixth switch SW6 by the CLK1 signal, and the third switch SW3 and the eighth switch SW8 and the CLK3 signal by the CLK2 signal. By the second switch (SW2) and the seventh switch (SW7), the fifth switch (SW5) and the tenth switch (SW10) by the CLK4 signal, the fourth switch (SW4) and the ninth switch (SW9) by the CLK5 signal Can be controlled on/off respectively.

6 shows a circuit configuration according to Mode 1 of FIG. 5. Referring to FIGS. 3, 5 and 6, the circuit operation according to mode 1 will be described. In mode 1, CLK1, CLK2 and CLK2 are used to input reset signals corresponding to pixels C1 and C2 of the Nth row (a, b) The CLK3 clock signal is applied, and the first switch SW1, the second switch SW2, the third switch SW3, the sixth switch SW6, and the seventh switch SW7 are applied by the clock signals of CLK1, CLK2 and CLK3. ) And the eighth switch SW8 are turned on. That is, the C1R1 signal, which is the reset signal of the C1 pixel (a) of the N-th row, is applied to the first column input terminal (C1), and the C2 pixel (b) of the N-th row is reset to the second column input terminal (C2). The signal C2R1 is applied.

Therefore, by the switching operation of the first switch SW1, the second switch SW2, and the third switch SW3, the reference voltage Vref and the N-th row are applied to the first capacitor Cbr and the second capacitor Car. Each of the reset values Vref-C1R1 of the C1 pixel (a) for may be stored. In addition, the reference voltage Vref and the N-th row are applied to the fifth capacitor Cdr and the sixth capacitor Ccr by the switching operation of the sixth switch SW6, the seventh switch SW7, and the eighth switch SW8. Vref-C2R1, which is a reset value of the C2 pixel b for, may be stored, respectively.

7 shows a circuit configuration according to mode 2 of FIG. 5. Referring to FIGS. 3, 5 and 7, the circuit operation according to mode 2 will be described. In mode 2, CLK1, CLK4 and The clock signal of CLK5 is applied, and the first switch (SW1), the fourth switch (SW4), the fifth switch (SW5), the sixth switch (SW6), the ninth switch ( SW9) and the tenth switch SW10 are turned on. That is, the C1S1 signal, which is the signal signal of the C1 pixel (a) of the N-th row, is applied to the first column input terminal (C1), and the signal of the C2 pixel (b) of the N-th row is applied to the second column input terminal (C2). The signal C2S1 is applied.

Accordingly, the reference voltage Vref and the N-th row are applied to the third capacitor Cbs and the fourth capacitor Cas by the switching operation of the first switch SW1, the fourth switch SW4, and the fifth switch SW5. Each of the signal values C1S1-Vref of the C1 pixel (a) for may be stored. In addition, by the switching operation of the sixth switch SW6, the ninth switch SW9, and the tenth switch SW10, the seventh capacitor Cds and the eighth capacitor Ccs have a reference voltage Vref and an N-th row. C2S1-Vref, which is the signal value of the C2 pixel (b) for, may be stored, respectively.

Subsequently, FIG. 8 shows a circuit configuration according to mode 3 of FIG. 5. Referring to FIGS. 3, 5, and 8, the circuit operation according to mode 3 will be described. In mode 3, CLK1 and CLK1 and The CLK2 clock signal is applied, and the first switch SW1, the third switch SW3, the sixth switch SW6, and the eighth switch SW8 are turned on by the clock signals of CLK1 and CLK2. That is, the C1R2 signal, which is the reset signal of the C1 pixel c of the N+1th row, is applied to the first column input terminal C1, and the C2 pixel (in the N+1th row) is applied to the second column input terminal C2. The C2R2 signal, which is the reset signal of d), is applied.

Accordingly, by the switching operation of the first switch SW1 and the third switch SW3, the reference voltage Vref and the reset value of the C1 pixel c for the N+1 row are Vref in the first capacitor Cbr. -C1R2 is saved. In addition, by the switching operation of the sixth switch SW6 and the eighth switch SW8, the fifth capacitor Cdr has a reference voltage Vref and a reset value Vref of the C2 pixel d for the N+1th row. -C2R2 can be saved. In this case, the amount of charge stored in the second capacitor Car and the sixth capacitor Ccr does not change.

9 shows a circuit configuration according to mode 4 of FIG. 5. Referring to FIGS. 3, 5, and 9, the circuit operation according to mode 4 will be described. In mode 4, CLK1 and CLK1 and The CLK4 clock signal is applied, and the first switch SW1, the fifth switch SW5, the sixth switch SW6, and the tenth switch SW10 are turned on by the clock signals of CLK1 and CLK4. That is, the C1S2 signal, which is the signal signal of the C1 pixel c of the N+1th row, is applied to the first column input terminal C1, and the C2 pixel of the N+1th row is applied to the second column input terminal C2. The C2S2 signal, which is the signal signal of d), is applied.

Therefore, by the switching operation of the first switch SW1 and the fifth switch SW5, the third capacitor Cbs has a reference voltage Vref and a signal value C1S2 of the C1 pixel c for the N+1th row. -Vref is saved. In addition, by the switching operation of the sixth switch SW6 and the tenth switch SW10, the seventh capacitor Cds has a reference voltage Vref and C2S2, which is a signal value of the C2 pixel d for the N+1th row. -Vref can be saved. In this case, the amount of charge stored in the fourth capacitor Cas and the eighth capacitor Ccs does not change.

As described above, after storing desired data in each capacitor by the operation of mode 1 to mode 4, the first switch SW1 is turned off, the second switch SW2, the fourth switch SW4, and the fifth switch ( When SW5) is operated, Vx values corresponding to the C1 pixels (a,c) of the nth and n+1th rows can be obtained. Here, the Vx value can be expressed as Equation 1 by the Q=CV equation.

In addition, when the first switch SW1 is turned off and the seventh switch SW7, the ninth switch SW9, and the tenth switch SW10 are operated, the C2 pixels (b, d) of the nth and n+1th rows are operated. You can find the Vy value corresponding to ). Here, the Vy value can be expressed as Equation 2 by the Q=CV equation.

Finally, when the eleventh switch SW11 operates and Vx and Vy are connected, the final output Vout value can be obtained. Here, the Vout value can be expressed as Equation 3.

That is, it is converted into a masked value according to the difference in capacitance values stored in the capacitors of Vx corresponding to the first column data storage unit 100 and Vy corresponding to the second column data storage unit 200. It simply performs a convolution operation. In addition, unwanted offsets occurring in pixels can be removed through the capacitance difference value ΔPixel.

As described above, the conventional image mask processing method has a processing method using software, but the mask processing method according to the present invention does not convert pixel values into digital codes in the image sensor, and changes the switch-capacitor structure in the analog preprocessing By using it, it is possible to process on hardware, so power consumption can be reduced and processing speed can be improved. In addition, since it is easy to calculate desired data in an image by using the capacitor characteristics, mask processing can be easily implemented on hardware.

On the other hand, the embodiments of the present invention disclosed in the specification and drawings are merely presented specific examples to aid understanding, and are not intended to limit the scope of the present invention. In addition to the embodiments disclosed herein, it is obvious to those of ordinary skill in the art that other modified examples based on the technical idea of the present invention may be implemented.

100: first column data storage unit 110: first reset signal storage unit
120: first signal signal storage unit 200: second column data storage unit
210: second reset signal storage unit 220: second signal signal storage unit
Cbr: 1st capacitor Car: 2nd capacitor
Cbs: 3rd capacitor Cas: 4th capacitor
Cdr: 5th Capacitor Ccr: 6th Coffee Sat
Cds: 7th Capacitor Ccs: 8th Coffee Sat
SW1: first switch (SW1) SW2: second switch
SW3: 3rd switch SW4: 4th switch
SW5: 5th switch SW6: 6th switch
SW7: 7th switch SW8: 8th switch
SW9: 9th switch SW10: 10th switch
SW11: 11th switch

Claims (12)

A first column data storage unit that stores data information on a first column in a capacitor and outputs data information on the first column stored in the capacitor; And
A second column data storage unit storing data information on a second column adjacent to the first column in a capacitor and outputting data information on the second column stored in the capacitor,
Mask processing is performed using data information stored in capacitors of the first column data storage unit and the second column data storage unit, respectively,
The first column data storage unit and the second column data storage unit are connected, and data information stored in the first column data storage unit and the data information stored in the second column data storage unit are calculated by a switching operation, and the final output is performed. Including an eleventh switch,
The first column data storage unit may include: a first column input terminal for applying a reset signal or a signal signal to the first column; A first switch for providing the reset signal or signal signal to a capacitor; A first reset signal storage unit for storing data on the reset signal; And a first signal signal storage unit for storing data on the signal signal,
The first reset signal storage unit may include: a first capacitor connected to the first switch and storing the reset signal; A second capacitor connected in parallel with the first capacitor; A second switch connected to the second capacitor and providing the reset signal to the second capacitor by a switching operation; And a third switch connected to a reference voltage input terminal and providing a reference voltage to the first capacitor and the second capacitor by a switching operation. The method of claim 1,
An image mask processing circuit using a switch-capacitor, wherein the capacitor of the first column data storage unit and the capacitor of the second column data storage unit are formed to be symmetric with each other. delete delete The method of claim 1, wherein the first signal signal storage unit,
A third capacitor connected to the first switch and storing the signal signal;
A fourth capacitor connected in parallel with the third capacitor;
A fourth switch connected to the fourth capacitor and providing the signal signal to the fourth capacitor by a switching operation; And
An image mask processing circuit using a switch-capacitor comprising a fifth switch connected to a reference voltage input terminal and providing a reference voltage to the third capacitor and the fourth capacitor by a switching operation. The method of claim 1, wherein the second column data storage unit,
A second column input terminal for applying a reset signal or a signal signal to the second column;
A sixth switch for providing the reset signal or the signal signal to the capacitor;
A second reset signal storage unit for storing data on the reset signal; And
An image mask processing circuit using a switch-capacitor comprising a second signal signal storage unit that stores data for the signal signal. The method of claim 6, wherein the second reset signal storage unit,
A fifth capacitor connected to the sixth switch and storing the reset signal;
A sixth capacitor connected in parallel with the fifth capacitor;
A seventh switch connected to the sixth capacitor and providing the reset signal to the sixth capacitor by a switching operation; And
An image mask processing circuit using a switch-capacitor comprising an eighth switch connected to a reference voltage input terminal and providing a reference voltage to the fifth capacitor and the sixth capacitor by a switching operation. The method of claim 6, wherein the second signal signal storage unit,
A seventh capacitor connected to the sixth switch and storing the signal signal;
An eighth capacitor connected in parallel with the seventh capacitor;
A ninth switch connected to the eighth capacitor and providing the signal signal to the eighth capacitor by a switching operation; And
An image mask processing circuit using a switch-capacitor comprising a tenth switch connected to a reference voltage input terminal and providing a reference voltage to the seventh capacitor and the eighth capacitor by a switching operation. delete Storing data information of a first column corresponding to an n-th row and a second column adjacent to the first column in a capacitor of a first column data storage unit and a capacitor of a second column data storage unit, respectively (n is 1 More than one natural number);
storing data information of the first column and the second column corresponding to the n+1th row in a capacitor of the first column data storage unit and a capacitor of the second column data storage unit, respectively; And
And performing mask processing by summing data information respectively stored in the capacitor of the first column data storage unit and the capacitor of the second column data storage unit,
The first column data storage unit and the second column data storage unit are connected, and data information stored in the first column data storage unit and the data information stored in the second column data storage unit are calculated by a switching operation, and the final output is performed. Including a switch to do,
The first column data storage unit may include: a first column input terminal for applying a reset signal or a signal signal to the first column; A first switch for providing the reset signal or signal signal to a capacitor; A first reset signal storage unit for storing data on the reset signal; And a first signal signal storage unit for storing data on the signal signal,
The first reset signal storage unit may include: a first capacitor connected to the first switch and storing the reset signal; A second capacitor connected in parallel with the first capacitor; A second switch connected to the second capacitor and providing the reset signal to the second capacitor by a switching operation; And a third switch connected to a reference voltage input terminal and providing a reference voltage to the first capacitor and the second capacitor by a switching operation. The method of claim 10, wherein storing data information of a pixel corresponding to the n-th row in a capacitor of the first column data storage unit,
Applying a first reset signal to the n-th row and storing the applied first reset signal in a capacitor of the first column data storage unit; And
And applying a first signal signal to the n-th row and storing the applied first signal signal in a capacitor of the first column data storage unit. The method of claim 10, wherein storing the data information of the pixel corresponding to the n+1th row in the capacitor of the second column data storage unit comprises:
Applying a second reset signal to the n+1th row and storing the applied second reset signal in a capacitor of the second column data storage unit; And
And applying a second signal signal to the n+1th row and storing the applied second signal signal in a capacitor of the second column data storage unit.

Images