KR102227413B1 - Logic device and manufacturing method thereof - Google Patents

Abstract

The present invention discloses a logic element as a plurality of transistors in which a passivation layer is formed of a material having a work function that is different from a work function of an amorphous oxide semiconductor channel layer to cover at least a portion of a top surface of the amorphous oxide semiconductor channel layer between a source electrode and a drain electrode. In particular, according to the invention, the passivation layer is formed of a material having a work function that is larger or smaller than the work function of the amorphous oxide semiconductor channel layer, and a relative difference in a contact area between the passivation layer of the transistors and the top surface of the amorphous oxide semiconductor channel layer is adjusted based on the above configuration, so that a level of movement of electrons between the passivation layer and the amorphous oxide semiconductor channel layer is adjusted, and thus the transistors are designed to operate as one of a relative depletion-type transistor and a relative enhancement-type transistor. Therefore, according to the related art, it is difficult to implement an enhancement-type transistor or a p-type channel layer when oxide is applied as a material for a channel layer, so that it is difficult to manufacture a complementary logic element. However, according to the present invention, the relative depletion-type transistor and the relative enhancement-type transistor in which oxide is applied to the channel layer as described above are applied, so that the complementary logic element is implemented and manufactured simply and advantageously.

Description

Logic device and its manufacturing method {LOGIC DEVICE AND MANUFACTURING METHOD THEREOF}

The present invention relates to a logic device, and more particularly, to a logic device that can be implemented with transistors in which an amorphous oxide is applied to a channel layer material.

In addition, the present invention relates to a method of manufacturing the logic device.

Recently, amorphous oxide semiconductors are being applied in earnest to next-generation electric and electronic products, and are used, for example, in organic light-emitting diodes (OLEDs) or active matrix LCDs as active channel layers of thin-film transistors (TFTs).

Since such amorphous oxide semiconductor is composed of a metal-oxide matrix and a conduction band is composed of a spherical ns orbital, it is advantageous because it exhibits high carrier mobility despite being amorphous.

Nevertheless, it is generally difficult to implement a p-type channel layer with an amorphous oxide semiconductor due to the characteristics of an amorphous oxide, and most are n-type channel layers. Therefore, it is difficult to implement a complementary logic device including both an n-type channel transistor and a p-type channel transistor with an amorphous oxide semiconductor, making it difficult to develop a technology that can effectively apply an amorphous oxide semiconductor to the manufacture of a logic device. Is requested.

1. Unexamined Patent Publication No. 10-2017-0123860 (November 9, 2017)

2. Registered Patent Publication No. 10-1413657 (2014. 6. 24)

Accordingly, an object of the present invention is to provide a logic device and a method of manufacturing the same, which can be implemented with transistors in which an amorphous oxide is applied to a channel layer material.

In order to solve the above problem, a logic device according to an aspect of the present invention includes a plurality of transistors electrically connected to each other, and the plurality of transistors are each formed in turn on a substrate, a gate electrode, a gate insulating layer, and an amorphous oxide semiconductor. A channel layer, a source electrode and a drain electrode formed to be spaced apart from each other on an upper surface of the amorphous oxide semiconductor channel layer, and formed to cover at least a part of an upper surface of the amorphous oxide semiconductor channel layer in a region between the source electrode and the drain electrode. And a passivation layer having a work function smaller than that of the amorphous oxide semiconductor channel layer, wherein the plurality of transistors include at least one first transistor having a first contact area between the passivation layer and an upper surface of the amorphous oxide semiconductor channel layer. , Consisting of a combination of one or more second transistors having a second contact area between the passivation layer and an upper surface of the amorphous oxide semiconductor channel layer and connected to the one or more first transistors, wherein the first contact area is greater than the second contact area. It is larger, and the first transistor has a relatively lower threshold voltage than the second transistor and operates as a driving transistor, and the second transistor has a relatively higher threshold voltage than the first transistor and operates as a load transistor.

In addition, a logic device according to another aspect of the present invention includes a plurality of transistors electrically connected to each other, wherein each of the plurality of transistors includes a gate electrode, a gate insulating layer, and an amorphous oxide semiconductor channel layer sequentially formed on a substrate, and the A source electrode and a drain electrode formed to be spaced apart from each other on an upper surface of the amorphous oxide semiconductor channel layer, and the amorphous oxide semiconductor channel layer formed to cover at least a portion of the upper surface of the amorphous oxide semiconductor channel layer in a region between the source electrode and the drain electrode And a passivation layer having a work function greater than a work function of, wherein the plurality of transistors include at least one first transistor having a first contact area between the passivation layer and an upper surface of the amorphous oxide semiconductor channel layer, the passivation layer, and Consisting of a combination of one or more second transistors having a second contact area between upper surfaces of the amorphous oxide semiconductor channel layer and connected to the one or more first transistors, the first contact area is larger than the second contact area, and the second contact area is larger than the second contact area. The second transistor has a relatively lower threshold voltage than the first transistor and operates as a driving transistor, and the first transistor has a relatively higher threshold voltage than the second transistor and operates as a load transistor.

In addition, optionally, the passivation layer of each of the first and second transistors may have the same width, and the passivation layer of the first transistor may have a length greater than that of the passivation layer of the second transistor.

In addition, optionally, the passivation layer of each of the first and second transistors may have a length shorter than that of the amorphous oxide semiconductor channel layer and may be spaced apart from the source electrode and the drain electrode.

Also, optionally, a distance between the passivation layer and the source electrode and the drain electrode may be 1 μm or more.

Also, optionally, the logic device may be one of an inverter, a NAND logic device, a NOR logic device, an encoder, a decoder, a MUX, a DEMUX, and a sense amplifier.

In addition, optionally, the first transistor may be a more depletion mode than the second transistor, and the second transistor may be a relatively more enhancement mode than the first transistor.

In addition, optionally, the first transistor may be a relatively increased type compared to the second transistor, and the second transistor may be a relatively more depleted type than the first transistor.

In addition, optionally, the passivation layer is indium zinc oxide (In-ZnO), tin oxide (SnO ₂ ), tin oxide (Zn-SnO), indium tin oxide (In-SnO), indium silicon oxide (ISO), Indium tin oxide (ITO), nickel (Ni), copper (Cu), indium (In), magnesium (Mg), tungsten (W), molybdenum (Mo), titanium (Ti), gold (Au), silver (Ag) ) And aluminum (Al).

In addition, optionally, the passivation layer may further include at least one material selected from the group consisting of a group I element, a group II element, a group III element, a group IV element, a group V element, and a lanthanum element.

In addition, optionally, the amorphous oxide semiconductor channel layer is silicon (Si), indium (In), zinc (Zn), tin (Sn), nitrogen (N), magnesium (Mg), niobium (Nb), aluminum (Al ), gold (Au), copper (Cu), germanium (Ge), titanium (Ti), lithium (Li), potassium (K), tungsten (W), molybdenum (Mo), antimony (Sb), yttrium ( It may be composed of an amorphous oxide including at least one selected from the group consisting of Y), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), and gallium (Ga). In addition, preferably, the composition of the amorphous oxide semiconductor channel layer may be SiZnSnO or SiInZnO. In addition, more preferably, the SiZnSnO is a silicon (Si) in the range of 0.01wt% to 40wt%, zinc (Zn) in the range of 20wt% to 80wt%, and tin in the range of 0.01wt% to 70wt%, respectively, relative to the total amount (Sn), and the SiInZnO may be 10 wt% or less of silicon (Si), 10 wt% to 95 wt% of indium (In), and 80 wt% or less of zinc (Zn) based on the total amount.

In addition, optionally, the composition of the substrate is a silicon substrate doped with a high concentration, polyimide (PI), polyamide (PA), polyamide-imide, polyurethane (polyurethane, PU). ), polyurethane acrylate (PUA), polyacrylamide (PA), polyethylene terephthalate (PET), polyether sulfone (PES), polyethylene naphthalate (PEN), Polycarbonate (PC), polymethylmethacrylate (PMMA), polyetherimide (PEI), polydimethylsiloxane (PDMS), polyethylene (PE), polyvinyl alcohol ( At least one selected from the group consisting of polyvinyl alcohol, PVA), polystyrene (PS), biaxially oriented PS (BOPS), acrylic resin, silicone resin, fluorine resin, modified epoxy resin, silicone, glass and tempered glass It may include.

In addition, optionally, the composition of the gate electrode is a silicon substrate doped with a high concentration, indium tin oxide (ITO), gallium zinc oxide (GZO), indium gallium zinc oxide (Indium Gallium Zinc Oxide); IGZO), Indium Gallium Oxide (IGO), Indium Zinc Oxide (IZO), Indium Oxide (In ₂ O ₃ ), Si, Mo, Al, Ag, Au, Cu and Ta It may include one or more selected from.

In addition, optionally, the composition of the gate insulating layer is silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), and tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O) at least one selected from the group consisting of Can include.

In addition, optionally, the substrate, the gate electrode, and the structure formed of the gate insulating layer may form ^{a p ++} -Si substrate or an N ⁺⁺ -Si substrate _{having a silicon oxide (SiO 2} ) film formed on an upper surface thereof.

In addition, optionally, each composition of the passivation layer and the amorphous oxide semiconductor channel layer may be the same between the plurality of transistors, respectively.

In addition, the method of manufacturing a logic device according to another aspect of the present invention is to sequentially form a gate electrode, a gate insulating layer, and an amorphous oxide semiconductor channel layer on a substrate, and spaced apart from each other on the upper surface of the amorphous oxide semiconductor channel layer. After forming a source electrode and a drain electrode, forming a passivation layer to cover at least a part of an upper surface of the amorphous oxide semiconductor channel layer in a region between the source electrode and the drain electrode to manufacture a plurality of transistors, the plurality of transistors A method of manufacturing a logic device comprising electrically connecting, wherein the forming of the passivation layer comprises: selecting a material of the passivation layer to have a work function smaller than that of the amorphous oxide semiconductor channel layer; and Some of the plurality of transistors operate as a relative depletion-type transistor having a relatively lower threshold voltage, and the other part operates as a relative increase-type transistor having a relatively higher threshold voltage. And adjusting the size of the contact area between the passivation layer and the amorphous oxide semiconductor channel layer to be relatively larger, and electrically connecting the plurality of transistors includes the part of the plurality of transistors as a driving transistor. And connecting the other parts to each other to form an electrical circuit to operate as a load transistor.

In addition, the method of manufacturing a logic device according to another aspect of the present invention is to sequentially form a gate electrode, a gate insulating layer, and an amorphous oxide semiconductor channel layer on a substrate, and spaced apart from each other on the upper surface of the amorphous oxide semiconductor channel layer. After forming a source electrode and a drain electrode, forming a passivation layer to cover at least a part of an upper surface of the amorphous oxide semiconductor channel layer in a region between the source electrode and the drain electrode to manufacture a plurality of transistors, the plurality of transistors A method of manufacturing a logic device comprising electrically connecting, wherein the forming of the passivation layer includes selecting a material of the passivation layer to have a work function greater than that of the amorphous oxide semiconductor channel layer; and Some of the plurality of transistors operate as a relative depletion type transistor having a relatively lower threshold voltage, and the other part operates as a relative increase type transistor having a relatively higher threshold voltage. And adjusting the size of the contact area between the passivation layer and the amorphous oxide semiconductor channel layer to be relatively smaller, wherein the step of electrically connecting the plurality of transistors includes the part of the plurality of transistors as a driving transistor. And connecting the other parts to each other to form an electrical circuit to operate as a load transistor.

Also, optionally, each composition of the passivation layer and the amorphous oxide semiconductor channel layer may be selected equally among the plurality of transistors, respectively.

According to the present invention, the passivation layer is made of a material having a work function greater than or less than that of the amorphous oxide semiconductor channel layer, and based on this, the passivation layer and the top surface of the amorphous oxide semiconductor channel layer of the plurality of transistors By controlling the relative difference between the contact areas between each other, the level at which electrons move between the passivation layer and the amorphous oxide semiconductor channel layer can be controlled, and accordingly, the plurality of transistors operate as one of a relative depletion type transistor and a relative increase type transistor. Can be designed to

Accordingly, according to the present invention, while applying the oxide to the channel layer, it is possible to implement and manufacture a complementary logic device simply and advantageously by applying the relative depletion transistor and the relative increase transistor according to the present invention.

1A and 1B each show a transistor according to an embodiment of the present invention.
2A to 2B are energy band diagrams for explaining a phenomenon in which electrons move between the conduction bands of the material of the passivation layers P1 and P2 and the amorphous oxide semiconductor channel layers C1 and C2 according to the present invention,
2A shows electron transfer from the passivation layer to the amorphous oxide semiconductor channel layer;
Figure 2b, on the contrary, shows electron transfer from the amorphous oxide semiconductor channel layer to the passivation layer.
3 shows the electrical characteristics of the first and second transistors of FIGS. 1A to 1B in which the passivation layer has a work function smaller than that of the amorphous oxide semiconductor channel layer and the length of each passivation layer is different, as shown in FIG. 2A. It is a graph.
4A to 4B illustrate an inverter (NOT logic device) manufactured according to an embodiment of the present invention, and FIG. 4A is a relative depletion transistor (“D-mode”) and a relative depletion transistor (“D-mode”) according to an embodiment of the present invention. It shows the structure of an inverter (NOT logic device) manufactured with an incremental transistor ("E-mode"), but in the transistors used, the passivation layer has a work function smaller than the work function of the amorphous oxide semiconductor channel layer. ;
4B shows an equivalent circuit diagram of the inverter shown in FIG. 4A.
4C is a variation of the embodiment shown in FIG. 4A, according to another embodiment of the present invention. In contrast to the embodiment of FIG. 4A, the passivation layer is an amorphous oxide semiconductor channel layer in transistors used in the inverter circuit. A structure of an inverter (NOT logic device) made of a relative depletion transistor ("D-mode") and a relative increase transistor ("E-mode") configured to have a work function greater than the work function of is shown.
5A and 5B are graphs showing the characteristics of the NOT logic circuit of the inverter of FIG. 4A,
5A shows input voltage (V _in )-output voltage (V _out ) characteristics;
Figure 5b shows the input voltage (V _in )-voltage gain (Gain) characteristics.
6A-6B illustrate a NAND logic device manufactured according to another embodiment of the present invention,
6A shows a structure of a NAND logic device implemented with one relative depletion transistor ("D-mode") and two relative increase transistors ("E-mode"), but transistors used in the same manner as in FIG. 4A In the case where the passivation layer has a work function smaller than that of the amorphous oxide semiconductor channel layer;
6B is an equivalent circuit diagram (left) and operation operation (right) of the NAND logic element of FIG. 6A.
In addition, FIG. 6C is a variation of the embodiment shown in FIG. 6A according to another embodiment of the present invention. In contrast to the embodiment of FIG. 6A, the passivation layer is an amorphous oxide semiconductor in transistors used in the NAND logic circuit. A structure of a NAND logic device made of a relative depletion transistor ("D-mode") and a relative increase transistor ("E-mode") configured to have a work function greater than the work function of the channel layer is shown.
7A-7B illustrate a NOR logic device manufactured according to another embodiment of the present invention,
7A shows a structure of a NOR logic device implemented with one relative depletion transistor ("D-mode") and two relative increase transistors ("E-mode"), but transistors used in the same manner as in FIG. 4A In the case where the passivation layer has a work function smaller than that of the amorphous oxide semiconductor channel layer;
Fig. 7B shows an equivalent circuit diagram (left) and operation operation (right) of the NOR logic element of Fig. 7A.
In addition, FIG. 7C is a variation of the embodiment shown in FIG. 7A according to another embodiment of the present invention. In contrast to the embodiment of FIG. 7A, the passivation layer is an amorphous oxide semiconductor in transistors used in the NOR logic circuit. A structure of a NOR logic device made of a relative depletion transistor ("D-mode") and a relative increase transistor ("E-mode") configured to have a work function greater than that of the channel layer is shown.

The present invention discloses a logic device configurable as a plurality of transistors to which an amorphous oxide is applied as a semiconductor channel layer material.

First, as will be described below, the logic device of the present invention is of two types referred to as "relative depletion mode transistor" and "relative enhancement mode transistor", which are terms used herein. It is composed of a plurality of transistors.

In particular, the term "relative" here simply refers to which one has a relatively higher or lower threshold voltage between the two types of transistors. That is, the term "relative depletion transistor" as used herein refers to a transistor having a relatively lower threshold voltage, that is, a relatively more depletion-type transistor than that of a "relative increase transistor". In addition, as an opposite concept, the term "relatively increasing transistor" as used herein refers to a transistor having a relatively higher threshold voltage, that is, a relatively higher increasing type compared to the "relative depletion transistor".

Then, the present invention will be described in detail with reference to the accompanying drawings.

First, FIGS. 1A and 1B each show a transistor according to an embodiment of the present invention.

1A-1B, the first transistor of FIG. 1A and the second transistor of FIG. 1B are sequentially gate electrodes G1 and G2, gate insulating layers GI1 and GI2, and an amorphous oxide semiconductor on a substrate SUB. Channel layers C1 and C2 are formed, and source electrodes S1 and S2 and drain electrodes D1 and D2 are formed on the amorphous oxide semiconductor channel layers C1 and C2 to be spaced apart from each other.

In the present invention, the amorphous oxide semiconductor channel layer (C1, C2) is, for example, silicon (Si), indium (In), zinc (Zn), tin (Sn), nitrogen (N), magnesium (Mg), niobium (Nb) ), aluminum (Al), gold (Au), copper (Cu), germanium (Ge), titanium (Ti), lithium (Li), potassium (K), tungsten (W) molybdenum (Mo), antimony (Sb) ), yttrium (Y), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), gallium (Ga), etc. It may be composed of, as examples, may be composed of SiZnSnO or SiInZnO. The amorphous oxide semiconductor channel layers C1 and C2 may be formed by a conventional process including PVD or CVD.

In particular, the first and second transistors are formed to cover at least a portion of the upper surfaces of the amorphous oxide semiconductor channel layers C1 and C2 in the region between the source electrodes S1 and S2 and the drain electrodes D1 and D2, It further includes passivation layers P1 and P2 made of a material different from the oxide semiconductor channel layers C1 and C2.

In the present invention, these passivation layers P1 and P2 are made of a material having a work function different from (ie, relatively larger or smaller) from the amorphous oxide semiconductor channel layers C1 and C2.

The basic mechanism according to this will be described with reference to Figs. 2a to 2b, and Figs. 2a to 2b show that electrons move between the conduction bands of the passivation layers P1 and P2 and the amorphous oxide semiconductor channel layers C1 and C2 materials according to the present invention. It is an energy band diagram to explain the phenomenon.

First, as shown in FIG. 2A, in the first and second transistor structures of FIGS. 1A to 1B, the work function of the materials of the passivation layers P1 and P2 is greater than the work function of the materials of the amorphous oxide semiconductor channel layers C1 and C2. As the value is smaller, electron injection in which electrons of the material of the passivation layers P1 and P2 move to the conduction band of the material of the amorphous oxide semiconductor channel layers C1 and C2 smoothly occurs.

That is, when the passivation layers P1 and P2 are made of a material having a smaller work function than the material of the amorphous oxide semiconductor channel layers C1 and C2, the threshold voltage is higher than that of the transistors in which the passivation layers P1 and P2 are not formed. Electrical characteristics are improved because it becomes a so-called depletion mode mechanism that decreases.

For example, such a depletion mechanism is that the amorphous oxide semiconductor channel layers (C1, C2) have a Si-Zn-SnO (work function of approximately 4.53 eV) composition, and the passivation layers (P1, P2) are indium silicon oxide (ISO) (approximately 4.49 eV), indium tin oxide (ITO) (approximately 4.51 eV), Ti/Al (approximately 3.92 eV) or Al (approximately 3.79 eV) composition.

Conversely, as shown in FIG. 2B, when the passivation layers P1 and P2 are made of a material having a larger work function than the material of the amorphous oxide semiconductor channel layers C1 and C2, conversely, electrons are transferred to the amorphous oxide semiconductor channel layer ( As the threshold voltage moves from C1 and C2 to the passivation layers P1 and P2, it becomes a so-called enhancement mode mechanism in which the threshold voltage increases, so electrical characteristics are degraded.

For example, this incremental mechanism is a combination in which the composition of the amorphous oxide semiconductor channel layers (C1, C2) is Si-Zn-SnO (approximately 4.53 eV) and the composition of the passivation layers (P1, P2) is Ag (approximately 4.64 eV). Can be implemented in the case of.

In an embodiment of the present invention, the passivation layers P1 and P2 are indium zinc oxide (In-ZnO), tin oxide (SnO ₂ ), tin zinc oxide (Zn-SnO), and indium tin oxide (In-SnO). , Silicon oxide (ISO), indium tin oxide (ITO), nickel (Ni), copper (Cu), indium (In), magnesium (Mg), tungsten (W), molybdenum (Mo), titanium (Ti), From the group consisting of gold (Au), silver (Ag), and aluminum (Al), one or more materials lower than the work function of the amorphous oxide semiconductor channel layer C may be selected.

In addition, in another embodiment of the present invention, the passivation layer (P1, P2) is a group I element such as lithium (Li) or potassium (K), magnesium (Mg), calcium (Ca), or strontium in addition to the material. Group II elements such as (Sr), group III elements such as gallium (Ga), aluminum (Al), indium (In) or yttrium (Y), titanium (Ti), zirconium (Zr), silicon (Si), tin Group IV elements such as (Sn) or germanium (Ge), group V elements such as tantalum (Ta), vanadium (V), niobium (Nb) or antimony (Sb), or lanthanum (La), cerium (Ce), Praseodymium (Pr), Neodymium (Nd), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolithium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er) , A lanthanum (Ln)-based element such as thulium (Tm), ytterbium (Yb), or rutedium (Lu) may be further included.

Hereinafter, in the present specification, in order to avoid repetitive description of the basic principle on which the present invention is based, the passivation layers P1 and P2 are basically used as a work function smaller than that of the amorphous oxide semiconductor channel layers C1 and C2 materials, as shown in FIG. 2A. The present invention will be described with a focus on configuring a logic device by transistors of a depletion mechanism made of a material having a material.

Accordingly, the present invention is not limited thereto, and the passivation layers P1 and P2 are larger than those of the amorphous oxide semiconductor channel layers C1 and C2 as shown in FIG. 2B instead of FIG. 2A according to the basic principle of the present invention to be described below. A logic device can naturally be configured by transistors of an incremental mechanism made of a material having a function, and this is also included in the scope of the present invention.

3 shows that the passivation layer has a work function smaller than that of the amorphous oxide semiconductor channel layer, and the first transistor (Fig. 1a) has a longer passivation layer (P1) than the second transistor (Fig. 1b), as shown in Fig. 2a. It is a graph showing the electrical characteristics of the structure.

Referring to FIG. 3, both the first and second transistors formed so that the passivation layers P1 and P2 cover portions of the upper surfaces of the amorphous oxide semiconductor channel layers C1 and C2 have a lower threshold voltage in the negative (-) direction. Type, but in particular, by adjusting the relative lengths of the passivation layers P1 and P2 of the first and second transistors, the first transistor (FIG. 1A) has a relatively negative threshold voltage than the second transistor (FIG. 1B). It is implemented as a relatively depletion transistor that is slightly lower in the (-) direction, that is, a relatively more depletion type, and the second transistor (FIG. 1B) has a relatively positive threshold voltage than the first transistor (FIG. 1A). It can be seen that it is implemented with a relatively incremental transistor that is slightly higher in the direction, that is, a relatively incremental type.

The logic device according to the present invention is composed of a plurality of transistors of any one of two types: such a relative depletion transistor (eg, the first transistor in FIG. 1A) and a relative increase transistor (eg, the second transistor in FIG. 1B).

To this end, in one embodiment of the present invention, first, when the passivation layer is made of a material having a work function smaller than that of the amorphous oxide semiconductor channel layer material, the passivation layer of the relative depletion transistor is It is designed to have a wider contact area with the surface of the amorphous oxide semiconductor channel layer than the passivation layer.

That is, the larger the contact area between the passivation layer and the surface of the amorphous oxide semiconductor channel layer, the larger the region where the electron injection mechanism for moving electrons from the passivation layer to the amorphous oxide semiconductor channel layer occurs, thereby increasing the threshold voltage of the transistor. It is formed in a more depletion type that becomes lower.

As an embodiment, referring to FIGS. 1A to 1B, the passivation layer P1 of the first transistor is longer than the passivation layer P2 of the second transistor, and thus electrons to the amorphous oxide semiconductor channel layer C1 Since the implantation region is relatively larger, when the first and second transistors of FIGS. 1A to 1B are electrically connected and combined, the first transistor operates as a relative depletion transistor and the second transistor operates as a relative increase transistor. can do. Each of these electrical characteristics is confirmed in FIG. 3.

In addition, on the contrary, in another embodiment of the present invention, when the passivation layer is made of a material having a work function greater than that of the amorphous oxide semiconductor channel layer material, contrary to the above, the passivation layer and the amorphous oxide semiconductor channel layer surface The wider the contact area of, the greater the area in which electrons move from the amorphous oxide semiconductor channel layer to the passivation layer, and thus the threshold voltage of the transistor becomes higher.

Therefore, contrary to the above, the first transistor (FIG. 1A) having a larger contact area between the passivation layer and the amorphous oxide semiconductor channel layer surface is a relative increase-type transistor, and the second transistor (FIG. 1B) having a smaller contact area is relatively It can operate as a depletion transistor.

As described above, according to the present invention, by configuring the relative depletion type transistor(s) as a driving transistor and the relative increasing type transistor(s) as a load transistor, various known logic devices including NAND and NOR can be configured. .

And, preferably, for precise and simple control, the relative depletion type and relative increase type transistors consist of the amorphous oxide semiconductor channel layer of each transistor made of the same material, and the amorphous oxide semiconductor channel layer of each transistor and the passivation thereon It can be designed by arbitrarily adjusting the contact area between layers.

In one embodiment of the present invention, the width of the passivation layers P1 and P2 is the same as the width of the amorphous oxide semiconductor channel layers C1 and C2 as shown in FIGS. 1A to 1B, but the passivation layer P1 , P2) Each length can be achieved by designing differently.

In addition, the passivation layers (P1, P2) are source electrodes (S1, S2) and drain electrodes (D1, D2) for good electrical isolation from the surrounding source electrodes (S1, S2) and drain electrodes (D1, D2). It is preferable to design the minimum separation distance between the and approximately 1㎛.

In addition, in another embodiment, the control of the contact area may be achieved by designing different widths and/or lengths of each of the passivation layers P1 and P2.

In addition, since the passivation layer can block transmission of light, oxygen, moisture, and/or impurities from the outside to the amorphous oxide semiconductor channel layer, the electrical characteristics of the transistor can be improved. In one embodiment, in order to effectively block the transmission, the thickness of the passivation layer of the present invention may be approximately 4 nm or more.

In addition, in an embodiment of the present invention, the substrate (SUB) is a silicon substrate doped with a high concentration, polyimide (PI), polyamide (PA), polyamide-imide, Polyurethane (PU), polyurethane acrylate (PUA), polyacrylamide (PA), polyethylene terephthalate (PET), polyether sulfone (PES), polyethylene naphthalate ( polyethylene naphthalate (PEN), polycarbonate (PC), polymethylmethacrylate (PMMA), polyetherimide (PEI), polydimethylsiloxane (PDMS), polyethylene (PE) ), polyvinyl alcohol (PVA), polystyrene (PS), biaxially oriented PS (BOPS), acrylic resin, silicone resin, fluorine resin, modified epoxy resin, silicone, glass and tempered glass. It may be one or more selected from the group consisting of.

In addition, in an embodiment of the present invention, the gate electrodes G1 and G2 are a silicon substrate doped with a high concentration, indium tin oxide (ITO), which are transparent conductive oxides, and gallium zinc oxide (GZO). ), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Oxide (IGO), Indium Zinc Oxide (IZO), Indium Oxide (In ₂ O ₃ ), Si, Mo, It may be one or more selected from the group consisting of Al, Ag, Au, Cu, and Ta.

In addition, in an embodiment of the present invention, the gate insulating layers GI1 and GI2 are silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), and titanium oxide ( TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O), and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O) It may be one or more selected from the group consisting of. _{In one embodiment, silicon oxide (SiO 2} ) is used as the gate insulating film (GI), and ^{the p ++} -Si substrate or N ⁺⁺ -Si substrate on which it is deposited is the integrated substrate (SUB)-gate electrode (G) -Can be used as a gate insulating film (GI).

In addition, in an embodiment of the present invention, the composition of the source electrode (S1, S2) and the drain electrode (D1, D2) is gold (Au), silver (Ag), copper (Cu), aluminum (Al), titanium It may be one or more selected from the group consisting of (Ti), tungsten (W), molybdenum (Mo), ITO, and ISO.

Preferred embodiments of the present invention as described above will be further described below. However, the embodiments described below by the present invention are provided to aid in an overall understanding of the present invention, and the present invention is not limited to the following examples.

Example: Fabrication of Relative Depletion Transistors and Relative Incremental Transistors

A gate insulating layer was formed with _{an oxide film (SiO 2} ) having a thickness of 50 to 200 nm on the upper end of the ^{P ++} -Si or N ^{++ -Si substrate.} In addition, an amorphous oxide semiconductor thin film layer composed of SiZnSnO or SiInZnO was deposited and photographed using the RF sputtering technique, and heat treatment was performed to activate the channel, increase the density, and remove impurities. Preferred examples of the composition of SiZnSnO are silicon (Si) in the range of 0.01wt% to 40wt%, zinc (Zn) in the range of 20wt% to 80wt%, and tin (Sn) in the range of 0.01wt% to 70wt%, respectively, based on the total amount. ), and preferred examples of the composition of SiInZnO are 10 wt% or less of silicon (Si), 10 wt% to 95 wt% of indium (In), and 80 wt% or less of zinc (Zn) based on the total amount. In addition, a source/drain electrode layer was deposited and formed using a photolithography method, and a passivation layer was deposited and formed.

The passivation layer is formed of a material (eg, Ag) that is smaller than the work function of the amorphous oxide semiconductor channel layer (eg, ISO, ITO, Ti/Al, or Al, etc.) or has a larger work function. The width was the same as the width of the amorphous oxide semiconductor channel layer, but the length was formed to be shorter than the length of the amorphous oxide semiconductor channel layer.

And, in order to implement two types of transistors used in the embodiments described below, that is, a relative depletion transistor ("D-mode") and a relative increase transistor ("E-mode"), another transistor used together Compared with the length of the passivation layer of, when the passivation layer has a work function smaller than the work function of the amorphous oxide semiconductor channel layer, the relative depletion transistor (eg, FIG. 1A) has a relatively longer length of the passivation layer, In the relative increase transistor (eg, FIG. 1B), the length of the passivation layer is relatively shorter. For example, when the length of the amorphous oxide semiconductor thin film layer is about 50 μm, the length of the passivation layer of the relative depletion transistor may be about 40 μm, and the length of the passivation layer of the relative depletion transistor may be about 20 μm.

Conversely, when the passivation layer material in the transistors used has a work function greater than the work function of the amorphous oxide semiconductor channel layer, the relative depletion transistor ("D-mode") has a relative length of the passivation layer. The length of the passivation layer is formed to be shorter (eg, FIG. 1B), and in the case of the relative increase-type transistor, the length of the passivation layer is relatively longer (eg, FIG.

Example: Manufacturing Inverter (NOT Logic Device)

4A is a diagram illustrating a structure of an inverter (NOT logic device) made of a relative depletion transistor ("D-mode") and a relative increase transistor ("E-mode") according to an embodiment of the present invention. This is the case in which the passivation layer has a work function smaller than that of the amorphous oxide semiconductor channel layer in the transistors. And, Fig. 4B shows an equivalent circuit diagram of the inverter shown in Fig. 4A.

The inverter of FIG. 4A is a serial connection by combining the transistors of FIGS. 1A and 1B and operates as a relative depletion transistor (D-mode) and a relative increase transistor (E-mode), respectively, and the relative depletion transistor (D-mode) is a driving transistor, and the relative increase-type transistor (E-mode) functions as a load transistor.

_{Accordingly, a power source V DD} is connected to the drain electrode D1 of the transistor D-mode, and an input voltage (V DD) is connected to the gate electrode terminal GT2 connected to the gate electrode G2 of the transistor E-mode. V _in ) can be applied.

In addition, a gate electrode terminal GT1 connected to the source electrode S1 of the transistor D-mode, the drain electrode D2 of the transistor E-mode, and the gate electrode G1 of the transistor D-mode. ) May be commonly connected to the output terminal V _out , and the source electrode S2 of the transistor E-mode may be grounded.

In addition, the substrate (SUB), gate electrodes (G1, G2), gate insulating layers (GI1, GI2), amorphous oxide semiconductor channel layers (C1, C2), and passivation layers in each transistor (D-mode and E-mode). The (P1, P2), the source electrodes (S1, S2), and the drain electrodes (D1, D2) may be formed of the same material both of the two transistors (D-mode and E-mode).

However, as described in the previous embodiment, the width of each passivation layer (P1, P2) is the same as the width of each amorphous oxide semiconductor channel layer (C), but the length of the passivation layer (P1) is the length of the passivation layer (P2). By designing to be formed to be larger, the relative depletion transistor D-mode on the left has a lower threshold voltage than the relative increase transistor E-mode on the right.

Table 1 below summarizes the electrical characteristics of each of the relative depletion transistor (D-mode) and the relative increase transistor (E-mode) constituting the inverter of FIG. 4A.

V _th
(V) I _on
(A) I _off
(A) I _On/Off μ _FE
(cm ² /V _s ) SS
(V/decade) V _hy
(V) Relative depletion
Transistor (D-mode) 0.27 6.22.E-04 4.27.E-12 1.46.E+08 45.45 0.56 1.31 Relative increase
Transistor (E-mode) 0.83 3.11.E-04 5.75.E-12 5.42.E+07 24.31 0.57 1.74

In addition, FIGS. 5A and 5B are graphs showing the characteristics of the NOT logic circuit of the inverter of FIG. 4A, in which FIG. 5A is an input voltage (V _in )-output voltage (V _out ), and FIG. 5B is an input voltage (V _in ). -It shows the characteristics of voltage gain, respectively.

Referring to FIG. 5A, the operation of the inverter logic circuit of FIG. 4A is largely described in three areas as follows:

(i) First, when the input voltage V _in as the first region is lower than the driving voltage of the relative incremental transistor E-mode, the power V _DD is output as an output _{voltage V out.}

(ii) And, as the second region, when the input voltage (V _in ) is greater than or equal to the driving voltage of the relative increasing transistor (E-mode), the inverter circuit of FIG. 4A has a full-swing characteristic and an output The voltage (V _out ) drops to almost 0V.

(iii) And, as a third region, the relative increase-type transistor E-mode exhibits an operating characteristic in which the _{output voltage V out is maintained at 0V when fully opened.}

(iv) However, in the relative depletion transistor D-mode, since the gate electrode G1 and the source electrode S1 are connected to each other, the circuit is always in an ON state when the circuit is driven.

In addition, referring to FIG. 5B, _{it can be seen that in the inverter circuit of FIG. 4A, when the power supply V DD} is 5V, the maximum voltage gain is displayed. Table 2 below summarizes the maximum voltage gain value according to the change of the _{power source (V DD} ) in the inverter circuit of FIG. 4A.

V _DD =1V V _DD =2V V _DD =3V V _DD =4V V _DD =5V Voltage gain
(Gain) 0.6225 2.755 6.4595 11.9695 15.8915

On the other hand, contrary to FIG. 4A, when the passivation layer has a work function greater than the work function of the amorphous oxide semiconductor channel layer in the transistors used in the inverter circuit, as described above, the transistor arrangement of FIG. 4A may be reversed. .

That is, a transistor having a relatively larger contact area between the passivation layer and the upper surface of the amorphous oxide semiconductor channel layer (i.e., the left transistor having the passivation layer P1 of FIG. 4A) becomes a relative increase-type transistor (E-mode), and the A transistor having a relatively smaller contact area (that is, a transistor on the right side having a passivation layer P2 in FIG. 4A) becomes a relative depletion transistor (D-mode).

Therefore, in this case, as shown in FIG. 4C, the relative increase transistor E-mode having the passivation layer P1 is a load transistor, and the relative depletion transistor D-mode having the passivation layer P2 is As the driving transistor, the inverter element can be configured by being disposed to be reversed from that of FIG. 4A.

Examples: Manufacturing of a NAND logic device and a NOR logic device

6A is a structure of a NAND logic device manufactured by connecting one relative depletion type transistor (“D-mode”) and two relative increase type transistors (“E-mode”) according to another embodiment of the present invention. However, as shown in FIG. 4A, in the transistors used, the passivation layer has a work function smaller than that of the amorphous oxide semiconductor channel layer. Further, FIG. 6B shows an equivalent circuit diagram and operation operation of the NAND logic device of FIG. 6A.

7A is a NOR logic manufactured by connecting one relative depletion transistor ("D-mode") and two relative increase transistors ("E-mode") according to another embodiment of the present invention. The structure of the device is shown, but in the transistors used as in FIG. 4A, the passivation layer has a work function smaller than that of the amorphous oxide semiconductor channel layer. And, Fig. 7B shows an equivalent circuit diagram and operation operation of the NOR logic element of Fig. 7A.

The NAND logic device and the NOR logic device in the embodiment of the present invention are constructed according to the basic circuit configurations of well-known NAND logic circuits and NOR logic circuits, as shown in Figs. 6A to 6B and 7A to 7B. In addition, for the NAND logic device and the NOR logic device, a relative depletion transistor ("D-mode") and a relative increase transistor ("E-mode") used in the inverter circuit of FIG. 4A may be similarly used.

In the present embodiment (Figs. 6A to 6B), in the case of a NAND logic circuit, a relative depletion type transistor (D-mode) as a driving transistor and two relative increase type transistors (E-mode) as a load transistor are formed using wire bonding. It is connected in series.

In addition, in the present embodiment (Figs. 7A to 7B), in the case of a NOR logic circuit, a relative depletion type transistor (D-mode) as a driving transistor using wire bonding, and two relative increase type transistors connected in parallel with each other as a load transistor. (E-mode) is connected in series.

In the present embodiments, the NAND logic device and the NOR logic device exhibit sufficient operating characteristics when voltages of -10V and 10V are applied to each of _{V IN1} and V _IN2 after fixing _{V DD to 5V, for example.} In other words, V _OUT is output close to the V _DD set value 5V (digital signal "1 (High)"), and when the relative incremental transistor (E-mode) is operated, V _OUT drops to 0V (digital signal "0 ( Low)") is observed. As a result, it is observed that the NAND logic device and the NOR logic device according to the present embodiments perform the same operation as the truth table shown on the right side of FIGS. 6B and 7B.

Meanwhile, in transistors used in NAND and NOR logic devices, when the passivation layer has a work function greater than the work function of the amorphous oxide semiconductor channel layer, the transistor arrangements of FIGS. 6A and 7A are reversed.

That is, similar to FIG. 4C above, a transistor having a relatively larger contact area between the passivation layer and the upper surface of the amorphous oxide semiconductor channel layer (i.e., the left transistor having the passivation layer P1 of FIG. 6A; the passivation layer P1 of FIG. 7A) ) Is a relatively incremental transistor (E-mode), and a transistor having a relatively smaller contact area (i.e., a right transistor having passivation layers P2 and P2' of FIG. 6A; The right transistor having passivation layers P2 and P2') becomes a relative depletion transistor D-mode.

Therefore, in this case, as shown in FIGS. 6C and 7C, respectively, the relative increase transistor E-mode having the passivation layers P1 and P1' is the load transistor on the right, and the relative increase-type transistor E-mode has the passivation layer P2. The depletion transistor (D-mode) is a driving transistor on the left, and is disposed so that the arrangement of each other is reversed, thereby constituting a NAND logic device and a NOR logic device.

As described above, according to the present invention, the passivation layer is formed of a material having a work function different from that of the amorphous oxide semiconductor channel layer so as to cover at least a part of the upper surface of the amorphous oxide semiconductor channel layer between the source electrode and the drain electrode. The device can be configured.

In particular, according to the present invention, the passivation layer is made of a material having a work function greater or less than the work function of the amorphous oxide semiconductor channel layer, and based on this, the passivation layer and the amorphous oxide semiconductor channel layer of the plurality of transistors By controlling the relative difference between the contact areas between the upper surfaces, the level at which electrons move between the passivation layer and the amorphous oxide semiconductor channel layer can be controlled, and accordingly, the plurality of transistors are one of a relative depletion type transistor and a relative increase type transistor. It can be designed to work.

Therefore, conventionally, when an oxide is applied as a channel layer material, it has been difficult to implement an incremental transistor or a p-type channel layer, making it difficult to manufacture a complementary logic device, but in the present invention, a relative depletion transistor in which an oxide is applied to the channel layer as described above. And it is possible to implement and manufacture a complementary logic device simply and advantageously by applying a relative increase-type transistor.

Above, the above-described preferred embodiments and examples of the present invention are disclosed for the purpose of illustration, and anyone of ordinary skill in the relevant field can make various modifications, changes, additions, etc. within the spirit and scope of the present invention. And, such modifications, changes, additions, etc. should be regarded as belonging to the scope of the claims.

As an example, the relative depletion transistor (D-mode) and the relative increase transistor (E-mode) according to the present invention are examples of logic devices, such as the inverter (NOT logic device), NAND logic device, and NOR logic device. In addition, it can be applied to well-known logic devices such as encoders, decoders, MUX, DEMUX, and sense amplifiers.

SUB: Substrate
G1, G2, G1', G2': gate electrode
GI1, GI2, GI1', GI2': gate insulating layer
C1, C2, C1', C2': amorphous oxide semiconductor channel layer
S1, S2, S1', S2': source electrode
D1, D2, D1', D2': drain electrode
P1, P2, P1', P2': passivation layer
GT1, GT2, GT1', GT2': Gate electrode terminal
D-mode: relative depletion transistor
E-mode: relative incremental transistor

Claims (22)

In the logic device comprising a plurality of transistors electrically connected to each other,
Each of the plurality of transistors
A gate electrode, a gate insulating layer, and an amorphous oxide semiconductor channel layer sequentially formed on the substrate;
A source electrode and a drain electrode formed to be spaced apart from each other on an upper surface of the amorphous oxide semiconductor channel layer;
A passivation layer formed to cover at least a part of an upper surface of the amorphous oxide semiconductor channel layer in a region between the source electrode and the drain electrode, and having a work function smaller than that of the amorphous oxide semiconductor channel layer,
The plurality of transistors have at least one first transistor having a first contact area between the passivation layer and an upper surface of the amorphous oxide semiconductor channel layer, and a second contact area between the passivation layer and an upper surface of the amorphous oxide semiconductor channel layer. It is composed of a combination of one or more second transistors connected to the first transistor, wherein the first contact area is larger than the second contact area,
The first transistor has a relatively lower threshold voltage than the second transistor and operates as a driving transistor, and the second transistor has a relatively higher threshold voltage than the first transistor and operates as a load transistor. device. In the logic device comprising a plurality of transistors electrically connected to each other,
Each of the plurality of transistors
A gate electrode, a gate insulating layer, and an amorphous oxide semiconductor channel layer sequentially formed on the substrate;
A source electrode and a drain electrode formed to be spaced apart from each other on an upper surface of the amorphous oxide semiconductor channel layer;
A passivation layer formed to cover at least a portion of an upper surface of the amorphous oxide semiconductor channel layer in a region between the source electrode and the drain electrode, and having a work function greater than that of the amorphous oxide semiconductor channel layer,
Each composition of the passivation layer and the amorphous oxide semiconductor channel layer is the same between the plurality of transistors,
The plurality of transistors have at least one first transistor having a first contact area between the passivation layer and an upper surface of the amorphous oxide semiconductor channel layer, and a second contact area between the passivation layer and an upper surface of the amorphous oxide semiconductor channel layer. It is composed of a combination of one or more second transistors connected to the first transistor, wherein the first contact area is larger than the second contact area,
The second transistor has a relatively lower threshold voltage than the first transistor and operates as a driving transistor, and the first transistor has a relatively higher threshold voltage than the second transistor and operates as a load transistor. device. The method according to claim 1 or 2,
The passivation layer of each of the first and second transistors has the same width, and the passivation layer of the first transistor has a length greater than that of the passivation layer of the second transistor. The method according to claim 1 or 2,
The passivation layer of each of the first and second transistors has a length shorter than that of the amorphous oxide semiconductor channel layer and is spaced apart from the source electrode and the drain electrode. The method of claim 4,
A logic device, wherein the passivation layer is spaced apart from the source electrode and the drain electrode of 1 μm or more. The method according to claim 1 or 2,
The logic device is one of an inverter, a NAND logic device, a NOR logic device, an encoder, a decoder, a MUX, a DEMUX, and a sense amplifier. The method of claim 1
The first transistor is a relatively more depletion mode compared to the second transistor, and the second transistor is a relatively more enhancement mode than the first transistor. According to claim 2
The first transistor is a logic device, characterized in that a relatively more incremental type than the second transistor, and the second transistor is a relatively more depletion type than the first transistor. The method according to claim 1 or 2,
The passivation layer is indium zinc oxide (In-ZnO), tin oxide (SnO ₂ ), tin zinc oxide (Zn-SnO), indium tin oxide (In-SnO), indium silicon oxide (ISO), indium tin oxide (ITO). ), nickel (Ni), copper (Cu), indium (In), magnesium (Mg), tungsten (W), molybdenum (Mo), titanium (Ti), gold (Au), silver (Ag) and aluminum (Al Logical device, characterized in that consisting of at least one material selected from the group consisting of ). The method of claim 9,
The passivation layer further comprises at least one material selected from the group consisting of a group I element, a group II element, a group III element, a group IV element, a group V element, and a lanthanum element. The method according to claim 1 or 2,
The amorphous oxide semiconductor channel layer includes silicon (Si), indium (In), zinc (Zn), tin (Sn), nitrogen (N), magnesium (Mg), niobium (Nb), aluminum (Al), gold (Au). ), copper (Cu), germanium (Ge), titanium (Ti), lithium (Li), potassium (K), tungsten (W), molybdenum (Mo), antimony (Sb), yttrium (Y), hafnium ( Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), and a logic device comprising an amorphous oxide containing at least one selected from the group consisting of gallium (Ga). The method according to claim 1 or 2,
The composition of the amorphous oxide semiconductor channel layer is a logic device, characterized in that SiZnSnO or SiInZnO. The method according to claim 1 or 2,
The composition of the amorphous oxide semiconductor channel layer is a logic device, characterized in that it comprises a component having the following content range relative to the total amount.
10 wt% or less of silicon (Si);
Indium (In) 10 wt% to 95 wt%; And
Zinc (Zn) 80wt% or less. The method according to claim 1 or 2,
The composition of the amorphous oxide semiconductor channel layer is a logic device, characterized in that it comprises a component having the following content range relative to the total amount.
0.01 wt% to 40 wt% silicon (Si);
Zinc (Zn) 20wt% to 80wt%; And
Tin (Sn) 0.01wt% to 70wt%. The method according to claim 1 or 2,
The composition of the substrate is a highly doped silicon substrate, polyimide (PI), polyamide (PA), polyamide-imide, polyurethane (polyurethane, PU), polyurethane acrylic Polyurethaneacrylate (PUA), polyacrylamide (PA), polyethylene terephthalate (PET), polyether sulfone (PES), polyethylene naphthalate (PEN), polycarbonate, PC), polymethylmethacrylate (PMMA), polyetherimide (PEI), polydimethylsiloxane (PDMS), polyethylene (PE), polyvinyl alcohol (PVA) , Polystyrene (PS), biaxially oriented polystyrene (biaxially oriented PS, BOPS), acrylic resin, silicone resin, fluorine resin, modified epoxy resin, silicon, glass, and tempered glass. Logic device. The method according to claim 1 or 2,
The composition of the gate electrode is a silicon substrate doped with a high concentration, indium tin oxide (ITO), gallium zinc oxide (GZO), indium gallium zinc oxide (IGZO), and indium oxide. Gallium (Indium Gallium Oxide; IGO), indium zinc oxide (Indium Zinc Oxide; IZO), indium oxide (In ₂ O ₃ ), Si, Mo, Al, Ag, Au, one or more selected from the group consisting of Cu and Ta Logic device comprising a. The method according to claim 1 or 2,
The composition of the gate insulating layer is silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), and tantalum oxide (Ta ₂ O ₅ ). , Barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O) characterized by comprising at least one selected from the group consisting of Logic device. The method according to claim 1 or 2,
The substrate, the gate electrode, and the structure formed of the gate insulating layer constitute a p ⁺⁺ -Si substrate or an N ⁺⁺ -Si substrate having a _{silicon oxide (SiO 2) film formed on an upper surface thereof.} The method according to claim 1 or 2,
Each composition of the passivation layer and the amorphous oxide semiconductor channel layer is the same between the plurality of transistors, respectively. A gate electrode, a gate insulating layer, and an amorphous oxide semiconductor channel layer are sequentially formed on a substrate, a source electrode and a drain electrode are formed to be spaced apart from each other on an upper surface of the amorphous oxide semiconductor channel layer, and in a region between the source electrode and the drain electrode A method of manufacturing a logic device comprising forming a passivation layer to cover at least a part of an upper surface of the amorphous oxide semiconductor channel layer to fabricate a plurality of transistors, and then electrically connecting the plurality of transistors,
The step of forming the passivation layer
Selecting a constituent material of the passivation layer to have a smaller work function than a constituent material of the amorphous oxide semiconductor channel layer;
Some of the plurality of transistors operate as a relative depletion type transistor having a relatively lower threshold voltage, and the other part operates as a relative increase type transistor having a relatively higher threshold voltage. Including the step of relatively larger the size of the contact area between the passivation layer and the amorphous oxide semiconductor channel layer of,
The step of electrically connecting the plurality of transistors comprises forming an electric circuit by connecting one part of the plurality of transistors to operate as a driving transistor and the other part to operate as a load transistor. Method of manufacturing a logic device. A gate electrode, a gate insulating layer, and an amorphous oxide semiconductor channel layer are sequentially formed on a substrate, a source electrode and a drain electrode are formed to be spaced apart from each other on an upper surface of the amorphous oxide semiconductor channel layer, and in a region between the source electrode and the drain electrode A method of manufacturing a logic device comprising forming a passivation layer to cover at least a part of an upper surface of the amorphous oxide semiconductor channel layer to fabricate a plurality of transistors, and then electrically connecting the plurality of transistors,
The step of forming the passivation layer
Selecting a constituent material of the passivation layer to have a larger work function than a constituent material of the amorphous oxide semiconductor channel layer;
Some of the plurality of transistors operate as a relative depletion type transistor having a relatively lower threshold voltage, and the other part operates as a relative increase type transistor having a relatively higher threshold voltage. Including the step of relatively smaller the size of the contact area between the passivation layer and the amorphous oxide semiconductor channel layer,
The step of electrically connecting the plurality of transistors comprises forming an electric circuit by connecting one part of the plurality of transistors to operate as a driving transistor and the other part to operate as a load transistor. Method of manufacturing a logic device. The method of claim 20 or 21,
Each composition of the passivation layer and the amorphous oxide semiconductor channel layer is selected equally among the plurality of transistors, respectively.

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