KR101413657B1 - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof are disclosed. The disclosed semiconductor device may be a complementary device including a p-type oxide thin film transistor and an n-type oxide thin film transistor. For example, the disclosed semiconductor device may be a logic device such as an inverter, a NAND device, a NOR device, or the like.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device and a manufacturing method thereof.

The present disclosure relates to a semiconductor device and a manufacturing method thereof.

Transistors are widely used as switching devices or driving devices in the field of electronic devices. In particular, since a thin film transistor can be manufactured on a glass substrate or a plastic substrate, it is useful in the field of flat panel display devices such as a liquid crystal display device or an organic light emitting display device.

In order to improve the operational characteristics of a transistor, a method of applying an oxide layer having a high carrier mobility, for example, a ZnO-based material layer, as a channel layer has been attempted. This method is mainly applied to a thin film transistor for a flat panel display.

When a silicon layer is used as a channel layer, an n-channel metal-oxide semiconductor (NMOS) transistor and a p-channel metal-oxide semiconductor (PMOS) transistor can be manufactured easily by changing the kind of element to be doped in the channel layer And thus it is easy to implement complementary metal oxide semiconductor (CMOS) devices. However, in the case of a transistor having an oxide layer as a channel layer, it is difficult to realize a complementary element.

One aspect of the disclosure provides a semiconductor device comprising at least two different oxide transistors.

Another aspect of the disclosure provides a method of manufacturing the semiconductor device.

One embodiment of the present invention is a thin film transistor including a first thin film transistor including a first source, a first drain, a first channel layer, and a first gate; And a second thin film transistor including a second source, a second drain, a second channel layer, and a second gate, wherein one of the first and second channel layers is a p-type oxide layer and the other is n Type oxide layer.

The first and second thin film transistors may have a bottom gate structure or a top gate structure.

One of the first and second thin film transistors may be a bottom gate structure, and the other may be a top gate structure.

At least one of the first and second thin film transistors may have a dual gate structure including another gate.

The first source and the first drain may be in contact with an upper surface or a lower surface at both ends of the first channel layer.

The second source and the second drain may be in contact with the upper surface or the lower surface at both ends of the second channel layer.

The first source and the first drain may include a first material layer in contact with both ends of the first channel layer and the second source and the second drain may have a second material layer in contact with both ends of the second channel layer, Material layer. The first and second material layers may be different material layers.

The first material layer may be in contact with the upper surface of the first channel layer and the second material layer may be in contact with the upper surface or the lower surface of the second channel layer.

The first source and the first drain may have a double-layer structure. In this case, the second source and the second drain may have a single-layer structure, or may have the same double-layer structure as the first source and the first drain.

The first drain and the second drain may be in contact with each other to constitute a common drain.

The semiconductor device may be one of an inverter, a NAND device, a NOR device, an encoder, a decorder, a multiplexer, a demultiplexer, and a sense amplifier.

Another embodiment of the present invention is a thin film transistor including a first thin film transistor including a first source, a first drain, a first channel layer and a first gate and a second thin film transistor including a second source, a second drain, A method of manufacturing a semiconductor device having a second thin film transistor, the method comprising: forming the first channel layer with a first conductive oxide on a lower layer; Forming a second conductive oxide layer on the lower layer and the first channel layer; And patterning the second conductive oxide layer to form the second channel layer spaced apart from the first channel layer.

Another embodiment of the present invention is a thin film transistor including a first thin film transistor including a first source, a first drain, a first channel layer and a first gate and a second thin film transistor including a second source, a second drain, A method of manufacturing a semiconductor device having a second thin film transistor, the method comprising: forming the first channel layer with a first conductive oxide on a lower layer; Forming a first electrode layer covering the first channel layer on the lower layer and a second electrode layer spaced apart from the first electrode layer; Forming the second channel layer in contact with the first and second electrode layers with a second conductive oxide on the lower layer between the first and second electrode layers; And patterning the first electrode layer, wherein the second electrode layer is the second source, and the first source, the first drain, and the second drain are formed by patterning the first electrode layer A method of manufacturing a semiconductor device is provided.

Another embodiment of the present invention is a thin film transistor including a first thin film transistor including a first source, a first drain, a first channel layer and a first gate and a second thin film transistor including a second source, a second drain, A method of manufacturing a semiconductor device having a second thin film transistor, the method comprising: forming the first and second channel layers with different conductive oxides on a lower layer; Forming a first material layer over the first channel layer over the lower layer; Forming a second material layer on the lower layer to cover the first material layer and the second channel layer; And patterning the first and second material layers to form the first source, the first drain, the second source, and the second drain.

Another embodiment of the present invention is a thin film transistor including a first thin film transistor including a first source, a first drain, a first channel layer and a first gate and a second thin film transistor including a second source, a second drain, A method of manufacturing a semiconductor device having a second thin film transistor, the method comprising: forming the first channel layer with a first conductive oxide on a lower layer; Forming a first material layer over the first channel layer over the lower layer; Forming a second material layer on the first material layer; Exposing a first region of the lower layer spaced apart from the first channel layer by first patterning the second and first material layers; Forming a second channel layer in contact with the second material layer on either side of the first region with a second conductive oxide on a first region of the lower layer; And a second patterning of the second and first material layers, wherein the first and second patterning of the second and first material layers cause the first source, the first drain, 2 source and the second drain are formed.

Another embodiment of the present invention is a semiconductor device comprising: first and second transistors connected in parallel to a power source; And third and fourth transistors serially connected to the drains of the first and second transistors, wherein the first and second transistors are p-type oxide transistors, and the third and fourth transistors are n-type oxide A NAND device as a transistor is provided.

The third and fourth transistors may share an n-type oxide channel layer. In this case, a connection wiring may be provided in contact with the n-type oxide channel layer between the gate of the third transistor and the gate of the fourth transistor, and the connection wiring may be connected to the gate of the third transistor or the fourth transistor Lt; / RTI >

The doping concentration of the n-type oxide channel layer between the gate of the third transistor and the gate of the fourth transistor may be higher than the doping concentration of the remaining region.

Another embodiment of the present invention is a semiconductor device comprising: first and second transistors connected in parallel to a power source; And third and fourth transistors serially connected to the drains of the first and second transistors, wherein the first and second transistors are n-type oxide transistors, and the third and fourth transistors are p-type oxide And a NOR element which is a transistor.

The third and fourth transistors may share a p-type oxide channel layer. In this case, a connection wiring which is in contact with the p-type oxide channel layer between the gate of the third transistor and the gate of the fourth transistor may be provided, and the connection wiring may be connected to the gate of the third transistor or the fourth transistor Lt; / RTI >

The doping concentration of the p-type oxide channel layer between the gate of the third transistor and the gate of the fourth transistor may be higher than the doping concentration of the remaining region.

According to an embodiment of the present invention, a complementary semiconductor device including at least two transistors in which an oxide semiconductor layer is applied as a channel layer can be implemented.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. The widths and thicknesses of the layers or regions illustrated in the accompanying drawings are exaggeratedly shown for clarity of the description. Like reference numerals designate like elements throughout the specification.

1 to 4 show a semiconductor device according to embodiments of the present invention.

1, first and second bottom gates BG10 and BG20 may be provided on a substrate SUB10 and a gate insulating layer GI10 covering first and second bottom gates BG10 and BG20. . The first and second oxide channel layers C10 and C20 may be provided on the gate insulating layer GI10. The first oxide channel layer C10 may be provided above the first bottom gate BG10 and the second oxide channel layer C20 may be provided above the second bottom gate BG20. One of the first and second oxide channel layers C10 and C20 may be a p-type oxide layer and the other may be an n-type oxide layer. The p-type oxide layer may be formed of a metal oxide such as Ni oxide, Nb oxide, Cu oxide, Cu oxide doped with? (Where? Is boron, aluminum, gallium or indium), SrCu oxide, beta is sulfur or selenium) and PbS oxide. The n-type oxide layer may be a ZnO-based oxide layer. In this case, the n-type oxide layer may further contain indium (In), further include indium (In) and gallium (Ga) Group element or other element. Since the first and second oxide channel layers C10 and C20 are formed of the oxides described above, they can be easily formed by a low-temperature process.

A first source electrode S10, a common drain electrode D10, and a second source electrode S20 may be provided on the gate insulating layer GI10. The first source electrode S10 may be in contact with one end of the first oxide channel layer C10 and the common drain electrode D10 may be in contact with the other end of the first oxide channel layer C10 and the second oxide channel layer C20. And the second source electrode S20 may be in contact with the other end of the second oxide channel layer C20. The common drain electrode D10 may be separated into a first drain electrode contacting the other end of the first oxide channel layer C10 and a second drain electrode contacting the one end of the second oxide channel layer C20. A protective layer (not shown) covering the first and second oxide channel layers C10 and C20, the first and second source electrodes S10 and S20, and the common drain electrode D10 is formed on the gate insulating layer GI10. a passivation layer may be further provided. The protective layer may be formed of an insulating layer such as silicon oxide and silicon nitride.

In FIG. 1, the first bottom gate BG10, the gate insulating layer GI10, the first oxide channel layer C10, the first source electrode S10, and the common drain electrode D10 constitute a first transistor T10. And the second bottom gate BG20, the gate insulating layer GI10, the second oxide channel layer C20, the second source electrode S20 and the common drain electrode D10 form the second transistor T20. Can be configured. One of the first and second transistors T10 and T20 is a p-channel transistor and the other is an n-channel transistor. Thus, the semiconductor device of this embodiment can be a complementary device.

1, the first source electrode S 10, the common drain electrode D 10 and the second source electrode S 20 are formed on the first and second oxide channel layers C 10 and C 20. It can be different. An example thereof is shown in Fig.

Referring to FIG. 2, a first source electrode S10 ', a common drain electrode D10', and a second source electrode S20 'may be provided on the gate insulating layer GI10. A first oxide channel layer C10 'is provided on the gate insulating layer GI10 between the first source electrode S10' and the common drain electrode D10 'in contact with the two electrodes S10' and D10 ' . Similarly, the second oxide channel layer C20 ', which is in contact with the two electrodes D10', S20 'on the gate insulating layer GI10 between the common drain electrode D10' and the second source electrode S20 ' May be provided. The first and second oxide channel layers C10 'and C20' may correspond to the first and second bottom gates BG10 and BG20 respectively and the materials of these C10 'and C20' And the second oxide channel layer (C10, C20).

1 and 2 show a case where the transistors T10, T10 ', T20 and T20' have a bottom gate structure, but according to another embodiment, the transistors may have a top gate structure. Examples thereof are shown in Figs. 3 and 4. Fig.

Referring to FIG. 3, first and second oxide channel layers C11 and C22 may be provided on the substrate SUB20. The first source electrode S11 and the common drain electrode D11 which are in contact with both ends of the first oxide channel layer C11 may be provided. The common drain electrode D11 may have a shape extended to be in contact with one end of the second oxide channel layer C22. And a second source electrode S22 contacting the other end of the second oxide channel layer C22. A gate insulating layer GI20 covering the first and second oxide channel layers C11 and C22, the first and second source electrodes S11 and S22 and the common drain electrode D11 is formed on the substrate SUB20, . The first and second top gates TG10 and TG20 may be provided on the gate insulating layer GI20. The first top gate TG10 may be located above the first oxide channel layer C11 and the second top gate TG20 may be located above the second oxide channel layer C22.

3, the positional relationship between the first and second oxide channel layers C11 and C22 and the first source electrode S11, the common drain electrode D11, and the second source electrode S22 may be modified as shown in FIG. have.

Referring to FIG. 4, the first source electrode S11 ', the common drain electrode D11' and the second source electrode S22 'are formed on both ends of the first and second oxide channel layers C11' and C22 ' Can be contacted. These structures are similar to those described with reference to Fig.

Reference numerals T10 ', T11 and T11' in FIGS. 2 to 4 denote a first transistor, and reference numerals T20 ', T22 and T22' denote a second transistor. One of the first transistors T10 ', T11 and T11' and the second transistors T20 ', T22 and T22' may be a p-type oxide thin film transistor and the other may be an n-type oxide thin film transistor. Thus, the semiconductor device according to the present embodiments may be a complementary device similar to the device of FIG.

5 to 8 may be plan views corresponding to Figs. 1 to 4, respectively.

Referring to FIGS. 5 and 6, the first bottom gate BG10 and the second bottom gate BG20 may be connected. Similarly, the first top gate TG10 and the second top gate TG20 of FIGS. 7 and 8 may also be coupled. The planar structure of Figs. 5 to 8 is merely an example, and can be variously modified.

The semiconductor device of Figs. 5 to 8 may be an inverter. In this case, the connection relationship between the components of the semiconductor device of FIGS. 5 to 8 and the various terminals VDD, Vin, Vout, and VSS is shown in each figure. At this time, it is assumed that the first oxide channel layers C10, C10 ', C11 and C11' are p-type oxide layers and the second oxide channel layers C20, C20 ', C22 and C22' are n-type oxide layers.

Referring to FIG. 5, the first and second bottom gates BG10 and BG20 may be connected to the input terminal Vin, and the first source electrode S10 may be connected to the power supply terminal VDD. The common drain electrode D10 may be connected to the output terminal Vout and the second source electrode S20 may be connected to the ground terminal VSS. This connection relationship may be similar in FIGS. 6 to 8. FIG. If the first oxide channel layers C10, C10 ', C11 and C11' are n-type oxide layers and the second oxide channel layers C20, C20 ', C22 and C22' are p-type oxide layers, The first source electrodes S10, S10 ', S11 and S11' are connected to the ground terminal VSS and the second source electrodes S20, S20 ', S22 and S22' are connected to the power source terminal VDD Can be connected.

Since the elements of FIGS. 5-8 can be complementary inverters, they can have better characteristics than E / E (enhancement / enhancement) mode or E / D (enhancement / depletion) mode inverter with two n-type oxide thin film transistors have. For example, the current consumption of the complementary inverter according to the present embodiments may be much smaller than that of the E / E mode and E / D mode inverter.

Figs. 9 and 10 show modifications of Figs. 5 and 7, respectively. The structure of FIG. 6 may be modified similarly to the structure of FIG. 5, and the structure of FIG. 8 may be modified similarly to the structure of FIG. 7 is modified as shown in FIG. This also applies to an inverter according to another embodiment described below.

11 shows a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 11, the first transistor T10 may have the same structure as the first transistor T10 of FIG. 1, and the second transistor T20 'may have the same structure as the second transistor T20' of FIG. Structure. Reference numeral D12 denotes a common drain electrode of the first and second transistors T10 and T20 '.

12 shows a semiconductor device according to another embodiment of the present invention.

12, the first transistor T11 may have the same structure as the first transistor T11 of FIG. 3 and the second transistor T22 'may have the same structure as the second transistor T22' It can have the same structure. Reference numeral D12 'denotes a common drain electrode of the first and second transistors T11 and T22'.

The source and drain electrodes of the first transistors T10 and T11 in FIGS. 11 and 12 are in contact with the upper surface of the corresponding channel layer, and the source and drain electrodes of the second transistors T20 'and T22' It can be said that it is in contact with the lower surface at both ends of the channel layer.

Figs. 13 and 14 may be plan views corresponding to Figs. 11 and 12, respectively.

13 and 14 may be an inverter. In this case, an example of the connection relationship between the elements of the semiconductor elements of Figs. 13 and 14 and the various terminals VDD, Vin, Vout, and VSS is shown in each drawing Respectively. This connection relationship may be similar to that in Figs. 5 to 8.

15 shows a semiconductor device according to another embodiment of the present invention. This embodiment is a modification of the structure of Fig. More specifically, in the structure of FIG. 15, the second transistor T20 'is modified into a top gate structure in FIG.

Referring to FIG. 15, the second transistor T22a may include a second top gate TG20 provided above the second oxide channel layer C20 '. A second gate insulating layer GI11 may be provided between the second oxide channel layer C20 'and the second top gate TG20.

16 shows a semiconductor device according to another embodiment of the present invention. This embodiment is a modification of the structure of Fig. More specifically, in the structure of FIG. 16, the first transistor T10 is modified to a top gate structure in FIG.

Referring to FIG. 16, the first transistor T11a may include a first top gate TG10 provided above the first oxide channel layer C10. A second gate insulating layer GI11 may be provided between the first oxide channel layer C10 and the first top gate TG10.

At least one of the two transistors in each of the structures of FIGS. 1-16 may have a dual gate structure. An example thereof is shown in Fig. 17 is a modification of the structure of Fig.

Referring to FIG. 17, the first transistor TT1 and the second transistor TT2 may have a dual gate structure. The first transistor TT1 may have a structure in which a first top gate TG10 is added to the first transistor T10 of FIG. The second transistor TT2 may have a structure in which a second bottom gate BG20 is added to the second transistor T22a in FIG.

18 shows a semiconductor device according to another embodiment of the present invention.

18, first and second bottom gates BG100 and BG200 may be provided on a substrate SUB100 and a gate insulating layer GI100 covering the first and second bottom gates BG100 and BG200. . The first and second oxide channel layers C100 and C200 may be provided on the gate insulating layer GI100. The first and second oxide channel layers C100 and C200 may correspond to the first and second oxide channel layers C10 and C20 of FIG. 1, respectively, and may be formed above the first and second bottom gates BG100 and BG200 As shown in FIG. A first material layer M1 may be provided on the gate insulating layer GI100 in contact with both ends of the first oxide channel layer C100. And a second material layer M2 contacting each of both ends of the second oxide channel layer C200. The second material layer M2 may also be provided on the first material layer M1. The first and second material layers M1 and M2 of the first oxide channel layer C100 may constitute the first source electrode S100 and the first oxide channel layer C100 may be formed of the first material layer The first material layer M1 and the second material layer M2 extending therefrom to one end of the second oxide channel layer C200 may constitute a common drain electrode D100. The second material layer M2 at the other end of the second oxide channel layer C200 may be the second source electrode S200. Reference numerals T100 and T200 denote the first and second transistors. As described above, in this embodiment, the electrode material (the first material layer M1) contacting the first oxide channel layer C100 and the electrode material contacting the second oxide channel layer C200 (the second material layer M2 ) May be different from each other.

In FIG. 18, the common drain electrode D100 may be divided into two drain electrodes. That is, the common drain electrode D100 may be divided into a first drain electrode of the first transistor T100 region and a second drain electrode of the second transistor T200 region. At this time, the first drain electrode may include a bilayer structure of a first material layer (M1) and a second material layer (M2), and the second drain electrode may have a single layer structure composed of a second material layer Lt; / RTI > The first and second drain electrodes may be in contact with each other to constitute a common drain electrode D100.

19 shows a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 19, the structure from the substrate SUB100 to the gate insulating layer GI100 may have the same structure as in FIG. A first oxide channel layer C100 may be provided on the gate insulating layer GI100 above the first bottom gate BG100. A first source electrode S100 'and a common drain electrode D100' may be provided on the gate insulating layer GI100 in contact with the upper surfaces of both ends of the first oxide channel layer C100. The common drain electrode D100 'may have a shape extended to the upper end of the second bottom gate BG200. And a second sour electrode S200 'may be provided at a predetermined distance from the common drain electrode D100'. On the gate insulating layer GI100 between the common drain electrode D100 'and the second source electrode S200', that is, on the gate insulating layer GI100 above the second bottom gate BG200, A layer C200 'may be provided. Both ends of the second oxide channel layer C200 'may be in contact with the common drain electrode D100' and the second source electrode S200 ', respectively. The first source electrode S100 ', the common drain electrode D100', and the second source electrode S200 'may have a multi-layer structure in which at least two material layers are stacked. For example, the first source electrode S100 ', the common drain electrode D100' and the second source electrode S200 'may have a double-layer structure in which the first and second material layers M1' and M2 ' have. Accordingly, both top surfaces of the first oxide channel layer C100 may be in contact with the first material layer M1 ', and both ends of the second oxide channel layer C200' may be in contact with the second material layer M2 ' . Reference numbers T100 'and T200' represent the first and second transistors. In some cases, the second material layer M2 'may not be provided in the region of the first transistor T100' and the first material layer M1 'may not be provided in the region of the second transistor T200' .

The structures of Figs. 18 and 19 can be variously modified. For example, at least one of the two transistors in Figures 18 and 19, respectively, may be modified into a top gate structure or a dual gate structure.

20A to 20C show a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 20A, first and second bottom gates BG10 and BG20 may be formed on a substrate SUB10, and a gate insulating layer GI10 may be formed to cover the first and second bottom gates BG10 and BG20. The first conductive type first oxide channel layer C10 may be formed on the gate insulating layer GI10 above the first bottom gate BG10. Next, a second conductive type oxide channel material layer C20a covering the first oxide channel layer C10 may be formed on the gate insulating layer GI10.

The second oxide channel layer C20a may be patterned to form a second oxide channel layer C20 above the second bottom gate BG20, as shown in FIG. 20B. When patterning the second oxide channel material layer C20a, the first oxide channel layer C10 may not be damaged. That is, the method of the present embodiment may be possible when there is an etch selectivity between the material of the first oxide channel layer C10 and the material of the second oxide channel layer C20. The material of the first oxide channel layer C10 and the material of the second oxide channel layer C20 are as described with reference to FIG. 1, but the method of the present embodiment can be applied when etching selectivity between two materials is available.

Referring to FIG. 20C, a first source electrode S10, a common drain electrode D10, and a second source electrode S20 may be formed on the gate insulating layer GI10. The first source electrode S10 and the common drain electrode D10 may be in contact with both ends of the first oxide channel layer C10, respectively. The common drain electrode D10 may have a shape extended to be in contact with one end of the second oxide channel layer C20. And the second source electrode S20 may be in contact with the other end of the second oxide channel layer C20. A protective layer (not shown) covering the first and second oxide channel layers C10 and C20, the first and second source electrodes S10 and S20, and the common drain electrode D10 is formed on the gate insulating layer GI10. Can be further formed. The protective layer may be formed of an insulating layer such as silicon oxide and silicon nitride. Next, the substrate product can be annealed at a predetermined temperature. This embodiment can be a method of manufacturing the structure of Fig.

If there is an etch selectivity between the material of the p-type oxide channel layer and the material of the n-type oxide channel layer, the structure of Figs. 2 to 4 can be manufactured using a method similar to Figs. 20A to 20C. For example, in the case of the structure of FIG. 2, a first source electrode S10 ', a common drain electrode D10' and a second source electrode S20 'are formed on the gate insulating layer GI10, A first oxide channel layer C10 'in contact with the electrode S10' and the common drain electrode D10 'is formed and a second oxide channel layer C10' is formed in contact with the common drain electrode D10 'and the second source electrode S20' The oxide channel layer C20 'can be formed.

However, even if there is no etching selectivity between the material of the p-type oxide channel layer and the material of the n-type oxide channel layer, the structure of Fig. 20B can be obtained by using a lift-off process. More specifically, as shown in FIG. 21, a photoresist film PR1 covering the first oxide channel layer 10 on the gate insulating layer GI10 and having an opening exposing the second oxide channel layer formation region A second oxide channel material layer 20a may be formed on the photoresist film PR1 and the second oxide channel layer formation region. Next, when the photoresist film PR1 and the second oxide channel material layer 20a provided thereon are removed, the second oxide channel material layer 20a may remain only in the second oxide channel layer formation region. As a result, a structure similar to that of FIG. 20B can be obtained.

22A to 22C show a method of manufacturing a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 22A, first and second bottom gates BG10 and BG20, a gate insulating layer GI10, and a first oxide channel layer of a first conductivity type are formed on a substrate SUB10, (C10) can be formed. Next, the source / drain electrode layer SD1 can be formed on the gate insulating layer GI10. The source / drain electrode layer SD1 may include first and second layers 1 and 2 spaced from each other. The first layer 1 may extend to one end of the second bottom gate BG20 while covering the first oxide channel layer C10. The second layer 2 may extend outside the other end above the other end of the second bottom gate BG20.

Referring to FIG. 22B, a second oxide channel layer C20 'of the second conductivity type, which is in contact with the first and second layers 1 and 2 on the gate insulating layer GI10 above the second bottom gate BG20, ) Can be formed. When forming the second oxide channel layer C20 ', the first oxide channel layer C10 is covered with the first layer 1. [ Therefore, the method of the present embodiment can be applied to the case where there is no etching selectivity between the material of the first oxide channel layer C10 and the material of the second oxide channel layer C20 '.

The first source electrode S 1 and the common drain electrode D 12 which are in contact with both ends of the first oxide channel layer C 10 can be formed by patterning the first layer 1, have. And the second layer 2 may be referred to as a second source electrode S20 '. Although not shown in the figure, the first and second oxide channel layers C10 and C20 ', the first and second source electrodes S10 and S20', and the common drain electrode D12 are formed on the gate insulating layer GI10. A protective layer can be further formed, and the resultant can be annealed at a predetermined temperature. This embodiment can be a method of manufacturing the structure of Fig.

If there is no etching selectivity between the material of the p-type oxide channel layer and the material of the n-type oxide channel layer, the structure shown in Figs. 12 and 15 to 17 can be manufactured by a method similar to Figs. 22A to 22C.

23A to 23C show a method of manufacturing a semiconductor device according to another embodiment of the present invention.

23A, first and second bottom gates BG100 and BG200 can be formed on a substrate SUB100 and a gate insulating layer GI100 covering the first and second bottom gates BG100 and BG200. Can be formed. The first and second oxide channel layers C100 and C200 may be formed on the gate insulating layer GI100. The first and second oxide channel layers C100 and C200 may correspond to the first and second oxide channel layers C10 and C20 of FIG. 1, respectively, and may be formed above the first and second bottom gates BG100 and BG200 As shown in Fig. The first material layer M1 covering the first oxide channel layer C100 may be formed on the gate insulating layer GI100.

Referring to FIG. 23B, a second material layer M2 covering the first material layer M1 and the second oxide channel layer C200 may be formed on the gate insulating layer GI100.

The second material layer M2 and the first material layer M1 are patterned to form the first source electrode S100, the common drain electrode D100 and the second source electrode S200 as shown in Fig. . The structure of these (S100, D100, S200) may be similar to that described with reference to Fig. In FIG. 23B, the second material layer M2 and the first material layer Ml may be patterned together in the same etching process, or may be individually patterned in different etching processes.

24A to 24D show a method of manufacturing a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 24A, first and second bottom gates BG100 and BG200 and a gate insulating layer GI100 may be formed on a substrate SUB100 similarly to FIG. 23A. The first oxide channel layer C100 may be formed on the gate insulating layer GI100 above the first bottom gate BG100. A first material layer M1 'covering the first oxide channel layer C100 is formed on the gate insulating layer GI100 and a second material layer M2' is formed on the first material layer M1 ' can do.

The first opening H1 may be formed above the second bottom gate BG200 by first patterning the second material layer M2 'and the first material layer M1' have. That is, by the primary patterning, the laminated structure of the first and second material layers M1 'and M2' can be divided into two parts separated on both sides of the second bottom gate BG200.

Referring to FIG. 24C, a second oxide channel layer C200 'may be formed on the gate insulating layer GI100 above the second bottom gate BG200. The lower surface of the both end portions of the second oxide channel layer C200 'may be in contact with the second material layer M2'.

Next, the second material layer M2 'and the first material layer M 1' are secondarily patterned to form a first source electrode contacted with both ends of the first oxide channel layer C 100, as shown in FIG. (S100 ') and the common drain electrode (D100'). The second material layer M2 'of the common drain electrode D100' may be in contact with the bottom surface of the second oxide channel layer C200 '. The second material layer M2 'and the first material layer M1', which are in contact with the other end surface of the second oxide channel layer C200 ', may constitute the second source electrode S200'. Although not shown, a protective layer can be further formed on the first and second oxide channel layers C100 and C200 'and the second material layer M2, and the resultant can be annealed to a predetermined temperature.

The method of FIGS. 24A to 24D can be applied when there is no etching selectivity between the material of the first oxide channel layer C100 and the material of the second oxide channel layer C200 '.

The semiconductor device according to the embodiments of the present invention described above can be used as a basic element in various circuits. For example, the semiconductor device according to the embodiment of the present invention can be applied to the above-described inverter, and the NAND device, the NOR device, the encoder, the decorder, the MUX, a multiplexer, and a sense amplifier. In addition, the inverter and other logic devices according to embodiments of the present invention can be applied to various fields such as a liquid crystal display, an organic light emitting display, and a memory device. In particular, since the transistor of the semiconductor device according to the embodiment of the present invention is an oxide thin film transistor, it can be easily formed by a low-temperature process and has various advantages such as excellent mobility characteristics. For example, the inverter and other logic devices according to embodiments of the present invention can be easily applied as a peripheral device of a three-dimensional laminated memory that can be formed by a low-temperature process such as a 1D (diode) -1R (multi-layer) cross point memory device.

Hereinafter, a NAND element and a NOR element including a semiconductor element according to an embodiment of the present invention will be described in more detail.

25 to 27 show a planar structure of a NAND device according to embodiments of the present invention. The NAND device according to the present embodiments may include two p-type oxide thin film transistors and two n-type oxide thin film transistors. The two p-type oxide thin film transistors may be connected in parallel to each other and may have a common drain electrode. The two n-type oxide thin film transistors may be connected in series to the common drain electrode.

Referring to FIG. 25, first and second bottom gates BG1 and BG2 extending in the Y-axis direction may be provided. A gate insulating layer (not shown) may be provided to cover the first and second bottom gates BG1 and BG2. The first and second oxide channel layers C1 and C2 may be provided on the gate insulating layer. One of the first and second oxide channel layers C1 and C2, for example, the first oxide channel layer C1 may be p-type and the other, for example, the second oxide channel layer C2 may be n- . The material of the first and second oxide channel layers C1 and C2 may be the same as the first and second oxide channel layers C10 and C20 of FIG. The first and second oxide channel layers C1 and C2 may be spaced apart from each other and across the first and second bottom gates BG1 and BG2. The first and the second source electrodes SS1 and SS2 may be provided in contact with both ends of the first oxide channel layer C1 and the common drain electrode DD1 may be provided in contact with the center of the first oxide channel layer C1. . The first and second source electrodes SS1 and SS2 may be connected to each other and the common drain electrode DD1 may be extended to be in contact with one end of the second oxide channel layer C2. And a third source electrode SS3 contacting the other end of the second oxide channel layer C2. And a first connection wiring CC1 that is in contact with a central portion of the second oxide channel layer C2 may be provided. The first connection wiring CC1 may be connected to the first bottom gate BG1 by the first contact plug CP1. And a second connection wiring CC2 which is in contact with the second bottom gate BG2 at the same height as the first connection wiring CC1. The second connection wiring CC2 and the second bottom gate BG2 may be connected by a second contact plug CP2.

The first bottom gate BG1 may be connected to the first input terminal Vin1 and the second connection wiring CC2 may be connected to the second input terminal Vin2. The first and second source electrodes SS1 and SS2 may be connected to the power supply terminal VDD and the common drain electrode DD1 may be connected to the output terminal Vout. And the third source electrode SS3 may be connected to the ground terminal VSS. The first connection wiring CC1 may serve to lower the resistance thereof by applying a gate voltage applied through the first input terminal Vin1 to the central portion of the second oxide channel layer C2. Therefore, the operation characteristics of the element can be improved by the first connection wiring CC1.

The first connection wiring CC1 may be connected to the second bottom gate BG2 instead of the first bottom gate BG1. An example thereof is shown in Fig.

Referring to Fig. 26, the first connection wiring CC11 is connected to the second bottom gate BG2 by the first contact plug CP11. The remaining configuration except for this can be the same as that shown in Fig. In this case, the first connection wiring CC11 can serve to lower the resistance thereof by applying a gate voltage attracted through the second input terminal Vin2 to the central portion of the second oxide channel layer C2.

25 and 26, the resistance of the center portion of the second oxide channel layer C2 is lowered by using the first connection wirings CC1 and CC11, but other methods are possible. For example, the resistance can be lowered by forming the n + region n1 at the center of the second oxide channel layer C2, as shown in Fig. 27, without using the first connection wirings CC1 and CC11 .

FIG. 28 shows a circuit configuration of the NAND element in FIGS. 25 to 27; FIG.

28, two p-type oxide thin film transistors pTFT1 and pTFT2 may be connected in parallel and two n-type oxide thin film transistors (nTFT1 and pTFT2) may be connected to the common drain of two p-type oxide thin film transistors pTFT1 and pTFT2 , nTFT2) may be connected in series. The connection relationship between the components of the NAND element and the various terminals VDD, Vin, Vout, and VSS may be the same as shown in FIG.

29 to 31 show a planar structure of a NOR element according to embodiments of the present invention. The NOR device according to the present embodiments may include two p-type oxide thin film transistors and two n-type oxide thin film transistors. The two n-type oxide thin film transistors may be connected in parallel to each other and may have a common drain electrode. The two p-type oxide thin film transistors may be connected in series to the common drain electrode.

Referring to FIG. 29, first and second bottom gates BG1 'and BG2' extending in the Y-axis direction may be provided. A gate insulating layer (not shown) may be provided to cover the first and second bottom gates BG1 'and BG2'. First and second oxide channel layers (C1 ', C2') may be provided on the gate insulating layer. One of the first and second oxide channel layers C1 'and C2', for example, the first oxide channel layer C1 'may be p-type and the other, for example, the second oxide channel layer C2' n-type. The materials of the first and second oxide channel layers (C1 ', C2') may be the same as the first and second oxide channel layers (C10, C20) of FIG. The first and second oxide channel layers C1 'and C2' may be spaced apart from each other and across the first and second bottom gates BG1 'and BG2'. First and second source electrodes SS1 'and SS2' that are in contact with both ends of the second oxide channel layer C2 'may be provided, and a common drain region, which is in contact with the center portion of the second oxide channel layer C2' An electrode DD1 'may be provided. The first and second source electrodes SS1 'and SS2' may be connected to each other and the common drain electrode DD1 'may extend to be in contact with one end of the first oxide channel layer C1. And a third source electrode SS3 'that is in contact with the other end of the first oxide channel layer C1'. And a first connection wiring CC1 'that is in contact with a central portion of the first oxide channel layer C1' may be provided. The first connection wiring CC1 'may be connected to the first bottom gate BG1' by the first contact plug CP1 '. And a second connection wiring CC2 'which is in contact with the second bottom gate BG2' at the same height as the first connection wiring CC1 '. The second connection wiring CC2 'and the second bottom gate BG2' may be connected by a second contact plug CP2 '.

The first bottom gate BG1 'may be connected to the second input terminal Vin2 and the second connection wiring CC2' may be connected to the first input terminal Vin1. The first and second source electrodes SS1 'and SS2' may be connected to the power supply terminal VDD and the common drain electrode DD1 'may be connected to the output terminal Vout. The third source electrode SS3 'may be connected to the ground terminal VSS. The first connection wiring CC1 'may serve to lower the resistance thereof by applying a gate voltage applied through the second input terminal Vin2 to the central portion of the first oxide channel layer C1'. Therefore, the operating characteristics of the element can be improved by the first connection wiring CC1 '.

The first connection wiring CC1 'may be connected to the second bottom gate BG2' instead of the first bottom gate BG1 '. An example thereof is shown in Fig.

Referring to FIG. 30, a first connection wiring CC11 'is connected to a second bottom gate BG2' by a first contact plug CP11 '. The remaining configuration except for this can be the same as in Fig. In this case, the first connection wiring CC11 'may serve to lower the resistance thereof by applying a gate voltage attracted through the first input terminal Vin1 to the central portion of the first oxide channel layer C1' .

29 and 30, the resistance of the central portion of the first oxide channel layer C1 'is lowered by using the first connection wirings CC1' and CC11 ', but other methods are also possible. For example, by forming the p + region p1 at the center of the first oxide channel layer C1 ', as shown in Fig. 31, without using the first connection wire CC1' and CC11 ' .

32 shows the circuit configuration of the NOR element shown in Figs. 29 to 31. Fig.

32, two n-type oxide thin film transistors (nTFT11, nTFT22) may be connected in parallel, and two p-type oxide thin film transistors (pTFT11, nTFT22) are connected to the common drains of two n-type oxide thin film transistors , pTFT22) may be connected in series. The connection relationship between the components of the NOR element and the various terminals (VDD, Vin, Vout, VSS) may be the same as that shown in FIG.

25 to 27 and 29 to 31 are for NAND and NOR devices including transistors of the bottom gate structure, but NAND and NOR devices including transistors having a top gate or dual gate structure can also be implemented.

While many have been described in detail above, they should not be construed as limiting the scope of the invention, but rather as examples of specific embodiments. For example, those skilled in the art will appreciate that the components and structures of devices according to embodiments of the present invention can be varied and modified, respectively. Therefore, the scope of the present invention is not to be determined by the described embodiments but should be determined by the technical idea described in the claims.

1 to 4 are sectional views of semiconductor devices according to embodiments of the present invention.

5 to 8 are plan views of the semiconductor devices of Figs. 1 to 4, respectively.

Figs. 9 and 10 are modifications of Figs. 5 and 7, respectively, according to the embodiment of the present invention.

11 and 12 are cross-sectional views of semiconductor devices according to other embodiments of the present invention.

Figs. 13 and 14 are plan views of the semiconductor devices of Figs. 11 and 12, respectively.

15 to 19 are sectional views of semiconductor devices according to other embodiments of the present invention.

20A to 20C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

21 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

22A to 22C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

23A to 23C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

24A to 24D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

25 to 27 are plan views of a NAND device according to embodiments of the present invention.

28 is a circuit diagram of the NAND element in Figs. 25 to 27. Fig.

29 to 31 are plan views of NOR devices according to embodiments of the present invention.

32 is a circuit diagram of the NOR element shown in Figs. 29 to 31. Fig.

Description of the Related Art [0002]

BG10, BG20, TG10, TG20: Gate

C10, C10 ', C11, C11': the first oxide channel layer

C20, C20 ', C22, C22': the second oxide channel layer

D10, D10 ', D11, D11', D12: drain electrode

S10, S10 ', S11, S11', S20, S20 ', S22, S22'

GI10, GI11, GI20, GI100: gate insulating layer

T10, T10 ', T11, T11a, T11', T100, T100 ', TT1:

T20, T20 ', T22, T22a, T22', T200, T200 ', TT2:

H1: First opening M1, M1 ': First material layer

M2, M2 ': second material layer n1: n + region

p1: p + region PR1: photosensitive film

SUB10, SUB20: Substrate VDD: Power terminal

Vin: Input terminal Vout: Output terminal

VSS: ground terminal

Claims (23)

A first thin film transistor including a first source, a first drain, a first channel layer, and a first gate; And And a second thin film transistor including a second source, a second drain, a second channel layer, and a second gate, Wherein one of the first and second channel layers is a p-type oxide layer and the other is an n-type oxide layer. The method according to claim 1, Wherein the first and second thin film transistors are a bottom gate structure or a top gate structure. The method according to claim 1, Wherein one of the first and second thin film transistors is a bottom gate structure and the other is a top gate structure. The method according to claim 1, Wherein at least one of the first and second thin film transistors further includes another gate. 5. The method according to any one of claims 1 to 4, The first source and the first drain are in contact with the upper surface or the lower surface at both ends of the first channel layer, And the second source and the second drain are in contact with the upper surface or the lower surface at both ends of the second channel layer. The method according to claim 1, Wherein the first source and the first drain comprise a first material layer contacted across the first channel layer, The second source and the second drain including a second material layer in contact with both ends of the second channel layer, Wherein the first and second material layers are different material layers. The method according to claim 6, The first material layer is in contact with the upper surface of both ends of the first channel layer, And the second material layer is in contact with an upper surface or a lower surface at both ends of the second channel layer. The method according to claim 6, Wherein the first source and the first drain have a double-layer structure, Wherein the second source and the second drain have a single-layer structure or a double-layer structure identical to the first source and the first drain. The method according to claim 1, Wherein the first drain and the second drain are in contact with each other to constitute a common drain. The method according to claim 1, Wherein the semiconductor device is any one of an inverter, a NAND device, a NOR device, an encoder, a decorder, a multiplexer, a demultiplexer, and a sense amplifier. A first thin film transistor including a first source, a first drain, a first channel layer and a first gate, and a second thin film transistor including a second source, a second drain, a second channel layer and a second gate, A method of manufacturing a semiconductor device, Forming the first channel layer with a first conductive oxide on a lower layer; And And forming the second channel layer with a second conductive oxide at a position spaced apart from the first channel layer on the lower layer. delete 12. The method of claim 11, wherein after forming the first and second channel layers, Forming a first material layer over the first channel layer over the lower layer; Forming a second material layer on the lower layer to cover the first material layer and the second channel layer; And And patterning the first and second material layers to form the first source, the first drain, the second source, and the second drain. delete First and second transistors connected in parallel to a power source; And And third and fourth transistors serially connected to the drains of the first and second transistors, The first and second transistors are p-type oxide transistors, And the third and fourth transistors are n-type oxide transistors. 16. The method of claim 15, The third and fourth transistors share an n-type oxide channel layer, And a connection wiring which is in contact with the n-type oxide channel layer between the gate of the third transistor and the gate of the fourth transistor, And the connection wiring is connected to the gate of the third transistor or the gate of the fourth transistor. 16. The method of claim 15, The third and fourth transistors share an n-type oxide channel layer, And the doping concentration of the n-type oxide channel layer between the gate of the third transistor and the gate of the fourth transistor is higher than the doping concentration of the remaining region. First and second transistors connected in parallel to a power source; And And third and fourth transistors serially connected to the drains of the first and second transistors, The first and second transistors are n-type oxide transistors, And the third and fourth transistors are p-type oxide transistors. 19. The method of claim 18, The third and fourth transistors share a p-type oxide channel layer, And a connection wiring which is in contact with the p-type oxide channel layer between the gate of the third transistor and the gate of the fourth transistor is provided, And the connection wiring is connected to the gate of the third transistor or the gate of the fourth transistor. 19. The method of claim 18, The third and fourth transistors share a p-type oxide channel layer, And the doping concentration of the p-type oxide channel layer between the gate of the third transistor and the gate of the fourth transistor is higher than the doping concentration of the remaining region. 12. The method of claim 11, wherein forming the second channel layer comprises: Forming a second channel material layer of the second conductivity type oxide on the lower layer and the first channel layer; And And patterning the second channel material layer. 12. The method of claim 11, wherein forming the second channel layer comprises: Forming a photoresist layer on the lower layer, the photoresist layer covering the first channel layer and having an opening exposing a region of the lower layer that is spaced apart from the first channel layer; Forming an exposed region of the lower layer and a second channel material layer of the second conductive oxide on the photoresist layer; And And removing the photoresist layer and the second channel material layer provided thereon. 12. The method of claim 11, wherein after forming the first and second channel layers, Forming an electrode material layer covering the first and second channel layers on the lower layer; And patterning the electrode material layer to form the first source, the first drain, the second source, and the second drain.

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