KR102227365B1 - Semi-conductor device having double-gate and method for setting synapse weight of target semi-conductor device within nerual network - Google Patents

Abstract

In embodiments, a body made of a first conductivity type semiconductor material; A source and a drain made of a second conductivity type semiconductor material and formed on the body; A first gate formed on the body with a gate insulating layer therebetween; A second gate formed to face the first gate with the body therebetween; And a semiconductor device including an insulating layer stack having a charge storage layer formed between the body and a second gate, and a method of controlling a synaptic weight of a target semiconductor device in a neural network made of the same.

Description

How to set the synaptic weight of a semiconductor device having a double gate and a target semiconductor device in a neural network {SEMI-CONDUCTOR DEVICE HAVING DOUBLE-GATE AND METHOD FOR SETTING SYNAPSE WEIGHT OF TARGET SEMI-CONDUCTOR DEVICE WITHIN NERUAL NETWORK}

The embodiments relate to a semiconductor device for a hardware-based neural network, and more specifically, a semiconductor device configured to perform a program operation through FN tunneling while being arranged in an array structure of a NOR flash memory, and a neural network composed of the semiconductor device. It relates to a method of independently setting the synaptic weights of semiconductor devices.

Recently, artificial intelligence-related technologies to utilize the functions of synapses and neurons in the biological nervous system are rapidly developing. A number of technologies are being developed to implement a neural network consisting of synapses and neurons from the software side. In addition, technologies for implementing the neural network in terms of hardware are also being developed considerably.

A neural network implemented in terms of hardware (hereinafter, “hardware neural network”) includes a synaptic array having a plurality of cells. In order to accurately design a hardware neural network, weights must be independently set for each cell. To this end, it is required to independently control the weight of the hardware neural network for each cell.

Typically, device candidates for use as synapses include SRAM, resistance change memory (e.g., ReRAM (resistive random access memory)), PCM (phase change memory), STT_MRAM (spin torque transfer magnetic random access memory), flash memory, etc. have. Among them, the flash memory has non-volatile characteristics and has very excellent characteristics in terms of reliability.

The flash memory may be classified into a NOR flash memory and a NAND flash memory according to a memory array structure. The NOR flash memory is a flash memory having an array structure in which the source region and the drain region intersect. Unlike NAND flash memory, since each cell is connected in parallel to each other and operates, it is only a source of unit synapses (eg, synaptic blocks). By reading the current, you can perform synaptic weighting calculations. Therefore, it is effective to use a NOR flash memory to construct a hardware neural network.

The conventional NOR flash memory uses a channel hot electron (CHI) method for a program (PGM) operation for weight setting. However, since the channel hot electron method requires a high drain current for a program operation, it is difficult to fabricate a device using polysilicon, so there is a limitation in that a device must be fabricated using single crystal silicon, and a large power consumption is required.

Meanwhile, as another method for operating a program (PGM, program), there is an FN tunneling method. However, when the FN tunneling method is applied to a conventional NOR flash memory, it is impossible to independently perform a program (PGM) operation for each section.

1 is a diagram for explaining a problem in the case of attempting a program (PGM) operation through an FN tunneling method for a target cell of a conventional NOR flash memory.

The NOR flash memory has an array structure including a word line WL, a bit line BL, and a common source line SCL. When the FN tunneling method is applied to set the weight of the target cell in the 2×2 block, the program voltage is applied through the word line WL0 connected to the target cell. Then, the program prohibition does not occur in the two cells sharing the word line WL0 by the common source line regardless of the voltage of the bit line BL0. That is, all other cells except the target cell are not programmed.

Korean Patent Publication No. 10-2015-0014577

According to an aspect of the present invention, an array structure of a conventional NOR flash memory can be formed in which drains of different semiconductor devices are adjacent, while a program (PGM)/erase (ERS) operation is performed through FN tunneling between double gates. A semiconductor device capable of performing can be provided.

Furthermore, it is possible to provide a method of independently setting a synaptic weight of a target semiconductor device through an FN tunneling method in a synaptic block composed of the semiconductor device.

A semiconductor device according to an aspect of the present invention includes: a body made of a first conductivity type semiconductor material; A source and a drain made of a second conductivity type semiconductor material and formed on the body; A first gate formed on the body with a gate insulating layer therebetween; A second gate formed to face the first gate with the body therebetween; And an insulating layer stack having a charge storage layer formed between the body and the second gate.

In one embodiment, the semiconductor device is: When an electric field from the first gate to the second gate is formed due to a potential difference between the first gate and the second gate while the source and the drain are floating, the first gate Tunneled electrons may be tunneled in the direction of the second gate.

In an embodiment, the insulating layer stack includes: a first stack insulating layer formed on the charge storage layer; And a second stack insulating layer formed to face the first stack insulating layer with the charge storage layer therebetween.

In one embodiment, when an electric field is formed due to a potential difference between the first gate and the second gate, the first stack insulating layer prevents damage to each insulating layer, allowing the charge of the first gate to tunnel in the direction of the second gate. can do.

In one embodiment, the first stack insulating layer may have a thickness of less than 7 nm.

In an embodiment, the first stack insulating layer may be further configured such that, when the electric field disappears, tunneled charges in the charge storage layer do not leak.

In one embodiment, the first stack insulating layer may have a thickness of 3 nm or more.

In an embodiment, when an electric field is formed due to a potential difference between the first gate and the second gate, the second stack insulating layer does not damage each insulating layer, the charge of the first gate tunnels in the direction of the second gate. It can be configured to inhibit doing.

In one embodiment, the second stack insulating layer may have a thickness of 8 nm or more.

In the above-described embodiments, the body may be formed of any one of polysilicon, amorphous silicon, and combinations thereof.

A neural network according to another aspect of the present invention has a plurality of the semiconductor device of claim 1 as a synaptic cell,

A synaptic block, comprising: a first synaptic array including a first semiconductor device and a second semiconductor device; And a second synaptic array including a third semiconductor device and a fourth semiconductor device, wherein each synaptic array includes a synapse block configured such that drains of different semiconductor devices are adjacent to each other; A drain line electrically connected to the drain region of each synapse array; A first gate line electrically connected to the first gate of each synapse array; And a source line electrically connected to a source region of the first synaptic array and a source region of the second synaptic array. It may include. Here, the drain line and the first gate line receive an input signal from a previous neuron, and the source line outputs an operation result in the synaptic block as an output signal to the next neuron.

In one embodiment, the synapse block is configured to: upon receiving the input signal, form a source signal based on the input signal and a preset weight for each semiconductor device, respectively.

In an embodiment, the output signal may be a sum of source signals for each semiconductor device.

In one embodiment, the synaptic block connects the previous neuron and another neuron through a first switching element that turns on/off electrical connection between the previous neuron, the next neuron, and the synaptic block, and A second gate line electrically connected to the second gate of the second gate and the second synaptic array; And a second switching element that turns on/off an electrical connection between the control circuit and the synapse block, and may be further connected to a control circuit that controls the semiconductor element through at least a portion of the plurality of lines.

In one embodiment, the output of the operation result is performed in an on state of the first switching element and an off state of the second switching element, and the operation of the control circuit is performed in the off state of the first switching element and the second It can be performed in the on state of the switching element.

According to another aspect of the present invention, a method of setting a synaptic weight of a target semiconductor device in a synaptic array including a plurality of semiconductor devices includes: After setting the weight of the first semiconductor device according to the tunneling, the target semiconductor device Controlling a potential difference between the first and second gates of the target semiconductor device to form an electric field for tunneling the internal charge; Controlling a voltage of a second gate of the other semiconductor device to prevent tunneling of charges in the other semiconductor device, sharing a first gate line between the first gate of the target semiconductor device and a control circuit; And controlling a voltage of a first gate of another semiconductor device to prevent tunneling of charges in another semiconductor device, sharing a second gate line between a second gate of the target semiconductor device and a control circuit. I can.

In an embodiment, the controlling a potential difference between the first and second gates of the target semiconductor device includes: applying a first voltage to a second gate of the target semiconductor device; And applying a second voltage to the first gate of the target semiconductor device. Here, a potential difference between the first and second gates of the target semiconductor device causes electrons of the first gate to form a channel for tunneling in the direction of the second gate.

In one embodiment, the method, in the controlling of the voltage of the second gate of the other semiconductor device, applies a voltage equal to the voltage of the first gate of the target semiconductor device to the second gate of the other semiconductor device. It may include steps.

In an embodiment, the controlling of the voltage of the first gate of the other semiconductor device includes a third voltage applied to the first gate of the other semiconductor device to be lower than a potential difference between the first and second gates of the target semiconductor device. It may include the step of applying a voltage.

In one embodiment, the third voltage is a voltage such that a potential difference between the first and second gates of the other semiconductor device becomes 40 to 60% of the potential difference between the first and second gates of the first semiconductor device. I can.

A semiconductor device according to an aspect of the present invention includes a double gate and has an asymmetric structure around a body. Using the above-described semiconductor device, an array structure of a NOR flash memory in which drains of semiconductor devices in the same array are adjacent can be formed. Here, the lines that control the drain are configured in contact to share adjacent drains in the same array.

The semiconductor device may perform a program operation through FN tunneling between double gates. In particular, even under the above-described array structure, the weight of the target semiconductor device can be independently set through FN tunneling.

By performing the program (PGM) operation through the FN tunneling method as described above, the power consumption can be reduced to approximately 1/1000 level compared to the channel hot electron (CHI) method.

As a result, if the semiconductor device is used, a low power/highly integrated synapse array can be formed, and further, it has improved performance compared to a conventional NOR flash memory-based neural network.

Furthermore, when a polycrystalline semiconductor material (eg, polysilicon) widely used in the conventional semiconductor field is used as a body of a semiconductor device, it is easy to expand into an array structure, and has advantageous advantages in terms of difficulty and integration of the process.

In order to more clearly describe the technical solutions of the embodiments of the present invention or the prior art, the drawings necessary in the description of the embodiments are briefly introduced below. The same reference numbers are used to identify similar elements shown in more than one figure. It is to be understood that the following drawings are for the purpose of describing the embodiments of the present specification and not for the purpose of limitation. In addition, some elements to which various modifications, such as exaggeration and omission, have been applied, may be shown in the drawings below for clarity of description.
1 is a diagram for explaining a problem when a program (PGM) operation is attempted through an FN tunneling method for a target cell of a conventional NOR flash memory.
2 is a conceptual perspective view of a synapse block having a synaptic array composed of a plurality of semiconductor devices according to an embodiment of the present invention.
3 is a conceptual cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.
4 is a cross-sectional view of a synaptic array included in a synaptic block according to an embodiment of the present invention.
5 is a TEM image diagram showing a cross section of a semiconductor device according to an embodiment of the present invention.
6 is a circuit diagram illustrating a neural network including a synaptic block according to an embodiment of the present invention.
7 is a diagram illustrating a connection configuration of the neural network of FIG. 6 in an inference mode.
FIG. 8 is a diagram illustrating a process of adjusting synaptic weights of a target cell in the synaptic block of FIG. 5.
9 is a diagram showing characteristics of the target semiconductor device of FIG. 8 in a process of setting synaptic weights.
10 is a diagram illustrating a result of the method of setting synaptic weights of FIG. 8.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings.

When a part is referred to as being "on" another part, it may be directly on top of another part, or other parts may be involved in between. In contrast, when a part is referred to as being "directly above" another part, no other part is involved in between.

Terms such as first, second and third are used to describe various parts, components, regions, layers and/or sections, but are not limited thereto. These terms are only used to distinguish one part, component, region, layer or section from another part, component, region, layer or section. Accordingly, a first part, component, region, layer or section described below may be referred to as a second part, component, region, layer or section without departing from the scope of the present invention.

The terminology used herein is only for referring to specific embodiments and is not intended to limit the present invention. Singular forms as used herein also include plural forms unless the phrases clearly indicate the opposite. As used in the specification, the meaning of "comprising" specifies a specific characteristic, region, integer, step, action, element and/or component, and the presence of another characteristic, region, integer, step, action, element and/or component, or It does not exclude additions.

Terms indicating a relative space such as "below" and "above" may be used to more easily describe the relationship of one part to another part shown in the drawings. These terms are intended to include other meanings or operations of the device in use together with their intended meaning in the drawings. For example, if the device in the drawing is turned over, certain parts described as being "below" other parts are described as being "above" other parts. Thus, the exemplary term “down” includes both up and down directions. The device can be rotated by 90° or other angles, and terms denoting relative space are interpreted accordingly.

Although not defined differently, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms defined in a commonly used dictionary are additionally interpreted as having a meaning consistent with the related technical literature and the presently disclosed content, and are not interpreted in an ideal or very formal meaning unless defined.

Semiconductor devices according to embodiments of the present invention may form an array structure having a structure similar to that of a NOR flash memory. Each semiconductor device in the array structure may independently perform a write (or program (PGM) and/or erase (or erase) operation) through FN tunneling (Folower-Nordheim tunneling). .

In an embodiment, the semiconductor device operates as a synaptic cell for forming a hardware-based neural network. The neural network includes one or more synaptic blocks, and the synaptic block includes a plurality of synaptic cells. In the present specification, since a synaptic cell refers to a semiconductor device utilized in a neural network, “semiconductor device” and “synaptic cell” are used interchangeably. And by the side in which a series of semiconductor devices are arranged, the term "memory array" is also used interchangeably with "synaptic array".

<Semiconductor device and synapse array>

2 is a conceptual perspective view of a synapse block having a synaptic array composed of a plurality of semiconductor devices according to an embodiment of the present invention.

Referring to FIG. 2, the synapse block 10 includes a plurality of semiconductor devices. The synapse block 10 has a synapse array in which at least one semiconductor device is arranged.

In one embodiment, the synapse block 10 includes a first synaptic array including a first semiconductor device A and a second semiconductor device B. In addition, in some embodiments, the synapse block 10 includes a second synaptic array including a third semiconductor device C and a fourth semiconductor device D. The first synaptic array and the second synaptic array are arranged in parallel.

Hereinafter, embodiments of the present invention will be described in detail using the synapse block 10 made of a 2×2 semiconductor device. However, it will be apparent to those skilled in the art that the configuration of the synaptic block 10 of the present invention is not limited thereto.

3 is a conceptual cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3, the semiconductor device of the synapse block 10 includes: a body 100 made of a first conductivity type (eg, p-type) semiconductor material; A source 210 and a drain 230 made of a second conductivity type (eg, n-type) semiconductor material and formed on the body 100; A first gate 310 formed on the body 100; A gate insulating layer 410 formed between the body 100 and the first gate 310; A second gate 330 formed to face the first gate 310 with the body 100 interposed therebetween; And an insulating layer stack 400 having a charge storage layer 430 formed between the body 100 and the second gate 330. Here, the source 210 and the drain 230 are in contact with the body 100 and are spaced apart from each other.

In some embodiments, the semiconductor device includes a substrate 500; It may be formed on the buried oxide film 600. In this specification, since the first gate 310 is positioned above the second gate 330 based on the substrate 10, the first gate 310 is referred to as a top-gate, and the second gate ( 330 may be referred to as a bottom-gate.

The body 100 may be formed of a material selected from a group of polycrystalline semiconductor materials having a clear grain boundary, including polysilicon or poly germanium, but is not limited thereto. Alternatively, it may be formed of a material selected from the group of amorphous semiconductor materials. As described above, since the body 100 is formed of a polycrystalline or amorphous semiconductor material instead of a single crystal semiconductor material, a three-dimensional stacking is possible.

The semiconductor device has double gates 310 and 330 with the body 100 interposed therebetween, and is configured to store electric charges in the charge storage layer 430 of the insulating layer stack 400. The charge is stored in the charge storage layer 430 when an electric field is formed in the semiconductor device. The charge storage layer 430 is electrically isolated so that the stored charge does not leak out after the electric field disappears. In an embodiment, as shown in FIG. 2, the insulating layer stack 400 may include insulating layers 420 and 440 formed to face each other with a charge storage layer 430 therebetween.

In one embodiment, the double gates 310 and 330 may be made of a polycrystalline semiconductor material including polysilicon. In addition, the double gate may be formed of a first conductivity (eg, n-type semiconductor material).

4 is a cross-sectional view of a synaptic array included in a synaptic block according to an embodiment of the present invention.

In a neural network, the program/erase operation is performed in units of synaptic blocks. The program/erase operation method of the synapse block 10 depends on the array structure of the semiconductor device.

Referring to FIG. 4, the synaptic array includes two or more semiconductor devices, and has an array structure in which drains of different semiconductor devices are arranged adjacent to each other.

For example, in a synaptic array having first and second semiconductor devices A and B, the drain region 231 includes drains (eg, 230A and 230B) of different semiconductor devices A and B. In addition, the source region 211 of the synaptic array is the sources 210A and 210B of the semiconductor devices A and B.

In some embodiments, the synapse array may be further arranged so that sources of different semiconductor devices are also adjacent. For example, when the synaptic array includes three or more semiconductor devices A, B, and C, sources (eg, 210B and 210C) of different semiconductor devices B and C are arranged. However, when a synaptic array in which sources are arranged adjacent to each other is used in a neural network, unlike drains (e.g., 230A, 230B) adjacent to the drain region 231 share a line, adjacent sources (e.g., 210B, 210C) ) Does not share a line and is connected to a separate line, and is configured to each output an operation signal for the input signal of the next neuron.

As such, the structure of the synaptic array in the synaptic block 10 illustrated in FIG. 4 is similar to that of a conventional NOR flash memory.

Typically, a NOR flash memory performs a program operation through a channel hot electron method (CHI). In the channel hot electron method, a strong voltage (eg, 12V to 14V) is applied to the control gate, and a voltage lower than the voltage of the control gate is applied to the drain. Accordingly, a semiconductor device attempting to perform a program/erase operation through a channel hot electron method requires a relatively high drain current. When the body 100 is formed of a polycrystalline or amorphous semiconductor material, the allowable current is smaller than that of a single crystal semiconductor material, and it is difficult to perform a program operation through the channel hot electron method.

On the other hand, in one embodiment, the semiconductor device of the synapse block 10 having an array structure similar to that of a conventional NOR flash memory performs a program and/or erase operation through the FN tunneling method.

<Program operation>

Referring again to FIG. 2, the program operation of the semiconductor device will be described.

The semiconductor device of the present invention performs a program operation by forming a channel from the top gate 310 to the bottom gate 330 through FN tunneling. The synaptic weight of the semiconductor device is adjusted through the program operation.

In one embodiment, an electric field is formed from the top gate 310 to the bottom gate 330. The electric field is formed by applying a higher voltage to the bottom gate 330 and applying a lower voltage to the top gate 310. For example, an electric field is formed by controlling the voltage of the top gate 310 to 0V and controlling the voltage of the bottom gate 330 to a positive value. The potential difference between the bottom gate 330 and the top gate 310 forming the electric field is the physical properties of the body 100, the thickness of the body 100, the physical properties of the insulating film 410, 420 or 440, the insulating film 410, 420, or 440) and depends on the thickness.

The potential difference forming the electric field may be referred to as a program potential difference. Then, when the voltage of the top gate 310 is 0V, the voltage of the bottom gate 330 is referred to as a program voltage.

In this way, when a program voltage is applied to the bottom gate 330, a channel is formed between the double gates 310 and 330, and charges are stored in the charge storage layer 430. Here, the program voltage is, in a semiconductor device having an insulating film 410, 420, or 440 that prevents the stored charge from leaking out of the charge storage layer 430 when the electric field disappears, the charge of the top gate 310 is The lowest voltage among voltages capable of tunneling the insulating layers 410 and 420 between the gate 310 and the charge storage layer 430 is a minimum value. In addition, the predetermined range has a voltage that does not damage each of the insulating layers 410, 420, and 440 when the corresponding voltage is applied as a maximum value.

To this end, the inside of the semiconductor device is designed to enable FN tunneling.

When a voltage within the range allowed by the body 100 (e.g., made of a polycrystalline or amorphous semiconductor material) is applied, the insulating layers 410 and 420 may cause the charge of the top gate 310 to tunnel to the bottom gate 330. It should be thin enough to be able to. If the thickness of the insulating layer 410 of the top gate 310 and/or the insulating layer 420 of the stack 400 is too thick, the tunneling current from the top gate 310 decreases, and weight adjustment is not performed.

In a conventional NOR flash memory in which a voltage of 10V or 12V is applied as a gate voltage, a tunneling insulating film having a thickness of 7nm or 10nm was used. However, when the tunneling insulating layers 410 and 420 of FIG. 2 are designed to be 7 nm and 10 nm, FN tunneling does not occur.

Accordingly, the insulating film 410 has a thickness thinner than that of a gate insulating film (eg, 7 nm to 10 nm) of a conventional transistor.

Meanwhile, the insulating layers 420 and 440 have a thickness thick enough to store electric charges in the charge storage layer 430 in the absence of an electric field. If the insulating layers 420 and 440 are too thin (eg, less than 3 nm), even when a read operation is performed through the top gate 310, leakage current is likely to occur due to leakage of electric charges from the charge storage layer 430.

In addition, the insulating layer 440 has a thickness thicker than that of the insulating layers 410 and 420 in order to suppress tunneling from the charge storage layer 430 to the bottom gate 330 under an electric field causing the insulating layers 410 and 420. For example, the insulating layer 440 is designed to have a thickness to suppress FN tunneling to the bottom gate 330 under the maximum voltage allowed by the body 100.

5 is a TEM image diagram showing a cross section of a semiconductor device according to an embodiment of the present invention.

In an embodiment, the insulating layer 410 or 420 may have a thickness of less than 7 nm in order to transfer electric charges through FN tunneling. In addition, the insulating layer 410 or 420 may have a thickness of 3 nm or more in order to prevent leakage of charge when the electric field is dissipated. Meanwhile, the insulating layer 440 has a thickness thicker than that of the insulating layers 410 and 420 in order to prevent the transfer of electric charges at a voltage at which tunneling occurs in the insulating layers 410 and 420.

In some embodiments, the gate insulating layer 410 is designed to have a thickness of 5 nm to 6 nm. In addition, the insulating film 420 of the stack 400 is designed to have a thickness of 3 nm to 4 nm. In addition, the insulating layer 440 between the charge storage layer 430 and the bottom gate 330 is designed to have a thickness of 8 nm to 9 nm.

For example, as shown in FIG. 5, the insulating films 410 and 420 have 5.18 nm and 3.35 nm, respectively, and the insulating film 440 has 8.64 nm.

In a semiconductor device having the insulating layers 410 and 420 having such a thickness, when a program voltage (eg, 10V to 15V) is applied to the bottom gate 330, a channel is formed between the gates 310 and 330, and the top gate The charge of 310 tunnels through the insulating layer 410, and then tunnels through the insulating layer 420 and moves to the charge storage layer 430, and tunneling to the bottom gate 330 is suppressed by the insulating layer 440. .

On the other hand, when the thickness of the body 100 is too thick, even if a voltage of a predetermined range is applied, the charge of the top gate 310 may not move to the charge storage layer 430. Accordingly, the body 100 has a thickness such that charges from the top gate 310 move to the charge storage layer 430 through the insulating layers 410 and 420 under an allowable electric field. For example, when the body 100 is made of polysilicon, the body 100 may be 20 nm or less.

As described below with reference to FIG. 8, the semiconductor device according to the embodiments of the present invention forms a synaptic array similar to the array structure of the NOR flash memory, while transferring charges to the charge storage layer 430 through the FN tunneling method. Can be saved.

<Eraise operation>

Similar to the program operation, the erase operation of the semiconductor device is also performed by FN tunneling. However, in order to generate FN tunneling for the erasing operation, an electric field is formed from the bottom gate 330 to the top gate 310. That is, the potential difference is set in the direction opposite to the program operation.

In the above example, by applying a voltage lower than the voltage of the top gate 310 to the bottom gate 330 (eg, a negative voltage having an absolute value equal to a positive voltage for a program operation), the charge storage layer 430 ) Stored in the charge storage layer 430 through FN tunneling, or by storing a hole in the charge storage layer 430 through FN tunneling, thereby performing an erasing operation.

The structure of the semiconductor device is not limited to FIG. 2. For example, the nitride layer stack 400 may be positioned in the direction of the top gate 310. In this case, the semiconductor device performs a read operation through the bottom gate 330.

The semiconductor device of FIG. 2 can be used as a single device that performs programming and/or erasing through FN tunneling. However, the present invention is not limited thereto, and may be expanded and utilized as a flash memory array.

In one embodiment, the flash memory array may be used to form a neural network as a synaptic array.

<Synaptic Block and Neural Network>

The synapse block 10 composed of the above-described semiconductor device is configured to perform an independent program and/or erase operation for each cell, so that an independent synaptic weight can be set for each cell. Also, by reading the source current of the synapse block, it is configured to perform a weighted sum operation.

6 is a circuit diagram showing a neural network including a synaptic block according to an embodiment of the present invention.

Referring to FIG. 6, the neural network 1 includes a neuron and a synaptic block 10 between neurons. Depending on the signal direction of the inference operation, neurons that transmit signals to the synaptic block 10 are referred to as pre-nuerons of the synapse, and neurons that receive signals from the synaptic block 10 are next to the synapse. It is referred to as a neuron (post-nueron).

Neurons and synaptic blocks 10 are connected to each other by a synaptic array. As shown in FIG. 6, when the synaptic block 10 includes two synaptic arrays, the previous neurons 21 and 22 and the next neurons 23 and 24 are connected to the synaptic block 10, respectively.

The neural network 1 includes a first switching element 40 that turns on/off an electrical connection between the synaptic block 10 and the neurons 21, 22, 23, and 24.

The synaptic weight of the synapse block 10 is set by a separate control circuit (eg, a peripheral circuit, etc.) 30. The control circuit 30 is connected to a target synaptic block 10 for which a weight is to be set in the neural network 1 and may be set by adjusting the weight of a specific synaptic cell of the synapse block 10. The control circuit 30 may control the synapse block 10 through a plurality of control lines.

Further, the control circuit 30 and the synapse block 10 are further connected through a second switching element 50 that turns on/off the electrical connection. The adjustment of the synaptic weight will be described in more detail with reference to FIG. 8 below.

The switching operation of the first and second switching elements 40 and 50 may be controlled by the control circuit 30 or may be controlled by a separate control device (eg, a computer, etc.).

In addition, the first and second switching elements 40 and 50 may be transistors, as shown in FIG. 6, but are not limited thereto.

7 is a diagram illustrating a connection configuration of the neural network of FIG. 6 in an inference mode.

When the neural network 1 performs an inference operation, the first switching element 40 electrically connects the previous neurons 21 and 22, the synaptic block 10, and the next neurons 23 and 24. As shown in Fig. 7, the synaptic array is connected to the previous/next neurons 21, 22, 23, and 24, respectively.

On the other hand, the synapse block 10 is disconnected from the control circuit 30 by the second switching element 50.

The synaptic block 10 receives an input signal from the previous neurons 21 and 22 and transmits the input signal and an operation signal based on the weight of the synaptic block 10 to the next neurons 23 and 24.

<Read operation>

Referring again to FIGS. 3 and 4, the operation of the synapse block 10 in the inference mode will be described in more detail.

The synapse block 10 of FIGS. 3 and 4 performs a read operation through the top gate 310. The synapse block 10 receives input signals from previous neurons 21 and 22 through the top gate 310 and/or the drain 230 (or the drain region 231).

In one embodiment, the neural network 1 includes a top gate line 315 connected to the top gate 310. Since the top gate line 315 is a line that receives an input signal from a previous neuron, it may be referred to as a pre-synaptic input line (PIL). When the synaptic block 10 includes a first synaptic array and a second synaptic array, the neural network 1 includes two top gate lines 1315 and 2315.

Further, the neural network 1 includes a drain line (DL) 235 connected to the drain 230 (or the drain region 231 ). The drain line 235 also receives input signals from previous neurons 21 and 22. When the synaptic block 10 includes a first synaptic array and a second synaptic array, the neural network 1 includes two drain lines 1235 and 2235.

In one embodiment, the drain line 235 is disposed parallel to the top gate line 315.

In some embodiments, the drain plug 233 is connected to share the drains of the two cells (eg, 230A, 230B) to increase the area efficiency of the array. For example, as shown in FIG. 3, the drain plug 233 is connected to the drain region 231 including the drains 230A and B of the two cells A and B, and the drain plug 233 is It is configured to contact both the drains 230A and 230B of the two cells A and B.

When the synaptic block 10 receives an input signal from the previous neurons 21 and 22 through the top gate line 315 and the drain line 235, the synaptic block 10 receives the input signal and a preset synaptic weight for each cell. Each output signal of the cell representing the product of is generated, and the output signal of each generated cell is transmitted to the next neuron (23, 24).

The neural network 1 includes a source line 215 connected to the source region 211. The source line 215 transmits a source current representing the product of the input signal and the synaptic weight to the next neurons 23 and 24.

In one embodiment, the source line 215 is disposed perpendicular to the top gate line 315. The source line 215 transmits a parallel sum of the output currents of the synaptic array located in a direction perpendicular to the direction of the top gate line 315 to the next neuron. The output current of the synaptic array represents the sum of individual source currents (ie, operation signals) of synaptic cells included in the array.

As a result, the neural network 1 may automatically perform a weighted sum operation of the synaptic block 10 through the source line 215.

In this way, since the source current becomes an output signal of the synaptic block 10 transmitted to the next neuron 23 and 24, the source line 215 may be referred to as a post-synpatic output line (POL). When the synaptic block 10 includes a first synaptic array and a second synaptic array, the neural network 1 includes two source lines 1215 and 2215.

<Set weight for each synaptic cell>

As described above, the semiconductor device in the synapse block 10 performs a program/erase operation through a potential difference between double gates (eg, through voltage control of the bottom gate 330 when the top gate 310 is 0V). do.

For the program/erase operation, an additional control line is required in addition to some of the control lines 235 and 315 for the read operation described above.

2 and 6, the neural network 1 includes a bottom gate line (BGL) 335 connected to the bottom gate 330 of the first and second synaptic arrays. When the neural network 1 includes a first synapse array and a second synapse array, the synapse block 10 includes two bottom gate lines 1335 and 2335.

Since each of the cells in the synaptic array is connected in parallel with the source line 215 and the drain line 235 and the source line 215 are perpendicular to each other, it is similar to the array structure of a NOR flash memory.

By the method of setting the weight of the synaptic block according to another aspect of the present invention, the synaptic weight of a specific target cell of the synaptic block 10 having an array structure similar to that of the NOR flash memory can be adjusted through the FN tunneling method. Naak, it is possible to set an independent synaptic weight for each cell of the synaptic block 10 through the FN tunneling method.

FIG. 8 is a diagram illustrating a process of adjusting synaptic weights of a target cell in the synaptic block of FIG. 5.

Referring to FIG. 8, in the weight control mode, unlike in the inference mode, the synaptic block 10 is disconnected from neurons and is connected to the control circuit 30 for weight control through FN tunneling.

For clarity of explanation, the process of adjusting the weight will be described on the assumption of an example of adjusting the synaptic weight of the semiconductor device A in the synaptic block 10 including the semiconductor devices A, B, C, and D.

The semiconductor device A is a target cell subject to weight adjustment, and the source 210A and the drain 230A of the target semiconductor device A are used to perform a program operation of the semiconductor device A through FN tunneling. Plot In one embodiment, the source and drain 210A and 230A are floated by turning off the first switching element 40.

A potential difference between the top gate 310A and the bottom gate 330B is controlled to form a channel from the top gate 310A to the bottom gate 330B. For example, by applying different voltages to the top gate 310A and the bottom gate 330B of the target semiconductor device A, the potential difference between the top gate 310A and the bottom gate 330B is controlled to form a channel. .

When an electric field is formed from the top gate 310A to the bottom gate 330B, charges of the top gate 310A move in the direction of the bottom gate 330B. In one example, the control circuit 30 controls the voltage of the top gate 310A to 0V through the top gate line 1315 connected to the semiconductor device A, and controls the bottom gate line 1335 connected to the semiconductor device A. ) Through FN tunneling to the bottom gate 310B to transfer electric charges to the charge storage layer 430A. As described above, the program voltage VPP may be, for example, 12V, but is not limited thereto.

Accordingly, a current path is formed from the top gate 310A to the bottom gate 330B, and charges tunneled from the top gate 310A move while tunneling toward the bottom gate 330B. The tunneled charge is finally captured in the charge storage layer 430 by the nitride layer 440 and the weight of the target cell A is adjusted.

In addition, the synaptic cells B, C, and D other than the target cell are controlled to be program-prohibited.

The semiconductor device B is a synaptic cell that shares the target semiconductor device A and the top gate line 1315, and the top gate 310B has the same voltage as the top gate 310A to adjust the weight of the semiconductor device A. Is in the authorized state. In the above example, 0V is applied to the top gate 310B.

In order to prevent FN tunneling in the semiconductor device B, the potential of the bottom gate 330B is controlled to the same potential as that of the top gate 310B. In the above example, the control circuit controls the voltage of the bottom gate 330B to 0V through the bottom gate line 2335.

Then, since an electric field from the top gate 310B to the bottom gate 330B is not formed in the semiconductor device B, weight control is prohibited.

The semiconductor device C is a synaptic cell that shares the target semiconductor device A and the bottom gate line 1335, and the program voltage of the bottom gate 330B is applied to the bottom gate 330C to adjust the weight of the semiconductor device A. It is set to. In the above example, 12V is already applied to the bottom gate 330C.

The channel of the semiconductor element C under the influence of the program potential difference (or program voltage VPP) of the semiconductor element A is boosted to prevent FN tunneling of the semiconductor element C. In the above example, the control circuit 30 applies a program prohibition voltage to the top gate 310C through the top gate line 2315 to prevent the transfer of electric charges.

The program prohibition voltage applied to the top gate 310C may be, for example, approximately half of the program voltage VPP (eg, 0.4 to 0.6 VPP), but is not limited thereto.

Then, the potential difference between the bottom gate 330C and the top gate 310C decreases, so that the charge of the top gate 310C can be prevented from being transferred to the charge storage layer 430C, and eventually the weight in the semiconductor device C Setting is prohibited.

The semiconductor device D is a synaptic cell that shares the semiconductor device C and the top gate line 2315 and shares the semiconductor device B and the bottom gate line 2335. For this reason, the top gate 310D of the semiconductor device D already has the same voltage as the program prohibition voltage of the top gate 310C, and the bottom gate 330D is the bottom gate 330D of the semiconductor device D It has the same voltage as the voltage of ).

In some embodiments, the semiconductor device D may have a potential difference between the gates 310D and 330D that will not cause FN tunneling. In this case, the program of the semiconductor device D is automatically prohibited due to the voltage control of the previous semiconductor devices A, B, and C.

In some other embodiments, the semiconductor device D may have a potential difference between the gates 310D and 330D for generating FN tunneling. However, in this case, FN tunneling occurs from the bottom gate 330D to the top gate 310D, and since there is no charge storage layer 430 in the top gate 310D, weight control does not occur. Since the flash memory generally performs an erase operation before the program operation, charges stored in the charge storage layer 430 do not move to the top gate 310D due to the aforementioned potential difference.

Then, another semiconductor device (B, C, or D) that shares the bottom gate line 335 by applying a program voltage (VPP) to the bottom gate 330 of the new target semiconductor device (B, C, or D) Through a process of applying a program prohibition voltage (eg, 0.5VPP) to the top gate 310 of, the synaptic weight may be independently adjusted for the remaining semiconductor devices B, C, and D in the synapse block 10. .

The erasing process of erasing the synaptic weights already set in the synaptic block 10 of FIG. 8 is similar to the process of setting the synaptic weights described above. However, as described above in the program/erase operation of the semiconductor device, an electric field in a direction opposite to the electric field for setting the synaptic weight may be applied to the target synaptic cell. For example, the synaptic weight may be erased by forming an electric field in the opposite direction by a voltage having the same absolute value and opposite sign as the program voltage for weight setting.

9 is a diagram showing characteristics of the target semiconductor device of FIG. 8 in a process of setting synaptic weights.

In the graph of FIG. 9, the x-axis represents the voltage of the bottom gate 310A, and the y-axis represents the current strength of the gate terminals 310A and 330A. The intensity of the current is an absolute value.

Experimentally, after plotting the source 210A and the drain 230A of the semiconductor device A in the synapse block 10, 0V was applied to the top gate 310A, and the voltage of the bottom gate 330A was changed from 0V. By changing to 14V, the currents of the top gate 310A and the bottom gate 330A were measured. As a result, it is confirmed that gate currents having the same size and opposite signs flow in the two terminals 310A and 330A.

That is, the graph of FIG. 9 indicates that the tunneling current formed toward the bottom gate 330A is based on tunneling from the top gate 310A.

In addition, the magnitude of the tunneling current of the semiconductor device A is on the order of 10 nA. The magnitude of the tunneling current is a very small value compared to the weight setting current of a conventional NOR flash memory. As a result, the graph of FIG. 9 shows that the semiconductor device and the synapse block according to the exemplary embodiments of the present invention perform a program operation through FN tunneling, so that it is less than one thousandth of a channel hot electron method used in a typical NOR flash memory. It supports that power consumption can be reduced.

10 is a diagram illustrating a result according to the method of setting synaptic weights of FIG. 8.

The synaptic weight of the target semiconductor device A may be determined by the method of setting the synaptic weight of the target semiconductor device described with reference to FIG. 8. The setting of the synaptic weight in the semiconductor device is expressed as a shift in the threshold voltage of the semiconductor device.

As shown in FIG. 10, only the threshold voltage of the semiconductor device A, for which the synaptic weight was intended to be set, was shifted to the right, and the threshold voltages of the remaining semiconductor devices B, C, D, which were prohibited from the program, were substantially It remains almost unchanged.

The present invention described above has been described with reference to the embodiments shown in the drawings, but these are merely exemplary, and those of ordinary skill in the art will understand that various modifications and variations of the embodiments are possible therefrom. However, such a modification should be considered to be within the technical protection scope of the present invention. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

Thanks to the 4th Industrial Revolution, the size of the artificial intelligence-related industry is increasing rapidly around the world, and in particular, research on electronic devices that mimic the functions of synapses and neurons in the biological nervous system are actively being conducted.

The semiconductor device according to the embodiments of the present invention can provide a synaptic array (and synapse block) that is friendly to conventional semiconductor processes and can have high reliability. Therefore, it is expected to have high competitiveness in the field of neural network technology in terms of hardware.

Claims (20)

A body made of a first conductivity type semiconductor material;
A source and a drain made of a second conductivity type semiconductor material and formed on the body;
A first gate formed on the body with a gate insulating layer therebetween;
A second gate formed to face the first gate with the body therebetween; And
Including an insulating layer stack having a charge storage layer formed between the body and the second gate,
The first gate is formed by applying a higher voltage to the second gate and applying a lower voltage to the first gate while the source and drain are floating, due to a potential difference between the first gate and the second gate And storing electrons in the charge storage layer through tunneling by an electric field from to the second gate.
delete The method of claim 1, wherein the insulating layer stack,
A first stack insulating layer formed on the charge storage layer; And
A semiconductor device further comprising a second stack insulating layer formed to face the first stack insulating layer with the charge storage layer therebetween.
The method of claim 3, wherein the first stack insulating layer,
A semiconductor device configured to allow charge of the first gate to tunnel toward the second gate when an electric field is formed by a potential difference between the first gate and the second gate, which prevents damage to each insulating layer.
The method of claim 4, wherein the first stack insulating layer,
A semiconductor device, characterized in that it has a thickness of less than 7 nm.
The method of claim 4, wherein the first stack insulating layer,
When the electric field is dissipated, the semiconductor device further configured to prevent the tunneled charge from leaking out of the charge storage layer.
The method of claim 6, wherein the first stack insulating layer,
A semiconductor device having a thickness of 3 nm or more.
The method of claim 3, wherein the second stack insulating layer,
And when an electric field is formed by a potential difference between the first gate and the second gate, which prevents damage to each insulating layer, the semiconductor device is configured to suppress tunneling of the charge of the first gate in the direction of the second gate.
The method of claim 8, wherein the second stack insulating layer,
A semiconductor device having a thickness of 8 nm or more.
The method according to any one of claims 1 and 3 to 9,
The body is a semiconductor device, characterized in that made of any one of a polycrystalline semiconductor material, an amorphous semiconductor material, and combinations thereof.
In a neural network having a plurality of semiconductor devices as synaptic cells,
The semiconductor device is:
A body made of a first conductivity type semiconductor material;
A source and a drain made of a second conductivity type semiconductor material and formed on the body;
A first gate formed on the body with a gate insulating layer therebetween;
A second gate formed to face the first gate with the body therebetween; And
Including an insulating layer stack having a charge storage layer formed between the body and the second gate,
The neural network is:
A synaptic block, comprising: a first synaptic array including a first semiconductor device and a second semiconductor device; And a second synaptic array including a third semiconductor device and a fourth semiconductor device, wherein each synaptic array includes a synaptic block configured such that drains of different semiconductor devices are adjacent to each other;
A drain line electrically connected to the drain region of each synapse array;
A first gate line electrically connected to the first gate of each synapse array; And
A source line electrically connected to a source region of the first synaptic array and a source region of the second synaptic array; Including,
Wherein the drain line and the first gate line receive an input signal from a previous neuron, and the source line outputs an operation result in the synaptic block as an output signal to a next neuron.
The method of claim 11, wherein the synaptic block:
Upon receiving the input signal, a neural network configured to respectively form a source signal based on the input signal and a preset weight for each semiconductor device.
The method of claim 12, wherein the output signal is
A neural network, characterized in that the sum of source signals for each semiconductor device.
The method of claim 11, wherein the synaptic block,
The previous neuron and the other neuron are connected through a first switching element that turns on/off the electrical connection between the previous neuron, the next neuron, and the synaptic block,
A second gate line electrically connected to the second gate of the first synaptic array and the second gate of the second synaptic array; And a second switching element that turns on/off an electrical connection between the control circuit and the synapse block, and is further connected to the control circuit for controlling the semiconductor element through at least a portion of the plurality of lines.
The method of claim 14,
The output of the calculation result is performed in an on state of the first switching element and an off state of the second switching element,
The operation of the control circuit is performed in an off state of the first switching element and an on state of the second switching element.
In a method of setting a synaptic weight of a target semiconductor device in a synaptic array including a plurality of semiconductor devices,
Controlling a potential difference between the first and second gates of the target semiconductor device to form an electric field for tunneling charges in the target semiconductor device after setting the weight of the first semiconductor device according to tunneling;
Controlling a voltage of a second gate of the other semiconductor device to prevent tunneling of charges in the other semiconductor device, sharing a first gate line between the first gate of the target semiconductor device and a control circuit;
A step of controlling a voltage of a first gate of another semiconductor device to prevent tunneling of charges in another semiconductor device, sharing a second gate line between the second gate of the target semiconductor device and a control circuit. Way.
The method of claim 16, wherein controlling a potential difference between the first and second gates of the target semiconductor device comprises:
Applying a first voltage to a second gate of the target semiconductor device; And
Including; applying a second voltage to the first gate of the target semiconductor device;
And a potential difference between the first and second gates of the target semiconductor device causes electrons of the first gate to form a channel for tunneling in a direction of the second gate.
The method of claim 16, wherein controlling the voltage of the second gate of the other semiconductor device comprises:
And applying a voltage equal to the voltage of the first gate of the target semiconductor device to a second gate of the other semiconductor device.
The method of claim 16, wherein controlling a voltage of the first gate of the another semiconductor device comprises:
And applying a third voltage to a first gate of another semiconductor device to be lower than a potential difference between the first and second gates of the target semiconductor device.
The method of claim 19, wherein the third voltage is
The method according to claim 1, wherein the voltage is such that a potential difference between the first and second gates of the other semiconductor device is 40 to 60% of the potential difference between the first and second gates of the first semiconductor device.

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