KR102214556B1 - Memory devices and modules - Google Patents

Abstract

An embodiment of the present invention may include a module error interface and a plurality of memory devices. Each memory device is connected to the module error interface, includes a data interface and a device error interface, and may be configured to exchange error information through the data error interface and the module error interface.

Description

Memory devices and modules {MEMORY DEVICES AND MODULES}

The present invention relates to a memory system architecture, and more particularly, to a memory system architecture having an error correction function.

The memory controllers can be configured to perform error correction. For example, the memory controller may read 72 bits of data, 64 bits of data and 8 bits of parity, from the memory module. The memory controller can perform other error correction techniques. Using such techniques, any errors in data read from the memory module can be identified and corrected. In addition, the memory controller can generate usable information related to the error. A system including a memory controller can make operational decisions based on error information, such as retiring a memory page, system halt, or the like. Such a memory controller can be integrated with the processor. For example, an Intel Xeon® processor may include an integrated memory controller configured to perform error correction.

However, if error correction is performed before data is received by the memory controller, error information related to the correction may not be available in the memory controller, and therefore not available to the system for system management decisions. May not.

The technical idea of the present invention provides a memory device and a module that provide low cost and low power characteristics.

A memory module according to an embodiment of the present invention includes a module error interface and a plurality of memory devices, each memory device being connected to the module error interface, including a data interface and a device error interface, and the device error It may be configured to exchange error information through an interface and the module error interface.

For example, a controller connected to each of the module error interface and the device error interfaces of the memory devices may be further included.

For example, the controller may further include a repeater.

For example, the controller may be connected to each of the device error interfaces through a separate bus.

For example, the controller may be connected to each of the device error interfaces through a common bus.

For example, each memory device may further include an identification input, and the memory device may be configured to receive an identification associated with the common bus through the identification input.

For example, the memory devices may be connected to a daisy-chain link.

For example, each memory may be configured to determine whether information received through the device error interface is related to the memory device in response to a signal received through the daisy chain line.

For example, it may further include a serial presence detection module connected to the controller and configured to communicate through the module error interface.

For example, the controller may further include an address input configured to receive an address, and the controller may be configured to respond to communication received through the module error interface based on the address.

For example, the controller may be configured to collect error information received through the device error interfaces of the memory devices.

A memory module according to an embodiment of the present invention includes a module error interface and a plurality of memory devices, each of which includes a data interface and a device error interface, and is configured to exchange error information through the device error interface. And a controller connected to the module error interface and the device error interface of each memory device.

For example, further comprising a module data interface, the controller may be connected to the module data interface and the data interface of each memory device.

For example, it may further include a serial presence detection module connected to the controller, the serial presence detection module can be accessed through the controller through the module error interface.

For example, the controller may be configured to receive a control signal from the serial presence detection module, and the controller may be configured to provide the control signal through the module error interface.

For example, the controller may be configured to determine addresses associated with the device error interfaces of the memory devices.

A method according to an embodiment of the present invention includes receiving communication through a module error interface of a memory module, reading error information from at least one memory device connected to the controller by a controller, and based on the error information. Thus, it may include the step of responding to the communication through the module error interface.

For example, the method may further include forwarding the communication to the at least one memory device.

For example, reading the error information by the controller may include accessing at least one of the at least one memory device through a corresponding dedicated bus.

For example, reading the error information by the controller may include accessing at least one of the at least one memory device through a common bus.

A system according to an embodiment of the present invention is configured to store data, correct an error in data read from the stored data, and generate error information in response to correcting the error in the data read from the stored data. A memory, and connected to the memory through a first communication path and a second communication path, receive data from the memory through the first communication path, and receive the error information from the memory through the second communication path It may include a processor configured to be.

For example, the error may be a single-bit error, and the error information may indicate that the error has been corrected.

For example, the error information may include corrected error information, and the processor may be configured to receive the corrected error information through a path different from the first communication path.

For example, the memory may be a dynamic random access memory module.

For example, the system may further include a controller connected to the processor and the memory and configured to communicate with the processor and the memory. The controller may be part of the second communication path.

For example, the controller may be a baseboard management controller.

For example, the controller may be connected to the processor by an interface conforming to an intelligent platform management interface.

For example, the controller may be connected to the memory by an interface conforming to the SMBus (System Management Bus).

For example, the controller may be configured to store the error information and provide the error information to the processor in response to a request received from the processor.

For example, the processor may include a memory controller connected to the memory, and the memory controller may be connected to the memory through the first communication path.

For example, the processor may include a memory controller connected to the memory, and the memory controller may not be configured to correct an error in data read from the memory.

For example, the first communication path may include a plurality of data lines and at least one data strobe line, and the memory exchanges an uncorrectable error by a signal transmitted through the at least one data strobe line. Can be configured to

For example, the system may further include a third communication path connected between the memory and the processor. The memory may be configured to exchange an uncorrectable error through the third communication path.

For example, the processor may be configured to request the error information generated by the memory.

For example, the processor may be configured to combine the error information with other information related to the memory.

For example, the other information may be based on information received through the first communication path.

For example, the processor may include an interface connected to the second communication path, and the processor may be configured to receive the error information through the interface and other information through the interface.

For example, the memory may include at least one serial presence detection system and a registering clock driver system, and the other information may be received from the at least one serial presence detection system and the registering clock driver system. .

A memory module according to an embodiment of the present invention may include at least one memory device configured to store data, a first interface, and a second interface. The first interface may be configured to transmit data stored in the at least one memory device, and the second interface transmits error information generated in response to correcting an error in data read from the at least one memory device. Can be configured to

For example, the second interface may include at least one serial presence detection interface and a registering clock driver interface.

For example, the memory module may further include a controller connected to the first interface and configured to change a data strobe signal transmitted through the first interface in response to detection of an uncorrectable error.

For example, the second interface may be configured to transmit error information in response to detection of an uncorrectable error.

A method according to an embodiment of the present invention may include reading data including an error from a memory module, generating error information based on reading the data including the error, and a command for reading the error information from a memory module. Receiving, and transmitting the error information from the memory module in response to the command.

For example, the method may further include receiving the error information from a controller, and transmitting the error information from the controller to a processor.

For example, the method may further include transmitting, from the controller, the command for reading the error information, and receiving the error information from the controller.

For example, the command for reading error information may be referred to as a first command for reading error information, and the method includes receiving, from the processor of the controller, a second command for reading error information, and The method may further include transmitting the first command from the controller in response to the second command.

For example, the method may further include exchanging an uncorrectable error by modifying a data strobe signal from the memory module.

For example, the method may further include, in a processor, generating additional information related to the memory module, and in the processor, combining the additional information with the error information.

For example, transmitting the error information from the memory module may include transmitting the error information and other information through a communication line.

For example, the other information may be information not related to the memory module.

A system according to an embodiment of the present invention includes a memory, a processor connected to the memory through a main memory channel, and a communication line separated from the main memory and connected to the memory and the processor, wherein the memory and the processor are It may be configured to communicate with each other through a memory channel and the communication line.

For example, the processor may include a memory controller, and the memory controller may be part of a main memory channel.

For example, the processor may be configured to receive system management information through the communication line.

For example, the system management information may include at least one of thermal information and power information.

For example, the memory may be configured to exchange error information with the processor through the communication line.

A system according to an embodiment of the present invention includes a memory without an error correction function, an error correction circuit configured to correct an error of data connected to the memory and read from the memory, and to generate error information in response to the error, and It may include a processor connected to the error correction circuit through the first communication path and the second communication path. The processor may be configured to receive corrected data from the error correction circuit through the first communication path, and the processor may be configured to receive the error information from the error correction circuit through the second communication path. have.

The second communication path may be configured to receive the error information from the error correction circuit and transmit the error information to the processor.

A method according to an embodiment of the present invention includes, in a memory device, reading data including an error in response to a read command received through a data interface, and writing error information based on reading the data including the error. And transmitting the error information from the memory module through the error interface.

For example, the method may further include re-reading the data read from memory in response to the error, and confirming the error in response to re-reading the data.

For example, if the re-read data indicates an uncorrectable error, the method may further include confirming the error as uncorrectable.

For example, if the re-read data is an uncorrectable error and indicates that the error is an uncorrectable error, the method may further include confirming the error as non-repairable.

For example, if the read data indicates that there is no error, the method may further include identifying the error as a soft-read error.

For example, the method may further include rewriting the corrected data in the memory in response to the error, which is a correctable error.

For example, if an uncorrectable error occurs during the rewriting, the method may further include checking the error as an uncorrectable error.

For example, if no error has occurred during the rewriting, the method may further include confirming the error as a soft-read error.

For example, if a correctable error occurs during the rewriting, the method may further include attempting to repair the memory.

For example, the method may further include checking the error based on a result of an attempt to repair the memory.

For example, the method may further include exchanging an uncorrectable error by modifying a data strobe signal from the memory module.

A memory module according to an embodiment of the present invention includes a data interface, an error interface, and a plurality of memory devices, each memory device being connected to the data interface and the error interface, and configured to store data. , The data interface, the error interface, and a controller connected to the memory, wherein the controller is configured to transmit data stored in the memory through the data interface, and the controller May be configured to transmit error information generated in response to correcting an error in data read from.

For example, the error interface may be configured to collect error information from the memory devices.

For example, for each memory device, the controller may be configured to modify a data strobe signal transmitted from the memory device to the data interface in response to detecting an uncorrectable error, and the data interface It may be configured to transmit a data strobe signal in response to a modified data strobe signal from one or more of the devices.

A memory device according to an embodiment of the present invention includes a memory configured to store data, a memory connected to the memory, reading data stored in the memory, diagnosing an error of the data read from the memory, and diagnosing the error. And a controller configured to check the error type of the error in response.

For example, the controller may check the error type as at least one of a soft-read error, a soft-write error, a hard error, a repairable error, and a non-repairable error.

For example, the controller may be configured to diagnose the error in response to re-reading the data.

For example, the controller may be configured to diagnose the error in response to rewriting the data.

For example, the controller may be configured to determine whether to repair the memory in response to rewriting the data.

According to an embodiment of the present invention, a memory device and a module that provide low cost and low power characteristics can be provided.

1 is a schematic diagram showing a system having a memory system architecture according to an embodiment of the present invention.
2 is a schematic diagram showing a system having a memory system architecture including a controller according to an embodiment of the present invention.
3 is a schematic diagram showing a system having a memory system architecture including a baseboard management controller (BMC) according to an embodiment of the present invention.
4 is a schematic diagram illustrating a system having a memory system architecture that does not perform processor-based error correction according to an embodiment of the present invention.
5 is a schematic diagram illustrating a system including a memory system architecture having a contaminated data strobe signal according to an embodiment of the present invention.
6 is a schematic diagram illustrating a system including a memory system architecture having a separate non-correctable error signal according to an embodiment of the present invention.
7 is a schematic diagram illustrating a system including a memory system architecture having a software module according to an embodiment of the present invention.
8 is a schematic diagram illustrating a system including a memory system architecture having an error detection and correction module according to an embodiment of the present invention.
9 is a schematic diagram illustrating a system including a memory system architecture having a collection module according to an embodiment of the present invention.
10 is a schematic diagram showing a system including a memory system architecture having an error correction module for collecting information from a memory control architecture module according to an embodiment of the present invention.
11 is a schematic diagram illustrating a system including a memory system architecture including a plurality of modules sharing interfaces according to an embodiment of the present invention.
12 is a schematic diagram showing a system including a memory system architecture having a correctable error module and a serial presence detection/register clock driver module sharing an interface according to an embodiment of the present invention.
13 is a schematic diagram illustrating a system including a memory system architecture with an error correction technology in DRAM according to an embodiment of the present invention.
14A to 14D are schematic diagrams illustrating a system including a memory system architecture with an error correction technique in a module according to embodiments of the present invention.
15 is a schematic diagram illustrating a memory module according to an embodiment of the present invention.
16 is a schematic diagram illustrating a memory module having an SPD or RCD interface according to an embodiment of the present invention.
17 is a schematic diagram illustrating a memory module having a separate non-correctable error interface according to an embodiment of the present invention.
18 is a schematic diagram illustrating a memory device according to an embodiment of the present invention.
19 is a schematic diagram illustrating a memory device according to an embodiment of the present invention.
20 is a schematic diagram illustrating a memory module including memory devices according to an embodiment of the present invention.
21 to 23 are schematic diagrams illustrating memory modules according to various embodiments of the present disclosure.
24 to 26 are schematic diagrams illustrating some of memory modules according to various embodiments of the present disclosure.
27 is a schematic diagram illustrating a memory module according to an embodiment of the present invention.
28 is a flowchart illustrating a method of exchanging error information according to an embodiment of the present invention.
29 is a flowchart illustrating a technique for handling an error according to an embodiment of the present invention.
30 is a flow chart illustrating a technique for handling errors according to an embodiment of the present invention.
31 is a flowchart illustrating a method of exchanging error information according to an embodiment of the present invention.
32 is a flowchart illustrating a method of exchanging error information according to an embodiment of the present invention.
33 is a flowchart illustrating a method of exchanging error information according to an embodiment of the present invention.
34 is a flowchart showing a method of exchanging error information according to an embodiment of the present invention.
35 is a schematic diagram illustrating a system equipped with a memory system architecture according to an embodiment of the present invention.
36 is a schematic diagram showing a server according to an embodiment of the present invention.
37 is a schematic diagram showing a server system according to an embodiment of the present invention.
38 is a schematic diagram showing a data center according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings in order to describe in detail enough to enable a person of ordinary skill in the art to easily implement the technical idea of the present invention. .

The present invention relates to a memory system architecture. The following description is disclosed to the extent that it can be made and used by those skilled in the art. Accordingly, the present invention is capable of making various changes and having various forms, and specific embodiments will be illustrated in the drawings and described in detail in the text. The illustrated embodiments will be described with methods and systems to provide a specific implementation.

However, these methods and systems will work effectively in other embodiments. “Example embodiment”, “one embodiment”, and “other embodiment” may refer to various embodiments as well as the same or different embodiments. These embodiments may be expressed as systems and/or devices including specific configurations. However, the systems and/or devices according to an embodiment of the present invention may include fewer configurations than the illustrated configuration, and a change in an arrangement or a change in types of configurations does not depart from the scope of the present invention. It can be done to the extent that it does not. Exemplary embodiments of the present invention may be described as a method including specific steps. However, such a method and system operation can effectively operate even in a method having additional steps in different and/or different order not contradictory to the embodiments of the present invention. Therefore, it should be understood that the embodiment to which the concept of the present invention is applied is not limited to the illustrated example.

Embodiments will be described as being included in a specific memory system architecture including certain elements. One of ordinary skill in the art to which the present invention pertains will appreciate that the embodiments of the present invention may operate in the same manner in a memory system architecture including other additional configurations or features. However, a person of ordinary skill in the art will appreciate that the method and system of the present invention can operate in the same manner in other structures. Methods and systems may be expressed as a single element in the context. However, it will be appreciated by those of ordinary skill in the art that the methods and systems may operate identically using a memory system architecture having a plurality of elements.

Those familiar with the technical field generally refer to the terms used herein, in particular the terms used in the appended claims, as open terms (i.e. the term'comprising' is'including but not limited to', the term'having' Should be interpreted as'having at least one'). For those skilled in the art, a specific number recited in a claim, even if it is expressly recited in the claim, should not be understood as the absence of a specific number limitation in a claim where no such reference exists. For example, the phrases'at least one' and'one or more' may be included in the dependent claims that follow to aid understanding. However, the use of such a phrase should not be construed as a limitation described by the unclear article'one' for the sake of an example.

In addition, where conventions such as'at least one of A, B, or C'are used, these phrases will be well understood by those familiar with the art (i.e., at least one of'A, B, or C). Inclusive system' includes the meaning of A alone, B alone, C alone, A and B, A and C, B and C, and/or A and B and C together, but is not limited to any one concept. ). For those familiar with the field, letters and/or phrases with two or more separate selectable terms in the detailed description, claims, or drawings are likely to include one, either, or both terms. Should be considered. For example, the phrase'A or B'should be understood to include the possibility of'A', or'B' or'A and B'.

1 is a schematic diagram showing a system having a memory system architecture according to an embodiment of the present invention. System 100 may include memory 102 coupled to processor 104. Memory 102 may be configured to store data. When data is read from memory 102, memory 102 may be configured to correct errors (if possible in the data). For example, memory 102 can be configured to correct single-bit errors. Memory 102 may be configured to detect double-bit errors. Although illustratively described as correcting errors of a specific number of bits, memory 102 may be configured to correct or detect errors of various number of bits. In addition, even though one or more error correction techniques result in single-bit error correction or double-bit error correction detection, memory 102 may perform any error correction techniques capable of correcting at least one error. I can.

Memory 102 may include a device configured to store data. In a particular example, memory 102 may be a dynamic random access memory (DRAM). The memory 102 may include a double data rate synchronous dynamic random access memory (DDR SDRAM) according to various standards such as DDR, DDR2, DDR3, DDR4, or the like. In another embodiment, the memory 102 may include static random access memory (SRAM), nonvolatile memory, or the like.

Memory 102 may be configured to correct errors in data read from stored data or to generate error information in response to attempting error correction. For example, the error information may include information about a corrected error, an uncorrected error, an absence of an error, the number of errors, or similar. The error information may include an actual error, an address of an error, a number of times an error has occurred, or information specific to the memory 102. In a particular example, the error information may include information about a single-bit error indicating that the memory 102 has corrected the single-bit error. Even if specific error information has been described, the error information may include any information about the error.

Processor 104 may be configured to be connected to memory and capable of executing instructions. For example, the processor 104 may be a general purpose processor, a digital signal processor (DSP), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), a programmable logic device, or similar. .

The processor 104 may be coupled to the memory 102 through a first communication path 106 and a second communication path 108. Processor 104 may be configured to receive data from memory via first path 106. For example, the first communication path 106 may be a system memory interface with signal lines for data signals, strobe signals, clock signals, enable signals, or the like. That is, the communication path 106 may be part of a main memory channel, which is an interface between the processor 104 and the memory 102 as a main system memory.

The processor 104 may be coupled to the memory 102 through another communication path, a second communication path 108. Processor 104 may be configured to receive error information from memory 102 via second communication path 108. Thus, in an embodiment, the processor 104 may be configured to receive error information and, in particular, corrected error information through the second communication path 108 rather than the first communication path 106. The corrected error information is information on the corrected error. As described above, the error information may include various types of information related to an error. Accordingly, the corrected error information may include similar types of information related to the corrected error.

The software 110 is shown to be connected to the processor 104. However, the software 110 may represent various programs, drivers, modules, routines, or the like that may be executed on the processor 104. For example, the software 110 may include drivers, kernel modules, daemons, applications, or the like. In some embodiments, software 110 may be configured to enable processor 104 to perform specific functions described herein.

Although one memory 102 has been used as an example, any number of memories 102 may be connected to the processor 104 through two communication paths similar to the communication paths 106 and 108. In an embodiment, each memory 102 is separated from the other memories 102 via a dedicated first communication path 106 and a dedicated second communication path 108 separate from the other memories 102. It may be connected to the processor 104 through. However, in other embodiments, the first communication path 106 may be shared by one or more memories 102 and the second communication path 108 may be shared by one or more memories 102. In addition, although a single first communication path 106 has been described, a plurality of first communication paths 106 may be provided between one or more memories 102. Similarly, although single second communication paths 108 have been described, a plurality of second communication paths 108 may be provided between one or more memories 102.

In an embodiment, error information may be exchanged through an out-of-band communication path. The second communication path 108 may be such an out-of-band communication path. That is, the main communication between the processor 104 and the memory 102 may be performed through the first communication path 106. In contrast, error information can be exchanged through the out-of-band communication path 108.

2 is a schematic diagram showing a system having a memory system architecture including a controller according to an embodiment of the present invention. In this embodiment, system 200 is similar to memory 102, processor 104, communication paths 106 and 108, and software 110 of FIG. 1, memory 202, processor 204, Communication paths 206 and 208, and software 210 may be included. However, the second communication path 208 may include a first bus 212 connected to the controller 214 and a second bus 216 connected between the controller 214 and the processor 204. That is, the controller 214 connected to both the processor 204 and the memory 202 may be part of the second communication path 208.

The controller 214 may be a device configured to be connected to the memory 202 and the processor 204. For example, the controller 214 may be a general purpose processor, a digital signal processor (DSP), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), a programmable logic device, or similar. .

Buses 212 and 216 may be various communication lines. For example, the buses 212 and 216 are SMBus (system management bus), I2C (inter-integrated circuit) bus, IPMI (intelligent platform management interface) compliant bus, Modbus bus, or similar Can be. In certain embodiments, at least a portion of the communication path 208 may operate at a generally slower transmission rate than the communication path 206. For example, the communication path 206 between the memory 202 and the processor 204 may be designed to be higher than a data-rate transfer of 10 GB/S. However, the communication path 208 may have a data transfer rate lower than 10 Mbit/s, 100 kbit/s, or the like. Thus, in some embodiments, the ratio of the data rate of the communication path 206 to the communication path 208 may be about 100, 1000, or more.

In an embodiment, the second communication path 208 may be a dedicated communication path. That is, the second communication path 208 can only be used for communication of information between the memory 202 and the processor 204. However, in other embodiments, the controller 214 may make other devices accessible. For example, the nonvolatile memory device 268 may be connected to the controller 214 by the bus 212. In another embodiment, other devices 266 may be connected to the controller 214. Thus, information other than the information from the memory 202 is transferred to and from the processor 204 and/or memory 202 via the bus 212 and/or 216. Can be. In particular, error information from memory 202 may be exchanged with processor 204 via second communication path 208, which is used for other purposes, including those with nonvolatile memory.

In an embodiment, the controller 214 may include a nonvolatile memory 254. Nonvolatile memory 254 may be configured to store error information from memory 202. Therefore, error information can be stored in the controller 214 even when the power is cut off. Processor 24 may be configured to request error information from controller 214. Accordingly, the controller 214 may be configured to respond to such a request by providing error information stored in the nonvolatile memory 254, and access the memory 202 to receive the error information in response to the processor 204 or the like. You can search.

In an embodiment, the controller 214 may be configured to poll the memory 202 for error information. In another embodiment, the memory 202 may be configured to push memory information to the controller 214. Regardless of this, the error information stored in the nonvolatile memory 254 may be generally up-to-date copy.

3 is a schematic diagram showing a system having a memory system architecture including a baseboard management controller (BMC) according to an embodiment of the present invention. In this embodiment, system 300 is similar to memory 202, processor 204, communication paths 206 and 208, and software 210 of FIG. 2, memory 302, processor 304, Communication paths 306 and 308, and software 310 may be included. However, the controller 314 may be a BMC 314.

The baseboard management controller (BMC) 314 may be configured to manage the system 300. For example, BMC 314 may be connected to various sensors of system 300, including sensors of processor 304, memory 302, other devices 366, or the like. BMC 314 can be configured to collect and report on various system parameters, such as temperature, cooling status, power status, or the like. BMC 314 may be configured to manage the system and enable access to information according to standards. The management information may be made available to the processor 304 and thus may be made available to the software 310. Alternatively, the BMC 314 may generate information usable through another communication path, such as an out-of-band communication path. Here, the out-of-band communication path may be any communication path that does not include the processor 304.

4 is a schematic diagram showing a system having a memory system architecture that does not perform processor-based error correction according to an embodiment of the present invention. In this embodiment, the system 400 includes memory 102, processor 404, communication paths 106 and 108 of FIG. 1, and a memory 402 similar to software 110, processor 404, and communication. Paths 406 and 408, and software 410. However, in this embodiment, the processor 404 may include a memory controller (MC) 450 and a machine check architecture (MCA) register 452.

The memory controller 450 may be integrated in the processor 404. The memory controller 450 may be a part of a main memory channel that is a main interface between the processor 404 and the memory 402. Memory controller 450 may be configured to control access to data stored in memory 402 via communication path 406. In some embodiments, memory controller 450 may be configured to correct errors, but when error correction is performed by memory 402, it may not have an opportunity to correct such errors. However, in this embodiment, the memory controller 450 may not be configured to correct an error in data read from the memory 402. The memory controller 450 may not be configured to report any errors based on data read from the memory 402.

The MCA register 452 is a register in which hardware errors can be reported. For example, a cache error, bus error, data error, or the like may be detected and reported in the MCA register 452. However, since the memory controller 450 is not configured to correct errors in the data read from the memory 402, any potential error information based on the data read from the memory 402 is the MCA register 452. May not be reported on. Regardless, as described above, error information may be exchanged with the processor 404 via the communication path 408. Thus, even without going through the memory controller 450 and the MCA register 452, error information may be available to the software 410.

In an embodiment, the availability of error information over the second communication path 408 may enable a low cost system 400. For example, a processor 404 with a memory controller 450 without any memory correction may be used, and error information may still be available. In particular, although memory error correction is desirable, a processor 404 without an error correction function may be used because there is error information available through the second communication path 408. Thus, software 410, including any software that uses error information, can still operate, as if the processor was able to correct memory errors. The processor 404 without error correction may be a lower power, lower cost processor. Thus, the overall power usage and cost of the system 400 can be reduced.

Although the memory controller 450 is shown to be integrated in the processor 404, the memory controller 450 may be separated from the processor 404. Regardless, communication path 408 may bypass memory controller 450 and other portions of processor 404 with error correction circuitry. Bypassing such components may allow the exchange of error information over the second communication path 408 to be largely independent of the memory controller 450, the MCA register 452, or the like. That is, although similar information is not available through the memory controller 450 and/or the MCA register 452, the error information may still be available.

5 is a schematic diagram showing a system including a memory system architecture having a poisoned data strobe signal according to an embodiment of the present invention. In this embodiment, the system 500 includes a memory 502, a processor 504, similar to the memory 102, processor 104, communication paths 106 and 108, and software 110 of FIG. Communication paths 506 and 508, and software 510 may be included. However, in this embodiment, the communication path 506 may include data lines 532 and data strobe line(s) 533. Other lines have been provided as part of the communication path 506. However, the lines are not shown for clarity.

In an embodiment, error information related to an uncorrectable error and error information related to a correctable error may be exchanged through different paths. As described above, correctable error information may be exchanged through the communication path 508. The non-correctable error information may include various other types of information based on the non-correctable error. Uncorrectable error information may be exchanged through the first communication path 506. For example, the memory 502 may be configured to correct an uncorrectable error by a signal transmitted (or not transmitted) through the data strobe line(s) 533. That is, during normal data transmission, a data strobe signal transmitted through the data strobe line(s) 533 may be toggled when data is transmitted. However, if the memory 502 detects an uncorrectable error, the memory 502 is a data strobe for transmission through the data strobe line(s) 533, different from the data strobe signal during normal data transmission. It can be configured to generate a signal. In particular, the memory 502 may be configured not to toggle the data strobe signal transmitted through the data strobe line(s) 533. When such a condition is detected, processor 504 may be configured to generate a hardware exception, which may be handled by software 510.

Although signals and/or lines in communication path 506 have been used as an example of a technique for exchanging an uncorrectable error, other signals and/or lines may be used to exchange an uncorrectable error with the processor. Regardless of how the exchange is made, by stopping the system 500 or taking other actions, the processor 504 may be configured to respond to such an exchange of non-correctable errors.

6 is a schematic diagram illustrating a system including a memory system architecture having a separate non-correctable error signal according to an embodiment of the present invention. In this embodiment, the system 600 includes memory 102, processor 104, communication paths 106 and 108 of FIG. 1, and memory 602 similar to software 110, processor 604, and communication path. 606 and 608, and software 610. However, in this embodiment, a separate communication path 634 may be connected between the memory 602 and the processor 604.

Similar to system 500 of FIG. 5, non-correctable errors may be exchanged with processor 604. In this embodiment, the memory 602 may be configured to exchange uncorrectable error information through the communication path 634. For example, the third communication path 634 may be a dedicated line separate from the first communication path 606. Accordingly, error information related to an uncorrectable error may be received by the processor 604 through a communication path different from the first and second communication paths 606 and 608.

7 is a schematic diagram illustrating a system including a memory system architecture having a software module according to an embodiment of the present invention. In this embodiment, the system 700 includes memory 102, processor 104, communication paths 106 and 108 of FIG. 1, and memory 702 similar to software 110, processor 704, and communication path. S 706 and 708, and software 710. However, in this embodiment, the software 710 may include a module 718.

Module 718 may represent a portion of software 710 configured to access error information 722 through a processor. For example, module 718 may include kernel modules, drivers, extensions, or the like. Module 718 may include drivers for interfaces associated with communication path 708. In certain embodiments, module 718 may include a driver associated with an IPMI bus, an IPMI2 bus, or the like. Other information 720 may be available to software 710. Error information 722 is shown separately to represent a portion of software 710 associated with error information 722.

In this embodiment, the module 718 may cause the processor 704 to request error information from the memory 702. For example, the memory 702 may generate error information. Thereafter, the processor 704 may transmit a request for error information through the communication path 708. The memory 702 may be configured to respond to the request with error information over the communication path 708.

8 is a schematic diagram illustrating a system including a memory system architecture having an error detection and correction module according to an embodiment of the present invention. In this embodiment, system 800 includes memory 702 of FIG. 7, processor 704, communication paths 706 and 708, and memory module 718 that operates in response to information 720 and 722. A memory 802 similar to software 710, a processor 804, communication paths 806 and 808, and software 810 including a memory module 818 that operates in response to information 820 and 822. can do. However, in this embodiment, the software 810 may include an error detection and correction (EDAC) module 824.

In an embodiment, the EDAC module 824 can manage error information provided from memory, cache, input/output devices, peripheral devices, buses, and/or other parts of the system 800 You can expose such information to the layer. In particular, EDAC module 824 can be configured to receive error information from module 818. The EDAC module 824 may be configured to combine error information with other information so that other modules, applications, or the like can access the error information.

9 is a schematic diagram illustrating a system including a memory system architecture having a collection module according to an embodiment of the present invention. In this embodiment, system 900 includes memory 702 of FIG. 7, processor 704, communication paths 706 and 708, and a module 718 that operates in response to information 720 and 722. Software 810, which includes a memory 902, processor 904, communication paths 906 and 908, and a module 818 that operates in response to information 920 and 922, similar to software 710 It may include. However, in this embodiment, the software 910 may include the second module 926. The second module 926 may be configured to receive the information 920. In particular, this other information 920 may include information that is not related to an error in the memory 902. At least a portion 921 of the other information 920 may be received by the first module 918. The first module 918 may combine some or all of the other information 920 from the second module 926 and the error information 922. The first module 918 may provide combined information in a single interface. For example, the first module 918 may be configured to provide combined information to an EDAC module, such as the EDAC module 824 of FIG. 8.

10 is a schematic diagram showing a system including a memory system architecture having an error correction module for collecting information from a memory control architecture module according to an embodiment of the present invention. In this embodiment, the system 1000 includes modules 918 and 926 that operate in response to memory 902, processor 904, communication paths 906 and 908, and information 920 and 922 of FIG. ), similar to software 910, including memory 1002, processor 1004, communication paths 1006 and 1008, and modules 1018 and 1026 that operate in response to information 1020 and 1022. Included software 1010 may be included. However, in this embodiment, the first module 1018 may be an error correction (EC) module, and the second module 1026 may be an MCA module.

The MCA module 1026 may be configured to control access to an MCA register, such as the MCA register 452 of FIG. 4. The information 1020 may represent information from the MCA register 452. The EC module 1018 may be configured to access the MCA module 1026 and recover the information 1020. The EC module 1018 may combine the information 1020 from the MCA module 1026 with the error information 1022 and provide the combined information in a single interface.

In particular, the EC module 1018 may provide an interface in a manner similar or the same as the MCA module 1026 allowing the processor 1004 to correct an error. For example, if the processor 1004 is configured to correct errors in data read from the memory 1002, the information may be available through the MCA module 1026. However, if the processor 1004 is not configured to correct an error in the data read from the memory 1002, the error information is transmitted by the communication path monitored by the MCA module 1026 due to the error being corrected in the memory 1002. If not, the MCA module 1026 will not be able to provide error information. Regardless of this, the EC module 1018 combines the information 1022 and the information 1020 obtained through the communication path 1008, and the MCA module 1026 provides the processor 1004 to the memory 1002. Information used to correct an error in data read from the MCA module 1026 or combined information similar or identical to the error information available to the MCA module 1026 may be provided. The software 1010 may use the same or similar interface regardless of whether the processor 1004 provides an error correction function. In other words, the processor 1004 having an error correction function is not essential for software that depends on sufficiently used error information. As a result, it is possible to reduce cost by the processor 1004 without an error correction function.

11 is a schematic diagram illustrating a system including a memory system architecture including a plurality of modules sharing interfaces according to an embodiment of the present invention. In this embodiment, system 1100 is similar to software 710 that operates in response to memory 702, processor 704, communication paths 706 and 708, and information 720 and 722 of FIG. 7. , Memory 1102, processor 1104, communication paths 1106 and 1108, and software 1110 that operates in response to information 1120 and 1122. However, in this embodiment, the software 1110 may include a first module 1118, a second module 1128, and an interface module 1130.

The first module 1118 is similar to the module 718 of FIG. 7. However, the first module 1118 may be configured to receive error information from the memory 1102 through the interface module 1130. The interface module 1130 may be configured to provide an interface to the communication path 1108. For example, the interface module 1130 may be a module configured to allow access through an IPMI bus.

Other modules such as the second module 1128 may also be configured to perform communication via the interface module 1130. For example, the second module 1128 may be configured to access other devices connected to the IPMI bus, or to access other portions of the memory 1102 such as thermal information or power information. Both error information and other information may be part of the information 1122 delivered by the interface module 1130. That is, error information may be transmitted using dedicated software through the entire path, but related or unrelated information or sources may be shared with modules, interfaces, buses, or the like.

12 is a schematic diagram showing a system including a memory system architecture having a correctable error module sharing an interface and a serial presence detect/registering clock driver module according to an embodiment of the present invention . In this embodiment, the system 1200 includes modules 1118 and 1128 operating in response to memory 1102, processor 1104, communication paths 1106 and 1108, and information 1120 and 1122 of FIG. And modules 1218 and 1228 that operate in response to software 1110 including memory 1202, processor 1204, communication paths 1206 and 1208, and information 1220 and 1222, including 1130. And software 1110 including 1230). However, in this embodiment, the first module 1218 is a corrected error (CE) module, and the second module 1228 is a serial presence detect (SPD)/register clock driver (registering clock). driver (RCD) module 1228.

In particular, the SPD/RCD module 1228 may be configured to access information related to the serial presence detection system and/or the register clock driver system. The SPD/RCD module 1228 may be configured to access one or both of such systems. The information can be accessed through the second communication path 1208. Accordingly, in the present embodiment, error information provided from the memory 1202 is information related to SPD/RCD and may be accessed through the communication path 1208.

13 is a schematic diagram illustrating a system including a memory system architecture with an error correction technology in DRAM according to an embodiment of the present invention. In this embodiment, the system 1300 is similar to the error correction module 1018 and the MCA module 1026 operating in response to the memory 1002, the processor 1004, and information 1020 and 1022 of FIG. , A memory 1302, a processor 1304, and a kernel 1310 including an error correction module 1318 and a machine check architecture (MCA) module 1326 that operate in response to information 1320 and 1322. . However, in this embodiment, each of the memories 1302 may be provided as a dual line memory module (ECC DIMM) having an ECC function.

Each ECC DIMM 1302 may be configured to store data and correct errors in the stored data. In this embodiment, the ECC DIMM 1302 may be connected to the memory controller 1350 of the processor 1304 through corresponding communication paths 1362. Communication path 1364 may include lines for carrying data signals and data strobe signals similar to communication path 506 of FIG. 5. ECC DIMM 1302 has a communication path 1308 including bus 312, BMC 314, and bus 1312, BMC 1314, and bus 1316 similar to bus 316 of FIG. Each may be connected to the processor 1304 through the.

In an embodiment, the ECC DIMM 1302 may be configured to correct one or more errors in data read from the ECC DIMM 1302. Error correction technologies include single error correction-double error detection (SEC-DEC) technology, single-chip chipkill technology, and double-chip chipkill technology. It may include. Any error correction technique can be used.

In the present embodiment, the memory controller 1350 may not be configured to perform error correction or, conversely, may not be configured to receive error information from the ECC DIMM 1302. Since the error has already been corrected in the data passing through the ECC DIMM 1302, the memory controller 1350 may not receive any information indicating a correctable error. However, error information, particularly corrected error information, may be communicated to the processor 1304 through a communication path 1308 such as the buses 1312 and 1316 and BMC 1314.

In an embodiment, the processor 1304 may be a processor that cannot perform error correction, but may be a processor having an interface that can be connected to the bus 1316. However, once the processor 1304 is set by the kernel 1310, in particular, the error correction module 1318, the overall system 1300 is configured to perform error correction similar to a system having a processor having an error correction function. Can be.

In an embodiment, the error correction module 1318 may generate a virtual memory controller having an error correction interface. For example, as described above, the error correction module 1318 may be configured to receive information from the MCA module 1326. In this case, the information may be information provided by an actual memory controller having an error correction interface without some or all error information. The error correction module 1318 may supplement error information for generating a complete set of information expected from the ECC interface of the memory controller. As a result, the EDAC module 1324, the memory ECC daemon 1358, other applications 1360, and the like can be used without modification of the processor and those used with error correction. For example, the EDAC module 1324 may be configured to poll the EC module 1318 for memory ECC information. Consequently, the EC module 1318 may return the error information received through the second communication path 1308. The memory ECC daemon 1358 in communication with the EDAC module 1324 may poll the EDAC module 1324 for error information. After that, the memory ECC daemon 1358 may take an action corresponding to the error information at the application level. Such actions may include page expiration, other error management actions to operate system 1300, actions to maintain a reliability level, recommendation for discard, and the like.

As described above, an uncorrectable error can be detected. Uncorrectable error information may be transferred to the error correction module 1318 through the memory controller 1350, the MCA register 1352, and the MCA module 1326. For example, an uncorrectable error may be transmitted as a non-maskable interrupt or an exception through the MCA module 1326. In a specific embodiment, regardless of how it is delivered to the memory controller 1350, the memory controller 1350 may generate a hardware exception in response to an uncorrectable error. The MCA module 1326 may intercept the above-described exception information and transmit it to the error correction module 1318. Then, the error correction module 1318 may transmit exception information to the EDAC module 1324. In addition to or instead of transmitting the non-correctable error information as described above, the non-correctable error information may be transmitted through the communication path 1308.

In an embodiment, the ECC DIMM 1302 may be configured to transmit the corrected data to the processor 1304. However, data errors may occur between the ECC DIMM 1302 and the memory controller 1350. Accordingly, some form of error correction may be performed between the ECC DIMM 1302 and the processor 1304 or the memory controller 1350. For example, data transferred from the ECC DIMM 1302 may be encoded with an error correction code intended to detect errors occurring on the communication link 1362. By such error correction, the entire path transmitted from the storage medium of the ECC DIMM 1302 to the processor 1304 may be protected by error correction.

14A to 14D are schematic diagrams illustrating a system including a memory system architecture with an error correction technique in a module according to embodiments of the present invention. Referring to FIG. 14A, the system 1400 may include similar configurations to the system of FIG. 13. However, in this embodiment, the ECC DIMM 1402 includes a buffer 1462. The buffer 1462 may be configured to correct an error included in data read from the ECC DIMM 1402. In particular, uncorrected data may be read from internal memory devices such as DRAM devices (not shown) of the ECC DIMM 1402. The buffer 1462 may be configured to correct an error of uncorrected data and generate corrected error information, similar to other memories described herein. The above-described error information is transmitted through the communication path 1408, and may be used by the methods described above. That is, the error information can be used by various methods described above regardless of how the error information is generated.

Referring to FIG. 14B, configurations of the system 1400 may be similar to those of FIG. 14A. However, in this embodiment, the EDAC module 1424 may be configured to exchange information with the MCA module 1426. For example, the EDAC module 1424 may be configured to poll the MCA module 1426 for hardware-related information, uncorrectable error information, or information available through the MCA module 1426. The EDAC module 1424 may be configured to combine information provided from the MCA module 1426 with information delivered from the error correction module 1418.

Referring to FIG. 14C, configurations of the system 1400 may be similar to those of FIG. 14A. However, in this embodiment, the MCELOG module 1425 may be configured to receive information from the error correction module 1418. The MCELOG module 1425 may be configured to record machine check events (MCEs) related to various system errors such as memory errors, data transmission errors, and the like. The MCELOG module 1425 may be configured to generate an interrupt to the memory ECC daemon 1458 and transmit error information to the memory ECC daemon 1458.

Referring to FIG. 14D, configurations of the system 1400 may be similar to those of FIG. 14C. However, in this embodiment, similar to the difference between FIGS. 14A and 14B, the MCELOG module 1425 is configured to receive information provided from the MCA module 1426 similar to the EDAC module 1424 of FIG. 14B. Can be.

Although, in FIGS. 14A to 14D, the ECC DIMM 1402 including the buffer 1462 was described, in another embodiment, various configurations of the system 1300 of FIG. 13 including the ECC DIMM 1302 may be applied. I can.

15 is a schematic diagram illustrating a memory module according to an embodiment of the present invention. The memory module 1500 may include one or more memory devices 1501, a data interface 1536, an error interface 1538, and a controller 1541. The data interface 1536 may be configured to transmit and receive data 1540 from data stored in the memory devices 1501. The memory module 1500 may be configured to generate error information for data read from one or more memory devices 1501. The error interface 1538 may be configured to transmit error information generated in response to correcting an error in data read from one or more memory devices 1501.

The data interface 1536 is an interface through which data stored in the memory devices 1501 is transmitted, and an interface through which data 1540 to be stored in the memory devices 1501 is received. For example, the data interface 1536 may include buffers, driver circuits, termination circuits, or other circuits for lines such as data lines, strobe lines, address lines, enable lines, clock lines, and the like.

The error interface 1538 may be an interface configured to communicate over a specific bus, such as SMBus, IPMI, or other buses described herein. In an embodiment, the error interface 1538 may be an existing interface through which the memory module 1500 exchanges error information and other information. Accordingly, the information 1542 may include not only error information but also other information.

The controller 1541 may be any device configured to be connected to the memory devices 1501. For example, the controller 214 may include a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device, and the like. As will be described later in detail, the controller 1541 may include a buffer such as an RCD or the like.

The controller 1541 may be connected to the memory devices 1501, the data interface 1536, and the error interface 1538. The controller 1541 may be configured to obtain error information. In an embodiment, the controller 1541 may obtain error information from the memory devices 1501, but in another embodiment, the controller 1541 corrects an error in data from the memory devices 1501 and It can be configured to generate information.

In an embodiment, the controller 1541 may be configured to exchange an uncorrectable error through the data interface 1536. For example, as described above, a data strobe signal can be used to indicate an uncorrectable error. The controller 1541 may be configured to adjust the strobe signal transmitted through the data interface 1536 in response to detecting an uncorrectable error.

16 is a schematic diagram illustrating a memory module having an SPD or RCD interface according to an embodiment of the present invention. In this embodiment, the memory module 1600 is similar to one or more of the memory devices 1501, the data interface 1536, the error interface 1538, and the controller 1541 described in FIG. The above memory devices 1601, a data interface 1636, an error interface 1638, and a controller 1641 may be included. However, the error interface 1538 of FIG. 15 may be the SPD/RCD interface 1638 here.

The SPD/RCD interface 1638 can be used to provide access to a serial presence detection (SPD) system or an RCD system (not shown). In a specific embodiment, error information may be available through a specific register or memory area in the above-described SPD or RCD system. Accordingly, error information can be obtained through the same interface from which SPD or RCD information can be obtained.

Since error information is available through the existing hardware interface, additional hardware is unnecessary. For example, a command received through the SPD/RCD interface 1638 for accessing error information is distinguished from other commands in address, register address, or other fields not used by the SPD/RCD system. In an embodiment, a new register of the SPD/RCD system may be defined to post error information. In other embodiments, existing registers may be reused to exchange error information.

17 is a schematic diagram illustrating a memory module having a separate non-correctable error interface according to an embodiment of the present invention. In this embodiment, the memory module 1700 is one or more similar to the one or more memory devices 1501, the data interface 1536, the error interface 1538, and the controller 1541 described in FIG. The above memory devices 1701, a data interface 1736, an error interface 1738, and a controller 1741 may be included. However, the memory module 1700 may also include an uncorrectable error interface 1744.

The uncorrectable error (UE) interface 1744 is a separate interface configured to allow the memory module 1700 to exchange uncorrectable errors. For example, the non-correctable error interface 1744 may be a dedicated line or a dedicated bus.

18 is a schematic diagram illustrating a memory device according to an embodiment of the present invention. In this embodiment, the memory device 1800 may include a data interface 1836 and an error interface 1838. The data interface 1836 and error interface 1838 may be similar to the data interface 1536 and error interface 1538 of FIG. 15. However, in the present embodiment, the data interface 1836 and the error interface 1838 may be interfaces to the memory device 1800 rather than a memory module such as the memory module of FIG. 15.

The memory device 1800 may include a controller 1841. The controller 1814 may be any device configured to be connected to the memory 1801 and interfaces 1836 and 1838. For example, the controller 1841 may include a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device, and the like.

The memory 1801 may be configured to store data. For example, the memory 1801 may be a memory cell array. However, in other embodiments, the data may be stored in other configurations. The memory 1801 may include electrical, magnetic, chemical, optical, or other types of storage media.

The controller 1841 may be configured to transmit data stored in the memory 1801 through the data interface 1836. The controller 1841 may be configured to receive data to be stored in the memory 1801 through the data interface 1836. Such transmission was marked as data 1840.

The controller 1841 may be configured to transmit error information generated in response to correcting an error in data read from the memory 1801 through the error interface 1838. The error information may be similar to the type of error information described above. The controller 1841 may be configured to receive a command, command, or other information via the error interface 1838. The transmission of such commands, orders, or other information is indicated by information 1842.

In this embodiment, both data 1840 and information 1842 are shown as being via controller 1841. However, in another embodiment, components of the memory device 1800 are controlled by the controller 1841, so that data 1840 and information 1842 may not pass through the controller 1841. For example, in some embodiments, data and/or error information may be provided to the data interface 1836 and the error interface 1838 under the control of the controller 1841, but may be via the controller 1841.

19 is a schematic diagram illustrating a memory device according to an embodiment of the present invention. In this embodiment, the memory device 1900 may include a memory cell array 1901. The memory cell array 1901 may include memory cells in which data is stored. In particular, the memory cell array 1901 may be configured to store encoded data. Sense amplifier 1902 and write circuit 1904 are present in memory device 1900 that allow data to be written to and read from memory cell array 1901 at an address specified by address 1906. This is an example of a circuit. However, in other embodiments, other read and write circuits may be associated with the memory cell array 1901. In addition, although sense amplifier 1902 and write circuit 1904 are shown as part of memory cell array 1901, such circuits can be separated from memory cell array 1901. In addition, although a single memory cell array 1901 is shown, a plurality of memory cell arrays 1901 may be provided.

The memory cell array 1901 may be connected to an error correcting code (ECC) engine 1908. The ECC engine 1908 may be configured to correct at least one error in the data read from the memory by encoding the data written to the memory cell array 1901 and decoding the data read from the memory cell array 1901. . In particular, the ECC engine 1908 may be configured to receive write data 1910. The ECC engine 1908 is configured to encode the write data 1910, so that the encoded data can be written to the memory cell array 1901 by the write circuit 1904 at the location specified by the address 1906. Similarly, the ECC engine 1908 may be configured to receive encoded data from the memory cell array 1901 and decode the data into decoded output data 1924. Such encoding and decoding can be performed according to various ECC algorithms such as those described herein. For example, SEC-DED (Single Error Correct-Double Error Detect) may be used as an example of the ECC algorithm, but other algorithms may also be used.

Although signals such as an address 1906 and write data 1910 are shown as signals used to write data to the memory cell array 1901, the memory device 1900 writes data to the memory cell array 1901. It can be configured to receive and process other related signals. However, such components have been omitted for clarity. In addition, other components that can modify the address 1906 or change the direction of access have also been omitted for clarity.

In a specific embodiment, during a write operation, the ECC engine 1908 may be configured to receive bits stored by the memory device 1900 as write data 1910. The ECC engine 1908 calculates the ECC bit value(s) for the write data 1910 into the memory cell array 1901 using the write circuit 1904, as with the original data values as encoded data. It may be configured to transmit ECC bit(s). Thereafter, the memory cell array 1901 may be configured to store the encoded data.

During a read operation, the ECC engine 1908 may be configured to receive encoded data from the memory cell array 1901. That is, the sense amplifier 1902 and other circuits may be used to read previously stored ECC bit(s) and original data values as encoded data. Thereafter, the ECC engine 1908 may decode the encoded data, generate output data 1924, and generate error information.

The output data 1924 may be output from the memory device 1900. In some embodiments, other components may be disposed between the ECC engine and the output of the memory device 1900. In some embodiments, buffer 1932 may be configured to buffer output data 1924. In some embodiments, RCD module 1934 may be configured to receive, buffer, and output output data 1924. Here, such optional components are shown in dotted lines.

The ECC engine 1908 may be configured to generate an error flag. For example, the ECC engine 1908 may be configured to generate a correctable error (CE) flag. The CE flag may be set when the ECC engine 1908 successfully corrects an n-bit error, and n may be less than or equal to the number of bit-errors the ECC engine 1908 is configured to correct. The ECC engine 1908 may be configured to generate an uncorrectable error (UE) flag. When the ECC engine 1908 detects the number of bit-errors that are larger than the number of bit-errors configured to be corrected by the ECC engine 1908, the UE flag may be set. In a particular example, with the SEC-DED, the CE flag indicates that a single-bit error has been corrected, and the UE flag may indicate that a two-bit error has occurred.

The ECC controller 1918 may be configured to correct error and manage related error information. The ECC controller 1918 may be configured to receive error information 1914 from the ECC engine. The error information 1914 may include information indicating whether there is no error, whether it is a correctable error, whether it is an error that cannot be corrected, and the number of errors. The ECC controller 1918 may be configured to receive an address 1906 associated with the read. Accordingly, the ECC controller 1918 can combine the error information 1914 and the address 1906 from the ECC engine 1908 into new error information. As will be described later in detail, the ECC controller 1918 may be configured to generate write data 1910 that are encoded by the ECC engine 1908 and written to the memory cell array 1901.

In an embodiment, the ECC controller 1918 may be configured to store error information. For example, the ECC controller 1918 may include a plurality of registers in which error information is stored. Various error information may be stored in the ECC controller 1918. As will be described later in detail, the record of the error may be stored including information about the error. For example, the error write may include information such as address information, data read from the type of error memory cell array 1901, whether repair or other actions have been executed.

In an embodiment, the ECC controller 1918 may be configured to perform communication 1926 with external devices. For example, communication 1926 may include transmission of error information. When a correctable error or an uncorrectable error occurs, the error information may be transmitted by the ECC controller 1918. Such transmission may be spontaneous or in response to a request from an external device, such as according to a regular schedule, occurrence of an error, during a refresh cycle, and the like.

In an embodiment, the ECC controller 1918 may be configured to communicate over a bus such as SMBus to exchange error information. In some embodiments, the memory device 1900 may include a command buffer 1928. The command buffer 1928 may be configured to buffer commands received through the bus for the ECC controller 1918.

In an embodiment, the memory controller 1900 may include an SPD module 1930. The ECC controller 1918 may be configured to communicate with the SPD module 1930. The SPD module 1930 may be configured to perform operations related to an SPD interface. In addition, the SPD module 1930 may be configured to enable access to error information through the ECC controller 1918. For example, certain commands received through the SPD module 1930 may be converted into appropriate commands and/or signals to access error information stored in the ECC controller 1918.

The DQS modifier 1920 may change the data strobe signal from the memory cell array 1901 in response to the error information 1916 from the ECC engine 1908, and may output the changed data strobe signal 1922. . In a specific embodiment, the error information 1916 may be a signal indicating whether an uncorrectable error has occurred. The DQS modifier 1920 is configured to change the data strobe signal 1912, so if the error information 1916 indicates that an uncorrectable error has occurred, the output data strobe signal 1922 may not be toggled. However, if an uncorrectable error signal has not occurred, the DQS modifier 1920 may pass the data strobe signals 1912. For example, the DQS modifier 1920 may include a logic circuit such as an OR gate, an AND gate, a NAND gate, and a transmission gate.

In an embodiment, the DQS modifier 1920 may be used to exchange time-sensitive information. For example, when an uncorrectable error occurs, the error may be related to the current read operation. While information related to an uncorrectable error, such as by SMBus, is exchanged with external devices by the ECC controller 1918, the communication path may operate at a slower rate than the communication path for data 1924. Accordingly, communication of occurrence of an uncorrectable error may be delayed compared to a corresponding read operation. Conversely, communication that an uncorrectable error has occurred by the DQS modifier 1920 may occur substantially simultaneously with a corresponding read operation. That is, the changed output data strobe signal 1922 is a data strobe signal related to transmission of data 1924 having an uncorrectable error.

Although specific components of the memory device 1900 have been described as examples, other components may be provided. For example, the memory device 1900 may be configured to receive or transmit various strobe signals, selection signals, control signals, enable signals, and the like.

20 is a schematic diagram illustrating a memory module including memory devices according to an embodiment of the present invention. In this embodiment, the memory module 2000 may include a data interface 2036 and an error interface 2038, similar to the data interface 1536 and error interface 1538 of FIG. 15. However, in this embodiment, the memory module 2000 may include a plurality of ECC memory devices 2001-1 to 2001 -N. The ECC memory devices 2001 may be any of the memory devices described herein, such as the memory devices 1800 and 1900 of FIGS. 18 and 19 described above.

Using the memory device 1800 as an example of the memory devices 2001, and referring to FIGS. 18 and 20, each of the memory devices 1800 may be connected to a data interface 2036 and an error interface 2038. I can. With respect to the data interface 2036, the data interfaces 1836 of the memory devices 1800 may form at least a part of the data interface 2036. For example, data input/outputs, strobe signals, and the like of each data interface 1836 may be collected in the data interface 2036. Address input and/or other control signals of the data interface 2036 may be distributed to the data interfaces 1836 of the memory devices 1800. Thus, data can be transmitted to or received from memory devices 1800 (and consequently, memory module 2000) via data interface 2036 to memory devices 1800 (consequently, memory module 2000). have.

Similarly, error interfaces 1838 may be connected to error interface 2038. The error interfaces 1838 can be connected in a variety of ways. For example, the error interfaces 1838 and the error interface 2038 may be connected to a common bus in the memory module 2000. In another example, the error interface 2038 may be directly connected to each error interface 1838 of the memory devices 2001. The error interface 2038 may be configured to collect error information from the memory devices 1800. Accordingly, the error information may be configured to be transmitted from the memory devices 1800 (as a result, the memory module 2000) through the error interface 2038.

Although the memory device 1800 of FIG. 18 is used as an example of the memory device 2001 of the memory module 2000, other memory devices may be used in other embodiments. For example, the memory device 1900 of FIG. 19 may be used as the memory devices 2001. Referring to FIG. 19, an address 1906, write data 1910, output data 1924, data strobe signal 1922, and the like of each memory device 1900 may be connected to a data interface 2036. Similarly, the ECC controller 1918 of each memory device 1900 may be connected to the error interface 2038.

21 to 23 are schematic diagrams illustrating memory modules according to various embodiments of the present disclosure. Referring to FIG. 21, in the present embodiment, the memory module 2100 is one or more memory devices similar to the one or more memory devices 1501, the data interface 1536, and the controller 1541 of FIG. 15. Devices 2101, a data interface 2136, and a controller 2141 may be included. The module error interface 2138 may be similar to the error interface 1538, and may be configured to exchange information 2142 similar to the information 1542, but the module error interface 2138 can be used with it and the memory devices 2101. The term "module" has been used to distinguish it from the device error interfaces 2139 of ). As will be described later in detail, the module error interface 2138 can be used for communication other than exchanging error information.

Here, each of the memory devices 2101 may include a data interface 2137 and a device error interface 2139 similar to the data interface 1836 and error interface 1838 of FIG. 18. The data interfaces 2137 of the memory devices 2101 may be connected to the data interface 2136 of the module, but such connections are not shown for clarity. Further, in some embodiments, the connection of the data interface 2136 and the data interfaces 2137 of the memory devices 2101 need not be via the memory controller 2141. For example, in some embodiments, data 2140 transferred from and to memory module 2100 may be buffered in controller 2141, but in other embodiments, such transfer may be ) Can be bypassed.

Each memory device 2101 may be connected to a module error interface 2138, and may be configured to exchange error information through a device error interface and a module error interface. In this embodiment, the controller 2141 may be connected to the device error interfaces 2139 and the module error interface 2138.

As will be described in more detail later, the controller 2141 may be configured to manage communication related to the memory devices 2101, such as communication related to error information. For example, the controller 2141 accesses error information related to the memory devices 2101 through the corresponding device error interfaces 2139, forwards communication with the memory devices 2101, and It may be configured to collect error information from 2101.

In certain embodiments, controller 2141 may include registers 2149 accessible through module error interface 2138. The controller 2141 may be configured to collect error information from the memory devices 2101 by communicating with the memory devices 2101 through the device error interfaces 2139. Such error information may be stored in registers 2149 and may be accessible to devices external to memory module 2100. Alternatively, the controller 2141 may be configured to combine error information or summarize error information. In particular, in an embodiment, each memory device 2101 may generate its own error information isolated from other memory devices 2101. Accordingly, when the controller 2141 accesses all of the memory devices 2101, the controller 2141 may be configured to generate additional error information that each memory device 2101 cannot generate. Although registers 2149 are used as an example, error information and other information may be stored in the controller 2141 in different ways.

In an embodiment, the controller 2141 may be configured to receive commands related to the memory devices 2101. As described herein, the controller 2141 may be configured to receive a command for reading error information. However, the controller 2141 may be configured to receive other types of communications related to the memory devices 2101. For example, the controller 2141 may be configured to receive commands related to maintenance of the memory devices 2101. As an example of such management, there may be a command for repairing memory cells in one or more memory devices 2101, rewriting data, or initializing a refresh cycle. The controller 2141 may be configured to receive such communications and communicate with the memory devices 2101 in response thereto.

Referring to FIG. 22, in the present embodiment, the memory module 2200 may be similar to the memory module 2100, but the memory module 2200 is connected to the controller 2141 and detects a serial presence (SPD). (2143) may include modules. The SPD 2143 may be configured to communicate through the controller 2141. For example, controller 2141 can be configured to forward communication to and from SPD 2143. In another embodiment, the controller 2141 may be configured to obtain information from the SPD 2143, and may act as a proxy for the SPD 2143 using such information through the module error interface 2138. . Although the module error interface 2138 uses the term "error", information other than the error information may be transmitted and received through the module error interface 2138.

In an embodiment, the controller 2141 may be configured to respond to an address associated with the SPD 2143. However, the controller 2141 is configured to respond to a different address or use additional information in the communication, such that whether the communication is intended for the SPD 2143, to access error information, or for the memory devices 2101. It may be determined whether it is intended or not for the controller 2141.

Referring to FIG. 23, in this embodiment, the memory module 2300 may be similar to the memory module 2100 of FIG. 21 or the memory module 2200 of FIG. 22. However, a registering clock driver (RCD) module 2145 may be used instead of the controller 2141. Here, the RCD 2145 may be configured to buffer data transmitted to the memory module 2300 and transmitted from the memory module 2300. In addition, RCD 2145 may be configured to provide the functions described herein in connection with controller 2141.

The SPD 2143 may be connected to the RCD 2145. Thus, similar to the memory module 2200, the SPD 2143 may be accessible through the RCD 2145, and the RCD 2145, similar to the controller 2141, as described above, the SPD 2143 It can act as a proxy for

24 to 26 are schematic diagrams illustrating some of memory modules according to various embodiments of the present disclosure. Referring to FIG. 24, in the present embodiment, the controller 2141, the memory devices 2101, and the SPD 2143 may be similar to those of FIG. 22. The controller 2141 may be connected to the bus 2452. Bus 2542 may be an SMBus, or other buses described herein. Bus 2542 may form part or all of module error interface 2138.

The controller 2141 may be configured to receive the address 2454. The address 2454 may be an input hardwired in hardware. In certain embodiments, address 2454 may be a series of pins on a memory module that, when inserted into a particular socket, are connected to a high or low value to distinguish the memory module from others connected to the same bus 2542 have.

In an embodiment, the address 2454 may be connected to the SPD module of the memory devices, but the address may be made for other purposes to communicate with the controller 2141 instead of the SPD such as the SPD 2143. Accordingly, the memory module described in this specification may be pin-compatible with an existing memory module.

In this embodiment, the SPD 2143 and the memory devices 2101 may be respectively connected to the controller 2141 through separate buses 2450. Here, the buses are indicated as buses 2450-1 to 2450-N to correspond to the memory devices 2101-1 to 2010-N. The bus 2450-N+1 may correspond to an additional bus connected to the controller 2141 and the SPD 2143. In a particular embodiment, each of the buses 2450 may be SMBus or other similar communication lines. However, in another embodiment, for example, a point-to-point communication link, including a communication line that may have only two endpoints, is used instead of the buses 2450. I can. That is, although the term bus is used, a communication line can be configured to be connected to two devices.

In an embodiment, the SPD 2143 may be configured to respond to the control signal 2147 or to generate the control signal 2147. The control signal 2147 may include an out-of band signal in relation to the bus 2450-N+1. For example, the control signal 2147 may include an interrupt signal. In particular, in an embodiment, the control signal 2147 may be an event signal related to the SPD 2143. The controller 2141 may be configured to receive or generate a control signal 2451. The control signal 2451 may be a signal used by the SPD 2143. However, since the controller 2141 may be configured to use an interface that the SPD 2143 may have, the SDP 2143 may not be configured to directly receive the control signal 2451. Accordingly, the controller 2141 may be configured to exchange the SPD 2143 and the control signal 2451 as the control signal 2147. Although a single control signal related to the SPD is used as an example, in another embodiment, a plurality of control signals may be forwarded to/from the SPD 2143, the memory devices 2101, or other components. . Such control signals are not shown for clarity, but may be provided.

In addition, the controller 2141 may include additional functionality beyond the SPD 2143, which may be associated with a control signal similar to the control signal 2147. For example, the control signal 2141 may be configured to generate an interrupt based on error information from the memory devices 2101. Thus, the control signal 2451 can be used to exchange not only the signal from the SPD 2143 but also an interrupt based on error information. The controller 2141 may be configured to determine whether such a control signal is intended for the controller 2141, the SPD 2143, or the like.

In an embodiment, many additional pins may be used for memory devices 2101. In a particular embodiment, the memory device 2101 may include two additional pins (one for a clock signal and one for a data signal). The controller 2141 includes 2x(N+2) pins for the buses 2452 and 2450-1 to 2450-N+1, three pins for the address 2454, and control signals 2451 and 2147. It may contain two pins for

Referring to FIG. 25A, in this embodiment, the controller 2141, the memory devices 2101, and the SPD 2143 may be similar to those of FIG. 24. However, the controller 2141 may be connected to the memory devices 2101 through the bus 2450-1, and may be connected to the SPD 2143 through the bus 2450-2. In this embodiment, the buses 2450-1 and 2450-2 may be separate buses.

Furthermore, the bus 2450-1 may be a common bus for the memory devices 2101. The bus 2450 may be SMBus buses. Since the plurality of memory devices 2101 may be connected to the bus 2450-1, each memory device 2101 may include a corresponding ID input 2456. ID 2456 may be similar to address 2454. For example, for each memory device 2101, a corresponding ID 2456 may be hardwired in hardware at a unique address among the memory devices 2101. In a particular example, each ID 2456 may include four pins that can hold high or low. Thus, 16 unique addresses may be available for IDs 2456. Although four pins are used as an example, any number of pins may be used to distinguish it from any number of memory devices 2101.

Each of the memory devices 2101 may be configured to transmit a corresponding ID 2456 to an address or other identifier used for the bus 2450-1. In an embodiment, the address generated from the ID 2456 may be an address used as a slave address for SMBus. In this embodiment, the SPD 2143 and the controller 2141 may be devices on the bus 2450-2. Thus, the address input need not be used for SPD 2143.

In an embodiment, a plurality of additional pins may be used for the memory devices 2101. In a specific embodiment, the memory device 2101 may include two additional pins (one for a clock signal and one for a data signal), similar to FIG. 24, but the IDs 2456 It may also contain 4 pins for The controller 2141 has six pins for the buses 2452, 2450-1, and 2450-2, three pins for the address 2454, and control signals 2451 and 2147, similar to FIG. 24. It may include two pins for ).

Referring to FIG. 25B, in this embodiment, the controller 2141, the memory devices 2101, and the SPD 2143 may be similar to those of FIG. 25A. However, the SPD 2143 and the memory devices 2101 may be connected to the controller 2141 through a common bus 2450. As described above, the memory devices 2101 may be configured to receive the ID 2456. Since the SPD 2143 is on the same bus 2450 as the memory devices 2101, the SPD 2143 may be configured to use a unique address among the SPD 2143 and the memory devices 2101. . SPD 2143 may be configured to receive ID 2457. The SPD 2143 may be configured to convert the ID 2457 into an address for use in the bus 2450.

In an embodiment, the shape of the ID 2457 may be different from the ID 2456. For example, ID 2457 may include three pins used to indicate the address of SPD 2143, while ID 2456 may each include four pins. In addition, IDs 2457 and IDs 2456 need not correspond to the same address. For example, ID 2457 of 010b and ID 2456 of 0010b may correspond to different addresses.

In an embodiment, a plurality of additional pins may be used for the memory devices 2101. In a specific embodiment, the memory device 2101 may include two additional pins (one for a clock signal and one for a data signal), similar to FIG. 24, but also ID 2456 It may also include 4 pins for ). The controller 2141 has 4 pins for the buses 2450 and 2452, 3 pins for the address 2454, and 2 pins for the control signals 2451 and 2147, similar to FIG. 24. Can include.

Referring to FIG. 26, in this embodiment, the controller 2141, the memory devices 2101, and the SPD 2143 may be similar to those of FIG. 25B. The SPD 2143 may be configured to receive the address 2454 similar to the controller 2141. However, in this embodiment, the memory devices 2101 may not be configured to receive IDs 2456. Conversely, the memory devices 2101 may be respectively connected to a common bus 2459, such as a single wire or net separated from the bus 2450-1. In an embodiment, the public bus may be a daisy-chain link.

In an embodiment, the memory devices 2101 may be connected to the bus 2459. The memory devices 2101 may be configured to determine whether information received through the controller 2141 is related to the memory device 2101 in response to a signal received through the bus 2459. In an embodiment, the memory devices 2101 may be configured to communicate through the bus 2459 to establish addresses of the memory devices 2101 on the bus 2450. For example, the first memory device can determine the address and increment the counter in response to the counter. The counter value may be transmitted to the second memory device 2101. The second memory device 2101 may be configured to determine an address and increment the counter in response to the counter. This process may continue until each memory device 2101 has a unique address.

In an embodiment, a plurality of additional pins may be used for the memory devices 2101. In a specific example, memory device 2101 may include two additional pins (one for a clock signal and one for a data signal), similar to FIG. 24, but for bus 2459. It may also contain one additional pin. Controller 2141, similar to FIG. 24, 6 pins for buses 2452, 2450-1, and 2450-2, 3 pins for address 2454, and control signals 2451 and 2147. Can include 2 pins for

In an embodiment, in any of the configurations described above, the controller 2141 may be configured to determine the addresses of the memory devices 2101 and the SPD 2143, if connected to the same bus. For example, the controller 2141 may be configured to dynamically allocate addresses to the memory devices 2101 and SPD 2143 using the SMBus address resolution protocol. Although a technique for determining addresses in one type of bus is used as an example, other techniques may be appropriately used for a particular bus 2450.

27 is a schematic diagram illustrating a memory module according to an embodiment of the present invention. In this embodiment, the memory module 2700 may be similar to the memory module 2100 of FIG. 21. However, a repeater 2750 was used as the controller 2141. The repeater 2750 and the repeater 2750 are configured to expand the communication line connected to the module error interface 2138 so that the error interfaces 2139 of the memory devices 2101 and the SPD 2143 can be connected to the communication line. Can be. For example, if the loading of memory devices 2101 and/or the nature of the network permit, repeater 2750 may only be a wire, such as a wire of a shared medium. In another example, repeater 2750 may include a device configured to allow more devices to be connected to the bus, or to allow longer buses. Although the term repeater is used, the repeater 2750 may include a hub, an extension device, a switch, a bridge, and the like. In addition, a device capable of expanding the network may be used as the repeater 2750. Since the memory devices 2101 are directly accessible through the module interface 2138, each memory device 2101 of the memory module 2700 obtains information about error information individually by an external controller such as BMC. I can.

In an embodiment, configurations of the memory devices 2101, the SPD 2143, and the repeater 2750 may be similar to those of FIG. 25B. That is, referring to FIGS. 25B and 27, the memory devices 2101 may be connected to the repeater 2750 and connected to the bus 2450, respectively. Each of the memory devices 2101 may be configured to receive an ID 2456. As a result, memory devices 2101 can be configured to determine respective addresses for use on bus 2450.

In an embodiment, specific addresses or IDs may be associated with various types of devices. For example, temperature sensors may be associated with a specific address or range of addresses. However, the memory devices 2101 may not have such an address or ID association. Thus, addresses, IDs, ranges of such parameters, and the like can be made for different purposes from other types of devices, such as devices not used in a system that can use the memory modules described herein. For example, the ID or address for the I2C mux may be used as the ID or address of the memory devices 2101.

28 is a flowchart illustrating a method of exchanging error information according to an embodiment of the present invention. In step 2800, an error may occur when reading data from memory. In response, in step 2802, an error may be diagnosed. As will be described later in more detail, not only the error is identified, but also other corrective actions for correcting the error may be taken.

In step 2804, error information may be reported. As described above, a communication line between the memory device, other components of the memory module, and the processor may be used to exchange error information. Reporting error information 2804 can be done over such communication lines.

29 is a flowchart illustrating a technique for handling an error according to an embodiment of the present invention. This embodiment exemplarily shows how a correctable error is handled (eg, how a correctable error is handled by the ECC controller of FIG. 19). In step 2900, after a correctable error (CE) occurs, a CE record may be generated. The CE record may contain various information related to the error described above.

In step 2902, the data can be read again. In this embodiment, in response to re-reading data, three consequences occur, such as when an error does not occur, when a correctable error occurs, or when an uncorrectable error (UE) occurs. I can. If no error occurs, in step 2904, the write can be marked as a soft-read error. If a correctable error occurs, in step 2908, the corrected data may be rewritten. If an uncorrectable error occurs, in step 2906, the error record may be updated to an uncorrectable error record.

As part of rewriting the data corrected in step 2908, an error may occur. If no error occurs, in step 2910, the error record may be marked as a soft-read error. If an uncorrectable error has occurred, in step 2906, the error record may be updated to an uncorrectable error record.

In step 2912, if a correctable error has occurred, it may be determined whether the memory cell is repairable. In a specific embodiment, the correctable error in this step may indicate whether the error cannot be repaired by rewriting. Thus, errors can be caused by hardware errors. Depending on the result of determining whether the memory cell can be repaired in step 2912, the error record can be further annotated and repaired. If the memory cell is repairable, in step 2914, the memory cell is repaired and the error may be marked as a hard error. If the memory cell is non-repairable, in step 2916, an error record may be marked as a non-repairable hard error. Thus, by the diagnosis described above, errors can be further categorized or repaired.

Although the rewrite in step 2908 was used as an example of an operation indicating an uncorrectable error, a correctable error, or no error, such information may be the result of other operations. For example, after rewriting data in step 2908, a read operation may be performed and similar error information may be generated.

30 is a flow chart illustrating a technique for handling errors according to an embodiment of the present invention. This embodiment is an example of how an uncorrectable error is handled (eg, how an uncorrectable error is handled by the ECC controller 1918 of FIG. 19 ). In step 3000, after an uncorrectable error (UE) occurs, a UE record may be generated. In some embodiments, the UE recording may be a result of an update to the UE recording in step 2906 described in FIG. 29 above.

In step 3002, data related to the UE record may be read again. In response to this, other operations may be performed. If an uncorrectable error occurs after reading again, in step 3006, the record may be marked as an unrepairable error. If no error occurs, in step 3004, the record can be marked as a soft-read error. If a correctable error occurs, in step 3008, the corrected error may be recorded again. Similar to the rewrite in step 2908 of FIG. 29, the result generated from the operation may come from other sources, such as reading the data again after the rewriting.

In response to the result of the rewriting of data, other operations may be performed. If the result is an uncorrectable error, in step 3006, the record may be marked as an unrepairable error. If no errors have occurred, in step 3010, the write can be marked as soft-read and soft-write errors.

In step 3012, if the result is a correctable error, it may be determined whether the memory cell is repairable. If the memory cell is repairable, in step 3014, a repair operation is performed, and the write may be marked as a soft-read and repairable hard error. If the memory cell is not repairable, in step 3016, the record may be marked as a soft-read and non-repairable hard error.

Although the various categorizations of errors have been described as described above, in some embodiments, all of such information may not be available outside of the memory device. Certain types of errors, such as the soft-read and soft-write errors of FIG. 20, for example, may be collected as soft-errors. Any collection, summary, etc. can be performed to generate error information to be transmitted from the memory device. In addition, the memory device can be configured to provide a specific level of detail.

In an embodiment, using a technique as described in FIGS. 29 and 30, the memory device performs error management techniques such as soft-read error recovery (eg, memory scrubbing, hard-error repair, etc.). Can be configured to

In an embodiment, the operations described above may be performed after a read operation occurs. In particular, the operations can be configured so as not to prevent the read operation. However, once an appropriate interval, such as a maintenance interval, refresh cycle, etc., occurs, error records can be processed, updated, and memory cells repaired.

Although specific sequences relating to error handling have been used as examples of criteria for categorizing errors or repairing memory cells, in other embodiments, other sequences may be used. For example, referring to FIG. 29, determining whether a memory cell can be repaired in step 2910 is accompanied by a CE during a reread operation in step 2902 and a CE during a rewrite operation in step 2908. If you do, it can be executed. However, in another embodiment, determining whether the memory cell is repairable in step 2910 may be performed only when the re-read operation in step 2902 causes CE after attempting a plurality of re-read operations. That is, in some embodiments, a specific criterion for categorizing errors may be different from the examples described above.

Furthermore, although specific names of error types have been used, in some embodiments, all of those error types may not be used. Similarly, in some embodiments, other error types may be used.

31 is a flowchart illustrating a method of exchanging error information according to an embodiment of the present invention. In step 3100, a read error may occur when reading data from the memory. In response to this, error information may be generated. For example, the read error may be a corrected correctable error. The error information may be information on a correctable error. For example, the read error may be a plurality of errors. In this case, the error information may be information on these errors.

In step 3102, a read error command may be received. In an embodiment, the read error command may be received by the memory module. If an error occurs, in step 3014, the memory may transmit error information. Before receiving the read error command in step 3102, the memory module may store error information regarding an error that has occurred. In step 3104, error information regarding an error that has occurred first may be transmitted in response to a read error command. However, if no error has occurred, transmission of error information in step 3104 may be transmission of information indicating that no error has occurred.

As described above, error information may be transmitted over the bus. In particular, the bus may be an out-of-band path with respect to the main data path of the memory module. Accordingly, the transmission in step 3104 may include transmitting error information through the bus.

31B is a flowchart illustrating a method of exchanging error information according to an embodiment of the present invention. Referring to FIGS. 31A and 31B, in the present embodiment, the operation of FIG. 31B may be an operation of a controller. In particular, in step 3106, a read error command may be transmitted from the controller. The read error command transmitted in step 3106 may be a read error command received in step 3102. As described above, in step 3104, error information may be transmitted. In step 3108, error information may be received at the controller. For example, the controller can be configured to poll a memory module. Accordingly, the controller may receive a read error command in step 3106 and receive error information in step 3108. As described above, the controller may include a memory, such as a nonvolatile memory, in which the memory controller may store error information. Thereafter, in step 3110, the error information may be transmitted to the processor.

Although the use of a controller that transmits a read error command has been described as an example, in another embodiment, in step 3106, the processor may transmit a read error command. In step 3102, the read error command may be received by the memory module, and in step 3110, the error information may be transmitted to the processor. That is, the error information need not be received or processed in the controller.

32 is a flowchart illustrating a method of exchanging error information according to an embodiment of the present invention. With reference to FIGS. 28 and 32, and using the memory module 2100 by way of example in step 3200, communication may be received through the module error interface 2138. In step 3202, error information may be read from at least one memory device 2101.

In an embodiment, reading the error information in step 3202 may be performed in response to the communication in step 3200. However, in another embodiment, reading the error information may be performed at different times (including, for example, before receiving the communication). Regardless, the error information from the memory devices 2101 in step 3204 may be used to respond to the communication.

Reading the error information in step 3202 may be performed in various ways. For example, each of the memory devices 2101 may be accessed through a corresponding dedicated bus, as shown in FIG. 24. In another embodiment, each of the memory devices 2101 may be accessed through a common bus, as shown in FIGS. 25A, 25B, or 25C. In another embodiment, communication may be forwarded to one or more memory devices 2101 such as repeater 2750 of FIG. 27.

Although the memory module of FIG. 21 is used as an example, the technology described herein may be used by other memory modules, systems, and the like.

33 is a flowchart illustrating a method of exchanging error information according to an embodiment of the present invention. In step 3300, a read error may occur. In step 3312, a read error command may be transmitted to the controller. For example, the controller may receive a read error command from the processor. In step 3314, the read error command may be transmitted to the memory module. For example, in step 3314, the controller forwards the read error command received from the processor to the memory module, transforms the read error command, or generates another read error command for the memory module, and sends the read error command to the memory module. Can be transmitted. The read error command transmitted in step 3314 may be received in step 3302, and in step 3304, the error information may be transmitted similarly to steps 3102 and 3104 of FIG. 31A. As described above, the error information may be transmitted to the processor.

As described above, the controller can poll the memory module for error information and store the error information. Thus, when a read error command is received by the controller from the processor, the controller may already have read error information. The controller can transmit the stored error information to the processor. However, the controller need not poll the memory module for more error information before the controller sends the stored error information to the processor.

34 is a flowchart showing a method of exchanging error information according to an embodiment of the present invention. In operation 3400, the processor may transmit a read error command. In response thereto, in step 3402, the processor may receive error information. In step 3406, the processor may combine the error information with additional information. As described above, the additional information may be various types of information, such as a state of a processor, a peripheral part, and buses, including information not related to a memory module. In a specific embodiment, the processor may combine error information with information from the MCA module.

In a particular embodiment, in step 3408, the combined information may be provided to the EDAC module. As described above, the EDAC module makes information about errors in various systems available to higher level applications.

35 is a schematic diagram illustrating a system equipped with a memory system architecture according to an embodiment of the present invention. In this embodiment, system 3500 may include a processor 2104 and software 2110, similar to the processor 104 and software 110 of FIG. 1. However, in this embodiment, the system 3500 may include a memory 3502 and an error correction circuit 3568.

In this embodiment, the memory 3502 may not be configured to correct an error. The memory 3502 is connected to the error correction circuit 3568 and may be configured to transmit data to the error correction circuit 2168 through the communication path 3352.

The error correction circuit 3568 may be configured to correct an error in data received from the memory 3502. The error correction circuit 3568 may be connected to the processor 2104 through the second communication path 3570 and the third communication path 3508. The second communication path 3570 is the main path through which the processor 3504 is configured to receive data. For example, the second communication path 3570 may be a system bus for the processor 3504.

On the other hand, the third communication path 3508 is similar to the communication path 108 described above. That is, the third communication path 3508 may be a separate out-of-band communication path including the controller 3514 or may be various modifications of the communication paths described above.

36 is a schematic diagram showing a server according to an embodiment of the present invention. In this embodiment, the server 3600 may include a stand-alone server, a rack-mounted server, a blade server, and the like. The server 3600 may include a memory 3602, a processor 3604, and a BMC 3614. The processor 3604 may be connected to the memory 3602 through a communication path 3606. The BMC 3614 may be connected to the processor 3604 through a bus 3616 and may be connected to the memory 3602 through a bus 3612. Each of the memory 3602, the processor 3604, the BMC 3614, the communication path 3606, and the buses 3612 and 3616 may be any one of the corresponding configurations described above.

37 is a schematic diagram showing a server system according to an embodiment of the present invention. In this embodiment, the server system 3700 may include a plurality of servers 3702-1 to 3702-N. Each of the servers 3702 may be connected to the manager 3704. One or more of the servers 3702 may be similar to the server 3700 described above. In addition, the manager 3704 may include a system having the memory system architecture described above.

The manager 3704 may be configured to manage the server 3702 and other components of the server system 3700. For example, the manager 3704 may be configured to manage settings of the server 3702. Each of the servers 3702 may be configured to exchange error information with the manager 3704. The error information may include correctable error information transmitted to a processor in any one of the servers 3702 as described above, or other error information based on correctable error information. The manager 3704 may be configured to take an action based on the error information. For example, the server 3702-1 may include a correctable error exceeding a threshold. The manager 3704 may be configured to transfer the function of the server 3702-1 to the server 3702-2 for management and/or replacement, and to shut down the server 2302-1. Although specific examples have been presented, the manager 3704 may be configured to take another action based on the error information.

38 is a schematic diagram showing a data center according to an embodiment of the present invention. In this embodiment, the data center 3800 may include a plurality of server systems 3802-1 to 3802-N. Server systems 3802 are similar to server system 3600 described in FIG. 36. Server systems 3802 may be connected to a network 3804 such as the Internet. Accordingly, the server systems 3802 may communicate with various nodes 3806-1 to 3806-M through the network 3804. For example, nodes 3806 may be a client computer, another server, a remote data center, a storage system, or the like.

Although specific embodiments have been described in the detailed description of the present invention, various modifications may be made without departing from the scope of the technical idea of the present invention. Therefore, the scope of the present invention should not be defined by being limited to the above-described embodiments, and should be defined by the claims and equivalents of the present invention as well as the claims to be described later.

100: system 102: memory
104: processor 106: first communication path
109: second communication path 110: software
700: memory module 702: memory
704: processor 706, 708: communication paths
710: software 718: module
1300: System 1302: ECC DIMM
1304: processor 1310: kernel
1312, 1316: Bus 1314: BMC
1318: error correction module 1324: EDAC module
1326: MCA module 1350: memory controller
1352: MCA register 1358: memory ECC daemon
1360: other applications 1364: communication paths
1500: memory module 1501: memory devices
1536: data interface 1538: error interface
1541: controller 1900: memory device
1901: memory cell array 1902: sense amplifier
1904: read circuit 1906: address
1908: ECC engine 1910: write data
1912: data strobe signal 1918: ECC controller
1920: DQS changer 1922: data strobe signal
1924: output data 1928: command buffer
1930: serial presence detection module 1932: buffer
1934: register clock driver module 2100: memory module
2101: memory device 2136: data interface
2137: data interface 2138: module error interface
2139: device error interface 2141: controller
2143: serial presence detection module 2145: registering clock driver
2149: register 2750: repeater

Claims (20)

An external module error interface for communicating error information from a memory module to a system control path outside the memory module;
An external module data interface of a memory module that communicates data between the memory module and the external main memory path and the memory module, the main memory path being separated from the system control path; And
Each memory device is configured to store data, and each memory device includes a device controller, a device error interface connected to an external module error interface, and a device data interface connected to an external module, and the error data interface includes the device data interface and Separate, including a plurality of memory devices inside the memory module,
Each device controller
Includes an ECC (error correcting code) engine,
The ECC (error correcting code) engine,
In order to create the modified data, the error of the data read from the memory device corresponding to the ECC engine is corrected,
Generate error information in response to correction of the error in the data,
Exchange the error information to the external module error interface through the device error interface, and
Exchange the modified data to the external module data interface through the device error interface, and
A memory module including an ECC controller for recording the error information in response to error correction of the ECC engine. The method of claim 1,
The memory module further comprises a module controller connected to the module error interface and each of the device error interfaces of the memory devices. The method of claim 2,
The module controller is a memory module including a repeater. An external module error interface for communicating error information from a memory module to a system control path outside the memory module;
An external module data interface of a memory module that exchanges data between the memory module and an external main memory path and the memory module, the main memory path being separated from the system control path; And
Including a plurality of memory devices inside the memory module,
Each memory device is a device data interface and a device error interface separate from the device data interface,
Each memory device,
In order to create the modified data, the error of the data read from the memory device corresponding to the ECC engine is corrected,
Generate error information in response to correction of the error in the data,
Exchange the error information to the external module error interface through the device error interface, and
A module controller connected to the external module error interface and the device error interface of each memory device, and connected to the external module data interface and the device data interface of each memory device,
The module controller,
A memory module for controlling the exchange of the error information from each device error interface to the external module error interface, and controlling the exchange of the modified data from each device data interface to the external module data interface. The method of claim 4,
The system control path,
A memory module comprising an out-of-band exchange path to the main memory. The method of claim 4,
The system control path,
Memory module with platform management bus. The method of claim 6,
The platform management bus is
A memory module including a system management bus (SMBus), an inter-integrated circuit (I2C) bus, an intelligent platform management interface (IPMI) bus, or a Modbus. The method of claim 4,
The system control path is a memory module that is slower than the main memory path. The method of claim 8,
The main memory path includes a first data rate, the system control path includes a second data rate, and the second data rate to live is less than or equal to 1/10 of the first data rate. The method of claim 4,
The module controller,
The memory module further comprising transmitting error information through the external module error interface. According to claim 1
The external module error interface,
A memory module that can receive polls for error information. The method of claim 1,
The system control path,
A memory module comprising an out-of-band exchange path to the main memory. The method of claim 1,
The system control path,
Memory module with platform management bus. The method of claim 13,
The platform management bus is
A memory module including a system management bus (SMBus), an inter-integrated circuit (I2C) bus, an intelligent platform management interface (IPMI) bus, or a Modbus. The method of claim 1,
The system control path is a memory module that is slower than the main memory path. The method of claim 15,
The main memory path includes a first data rate, the system control path includes a second data rate, and the second data rate to live is less than or equal to 1/10 of the first data rate. The method of claim 2,
The module controller,
The memory module further comprising transmitting error information through the external module error interface. The method of claim 4
The external module error interface,
A memory module that can receive polls for error information. delete delete

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