KR102208989B1 - 강화 학습을 통한 디바이스 배치 최적화 - Google Patents

강화 학습을 통한 디바이스 배치 최적화 Download PDF

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KR102208989B1
KR102208989B1 KR1020197026115A KR20197026115A KR102208989B1 KR 102208989 B1 KR102208989 B1 KR 102208989B1 KR 1020197026115 A KR1020197026115 A KR 1020197026115A KR 20197026115 A KR20197026115 A KR 20197026115A KR 102208989 B1 KR102208989 B1 KR 102208989B1
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사무엘 벤지오
모하메드 노로우지
베누아 스테이너
제프리 에드게이트 딘
휴 히 팜
아잘리아 미르호세이니
꾸옥 브이. 르
나빈 쿠말
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라스무스 멍크 라센
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KR1020197026115A 2017-03-24 2018-03-23 강화 학습을 통한 디바이스 배치 최적화 Active KR102208989B1 (ko)

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PCT/US2018/024155 WO2018175972A1 (en) 2017-03-24 2018-03-23 Device placement optimization with reinforcement learning

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KR102634706B1 (ko) 2023-05-31 2024-02-13 주식회사 애자일소다 데드 스페이스의 최소화를 위한 집적회로 설계 장치 및 방법
KR102645072B1 (ko) 2023-05-31 2024-03-08 주식회사 애자일소다 매크로의 핀 방향 최적화를 위한 후처리 장치 및 방법
KR102713624B1 (ko) 2023-12-20 2024-10-08 주식회사 애자일소다 비사각형상의 분해 및 처리를 이용한 배치 최적화 장치 및 방법

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Cited By (4)

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Publication number Priority date Publication date Assignee Title
KR102603130B1 (ko) 2022-12-27 2023-11-17 주식회사 애자일소다 강화학습 기반의 면적 및 매크로 배치 최적화를 위한 설계 시스템 및 방법
KR102634706B1 (ko) 2023-05-31 2024-02-13 주식회사 애자일소다 데드 스페이스의 최소화를 위한 집적회로 설계 장치 및 방법
KR102645072B1 (ko) 2023-05-31 2024-03-08 주식회사 애자일소다 매크로의 핀 방향 최적화를 위한 후처리 장치 및 방법
KR102713624B1 (ko) 2023-12-20 2024-10-08 주식회사 애자일소다 비사각형상의 분해 및 처리를 이용한 배치 최적화 장치 및 방법

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US20240062062A1 (en) 2024-02-22
CN110268422B (zh) 2023-12-01
CN110268422A (zh) 2019-09-20
WO2018175972A1 (en) 2018-09-27
EP3559868B1 (en) 2025-05-07
US10692003B2 (en) 2020-06-23
US11803747B2 (en) 2023-10-31
EP4553715A2 (en) 2025-05-14
EP3559868A1 (en) 2019-10-30
JP2020512639A (ja) 2020-04-23
EP4553715A3 (en) 2025-08-13
JP6790286B2 (ja) 2020-11-25
KR20190113928A (ko) 2019-10-08
US20200279163A1 (en) 2020-09-03
US20190303761A1 (en) 2019-10-03
CN117648971A (zh) 2024-03-05

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