KR102207215B1 - Three dimensional flash memory for integrating and manufacturing method thereof - Google Patents

Abstract

Disclosed are a three-dimensional flash memory for integration and a method of manufacturing the same. According to an embodiment, the 3D flash memory includes at least one memory cell string extending in one direction; the at least one memory cell string includes at least one channel layer and at least one charge surrounding the at least one channel layer. Including a storage layer -; And a plurality of word lines connected in a vertical direction with respect to the at least one memory cell string, and each contact of the plurality of word lines is provided in a minimized partial area among the entire areas of each of the plurality of word lines. It is characterized in that it is formed.

Description

Three-dimensional flash memory for integration and its manufacturing method TECHNICAL FIELD TECHNICAL FIELD [0003] THREE DIMENSIONAL FLASH MEMORY FOR INTEGRATING AND MANUFACTURING METHOD THEREOF}

The following embodiments relate to a three-dimensional flash memory and a method of manufacturing the same, and more particularly, a description of a three-dimensional flash memory and a method of manufacturing the same to achieve integration.

Flash memory is an electrically erasable programmable read only memory (EEPROM), which electrically controls input and output of data by Fowler-Nordheimtunneling or hot electron injection. .

In recent flash memories, a three-dimensional structure in which cells are vertically stacked and the degree of integration is increased in order to meet the excellent performance and low price demanded by consumers is applied. Referring to FIGS. 1 to 2 showing the conventional 3D flash memory, the 3D flash memory 100 includes a channel layer 110 formed in a vertical direction, and a charge storage layer 120 formed to surround the channel layer 110. , A plurality of electrode layers 130 connected to the charge storage layer 120 and stacked in a horizontal direction, and a plurality of insulating layers 140 alternately interposed between the plurality of electrode layers 130. Hereinafter, since each of the plurality of electrode layers 130 is used as a word line, the plurality of electrode layers 130 will be described as a plurality of word lines 130.

Here, since each of the plurality of word lines 130 has to be formed with a contact 131 to be connected to an external wiring, the plurality of word lines 130 form a step shape as shown in the drawing.

In particular, since the contact 131 of each of the plurality of word lines 130 is formed over the entire area of the step shape of each of the plurality of word lines 130, the area wasted in the 3D flash memory 100 It becomes severe. Moreover, the higher the 3D flash memory 100 is formed, the higher the occupancy of the area in which the contact 131 is formed relative to the total area of the memory, resulting in a disadvantage that the overall degree of integration is lowered.

Accordingly, there is a need to propose a three-dimensional flash memory technology that achieves integration by reducing the contact formation area.

One embodiment proposes a 3D flash memory and a method of manufacturing the same to achieve integration by reducing a contact formation area.

In more detail, exemplary embodiments propose a 3D flash memory in which a contact of each of a plurality of word lines is formed only in a small portion of the entire area of each of the plurality of word lines, and a method of manufacturing the same.

According to an embodiment, in the 3D flash memory for integration, at least one memory cell string extending in one direction-the at least one memory cell string includes at least one channel layer and the at least one channel layer. Including at least one charge storage layer surrounding; And a plurality of word lines connected in a vertical direction with respect to the at least one memory cell string, and each contact of the plurality of word lines is provided in a minimized partial area among the entire areas of each of the plurality of word lines. It is characterized in that it is formed.

According to one side, the plurality of word lines are the same as the at least one memory cell string, as contacts of each of the plurality of word lines are formed only in a minimized portion of the entire area of each of the plurality of word lines. It may be characterized in that a space in which at least one other memory cell string not disposed in the array is formed is secured.

According to the other side, the plurality of word lines are shared by the at least one memory cell string and the at least one other memory cell string as the at least one other memory cell string is formed in the space. You can do it.

According to another aspect, the minimized partial area in which each contact of each of the plurality of word lines is formed is an area located in the same row on the entire area of each of the plurality of word lines. I can.

According to an embodiment, a method of manufacturing a 3D flash memory for integration may include preparing a mold structure in which a plurality of word lines and a plurality of insulating layers are alternately stacked; At least one memory cell string on the mold structure except for a minimized partial region in which each contact of each of the plurality of word lines is formed-the at least one memory cell string includes at least one channel layer and the at least one Extending in one direction-including at least one charge storage layer surrounding the channel layer; Etching the minimized partial area into a step shape; And forming a contact of each of the plurality of word lines in the etched region.

According to one side, the forming of the at least one memory cell string extending in one direction may include securing a space in which at least one other memory cell string not disposed in the same array as the at least one memory cell string is formed. Forming at least one memory cell string extending in the one direction; And forming the at least one other memory cell string extending in the one direction in the space.

According to the other side, the forming of the at least one other memory cell string extending in the one direction may include the plurality of word lines being shared by the at least one memory cell string and the at least one other memory cell string. The at least one other memory cell string may be extended and formed in the one direction.

According to another aspect, the minimized partial area in which the contact of each of the plurality of word lines is to be formed is an area located in the same row on the entire area of each of the plurality of word lines. I can.

According to an embodiment, in the 3D flash memory for integration, at least one memory cell string extending in one direction-the at least one memory cell string includes at least one channel layer and the at least one channel layer. Including at least one charge storage layer surrounding; And a plurality of word lines connected in a vertical direction to the at least one memory cell string, wherein a contact of each of the plurality of word lines is a whole area of each of the plurality of word lines As the at least one memory cell string and at least one other memory cell string not disposed in the same array are formed, a space in which at least one other memory cell string is formed, and at least one other memory cell string formed in the secured space is secured. It is characterized by being shared by a memory cell string and the at least one memory cell string.

According to an embodiment, in the 3D flash memory for integration, at least one memory cell string extending in one direction-the at least one memory cell string includes at least one channel layer and the at least one channel layer. Including at least one charge storage layer surrounding; And a plurality of word lines connected in a vertical direction with respect to the at least one memory cell string, and each contact of the plurality of word lines includes a minimized partial area among the entire areas of each of the plurality of word lines- The minimized partial region is formed only in the region located in the same row on the entire region of each of the plurality of word lines.

Embodiments may propose a 3D flash memory and a method of manufacturing the same to achieve integration by reducing the contact formation area.

In more detail, exemplary embodiments may propose a 3D flash memory in which a contact of each of a plurality of word lines is formed only in a small portion of the entire area of each of the plurality of word lines, and a method of manufacturing the same.

1 is a cross-sectional view showing a conventional 3D flash memory.
2 is a top view showing a conventional 3D flash memory.
3 is a top view illustrating a 3D flash memory according to an exemplary embodiment.
4A to 4B are cross-sectional views illustrating a 3D flash memory according to an exemplary embodiment.
5 is a flowchart illustrating a method of manufacturing a 3D flash memory according to an exemplary embodiment.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the embodiments. In addition, the same reference numerals shown in each drawing denote the same member.

In addition, terms used in the present specification are terms used to properly express preferred embodiments of the present invention, which may vary depending on the intention of users or operators, or customs in the field to which the present invention belongs. Accordingly, definitions of these terms should be made based on the contents throughout the present specification.

3 is a top view illustrating a 3D flash memory according to an exemplary embodiment, and FIGS. 4A to 4B are cross-sectional views illustrating a 3D flash memory according to an exemplary embodiment.

3 to 4B, a 3D flash memory 300 according to an exemplary embodiment includes at least one memory cell string 320 and a plurality of word lines 330 extending in one direction on a substrate 310. Includes. In the 3D flash memory 300, a drain line may be disposed above and connected to at least one memory cell string 320, and each of the plurality of word lines 330 may be connected to an external wiring through a contact 331. have. Hereinafter, the drain line and the external wiring are shown only in FIG. 3 and are omitted in FIGS. 4A to 4B.

The at least one memory cell string 320 includes at least one channel layer 321 and at least one charge storage layer 322 surrounding the at least one channel layer 321. At least one channel layer 321 may be formed of single crystal silicon or poly-silicon, and a selective epitaxial growth process or a phase transition epitaxial process using the substrate 310 as a seed, etc. It can be formed as

At least one charge storage layer 322 is a component that stores charge from current flowing through the plurality of word lines 330, and, for example, may also be formed in a structure of ONO (Oxide-Nitride-Oxide). I can. Hereinafter, the at least one charge storage layer 322 will be described as including only a vertical element extending in one direction orthogonal to the substrate 310, but is not limited thereto and the plurality of word lines 330 and It may further comprise parallel and contact horizontal elements.

The plurality of word lines 330 are connected in a vertical direction to the at least one memory cell string 320, and may be alternately disposed with the plurality of insulating layers 340. The plurality of word lines 330 may be formed of a conductive material such as tungsten, titanium, tantalum, or the like, and the plurality of insulating layers 340 may be formed of various materials having insulating properties.

In this case, the plurality of word lines 330 are formed to have a step shape, and may be connected to an external wiring through each contact 331 formed in the step shape. In particular, the contact 331 of each of the plurality of word lines 330 is formed only in a minimized partial area of the entire area of each of the plurality of word lines 330. Hereinafter, the fact that the contact 331 of each of the plurality of word lines 330 is formed only in a portion of the minimized region is only a region corresponding to the cross-section of the contact 331 among the entire regions of each of the plurality of word lines 330. This means that the contact 331 is formed.

In addition, the minimized partial area in which the contact 331 of each of the plurality of word lines 330 is formed may be an area located in the same row on the entire area of each of the plurality of word lines 330. . That is, while the contact 331 is formed only in a region corresponding to the cross section of the contact 331 among the entire regions of each of the plurality of word lines 330, the contact 331 is the same for each of the plurality of word lines 330. It may be formed in a region located in a row.

In this way, as the contacts 331 of each of the plurality of word lines 330 are formed only in a small portion of the entire area of each of the plurality of word lines 330, the same array as at least one memory cell string 320 A space 351 in which at least one other memory cell string 350 that is not disposed in is formed may be secured. Accordingly, the 3D flash memory 300 includes more memory cell strings 320 and 350, and thus the degree of integration may be improved. Hereinafter, the same array as at least one memory cell string 320 includes at least one memory cell string 320 and a memory cell string disposed in the same column as the at least one memory cell string 320 It refers to a set of memory cell strings, wherein at least one other memory cell string 350 not disposed in the same array as at least one memory cell string 320 is a column different from the at least one memory cell string 320 Refers to a string of memory cells arranged in

Here, as at least one other memory cell string 350 is formed in the space 351, the plurality of word lines 330 are at least one memory cell string 320 and at least one other memory cell string 350. Can be shared by Hereinafter, the fact that the plurality of word lines 330 are shared by at least one memory cell string 320 and at least one other memory cell string 350 means that the plurality of word lines 330 are at least one memory. This means that it is used to supply current to both the cell string 320 and at least one other memory cell string 350.

In the 3D flash memory 300 according to an exemplary embodiment, as described, the contact 331 of each of the plurality of word lines 330 is placed in a minimized portion of the entire area of each of the plurality of word lines 330. By forming a space 351 in which at least one other memory cell string 350 not disposed in the same array as the at least one memory cell string 320 is formed, a larger number of memory cell strings 320 are secured. 350) may be included. Accordingly, the degree of integration of the 3D flash memory 300 can be significantly improved.

5 is a flowchart illustrating a method of manufacturing a 3D flash memory according to an exemplary embodiment. Hereinafter, as a subject performing the 3D flash memory manufacturing method, an automated and mechanized manufacturing system may be used, and the 3D flash memory manufactured through the steps S510 to S540 described below, see FIGS. 3 to 4 Thus, the above-described structure is assumed.

Referring to FIG. 5, the manufacturing system according to an exemplary embodiment prepares a mold structure in which a plurality of word lines and a plurality of insulating layers are alternately stacked in step S510.

Subsequently, in step S520, the manufacturing system includes at least one memory cell string (at least one memory cell string includes at least one memory cell string) in the remaining regions except for a minimized partial region where each contact of each of the plurality of word lines on the mold structure is formed. A channel layer and at least one charge storage layer surrounding at least one channel layer) are formed extending in one direction.

For example, the manufacturing system generates vertical holes in the remaining regions except for the minimized partial regions in which contacts of each of the plurality of word lines are to be formed so that the substrate included in the mold structure is exposed, and then at least one charge storage layer is formed. At least one memory cell string may be formed by depositing in the vertical hole and filling at least one channel layer therein.

Here, the minimized partial area in which the contact of each of the plurality of word lines is to be formed is an area corresponding to the cross-section of the contact among the entire areas of each of the plurality of word lines, and is located in the same row on each area of the plurality of word lines. It may be an area located.

In addition, in step S520, the manufacturing system moves at least one memory cell string in one direction in the remaining area to secure a space in which at least one other memory cell string not disposed in the same array as the at least one memory cell string is formed. After the extension is formed, at least one other memory cell string may be extended in one direction in the space.

Accordingly, operation S520 may be a step of extending at least one other memory cell string in one direction so that the plurality of word lines are shared by at least one memory cell string and at least one other memory cell string.

In this way, since the manufacturing system leaves only a minimized partial region of the entire region of each of the plurality of word lines as a contact forming region in step S520, the memory cell strings are formed in all regions except for the minimized region. The degree of integration of the cell string can be further improved.

Thereafter, in step S530, the manufacturing system etch the minimized partial area where each contact of each of the plurality of word lines is to be formed in a step shape.

Thereafter, the manufacturing system forms a contact of each of the plurality of word lines in the region etched in step S540.

As described above, although the embodiments have been described by the limited embodiments and drawings, various modifications and variations are possible from the above description by those of ordinary skill in the art. For example, the described techniques are performed in a different order from the described method, and/or components such as a system, structure, device, circuit, etc. described are combined or combined in a form different from the described method, or other components Alternatively, even if substituted or substituted by an equivalent, an appropriate result can be achieved.

Therefore, other implementations, other embodiments, and claims and equivalents fall within the scope of the claims to be described later.

Claims (10)

In the three-dimensional flash memory aiming at integration,
At least one memory cell string extending in one direction, the at least one memory cell string including at least one channel layer and at least one charge storage layer surrounding the at least one channel layer; And
A plurality of word lines connected in a vertical direction to the at least one memory cell string
Including,
Each contact of the plurality of word lines,
It is characterized in that it is formed only in a minimized partial region corresponding to a cross section of each contact of the plurality of word lines among the entire regions of each of the plurality of word lines,
The plurality of word lines have a step shape only in the minimized partial area. The method of claim 1,
The plurality of word lines,
At least one other memory cell not disposed in the same array as the at least one memory cell string, as contacts of each of the plurality of word lines are formed only in a minimized partial area of the entire area of each of the plurality of word lines A 3D flash memory, characterized in that to secure a space in which a string is formed. The method of claim 2,
The plurality of word lines,
As the at least one other memory cell string is formed in the space, the 3D flash memory is shared by the at least one memory cell string and the at least one other memory cell string. The method of claim 2,
The minimized partial area in which the contact of each of the plurality of word lines is formed,
3D flash memory, characterized in that the region is located in the same row on the entire region of each of the plurality of word lines. In the manufacturing method of a three-dimensional flash memory aiming at integration,
Preparing a mold structure in which a plurality of word lines and a plurality of insulating layers are alternately stacked;
At least one memory cell string on the mold structure except for a partial region corresponding to a cross-section of each of the plurality of word lines in which each contact is to be formed. Forming a memory cell string extending in one direction, including at least one channel layer and at least one charge storage layer surrounding the at least one channel layer;
Etching only the minimized partial area into a step shape; And
Forming a contact of each of the plurality of word lines in the etched region
3D flash memory manufacturing method comprising a. The method of claim 5,
The step of forming the at least one memory cell string extending in one direction,
Extending and forming the at least one memory cell string in the one direction to secure a space in which at least one other memory cell string not disposed in the same array as the at least one memory cell string is formed; And
Forming the at least one other memory cell string extending in the one direction in the space
3D flash memory manufacturing method comprising a. The method of claim 6,
The step of forming the at least one other memory cell string extending in the one direction,
Forming the at least one other memory cell string extending in the one direction so that the plurality of word lines are shared by the at least one memory cell string and the at least one other memory cell string Flash memory manufacturing method. The method of claim 5,
The minimized partial area in which the contact of each of the plurality of word lines is to be formed,
And an area positioned in the same row on the entire area of each of the plurality of word lines. delete delete

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